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1 A Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions for STT-MRAM Scalability Studies Jongyeon Kim 1 , An Chen 2 , Behtash Behin-Aein 2 , Saurabh Kumar 1 , Jian-Ping Wang 1 , and Chris H. Kim 1 1 University of Minnesota, Minneapolis, MN 55455 USA 2 GLOBALFOUNDRIES, Sunnyvale, CA 94085 USA [email protected] Model download website: mtj.umn.edu
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Page 1: A Technology-Agnostic MTJ SPICE Model with User …mtj.umn.edu/CICC15_MTJ_slides.pdf1 A Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions for STT-MRAM Scalability Studies

1

A Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions

for STT-MRAM Scalability Studies

Jongyeon Kim1, An Chen2, Behtash Behin-Aein2, SaurabhKumar1, Jian-Ping Wang1, and Chris H. Kim1

1University of Minnesota, Minneapolis, MN 55455 USA2GLOBALFOUNDRIES, Sunnyvale, CA 94085 USA

[email protected]

Model download website: mtj.umn.edu

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2

Overview

• Spin-Transfer Torque (STT) MRAM: Basic Concepts

• Magnetic Tunnel Junction (MTJ):Key Physics to Be Modeled

• Model Framework and Implementation

• Case Study: STT-MRAM Scalability and Variability Simulations

• Summary

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3

STT-MRAM Basics

[1] R. Takemura, JSSC 2010 (Hitachi)

STT-MRAM bit-cell structure and STT switching

• Key features: Nonvolatile, compact, CMOS compatible, high endurance

Type Stand-alone Embedded

WTX Minimum 18F

1T-1MTJ 6F2 57F2

2T-1MTJ 8F2 40F2

Bit-cell area comparison1T-1MTJ layout 2T-1MTJ layout

* SRAM: ~120F2[1]

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4[1] K. Lee, TMAG 2011 (Qualcomm) [2] G. Jan, VLSI 2014 (TDK)

• Low power main memory

• Embedded cache memory:

- No standby power, compact size

- Low latency due to reduced global

interconnect delay

Target Applications & Recent Progress

[1]

� STT-MRAM target applications

• 8Mbits embedded STT-MRAM

• 90nm CMOS/ 50F2 1T-1MTJ

• 150% TMR, 4/5ns Read/Write

• Less than 1ppm bit error rate

for 10yr retention/125C

� Recent demonstration by TDK [2]

Chip micrograph and write shmoos

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5

STT-MRAM Scaling Challenges

[1] K. Ono, IEDM 2009 (Hitachi)

[1]

Read-disturb

• One critical issue is the conflict between read and write operations which becomes more severe with MTJ scaling

• The development of a scalable MTJ SPICE model is a key aspect of exploring the potential of STT-MRAM in future technology nodes

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• Thermal stability (Δ) determines the degree of nonvolatility• Thermal stability is defined as Eb with respect to thermal fluctuation• Hk decides the energetic preference of spin direction (i.e. easy axis):

In-plane or perpendicular magnetic anisotropy

• Eb: Energy barrier, V: Magnet volume, • Hk: Anisotropy field, Ms: Saturation magnetization

[1]

[1] R. Takemura, JSSC 2003 (Hitachi)

Tk

VMH

Tk

E

B

sk

B

b

2==∆

Thermal stability and magnetic anisotropy

Key MTJ Physics to Be Modeled

: Thermal stability factor

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7

Key MTJ Physics to Be Modeled

STT-induced dynamic spin motion

Temperature-dependent R-V curveSwitching current vs. pulse width

[1]

M

HK

[1] J. Sun, Nature 2003 (IBM)

Thermally assisted switching region

*TMR: Tunneling magnetoresistance ratio

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8

Proposed Technology-Agnostic SPICE-Compatible MTJ Model

User-defined input parameters

� Covers all types of anisotropy sources (shape, crystal, and interface)� Dimension-dependent anisotropy field enables scalability and variability

analyses� Changing the initial angle parameter allows convenient simulation of MTJ

switching probability

Overall model framework

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9

SPICE Implementation

SPICE implementation of LLG equation (only y-coordinate shown for simplicity)

• Internal variables are represented as node voltages using circuit elements • Differential behavior of magnetization by emulating an incremental charge

build-up over time in a capacitor: I=C∙dV/dt

sF MeWLt

PR

2

h=

ySTTI ,yDMPI ,

MTJI

)( yMV

γ

α21+

=C

)( KefxHV

)( sttAV

yPRCI , )(0yMV

)( KefyHV )( KefzHV

sF

sttpsttKeffKeff

Met

PJAMMMAHMMHM

dt

Md

2),()(

12

h=××⋅+××⋅−×−=⋅

γ

α

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10

Model Verification

MTJ switching characteristicsComparison with measurement data

In-plane switching Perpendicular switchingTemp. dependency of material parameters

[1] H. Zhao, JAP 2011 (UMN) [2] C. J. Lin, IEDM 2009 (TSMC)

[1], [2]

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11

Overview

• Spin-Transfer Torque (STT) MRAM: Basic Concepts

• Magnetic Tunnel Junction (MTJ):Key Physics to Be Modeled

• Model Framework and Implementation

• Case Study: STT-MRAM Scalability and Variability Simulations

• Summary

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12

Scalability Study: MTJ Options

1. In-plane MTJ (IMTJ)• Geometry dependent shape anisotropy

• Longer dimension → Easier magnetization

• high polarization but high switching current due to Hdz

η

πα

h

)2(20

SKFSC

MHtMeJ

+=

2. Crystal perpendicular MTJ (c-PMTJ)• Crystal perpendicular anisotropy from

high-Ku materials (FePt, FePd, etc)

• Hdz reduces switching current

• Low polarization, high dampingη

πα

h

)4(20

SKFSC

MHtMeJ

−= ⊥

3. Interface perpendicular MTJ (i-PMTJ)• Interface perpendicular anisotropy in thin CoFeB

• CoFeB turns from in-plane to perpendicular when tF < tc (~1.5nm)

• Which MTJ technology is best from a scaling perspective?

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13

MTJ scaling methods under iso-retention condition

Scalability Study: Ic Scaling Trend

• MTJ scaling based on iso-retention using realistic materials• Interface PMTJ shows the superior switching efficiency over the scaling

MTJ scaling scenario Critical switching current (Ic) trend

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. . .

. . . . . .

. . .. . .

..Variability Study: Simulation Setup

Readpath

Write path

STT-MRAM column circuit

• Optimized bit-cell connection for symmetric current driving• Bi-directional write current driver, dual-voltage WL driver• Parallelizing read current, Mid-point reference circuit using IRef=(IAP+IP)/2

Overall memory operation

CMOS 65nm, i-PMTJ (Δ=70), 85ºC

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Variability Study: Write and Read Delays

• Write and sensing delay distributions with 6σ values • Includes realistic variation for both MTJ (i.e. W, L, tF, RA) and CMOS (i.e.

transistor W, L, Vth, Tox)

0

10

20

30

0

0.5 1

1.5 2

0

10

20

30

3.5

4.5

5.5

6.5

7.5

STT-MRAM 6σ write delay VDD (1.2V): 7.49ns VDD+0.1V: 6.49ns VDD+0.2V: 5.80ns VDD+0.3V: 5.29ns

4.5 7.5

Write delay (ns)5.5 6.5

30

10

0

20

Pe

rce

nti

le (

%)

3.5

STT-MRAM 6σ sensing delay TMR 100%: 1.32ns TMR 200%: 0.82ns TMR 300%: 0.67ns

0.5 < 2.0

Sensing delay (ns)1.0 1.5

30

10

20

Pe

rce

nti

le (

%)

0

Read failures

0

CMOS 65nm, i-PMTJ (Δ=70), 85ºC

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Model Download Website

http://mtj.umn.edu

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Summary

• We have developed a technology-agnostic MTJ model for

benchmarking future STT-MRAMs

• The proposed compact model is useful for studying the

scalability and variability of different MTJ devices and

material options.

• Model available online at mtj.umn.edu

Acknowledgements

• This work was supported in part by C-SPIN, one of six

centers of STARnet, a Semiconductor Research Corporation

program, sponsored by MARCO and DARPA.


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