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A Tutorial on Hybrid PLL Design for Synchronization in Wireless Receivers

(companion paper to the workshop “Synchronization and Receiver Structures in Digital Wireless Communications”)

Yair Linn

University of British Columbia Vancouver, BC, Canada

ylinn@ece.ubc.ca

Abstract - Coherent reception in digital wireless communications involves generating a local carrier that is in phase with the received carrier, and then using this local carrier in order to demodulate the received signal. Generation of the local carrier is generally done via a Phase Lock Loop (PLL). The receiver also includes a symbol timing synchronization PLL, whose purpose is to determine the optimal time for sampling of the received signal in order to sample each symbol at its peak and thus minimize the error rate. The objective of the workshop entitled “Synchronization and Receiver Structures in Digital Wireless Communications” [1] is to develop a systematic method for the incorporation of digital signal processing theory into the design and implementation of hybrid PLLs used in digital communications. Additionally, the workshop aims to provide an overview of all the important elements in the receiver, their operation, and their interactions. In this companion paper we shall only outline the core material of the workshop while omitting many mathematical derivations and other important content that shall only be presented in the workshop. Nonetheless, an attempt has been made to make this paper self-contained and thus it is hoped that this paper can serve as a useful reference for workshop attendees and for others.

I. INTRODUCTION Until the mid-to-late 1980s, most literature on the subject of coherent receivers was devoted to analog implementations. In the past decade or so, some books (including [2], [3]) and many papers (e.g. [4], [5]) have been published that deal with exclusively digital receivers – i.e. those in which sampling of the received bandpass or near-baseband signal is performed, and the entire demodulation process is done digitally. Many contemporary coherent receivers, however, have neither a completely analog nor a completely digital implementation. Such receivers have hybrid architectures similar to Fig. 1, that is where I-Q demodulation is done in the analog domain, using a coherent carrier that is controlled by a digitally implemented loop filter and phase detector. This structure is particularly suited for high-datarate communications (for example (in current technology) for symbol rates which are above 50 MHz) where sampling and

real-time processing of the IF or near-baseband signal is either impossible or uneconomical.

Using the architecture of Fig. 1 allows the designer to enjoy architectural benefits which are unavailable when using a completely analog or completely digital receiver. As alluded to earlier, sampling the baseband signal rather than the IF or near-baseband signal generally allows more inexpensive samplers which operate at a lower clock rate to be used. Furthermore, the fact that downconversion of the incoming signal is done in the analog domain considerably simplifies the digital logic required, since the latter is relieved from the need to perform downconversion of the complex (i.e. I-Q) sampled signal (see [2 Chap. 4] for a description of such a completely digital receiver operating on a near-baseband signal).

On the other hand, having the I-Q demodulator in the analog domain driven by an analog local carrier allows an arbitrarily high IF frequency IFf to be used with the aid of an external mixer and a fixed oscillator (see Fig. 1). Thus, with a relatively inexpensive low frequency DDS (Direct Digital Synthesizer) and an additional (relatively inexpensive) fixed RF oscillator, the use of an expensive and difficult to use high frequency VCO (Voltage Controlled Oscillator) is averted. Moreover, the long-term stability and phase noise characteristics achievable with DDS chips are difficult to attain using a VCO.

The advantages of implementing the phase detector and the matched and loop filters digitally are numerous. First and perhaps foremost, the repeatability of filter and transient response specifications that can be achieved via a digital implementation is exceedingly difficult to duplicate in an analog implementation. Second, arbitrarily complicated phase detector and filter structures may be implemented, whereby that complexity is only limited by the amount of logic and computing power available for the digital section’s implementation. Finally in this very non-exhaustive list, the implementation of certain synchronization loop elements by digital means allows testability and probing with accuracy and availability that is hard to attain in a completely analog system; for example, if the loop filter is implemented digitally then its (digital) input may be monitored by a computer console or analyzed in real time using the FFT transform.

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Though the digital portion of the receiver could be implemented either in hardware or in software, the workshop and this paper focus on fixed-point hardware implementations. The reason is that, first, fixed-point hardware implementations, as shall be shown, will always have distinct performance advantages due simply to the fact that fixed-point hardware implementations can always be made to operate faster than any software and/or floating point implementation. Secondly, more intriguing challenges are present when trying to design a hardware system: while a software system could be implemented in a high-level language, in contrast when implementing a fixed-point hardware system the designer must explicitly address such issues as scaling and overflow, logic resource usage, implementation of mathematical operations, etc.

In this paper, we shall endeavor to bridge the gap between, on the one hand, what is known in DSP, PLL and control theory, and, on the other hand, the architectural and implementation issues pertaining to hybrid receivers. The process will begin with rigorous analysis of “classical” or analog PLL theory, and we will arrive at a step-by-step method with which we can design analog PLLs. Subsequently we shall develop a mathematical model that describes the hybrid PLL. Then, the implementation of the components of that model will be dwelled upon, culminating with the presentation of a step-by-step procedure for hybrid PLL design.

II. UNDERSTANDING THE MEANING OF SYNCHRONIZATION

Before delving into mathematics, it may be worthwhile to attempt to attain an intuitive understanding of the meaning of carrier and symbol synchronization in a receiver.

To this end, let us assume a BPSK communications system where the baseband data pulse is rectangular, and let us look at the waveforms at the outputs of the I and Q matched filters (note that the post-matched-filter pulse shape is triangular). The system’s symbol rate is denoted as 1/T .

In Fig. 2 we see the situation that occurs when there is perfect carrier and symbol synchronization (a noiseless BPSK signal is assumed). The small circles denote the samples (at 1 sample/symbol). As we can see, the receiver’s carrier is in complete synchronization with the input carrier (as seen by the fact that the Q channel is always 0) and the symbol timing synchronization loop is also working perfectly (as seen by the fact that the samples of the I channel are always taken at the symbol’s peak).

Conversely, in Fig. 3 we see what happens when the carrier loop is unlocked and there is also a timing mismatch between the receiver and transmitter symbol clocks. The carrier frequency error manifests itself in the signal meandering between the I and Q channels, while the timing error manifests itself in that the samples (the small circles) are offset from the peaks of the symbols. Clearly, data cannot be recovered under these conditions.

It is also instructive to look at various scenarios using I-Q graphs. In Fig. 4 we see a BPSK signal where the carrier PLL is locked. On the left-hand side of Fig. 4 we see a signal

MatchedFilter

MatchedFilter

90o

Antialiasing Filter

Antialiasing Filter

LoopFilter

DDS (DirectDigital

Synthesizer)

2cos(2 )IF of t tπ ω θ+ ∆ +

2sin(2 )IF of t tπ ω θ− + ∆ +

I(t)

Q(t)

PhaseDetector

Q(nTs)

( )h t

( )h t

IF FilterIF Input

Fixed Oscillator

I(nTs)

Fig. 1 – General structure of a hybrid carrier PLL for digital communications. The parts within the dashed line in are implemented digitally, while the rest are analog components (the samplers and DDS are mixed-signal components). 1/Ts is the sample rate.

Fig. 2 – Ideal situation: no carrier error, no timing error.

Fig. 3 - Carrier frequency error of 1/(50 )T⋅ . Timing error of / 4T .

Fig. 4 – I-Q Graphs for

0/ 7 dBSE N = . Left: no timing or carrier

error. Right: no carrier error, timing error of / 4T .

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with 0/ 7 dBSE N = where the symbol timing recovery is

perfect. On the right, we see the effects of a timing error of / 4T . Clearly, the timing error causes some data points to

cross the decision region boundary (which is the vertical line I=0), hence worsening the error rate as compared to the perfect-timing recovery case.

In Fig. 5‘s left we see the effect of carrier frequency error on the I-Q graph; obviously, in this case no data recovery is possible. The case of a constant carrier phase error is shown on the right-hand side. Though data recovery is possible, the error rate will suffer tremendously as a result of the fact that many more of recovered symbols have crossed the decision region boundary I=0 (as compared to Fig. 4 left).

In Fig. 6 we see the effects of carrier phase jitter. On the left, we see how an I-Q graph would look for

0/ 30 dBSE N = for an ideally synchronized receiver. On the right, we see the effects of carrier phase jitter, that is a phase error

eθ which has a zero-mean and Gaussian distribution with

var( ) 20oeθ = . Although for BPSK and

0/ 30 dBSE N = the

effects upon the error rate will be mild, the effect upon the error rate would be much more grave for a lower

0/SE N and/or a higher modulation index (e.g. QPSK, 8-PSK, etc.).

Clearly, as we’ve seen in this section, achieving carrier and symbol timing synchronization is crucial for proper data recovery. In the receiver, the synchronized carrier and symbol clock are generated by using PLLs. In this paper we treat only carrier synchronization, though the application to symbol timing PLLs is straightforward (see [1])

III. ANALOG PLL THEORY A PLL’s purpose is to generate an output signal ( )oy t

that is in phase and frequency synchronization with the input signal ( )iy t . A general schematic of the PLL is shown in

Fig. 7. There, we have ( )( ) sin ( )i i iy t A t tω θ= ⋅ + and

( )( ) cos ( )o i oy t B t tω θ= ⋅ + . The fact that both ( )iy t and

( )oy t contain the term i tω does not necessarily mean that we assume that their frequencies are equal; we have simply incorporated the frequency-error induced phase difference, defined as tω∆ ⋅ , into 0 ( )tθ (see [6 Sec. 3.1]).

The purpose of the PLL is to control the VCO in such a manner that 0( ) ( )i t tθ θ= . Note that ( )iy t and ( )oy t are in quadrature (i.e. one is a sine and the other is a cosine) but a signal that is phase-coherent with ( )iy t is easily obtained

(when in lock) via a 090 phase shift network applied to ( )oy t (not shown in Fig. 7).

A. The equivalent baseband nonlinear model The problem with PLLs is that ( )i tθ , the phase

information upon which the PLL operates, is “hidden” within the input signal ( )( ) sin ( )i i iy t A t tω θ= ⋅ + . The

only way that we can extract phase information upon which the PLL can operate is to use a nonlinearity in the phase

detector. This makes exact PLL theoretical analysis very difficult because we are dealing with nonlinear differential equations.

For example, consider the phase detector defined as ( ( ), ( )) ( ) ( )i o i oPD y t y t y t y t= ⋅ . We then have:

( ) ( )

( )( )

( ( ), ( )) ( ) ( )sin ( ) cos ( )

sin ( ) ( ) sin(2 ( ) ( ))2

i o i o

i i i o

i o i i o

PD y t y t y t y tA t t B t tAB t t t t t

ω θ ω θ

θ θ ω θ θ

= ⋅

= + ⋅ +

= − + + +

(1)

If we assume that the loop filter obliterates the double frequency term, then we can denote the effective phase detector output as:

( )( ( ), ( )) 0 .5 sin ( ) ( )i o i oP D y t y t A B t tθ θ= − (2)

Note that (2) is a nonlinear function of ( )i tθ and ( )o tθ . Analysis of the PLL is done in the phase domain. We

already saw in (2) that the effective phase detector output is a function of ( )i tθ and ( )o tθ , not of ( )iy t and ( )oy t . Thus, an equivalent baseband nonlinear model of the PLL is given in Fig. 8.

Fig. 5 – I-Q Graphs. Left:

0/ 15 dBSE N = with carrier frequency

error, no timing error. Right: 0/ 7 dBSE N = with constant carrier

phase error of 0.4π , no timing error.

Fig. 6 – I-Q graphs for

0/ 30 dBSE N = . Left: no carrier or frequency

error. Right: Gaussian carrier phase jitter with var( ) 20oeθ = .

Phase Detector Loop Filter

VCO

( )iy t( )oy t

Fig. 7 – General diagram of a PLL showing input and output signals.

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Let’s make some preliminary and general assumptions regarding the loop components, as shown in Fig. 9:

• The phase detector is a nonlinear device that gives as its output a function of the phase difference

( ) ( )i ot tθ θ− . We define this phase detector function

as ( ( ) ( ))i oPD t tθ θ− . • The loop filter is linear time invariant (LTI) with

impulse response ( )f t . • The VCO is a device that outputs a frequency as a

function of the voltage. Frequency is the derivative of the phase. Therefore, we can write for the VCO ( )

2

( )( )o

V

d tK u t

dtθ

= ⋅ . In the Laplace domain, the

VCO transfer function is therefore, from inspection,

2

( )( )( )

o Vs KV sU s sθ

= . We see that in the phase

domain the VCO is an integrator. Thus we have the following:

1( ) ( ( ) ( ))i ou t PD t tθ θ= − (3)

2 1( ) ( ) ( )u t u t f t= ⊗ (4)

( )2

( )( )o

V

d tK u t

dtθ

= ⋅ (5)

We can combine (3)-(5) to reach the differential equation: ( )( )

( ( ( ) ( )) ( ))oV i o

d tK PD t t f t

dtθ

θ θ= ⋅ − ⊗ (6)

Eq. (6) is problematic because it is a nonlinear differential equation (because the function PD is generally nonlinear). For the forthcoming nonlinear analysis, we assume the phase detector has a sinusoidal function, i.e. that:

( ( ) ( )) sin( ( ) ( ))i o d i oPD t t K t tθ θ θ θ− = − (7)

dK is called the phase detector gain. For example for the multiplier phase detector we have from (2) that

/ 2dK AB= .

B. The loop filter The loop filters for the vast majority of PLLs are

extremely simple (see Sec. III.G and [7 Sec. 2.4]). We thus limit ourselves to discussing the following loop filters.

1) Constant gain The simplest loop filter is simply a constant gain, as follows:

( ) aF s K= (8) 2) Lag filter

The lag filter is a simple lowpass filter:

1

1( )1aF s K

sτ=

+ (9)

3) Lag-lead filter The lag-lead filter is:

2

1

1( )1a

sF s Ksττ

+=

+ (10)

4) Integrator-lead filter The integrator-lead filter is:

2

1

1( ) asF s K

sττ+

= (11)

C. Nonlinear PLL equations Using these filter functions, we can arrive at nonlinear differential equations for each of the filter cases. Let us define for convenience the loop gain as d a VK K K K . We then can use eq. (6), along with the equivalence of the Laplace variable to the derivative operator in the time domain (that is, ( ) /s L d dt= • ) to arrive at [6 Sec. 3.5]:

• For ( ) aF s K= :

sin( )oi o

d Kdtθ θ θ= − (12)

• For 1

1( )1aF s K

sτ=

+:

( )2

1 02 sino oi

d d Kdt dtθ θτ θ θ+ = − (13)

• For 2

1

1( )1a

sF s Ksττ

+=

+:

( )

( )

2

1 02

2 0

sin

cos

o oi

i oi

d d Kdt dt

d dKdt dt

θ θτ θ θ

θ θτ θ θ

+ = −

+ − −

(14)

• For 2

1

1( ) asF s K

sτ

τ+

= :

Phase Detector LoopFilter

VCO

( )i tθ

( )o tθ1( )u t

2 ( )u t

Fig. 8 – General equivalent baseband model of the PLL in the phase domain.

( )i tθ

( )o tθ1( )u t

2 ( )u t

( ( ) ( ))i oPD t tθ θ−

( )2

( )( )o

V

d tK u t

dtθ

= ⋅

Fig. 9 – Nonlinear equivalent baseband model of the PLL.

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( )

( )

2

1 02

2 0

sin

cos

oi

i oi

d Kdt

d dKdt dt

θτ θ θ

θ θτ θ θ

= −

+ − −

(15)

The filters are easy to implement in analog form (see [7 Chap. 2]). However, we shall not discuss the analog implementation of the loop filters because we are interested implementing them digitally.

D. Linearized PLL model Eqs. (12) to (15) are nonlinear differential equations

which are very difficult to solve theoretically (although it should be noted that they are very easy to simulate). Thus, for theoretical analysis, what we can do is to assume that the PLL is locked and that the phase error is small enough so that we can approximate sin( ( ) ( )) ( ) ( )i o i ot t t tθ θ θ θ− ≈ − . A general block diagram of the linearized PLL model is shown in Fig. 10.

There is an important conclusion from the assumption of small ( )e tθ (where ( ) ( ) ( )e i ot t tθ θ θ− ) that led to the linear model. We can deduce that the linear model is valid for small ( )e tθ for any phase detector for which

0( ( )) ( )ee d ePD t K tθθ θ→→ . In fact, all phase detectors

which have good performance will have

0( ( )) ( )ee d ePD t K tθθ θ→→ . Thus, we can conclude that

the linear model is valid for all phase detectors, provided that ( ) 0e tθ → . The only thing we need to find out in order to

model a particular phase detector is to ascertain its dK . Using the small signal assumption 0e i oθ θ θ= − → we

can simplify (12)-(15) to the following linear differential equations (using cos( ) cos(0) 1i oθ θ− → = and

sin( )i o i oθ θ θ θ− → − ):

• For ( ) aF s K= :

oo i

d K Kdtθ θ θ+ = (16)

• For 1

1( )1aF s K

sτ=

+:

2

1 2o o

o id d K Kdt dtθ θτ θ θ+ + = (17)

• For 2

1

1( )1a

sF s Ksττ

+=

+:

2

1 2 22 (1 )o o io i

d d dK K K Kdt dt dtθ θ θτ τ θ τ θ+ + + = + (18)

• For 2

1

1( ) asF s K

sττ+

= :

2

1 2 22o o i

o id d dK K K Kdt dt dtθ θ θτ τ θ τ θ+ + = + (19)

E. Solutions of the linearized PLL equations Once we are given ( )i tθ we can solve the linear

differential equations (16)-(19) in the time domain (see for example [7 Chap. 4], [6 Chap. 5]). However perhaps a more informative approach is to solve the equations in the Laplace domain. We exemplify this for a PLL using the lag-lead filter

2

1

1( )1a

sF s Ksττ

+=

+. The open loop function is:

( )( ) ( ) ( ) d Vd

K F s KG s K F s V ss

= = (20)

The closed loop system function of the system in Fig. 11 is:

( )( ) ( )

2

1

2

1

2

2 1 1

2 21 2

1 1

1( ) 1( )( ) 1( ) 1 ( ) 1

1

1 ( )11 1 ( )

Vd a

o

Vid a

d a V

d a V

KsK Ks s sG sH s Kss G s K K

s sKK s

K K K s P sK Ks s K K K s Q ss s

τθ τ

τθττ

τ τ τττ τ

τ τ

++

= = =++ ++

++

= =++ + + + +

(21)

This corresponds to the transfer function of a second order system, whose denominator is often written in the form of:

2 2( ) 2 n nQ s s sζω ω= + + (22)where ζ is known as the damping ratio and nω is known as the natural (radian) frequency. ζ and nω have been extensively studied in control literature, and their effects on the temporal and frequency response characteristics of control loops have been thoroughly documented. The reader is directed for example to [7], [8], [9],and [10] for more details. Comparing (21) and (22), we find that:

1/n Kω τ= (23)and using (21), (22) and (23):

222

21 1

2 21

1 1 12 2

1 1 12 2

nn

n n

n

KK

KK K

ωτζ ω ττ τ ω ω

ω τ ττ

= + = +

= + = +

(24)

and by plugging (23) and (24) into (21) we get:

iθ

oθ( )F s ( ) vKV s

s=eθ

Fig. 10 – General block diagram of linearized PLL model.

+- Kd

iθ

oθ

eθLoop Filter VCO

2

1

1( )1a

sF s Ksττ

+=

+ ( ) vKV ss

=

Fig. 11 – Linearized PLL model using the lag-lead filter.

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2

2 2

2( )

2

nn n

n n

sKH s

s s

ωζ ω ω

ζω ω

− + =

+ + (25)

As is customary, we assume a high-gain loop, as defined by:

nK ω>> (26)There is no true loss of generality incurred by making this assumption, as virtually all PLLs (indeed, all control loops) are intentionally designed to have a high loop gain. This is because a high loop gain makes the loop bandwidth and damping factor relatively insensitive to variations in the gains dK , aK , and VK (see [8 Chap. 14]). After making the assumption of (26), eq. (25) can be reduced to:

2

2 2

2( )2

n n

n n

sH ss s

ζω ωζω ω

+=

+ + (27)

which is a transfer function form that has been analyzed extensively in the PLL and control systems literature (e.g. [7], [8], [12], [10]).

Table 1 lists several key PLL characteristics as a function of the loop filter. We want to be able to set ζ and nω independently, and at the same time ensure a high loop gain, that is nK ω>> . The only filters that allow us to do this are

2

1

1( )1a

sF s Ksττ

+=

+ and 2

1

1( ) asF s K

sτ

τ+

= . There is an

advantage in using 2

1

1( )1a

sF s Ksττ

+=

+ when implemented

digitally because it has a bounded dynamic range (whereas,

the integrator in the denominator of 2

1

1( ) asF s K

sττ+

=

could potentially cause overflow problems in the digital loop filter under certain conditions). We thus choose

2

1

1( )1a

sF s Ksττ

+=

+ for the remainder of this paper.

F. The phase error response We can easily arrive at the transfer function that

determines relates the phase-error ( )e sθ to the input phase:

( ) ( ) ( ) ( )( ) 1 1 ( )( ) ( ) ( )

e i o oe

i i i

s s s sH s H ss s s

θ θ θ θθ θ θ

−= − = − (28)

For our choice of filter 2

1

1( )1a

sF s Ksττ

+=

+ we have

2

2 2( )2

nK

en n

sH ss s

ω

ζω ω

>>

≈+ +

(29)

G. 3rd-order and higher order loops Sometimes, for very specialized applications, a 3rd-order

or higher order PLL is necessary. This is generally necessary to be able to accurately track phase signals which include frequency accelerations or higher-order frequency changes. The problem with higher-order loops is that there is always the threat of them being unstable depending upon the loop gain. This can be easily seen in the Root-Locus plot (see [7

Sec. 2.5]). In contrast, 2nd-order PLLs are unconditionally stable. Therefore higher-order loops should be avoided if possible. This is why the vast majority of PLLs in digital communications are 2nd-order [7 Sec. 2.4].

IV. CHOICE OF PARAMETERS FOR THE ANALOG PLL

A. Choosing ζ The choice of ζ is determined by our desire to achieve

the fastest PLL response but with minimal overshoot. Moreover, we would like ζ to be optimal in terms of noise performance. To aid us in our choice we can look at [7 Table 7.2], [7 Chap. 2], and [13 Chap. 2]. We choose 0.95ζ = because:

It is a good compromise between the optimal values for

several optimization criteria (see [7 Table 7.2]) The response is underdamped (i.e. fast response), but

not too much (i.e. not too much overshoot) (see [7 Chap. 2] and [13 Chap. 2])

We get a phase margin of about 075 , which doesn’t increase much if we increase ζ further (see [13 Fig. 2.4-3])

B. Finding the optimal natural radian frequency Before going on to choose nω (or , equivalently, the

natural frequency / 2n nf ω π ) let’s characterize the PLL a little more. For a given PLL, some fundamental questions are: What is the frequency offset for which we are guaranteed that the PLL will lock within a given time? (Answer: the Lock Range Lω∆ , and it will lock within LT seconds, the lock-in time); What is the largest frequency step that the PLL can handle without losing lock? (Answer: the Pull-out Range POω∆ ); What is the maximum frequency range where we are guaranteed that the PLL will lock eventually? (Answer: the Pull-in Range Pω∆ ); What is the maximum frequency range within which the PLL can maintain lock if the input frequency is changed very slowly? (Answer: the Hold Range Hω∆ ). In Table 2 we see PLL

Table 1 – PLL Characteristics for 1st and 2nd-order PLLs (from [11 App. A], [10 Chap. 2])

( )F s nω ζ ( )H s

aK K --------- Ks K+

1

11aK

sτ+

1

Kτ

1

12 Kτ

2

2 22n

n ns sωζω ω+ +

2

1

11a

sKsττ

++

1

Kτ

21

1 12

KK

ττ +

2

2 2

2

2

nn n

n n

sK

s s

ωζ ω ω

ζω ω

− +

+ +

2

1

1a

sKsτ

τ+

1

Kτ

2

12Kττ

2

2 2

22

n n

n n

ss s

ζω ωζω ω

++ +

- 7 -

parameters for the second order PLL. For more information see [10 Chap. 2]).

Where should the PLL be operating? The pull-in process is too unreliable and too long for us to count on during normal operation. Therefore, we must design our PLL so that it operates in the lock range

Lω∆ (note that the PLL will lock within LT seconds within the range

Lω±∆ ). This, in turn, influences our choice of nω and may affect the stability requirements upon the transmission carrier.

Additional considerations in choosing nω emanate from the desire to achieve minimal phase-error jitter

2 2( )e i oθ θ θ= − . For detailed treatment of such optimizations, see for example [14] (especially [14 Chap. 10]) as well as [6 Chap. 8]. Here, we only briefly present the main aspects of the optimization procedure. Essentially, we want our output carrier to follow the input carrier exactly. Therefore, we want our PLL to pass the input carrier phase noise ⇒ this means we want large nω . Conversely, we want our output carrier to suppress the contribution of thermal-induced phase noise ⇒ this means we want small

nω . These two constraints are contradictory. We therefore must optimize, i.e. find the best nω that will pass as much input carrier phase noise as possible but at the same time suppress as much thermal-induced phase noise as possible. It can be easily shown that this is optimization of nω in order

to minimize 2 2( )e i oθ θ θ= − . Formally, suppose that the

input carrier phase noise has a spectrum ( )Pi

fθΦ and that

the thermal-induced phase noise has a spectrum ( )Ti

fθΦ . It

can be shown that the phase-error variance will be [11 App. A]:

2 22

0 0

( ) ( 2 ) ( ) 1 ( 2 )Ti Pie f H j f df f H j f dfθ θθ π π

∞ ∞

= Φ + Φ −∫ ∫ (30)

The optimization according to minimal phase jitter (=minimum 2

eθ ) is to design the PLL so that (30) is minimized.

C. Other optimality criteria Minimum phase jitter is not the only optimization criterion

of the loop. The loop can be optimized for something else (e.g. to maximize the sweep rate, minimize the pull-in time, etc.) However, the minimum-jitter criterion is the most important and most widely used criterion in wireless communications. It is easy to see why: phase-jitter has a direct effect upon the error rate (see for example Fig. 6 and [3 Fig 2.9]).

V. A STEP-BY-STEP PLL DESIGN PROCEDURE We are now ready to present a step-by-step PLL design

procedure. Assumed given are the input carrier phase noise characteristics and the input SNR (Signal to Noise Ratio) denoted as iSNR (see [15 Chap. 6] or the workshop notes [1] for a detailed treatment and definition of iSNR ). Clearly,

the PLL must operate at various iSNR , so we should design

the PLL for the worst-case value (i.e., the lowest iSNR ). The procedure is shown in Fig. 12. It is quite

straightforward. The most difficult step is determination of the optimal nω , since this involves taking into account the carrier phase noise characteristics as well as computing the effects of thermal noise (see [14 Chap. 10], [6 Chap. 8]).

A. Design of PLLs for digital modulations Although Fig. 12 was developed with no specific

modulation in mind, it is entirely applicable to any modulation type. The only modulation-dependant things are (a) the phase detector and its gain dK , and (b) the squaring loss (which influences the noise calculations and hence the choice of nω , see for example [14 Chap. 10], [7 Sec. 11.2]). Both dK and the squaring loss are easy to calculate: dK is calculated from the slope of the phase detector S-Curve at

0eθ = (can be done via simple open-loop simulations), while the squaring loss is calculated either theoretically or via simple open-loop simulations (see for example [16],[17],[18], [2 Chap. 5, 6]).

VI. HYBRID IMPLEMENTATION OF THE PLL A. Preliminary assumptions In this paper we are dealing with a fixed-point hardware

implementation of the hybrid receiver in Fig. 1. We shall assume that the system has a high data rate (for example above 1 MHz) for, as discussed in the introduction, it is for such high data rates that the hybrid receivers become particularly attractive. For the purposes of this discussion it is sufficient to broadly characterize the phase detector sample rate. A phase detector in digital communications usually produces a new phase estimate for every symbol, and thus the phase detector output sample rate is assumed to be the same order of magnitude as the symbol rate. Thus, if we denote the phase detector output sample rate as 1/p pf T= ,

then we have that 1/ 1/pT T∼ , where 1/T is the symbol

rate and “~” denotes equal orders of magnitude. Again, since we are dealing with high datarate communications systems, this rate is in the order of at least several MHz.

Carriers that are used in coherent communications, generally have phase noise whose content can be assumed non negligible up to a distance from the carrier of 1 KHz to

Table 2 – PLL Parameters for second-order PLL with loop filter

2

1

1( )1a

sF s Ksττ

+=

+ (see [10 Chap. 2], [7 Chap. 4]).

Parameter Meaning Value Lω∆ Lock Range 2L nω ζω∆ ≈

LT Lock-in time 2 / 1/L n nT fπ ω≈ =

POω∆ Pull-out range 1.8 ( 1)PO nω ω ζ∆ ≈ +

Pω∆ Pull-in range 4 2P n d VK Kω ζω π∆ ≈

Hω∆ Hold Range H Kω∆ ≈

- 8 -

at most several KHz; for example, a common specification for a frequency source used for coherent digital communications is that its phase noise have a spectral density of about 70 /dBc Hz− at a 1 KHz distance from the carrier. Such a specification can be found for example in the DVB-S2 standard (the European home satellite dish broadcasting standard), where the specification is

68 /dBc Hz− at a 1 KHz (see [19]). For coherent communications nf is in general the same order of magnitude as the bandwidth of the significant phase-noise content of the received carrier. While this bandwidth is thus specific to the particular carrier and operating conditions of the particular receiver, we can safely say that the order of magnitude for nf is at most several KHz . An important conclusion can now be inferred. We can safely say that:

p nf f>> (31)The relation expressed in (31) will turn out to be of pivotal importance. In fact, it is the relation in (31) that differentiates the analysis of the system discussed in this paper with that of just any arbitrary hybrid control loop.

B. The Direct Digital Synthesizer (DDS) In the hybrid implementation of the PLL, the loop filter is

implemented digitally, and the VCO is implemented though the use of a Direct Digital Synthesizer. A Direct Digital Synthesizer (DDS) is an Integrated Circuit (IC) that accepts a digital control word (heretofore referred to as the tuning word) at its input, and outputs a continuous-time sinusoidal

waveform whose frequency corresponds to that tuning word. The DDS consists of a Numerically Controlled Oscillator (NCO) that is the input to a Digital to Analog Converter (DAC), which is followed by smoothing filter that rejects the image frequencies that appear at the DAC output ([11 App. A], [20]). It is stressed that the frequency waveform produced by the DDS is phase continuous, regardless of the frequencies through which its output transitions. This is a fundamental requirement if the DDS is to be used in a PLL.

The linearized equivalent PLL model for Fig. 1 is shown in Fig. 13. An example of a DDS is the AD9851 chip manufactured by Analog Devices, discussed in [20].

The advantages of using a Direct Digital Synthesizer instead of a VCO include:

1. The frequency of the DDS can be controlled

precisely by the tuning word, typically to a precision of a fraction of a Hertz.

2. The phase noise and frequency drift of the DDS is primarily determined by its clock source, which can be a fixed-frequency crystal oscillator that can have excellent characteristics at very inexpensive prices.

3. Parasitic analog effects, which often plague VCO circuits, are eliminated when a DDS is used. This includes for example the sensitivity of the VCO to its power supply; often, the sensitivity of the VCO to the power supply causes frequency modulation of the VCO output due to power supply fluctuations, thus severely hampering the VCO’s operation.

As seen in Fig. 14, the tuning word controls the output frequency by determining by how much the phase of the output wave will increase each rising edge of the reference clock. Denoting this clock rate as 1/D Df T= , the number of bits in the phase accumulator register as N and the tuning word as Dw , we have that the DDS’s output frequency is:

12 2

D Dw DN N

D

w wf fT

= = (32)

Of course, (32) is only valid so long as the Nyquist criterion is observed, namely that there are at least two samples of each period of the output sinusoid, so that the DAC can reconstruct the waveform without aliasing. This means that (32) is valid so long as:

2 2D D

w DN

w ff f= < (33)

Decide upon (usually 0.8 1.3)

ζ

ζ≤ ≤

We choose 0.95ζ =

2

1

We choose1 ( )1a

sF s Ksττ

+=

+

2

1

1 22

Compute loop filterpoles and zeros.

1For F(s)= we have1

2 1 and

a

n n

sKs

KK

ττ

ζτ τω ω

++

= = −

Compute loop filter gain , making sure it is large enough so that the loop gain and that steady-state errorsare small enough

a

d a V n

K

K K K K ω=

nC ho o se acco rd in g to perfo rm an cerequ irem en ts

ω

Fig. 12 – Step-by-Step PLL design procedure for analog PLLs.

+-

Kd

iθ

oθ

eθ ( )B z Direct DigitalSynthesizer

LoopFilter

Phase Detector Data Rate = 1/ pT

Fig. 13 – Hybrid PLL equivalent linearized baseband model.

- 9 -

which will only occur if 12NDw −< . Thus

the maximum value of the control word that can theoretically produce a unaliased sinusoid will be 12 1N

Dw −= − , and that waveform will have a frequency

of 12 1

2 2

NN D

w DN

ff f−

→∞−= ⋅ → .

However, this limit cannot be achieved nor approached in practice because the post-DAC filter needed to separate the fundamental frequency from its first image (which is at D wf f− , see [20]) will be unrealizable. A more practical limit which allows for a realizable output filter is ,max 0.4w Df f≈ . VII. MATHEMATICAL MODELING

OF THE DDS From Fig. 14 it emerges that the DDS

outputs a given frequency for a given tuning word at its input. Assume that the control word of the DDS is updated at a rate of 1/u uf T= Hz. uf is much slower than the reference clock of the DDS Df , because several samples of the NCO must by traversed between updates of the control word, if those updates are to be expressed at the DDS output. This is further merited because of the time it takes to physically program the new control word into the DDS (i.e. send the right control pulses and data values to the appropriate pins of the DDS chip). Thus we may write:

u Df f<< (34) The operation of the DDS within a

PLL is illustrated in Fig. 15. The mathematical model of the DDS is shown in Fig. 16. To see why this model is valid, all that needs be done is to compare the behavior of the system shown in Fig. 16 with Fig. 15 (right), and realize that that behavior is identical.

It is emphasized and reiterated that neither the DAC nor the VCO in Fig. 16 are in fact present in the DDS; they are purely virtual mathematical constructs. Consequently, we may define the parameters of the DAC and VCO as we please, so long as the input and output behavior of the model in Fig. 16 behaves identically to that of the DDS.

With that constraint on the model’s behavior, let us now characterize the DAC and VCO that appear there. Dealing first with the DAC, as the DDS is updated at a rate of uf , that is the conversion rate of the equivalent DAC in Fig. 16. Furthermore, since the DDS output frequency remains constant so long as the tuning word is not changed, this corresponds to the DAC in Fig. 16 being of the ZOH (Zero Order Hold) type [9 Chap. 11]. We shall further decide that

the DAC has unit gain, i.e. its output (which has the dimensions of Volts) is simply Dw Volts when it has the

tuning word Dw at its input. Recalling once more that the

DAC is updated every uT seconds, we have that the Laplace transfer function of the ZOH is:

( )2

( ) ( ) ( ) ( )sinh / 21

/ 2

uu

ZOH ZOH usTsT

uu

u

H s L h t L u t u t TsTe T e

s sT

− −

= = − −

−= =

(35)

The DAC receives a digital signal as its input and outputs a continuous time signal, and hence strictly speaking its response cannot be represented in the Laplace domain. To get around this difficulty, the DAC may be modeled by a system with a transfer function of (35) that is preceded by a module which converts the DAC’s input sequence into a train of impulses in the continuous time domain. Denoting

Fig. 14 – Explanation of DDS Operation.

- 10 -

the DAC’s input sequence as ( )nυ and the input to the ZOH

as ( )tη , we have the relationship ( ) ( ) ( )un

t n t nTη υ δ∞

=−∞

= −∑ .

Turning our attention to the DDS model’s virtual VCO, two parameters are of interest to us: its center frequency and its tuning sensitivity. The center frequency is in fact unimportant for the equivalent linearized baseband PLL analysis. All that is needed for PLL analysis is to characterize the VCO’s tuning sensitivity VK , whose units are 1 1Radians Sec Volt− −⋅ ⋅ . The output phase of the VCO is:

0 0

( ) 2 ( ) 2 ( )2

t tD

out w DN

ft f d w dθ π τ τ π τ τ= =∫ ∫ (36)

Taking the Laplace transform of both sides of (36), we have: ( )( ) 2

2D D

out N

f w sss

θ π= ⋅ (37)

Remembering that we have set the DAC in Fig. 16 to have unit gain, we have that the voltage at the input of the VCO is

( ) ( )D DV t w t= and consequently ( ) ( )D DV s w s= . Plugging the last equality into (37) and dividing both sides by ( )DV s , we have that the transfer function of the VCO is:

2( ) 2( )( )

DN

outv

D

fsH s

V s s

πθ= = (38)

Thus, comparing (38) to the transfer function form of a VCO, which is /VK s , we have by inspection:

Radians2 2 Sec×Volt

DV N

fK π= (39)

Equations (35) and (39) now allow us to express Fig. 16 in terms of the Laplace transform. This is done in Fig. 17. Analysis of the hybrid PLL is now facilitated by inserting the model of Fig. 17 into Fig. 13 which in turn results in the model shown in Fig. 18.

There is an outstanding issue that must be resolved in Fig. 18: the sampling rates at the input and output of ( )B z are

pf and uf , respectively, and these are not necessarily equal.

In order to establish a relationship between pf and uf ,

recall that p nf f . Thus, we make the assumption that:

p u nf f f≥ >> (40)The difference in magnitudes expressed in (40) can be

quite dramatic. Consider for example a 100 MHz symbol rate data system, i.e. 61/ 100 10 HzpT = ⋅ . A typical value

for nf is 2000 Hznf = . A typical value for the DDS update rate in this case, as we shall see in the subsequent sections, would be for example 61/ 2 10 HzuT = ⋅ . Given the sometimes substantial disparity between pf and uf , one

would strive to achieve two goals. First, we want to find the minimum value of uf that would allow the PLL to function appropriately. Secondly, we want to implement the digital loop filter for the much smaller sampling rate of uf rather

Fig. 15 – Illustration of DDS operation vs. operation of an analog VCO.

/ 2i if ω π is the input signal’s frequency; of is the analog VCO

output frequency; wf is the DDS’s output frequency. Shown are: Left:

operation of analog PLL with VCO (PLL is in perfect lock); Right: operation of hybrid PLL with DDS (PLL is in perfect lock). Note that the granularity of the frequency steps is exaggerated in order to demonstrate the effects of the update rate on the DDS output frequency.

DAC VCO

DDS Equivalent Mathematical Model

Dig

ital T

unin

gW

ord

wD

Out

put

Freq

uenc

y f w

Fig. 16 – Equivalent mathematical model of a DDS.

Dig

ital T

unin

gW

ord

wD

Out

put

Freq

uenc

y f w

122

DN

fs

π ⋅

ZOH VCO

Digital-Sequence toImpulse Train Converter

rate = 1/Tu

DAC

( )sinh / 2exp( / 2)

/ 2u

u uu

sTT sT

sT− ⋅

Fig. 17 – Laplace Domain model of the DDS.

+-

iθ

oθ

eθ ( )sinh / 2exp( / 2)

/ 2u

u uu

sTT sT

sT− ⋅ 12

2DN

fs

π ⋅

ZOH VCO

Phase Detector Data Rate = 1/ pT

( )B z

LoopFilter

Kd

DDS Equivalent ModelDigital Sequence to

Impulse TrainConverterrate = 1/Tu

Fig. 18 – Hybrid PLL model with DDS equivalent model inserted.

+-

iθ

oθ

eθ

Digital Sequence toImpulse Train Converter

rate = 1/TuZOHVCO

Phase Detector Data Rate = 1/ pT

( )B z

LoopFilter

Kd M↓

Decimator

DecimationFilter

DAC

DDS Equivalent Model

( )2sinh / 2

/ 2

usTu

uu

sTT e

sT

−

⋅

Mπ−

Mπ

122

DN

fs

π ⋅

Fig. 19 – Hybrid PLL model with decimation.

- 11 -

than at rate pf . Having established the goal of implementing

( )B z at a sampling rate of uf , it is clear that the sampling rate of the data at the input of ( )B z needs to be reduced through use of decimation, i.e. by filtering by a decimation filter and then using a decimator. This is shown in Fig. 19. The decimation ratio in Fig. 19 is:

/ /u p p uM T T f f= = (41)An implicit assumption in the development of the model

of Fig. 19 is that the spectral content of ( )d e pK nTθ is fully

contained in the discrete-time frequency interval of [ ]/ , /M Mπ πΩ∈ − , or, equivalently, that ( )d eK tθ is

fully contained in the continuous domain in the interval

, ,2 2 2 2

p p u uf f f fM Mπ π

π π − ⋅ ⋅ = −

, where the last equality

was facilitated by (41). This always holds. To see why, let’s define max max[ , ]f f f∈ − as the frequency bandwidth of

( )d eK tθ . It is easily seen (even intuitively) that we will

have max nf f∼ , say for example max 2 nf f= . But from (40)

we have p u nf f f≥ >> so we also have maxp uf f f≥ >> .

VIII. CALCULATION OF THE DIGITAL LOOP FILTER The models obtained in previous sections allow us to now

to compute ( )B z that so that a desired closed loop transfer function for the PLL is achieved. In this section, we shall assume that the virtual DAC (which is part of the DDS equivalent model), the decimation filter, and the decimator are all ideal (in later sections, we derive the conditions that ensure that these assumptions are appropriate). Under those conditions, the succession sampling at rate pf -decimation

filter-decimator by M is equivalent to sampling the signal ( )d eK tθ at a rate of uf . Thus, under the assumptions of this

section, we may simplify Fig. 19 to Fig. 20. A. How do we determine B(z)? If one compares Fig. 20 to Fig. 11 it is seen by inspection

that the blocks amalgamated and denoted collectively as ˆ ( )F s in Fig. 20 correspond to the loop filter ( )F s that

appears in Fig. 11. Since all other loop components are equal in both figures, if we can design a filter ( )B z so that ˆ ( ) ( )F s F s= this will imply that the closed loop transfer

function of both figures will be identical. Consequently, it can immediate be seen from the structure of ˆ ( )F s that ( )B z may be deduced from ( )F s by using the bilinear transformation method [21 Sec. 7.1]. We now proceed to find ( )B z using that method.

The filter 2

1

1( )1a

sF s Ksττ

+=

+ has a pole at 11 /s τ= − and

a zero at 21 /s τ= − . To use the bilinear transformation, we must first pre-warp[21 Sec. 7.1] these two frequency points:

1 1

1 1 tan u

u

TT

πτ π τ

=

and

2 2

1 1 tan u

u

TT

πτ π τ

=

(42)

and then construct the pre-warped transfer function of the analog filter:

2

1

1( )1a

sD s Ksττ

+=

+ (43)

Now we can employ the bilinear transformation [21 Sec. 7.1] in order to determine ( )B z as follows:

1

21

1

11

12 22

11 1 1

11

2 11

2 111

( ) ( )2 11

1

2 22 1 1 11

2 2 21 1 1 1

ua

u

u uua

u u u

u

zs T z

zT z

B z D s Kz

T z

zT TT

Kz

T T T

τ

τ

τ ττ

τ τ τ

−

−

−

−

−

−

−

−−=+

−+ + = = −+ +

+ − ++ = ⋅ + + − +

(44)

Now let us define:

2 21

2 21 1u uT Tτ τβ

= − +

1 11

2 21 1u uT Tτ τα

= − +

(45)

and:

2 12 21 1au u

KT Tτ τγ

= + +

(46)

then ( )B z may be expressed as: 1

11

1

1( )1

zB zz

βγα

−

−

+= ⋅ +

(47)

The transition to direct-form II implementation is immediate [21 Chap. 6] and is shown in Fig. 21.

IX. EFFECTS OF NON-IDEAL VIRTUAL DAC AND COMPUTATION OF REQUIRED DDS UPDATE RATE The derivations of the previous section assumed that the

(virtual) DAC converter (which is part of the DDS mathematical model (Fig. 16)) could be considered ideal. However, that DAC is not ideal, and in fact it was shown that it is a DAC of the ZOH type (Fig. 17). As shall be shortly seen, this observation has a profound impact on the

+-

iθ

oθ

eθVCO

Sample Rate uf

( )B z

LoopFilter

KdIdealDAC

122

DN

fs

π ⋅

ˆ ( )F sSample Rate uf

Fig. 20 – Hybrid PLL model, assuming ideal virtual DAC, ideal decimation filter, and ideal decimator.

- 12 -

PLL’s performance and serves to constrain the rate uf above a certain minimum, which will be calculated.

Modifying Fig. 20 to account for the DAC’s non-ideality, while still assuming that the decimation process is perfect, results in the system depicted in Fig. 22.

A. Influence of virtual DAC nonideality on the phase margin of the PLL

While amplitude interference from aliases passed by the non-ideal virtual DAC will cause a degradation in performance, it will not in general lead to PLL instability (see [1]). In contrast, as we shall now see, the effect upon the phase response of the signals in the PLL is much more important and will lead to a higher necessary minimum uf .

We analyze the effect upon the phase response by considering the effect on the phase margin of the PLL. If the DAC were ideal, we would have that ˆ ( ) ( )F s F s= (see Fig. 20 and Fig. 11), and then the open loop transfer function of the hybrid PLL would be ( ) ( ) /d VG s K F s K s= .

We now assume that the aliases contribute negligibly to the signal at the output of the DAC (see [1] for justification). Furthermore, we assume that the ZOH magnitude distortion of the primary reconstructed signal is negligible (this is true due to maxuf f>> ; see Sec. VII and [1]). Under these assumptions, we can reduce Fig. 22 to the circuit of Fig. 23. A quick comparison of Fig. 23, Fig. 20, and Fig. 11, shows that in this case the open loop transfer function will be:

2 2ˆ ˆ( ) ( ) / ( ) / ( )u usT sT

d V d VG s K F s K s K e F s K s e G s− −

= = = (48)

The phase margin of a PLL is defined as the number of degrees above –180 that the phase of the open loop response possesses when its magnitude is unity [13 Chap. 2]. As a formula, this means that for the systems of Fig. 20 and Fig. 11, if Cf , which we call the crossover frequency, is the frequency in which ( 2 ) 1CG j fπ = , then the phase margin

for those systems is: ( ) ( 2 ) ( 180) DegreesCPM G G j fπ= − − (49)

where ( 2 )CG j fπ is in degrees. If we now turn our attention to the system of Fig. 23, we have from (48) that:

ˆ ( 2 ) ( 2 ) ( 2 ) 1C uj f TC C CG j f e G j f G j fππ π π−= = = (50)

that is, the crossover frequency remains unchanged. Evaluating the phase margin of ˆ ( )G s , we have:

( )( )

ˆ ˆ ( 2 ) ( 180)

( 2 ) ( 180)

( 2 ) ( 180) exp( )( ) 180 Degrees

C u

C

j f TC

C C u

C u

PM G G j f

e G j f

G j f j f TPM G f T

π

π

π

π π

−

= − −

= − −

= − − + −= − ⋅

(51)

We see that the effect of the phase shift is a decrease in the phase margin by 180 C uf T⋅ degrees. A decrease in the phase margin in an extremely undesirable occurrence, as it may cause an underdamped response of the loop and could

lead to instability of the PLL (see [13 Chap. 2]). Thus we must find a condition on uf so that that decrease is tolerable. If we are willing to tolerate a decrease in the phase margin of

Ad degrees, we see from (51) that this means that

180 C u Af T d⋅ < (52)or:

180u C

A

f fd

> ⋅ (53)

It can be shown that for a loop filter in the form of 2

1

1( )1a

sF s Ksττ

+=

+ we have [13 Sec. 2.4]:

2C nf fζ≈ (54)Thus from (53) and (54) we have:

180 2u nA

f fd

ζ> ⋅ (55)

Exact linear-system theory analysis of models which include terms of the type exp( )sτ− is impossible due to the non-polynomial nature of this term and the infinite number of root-locus branches which such terms generate [8 Sec.

Z-1

1β1α−

γ

x(n) y(n)

Fig. 21 – Direct-form II implementation of B(z).

+-

iθ

oθ

eθ

VCO

Sample Rate uf

( )B z

Loop Filter

Kd

122

DN

fs

π ⋅

ˆ ( )F s

ZOH

Digital-Sequence toImpulse Train Converter

rate = 1/Tu

DAC

( )2sinh / 2

/ 2

usTu

uu

sTT e

sT

−

⋅

Fig. 22 – Hybrid PLL model, assuming ideal decimation but non-ideal DAC.

+-

iθ

oθ

eθ

VCO

Sample Rate uf

( )B zLoop Filter

Kd

ˆ ( )F s

exp( / 2)usT−

DAC

IdealDAC

122

DN

fs

π ⋅

Fig. 23 – Hybrid PLL model, assuming DAC incurs only phase distortion of the fundamental reconstructed signal.

- 13 -

7.12]. Instead, we compute the effects on the phase margin

(PM) and, then, (if we assume 2

1

1( )1a

sF s Ksττ

+=

+) using the

relationship 0.01 PMζ ≈ ⋅ (see [13 Fig. 2.4-3]) we can define an effective ζ , denoted as effζ , which is defined as

0.01eff PMζ ⋅ . We can then think of the PLL with time

delay as a second-order system with damping factor effζ .

Acceptable values of ζ are 0.7 1.5ζ≤ ≤ , where for carrier synchronization PLLs recommended values are generally 0.8 1.3ζ≤ ≤ (see [7 Chap. 7]). So we can’t play with ζ in (55) but only with uf . If we wish to limit the degradation in the phase margin to 010Ad = w.r.t. the analog implementation, then, for 0.95ζ = , using (55) this means

that we need to have 180 2 0.95 34.210u n nf f f> ⋅ ⋅ = . If we wish

to limit the degradation to 03Ad = then, for 0.95ζ = , using (55) this means that we need to have

180 2 0.95 1143u n nf f f> ⋅ ⋅ = . Once uf is determined, the

phase margin is computed and for subsequent analysis the system is considered to be a second-order system with natural frequency nf and a damping factor of

0.01eff PMζ = ⋅ .

In Fig. 24 we see bode-diagram example of how the phase margin of the PLL is affected by the delay term exp( / 2)usT− . As we can see there, as expected the crossover frequency remains unchanged but the phase-margin is degraded due to the presence of the delay term.

X. IMPLEMENTATION OF THE DECIMATION FILTER We shall now analyze the decimation filter and find a

structure for its efficient implementation in hardware. A filter with impulse response ( )DFh n will relate the output to its input through the well-known convolution relation:

( ) ( ) ( )DFm

y n h m x n m∞

=−∞

= −∑ (56)

If we decimate by M at the output of this filter, that is take only one out of every M output samples, we have:

( ) ( ) ( )DFm

y k h m x Mk m∞

=−∞

= −∑ (57)

The decimation filter ( )DFh n is an FIR filter [22] whose length we shall denote as L, and thus (57) can be reduced to:

1

0( ) ( ) ( )

L

D Fm

y k h m x M k m−

=

= −∑ (58)

The direct-form realization of (58) is shown in Fig. 25. Regrettably, this direct-form implementation, while easy

to visualize and analyze, often requires too many resources for it to be implemented in fixed-point hardware. To see this, note that there are L multipliers that need to operate at rate

pf . Furthermore, the addition that produces the input to the

decimator by M also needs to operate at the high sample rate, which becomes increasingly difficult to implement for a large L. Some improvements can be attained by using alternate filter topologies such as in [22 Fig. 6.28], and [22 Fig. 6.31]; however, even with these manipulations, the logic resources requirements are often still excessive.

To make efficient hardware implementation possible, consider the unit-gain rectangular window filter, that is:

1 0 n L-1( )

0 otherwiseDFh n L

≤ ≤=

(59)

which has the transfer function of (using the summation formula 1

011

N nn

Nααα−

=−−=∑ [23 eq. 19.4]):

( )1

0

2 2 2

2 2 2

12

( ) ( )

1 1 11

22

s in21

s in ( / 2 )

j j nD F

nj LL

jj

nL L Lj j j

j j j

Lj

n

H e h n e

eeL L e

e e e jje e e

L

eL

∞Ω − Ω

= − ∞− Ω−

− Ω− Ω

=Ω Ω Ω− −

Ω Ω Ω− −

−− Ω

=

−= =−

−=−

Ω

= ⋅Ω

∑

∑

(60)

The (one-sided) passband of that filter is [ ]0,2 / Lπ , and

consequently since we are aiming for a passband of [ ]0, / Mπ we choose 2L M= , and (60) is transformed to:

2 12 1 sin( )

2 sin( / 2)

MjjDF

MH e eM

−− ΩΩ Ω

= ⋅Ω

(61)

The response of this filter for 8M = is shown in Fig. 26.

Fig. 24 – Bode diagram comparison of an example open loop function G(s) with and without delay. x(n)

(0)DFh

Z-1

(1)DFh

Z-1

(2)DFh

Z-1

( 1)DFh L−( 2)DFh L−y(k)

M↓

Fig. 25 – Direct-form implementation for ( )DFh n (see [21Chap. 6]).

- 14 -

As can be seen in Fig. 26, there is some distortion in the passband, and the sidelobes can be considered relatively high. However, it can be shown (see the workshop notes [1]) that these effects cause an increase of at most 10.9% (or less than 0.5 dB) in the noise power inside the loop, which for the overwhelming majority of applications is palatable.

We have just shown that the rectangular filter provides acceptable performance when it serves as a decimation filter inside the PLL. We now show that dramatic savings in logic resources can be attained (w.r.t. Fig. 25) if that rectangular filter is implemented wisely. Combining Eq. (58), (59), and since 2L M= , we have:

2 1

0

1( ) ( )2

M

my k x Mk m

M

−

=

= −∑ (62)

Now let’s separate (62) into even and odd samples: 2 1

0

2 1

0

1 (2 ) k=2r2

( )1 (2 ) k=2r-1

2

M

m

M

m

x Mr mM

y kx Mr M m

M

−

=

−

=

−= − −

∑

∑ (63)

An illustration of (63) is given in Fig. 27, which immediately suggests the simple implementation shown in Fig. 28.

Note that the Integrate and Dump (IAD) modules in Fig. 28 require no multiplications at all (their precise structure will be shown shortly). The division by 2M shown in that figure is sill prohibitive to compute in hardware; however if 2M is chosen to be a power of 2, i.e. 2 2PM = , then the division by 2M can be approximated by a block that simply discards the lower ( )2log 2M P= bits, which is a trivial

operation to perform in hardware (for example, for 2 8M = we have 32 2M = and so the division would be approximated by discarding the lower 3 bits).

A simplified diagram of the implementation of the integrate and dump module is shown in Fig. 29. Note that in that figure the division by 2M is done within the IAD module (in order to reduce the number of bits required for the output register). Also, the output rate is 1/(2 )uT , not

1/ uT ; this is because the IAD will be used in conjunction with a second IAD module (as in Fig. 28), which will produce an output sample at a rate of 1/(2 )uT Hz halfway between each pair of samples of the first IAD module, and hence the total output rate for ( )y k will be 1/ uT , as required. The “control logic” cloud tells the IAD module when to “integrate” and when to “dump” its result to the output register, and thus must work in tandem with the adjacent IAD module in order to produce the desired result at the output of the decimation filter in Fig. 28. Hence it is advantageous to implement the structure of Fig. 28 as a single module. The “control logic” cloud is essentially little more than a carefully controlled counter that controls the timing of signals within the IAD modules, as shown in Fig. 28. This control logic is straightforward to implement in hardware.

In conclusion, we see that we can implement a nearly ideal decimation filter with only two adders (one per IAD), 4

registers (2 per IAD), and some additional (yet quite simple) control logic. This is a huge reduction in logic resources as compared to the implementation of Fig. 25.

XI. EFFECTS OF IMPLEMENTATION LATENCY In Section IX we found that the update rate of the DDS

has a measurable impact on the phase margin of the PLL.

Fig. 26 – Amplitude response ( )j

DFH e Ω for M=8 (2M=16).

Fig. 27 – Explanation of decimation by M using a rectangular window filter. Shown is operation for M=4 (2M=8).

x(n) y(k)

Integrate and Dump2M samples, start

integrations at times:n=2rM-(2M-1)

Integrate and Dump2M samples, start

integrations at times:n=(2r-1)M-(2M-1)

Switch: Selectupper branch for

k=2r-1,lower branch for

k=2r

Divideby 2M

Divideby 2M

Fig. 28 - Efficient hardware implementation of the decimation filter (the “Staggered Integrate and Dump” implementation).

Reg1D Q

Clear

Reg2D Q

Clock Rate 1/Tp

Input at rate 1/Tp

Clock Rate 1/(2Tu)

DiscardLower

log2(2M)bits

Output at rate 1/(2Tu)

ControlLogic

B bits B bitsB+log2(2M)bits

B+log2(2M)bits

B bitsB+log2(2M) bits

Fig. 29 – Implementation of the Integrate and Dump module.

- 15 -

This is in fact a special case of a more general phenomenon, which is the effect of a delay element within a control loop on the latter’s phase margin. Assume we have designed the decimation filter as per (61). We can incorporate this filter into the model of Fig. 19 as shown in Fig. 30.

The effects of the decimation filter magnitude response on the loop are negligible (see Sec. X and [1]), and thus we shall assume for the ensuing analysis that the decimation filter magnitude response is ideal, i.e. that has an ideal LPF magnitude response in the interval [ ]/ , /M Mπ π− .

Regarding the delay introduced by the decimation filter,

which takes the form of 2 1

2Mj

e−

− Ω, we shall shortly see that it

must be taken into account when the PLL is designed. It is advantageous for the purposes of analysis to transform this delay into the continuous (= Laplace) domain. A delay of

2 12

Mje

−− Ω

in the discrete-time Fourier domain means a delay of 0.5(2 1)M − samples, which, taken at a rate of

1/p pf T= , corresponds to a delay of 0.5(2 1) pM T− seconds.

Such a delay has the Laplace transfer function representation

of 2 1exp2 p

Ms T− −

. Transforming the delay into the

Laplace domain and ignoring any magnitude effects of the decimation filter, we have the equivalent representation of the PLL of Fig. 31.

We shall also insert into the open loop transfer function a pure delay exp( )IsT− , which will model any additional implementation latencies totaling IT seconds (such as the delays associated with data path pipelining, latencies incurred in the various digital chips, PCB trace length latencies, etc.). The revised model is shown in Fig. 32 (where ˆ ( )G s is defined in Sec. IX).

The impact of the delay elements in Fig. 32 is best analyzed as it is ascribed to the decrease in the phase margin that it incurs. We see that, taking into account the delays in Fig. 32, the open loop transfer function is:

2 1 ˆ( ) exp ( )2I p

MG s s T T G s − = − + (64)

Using precisely the same set of derivations as was used to derive (51) from (48), we find that:

2 1ˆ( ) ( ) 180 22C I p

MPM G PM G f T T− = − ⋅ +

(65)

where it is emphasized that, due to the fact that ˆ( 2 ) ( 2 ) ( 2 )G j f G j f G j fπ π π= = (see (48) and (64)) we

have that the crossover frequency Cf is identical for all

three transfer functions ( )G s , ˆ ( )G s , and ( )G s , and is approximated by 2C nf fζ≈ (see (54)).

Define for convenience the total implementation delay as: 2 1

2d I pMT T T− +

(66)

In the same manner as was done in the derivations (52) to

(55), it is easy to show that if we wish to bound latency’s impact on the phase margin by Ld degrees, we must have:

2 12 180 2 720

L Ld I p

C n

d dMT T Tf fζ

− = + < ≈ ⋅ ⋅ (67)

For insight into the meaning of (67), it is instructive to construct a table of the maximum allowable dT as a function of nf , assuming a maximum allowed phase margin degradation of 010Ld = and 0 .95ζ = . This is shown in Table 3. As seen there, the constraint on the phase margin is clearly a limiting factor on what loops can be implemented, and this phase margin degradation must be taken into account when designing the loop. From Table 3 it is also clear that with a hardware implementation one can strive (using current technology) to implement loops with nf up to an order of several tens of KHz, while for a software implementation current technology limits the implementation to nf of at most several KHz. Thus we observe the more general conclusion that a hardware implementation will

+-

iθ

oθ

eθ

Digital Sequence toImpulse Train Converter

rate = 1/TuZOH

VCO

Phase Detector Data Rate = 1/ pT

( )B z

LoopFilter

Kd M↓

Decimator

DAC

DDS Equivalent Model

Decimation Filter ( )jDFH e Ω

1 sin2 sin( / 2)

MM

Ω⋅

Ω2 1

2Mj

e−

− Ω

( )2sinh / 2

/ 2

usTu

uu

sTT e

sT

−

⋅122

DN

fs

π ⋅

Fig. 30 - Hybrid PLL model with decimation filter response.

+-

iθ

oθ

eθ

VCO

Sample Rate uf

( )B z

LoopFilter

Kd

122

DN

fs

π ⋅

ˆ ( )F s

ZOH

Digital-Sequence toImpulse Train Converter

rate = 1/Tu

DAC

2 12 p

Ms Te−

−( )2

sinh /2/2

usTu

uu

sTT e

sT

−

⋅

Fig. 31 – Hybrid PLL model with decimation filter latency converted to Laplace domain. Magnitude effects of the decimation filter are ignored.

+-

iθ

oθ

eθ ˆ( )G sexp( )IsT−2 1exp2 p

Ms T− −

Fig. 32 – Hybrid PLL model with implementation delay added.

- 16 -

always have the advantage of being able to implement PLLs which have higher natural frequencies; this is equivalent to saying that a hardware implementation will be able to cope with a noisier carrier (i.e. one with a wider phase-noise bandwidth).

Another quantity that affects the phase margin is the DDS update rate uf , as detailed in (51). The value of dT is has a strong connection to 1/u uT f= . To see this, consider that

/p uM f f= , and putting that into (66) yields:

2 / 12 2 2

p u p p pd I p I p I u

u

f f f T TT T T T T T T

f−

+ = + − = + −

(68)

Furthermore, IT is also a strong function of uf (but not

necessarily exclusively determined from uf ). Justification

for this is as follows: recall that IT represents the additional implementation delays. Consider for example a logic path

that is part of the data path to the DDS, and which contains two registers that are clocked by the post-decimation clock of rate uf as detailed in Fig. 34. Each such stage will add a delay of uT to the open loop transfer function. Additional delays which are not of this type may be present too and are also included in IT .

Hence it is clear that in order to bound the total degradation in the phase margin which is caused both by the DDS and the system delay, it is necessary to first find uf that satisfies (55), and

then, using this value of uf , compute or estimate

IT and dT and check if (67) is satisfied. If not,

then either uf must be increased, Ld increased,

or, if at all possible, nf decreased. It is generally unwise to meddle with the value of ζ (see Sec. IX).

XII. STEP-BY-STEP PROCEDURE FOR DESIGNING A HYBRID PLL

We are now in a position to outline a step-by-step procedure for designing a hybrid PLL. The procedure is shown in Fig. 33.

A. Comments on the design procedure The series of steps outlined in Fig. 33 can be

easily performed by a computer program, e.g. using Matlab or C code. In fact, the values obtained by such a computer program may be directly incorporated into the design of the ASIC or FPGA that is used to implement the digital section. The author has indeed carried out such an algorithm to automatically generate values that were then used in the FPGA implementation of hybrid systems, and has found it to be quite an effective and accurate design methodology.

Moreover, due to the tight link between dT and uT (see Sec. XI), very often the system’s architecture will make it possible to deduce a formula linking dT and uT , which will enable Ld to be determined from Ad or vice versa. For example, if we have /u dT T α= then it can be easily seen that if (55) is satisfied then setting 2L Ad dα= ⋅ will ensure that (67) is satisfied. Hence, if a relation between dT and uT can be found, then the first two steps in Fig. 33 can be united, where Ld would be determined from Ad in order to ensure a total phase margin degradation of A Ld d+ . Table 3 – Maximum allowed implementation latency as a function of

nf , for 010Ld = and 0.95ζ =

nf Maximum Allowed dT 1MHz 14.6 nanoseconds 100 KHz 146 nanoseconds 10 KHz 1.46 microseconds 1 KHz 14.6 microseconds 100 Hz 146 microseconds

Decide on allowed phase-margin degradation due to

the DDS, dA

From Analog PLL Design Procedure

Forexample

dA=3o

This algorithm finds the maximum which is a power of 2 such that

180 > 2

and2 1

2 720

pu n

A

Ld I p

n

M

ff f

M d

dMT T Tf

ζ

ζ

= ⋅

− = + < ⋅

M=2

M=M/2

No

fu=fp/M

M=2M

Decide on allowed phase-margin degradation due tothe digital logic latency, dL

Forexample

dL=7o

Yes

1 1 2 2

Prewarp:

1 1 1 1tan and tanu u

u u

T TT T

π πτ π τ τ π τ

= =

Implement the loopfilter and the

decimation filterusing the

hardware-efficientstructures that

were presented

180Check if > 2

and2 1

2 720

pn

A

Ld I p

n

ff

M d

dMT T Tf

ζ

ζ

⋅

− = + < ⋅

11

11

1 11

2 21

2 1

Design the loop filter as:

1( ) 1

with

2 21 1

2 21 1

2 21 1

u u

u u

au u

zB zz

T T

T T

KT T

βγα

τ τα

τ τβ

τ τγ

−

−

+= ⋅ +

= − +

= − +

= + +

Fig. 33 – Flow chart of procedure for design of hybrid PLL.

Clock Rate fu

LogicFrom Loop Filter Towards DDS

Reg1D Q

Reg2D Q

Fig. 34 – How a pipeline stage in the datapath from the loop filter to the DDS inserts a delay of Tu into the open loop transfer function.

- 17 -

B. Digital implementation inside FPGA or ASIC Finally, we now have enough information to allow us to

draw a schematic of the implementation of the digital logic inside the FPGA or ASIC. This is shown in Fig. 35. The widths of the internal busses are given in Fig. 35; while simply an example, they are typical choices as they emanate from a variety of system parameters, such as number of sampler bits, the number of bits needed for a DDS tuning word, as well as the general desire to minimize logic resources by minimizing the width of the datapath in the chip. To that end, notice that the only part of the chip that has a datapath width greater than 8 bits is from the output of the loop filter to the DDS.

The decimation filter and the loop filter are implemented as per Fig. 28 and Fig. 21, respectively. In order to actually implement the loop filter, its implementation specific parameters (such as coefficient quantization and the datapath widths inside the filter, etc.) need be determined. These topics are beyond the scope of this paper (see for example [21 Secs. 6.7-6.10]), but it shall be commented here that in the author’s experience an excellent implementation of the loop filter (in terms of quantization noise) can be achieved when the coefficients are quantized to 16 bits (1 sign bit + 15 data bits). Finally, some explanation may be in order regarding the addition of the value CENw to the output of the loop filter before the result is passed to the DDS. This is due to the fact that the PLL provides the correction to the DDS that is needed in order to maintain lock. The tuning word

CENw is the tuning word that corresponds the center frequency of the DDS (= the center frequency of the VCO in the DDS equivalent model).

XIII. CONCLUSIONS This paper has developed and presented techniques for the design and implementation of hybrid PLLs. The paper began with a discussion of “classical” analog PLL design. Then, a mathematical model that described the hybrid architecture was developed and analyzed. It was found that the update rate of the DDS and the total allowed implementation latency were crucial parameters concerning the PLL’s stability. Implementation of the decimation filter in fixed-point hardware was discussed, and it was found that an exceedingly efficient implementation exists. Design of the

loop filter in fixed-point hardware was also addressed. We then proceeded to outline a step-by-step procedure for the design and implementation of a hybrid system. Further analysis and derivations can be found in [1], which may be obtained by contacting the author.

REFERENCES [1] Y. Linn, "Synchronization and Receiver Structures in Digital

Wireless Communications (workshop notes)," in Seminario Internacional 15 Años. Bucaramanga, Colombia, Aug. 15-19, 2006.

[2] H. Meyr, M. Moeneclaey, and S. Fechtel, Digital communication receivers: synchronization, channel estimation, and signal processing. NY: Wiley, 1998.

[3] U. Mengali and A. N. D'Andrea, Synchronization techniques for digital receivers. NY: Plenum Press, 1997.

[4] F. M. Gardner, "Interpolation in digital modems. I. Fundamentals," IEEE Trans. Commun., vol. 41, no. 3, pp. 501-507, Mar. 1993.

[5] L. Erup, F. M. Gardner, and R. A. Harris, "Interpolation in digital modems. II. Implementation and performance," IEEE Trans. Commun., vol. 41, no. 6, pp. 998-1008, Jun. 1993.

[6] A. Blanchard, Phase-locked loops. Application to coherent receiver design. NY: Wiley, 1976.

[7] F. M. Gardner, Phaselock techniques, 2nd ed. NY: Wiley, 1979.

[8] J. J. D'Azzo and C. H. Houpis, Linear control system analysis and design : conventional and modern, 3rd ed. NY: McGraw-Hill, 1988.

[9] R. C. Dorf, Modern control systems, 5th ed. MA: Addison-Wesley, 1989.

[10] R. E. Best, Phase-locked loops: theory, design, and applications, 2nd ed. NY: McGraw-Hill, 1993.

[11] R. L. Peterson, R. E. Ziemer, and D. E. Borth, Introduction to spread-spectrum communications. NJ: Prentice Hall, 1995.

[12] R. C. Dorf, Modern control systems, 4th ed. MA: Addison-Wesley, 1986.

[13] H. Meyr and G. Ascheid, Synchronization in digital communications. NY: Wiley, 1990.

[14] W. P. Robins, Phase noise in signal sources. (Theory and applications). London: Peter Peregrinus, 1982.

[15] D. H. Wolaver, Phase-locked loop circuit design. NJ: Prentice Hall, 1991.

[16] B. T. Kopp and W. P. Osborne, "Phase jitter in MPSK carrier tracking loops: analytical, simulation and laboratory results," IEEE Trans. Commun., vol. 45, no. 11, pp. 1385-1388, Nov. 1997.

[17] W. P. Osborne and B. T. Kopp, "An analysis of carrier phase jitter in an M-PSK receiver utilizing MAP estimation," in Proc. MILCOM '93, Boston, MA, USA, 1993, pp. 465-470.

[18] W. P. Osborne and B. T. Kopp, "Synchronization in M-PSK modems," in Proc. ICC '92, Chicago, IL, USA, 1992, pp. 1436-1440.

[19] ETSI (European Telecommunications Standards Institute), "DVB-S2 Technical Report ETSI TR 102 376 V1.1.1," 2005.

[20] Analog Devices, "AD9851 Datasheet, Rev. C," retrieved from www.analog.com.

[21] A. V. Oppenheim and R. W. Schafer, Discrete-time signal processing. NJ: Prentice Hall, 1989.

[22] R. E. Crochiere and L. R. Rabiner, Multirate digital signal processing. NJ: Prentice-Hall, 1983.

[23] M. R. Spiegel, Mathematical handbook of formulas and tables. NY: McGraw-Hill, 1968.

Ie(n)

Qe(n)

8

8

Decimation Filter anddecimation by M,

Staggered Integrate-and- Dump

implementation

B(z)DDS

ProgrammingState Machine

To DDS

8

8 32

wCEN

32

32

PhaseDetector

Matched filtering anddecimation to 1 sample/

symbol, where the outputsamples are the “even”

samples (i.e on the peak ofsymbols (timing is achieved

using the symbol PLL))

8

8

I(nTs)

Q(nTs)

Loop Filter

Fig. 35 – Schematic of the contents of the FPGA or ASIC used to implement the digital section of the carrier PLL.