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1980 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 8, AUGUST 2011

Design and Implementation of Fully IntegratedDigitally Controlled Current-Mode Buck Converter

Man Pun Chan, Student Member, IEEE, and Philip K. T. Mok, Senior Member, IEEE

Abstract—Digital current-mode control is a dual-loop controlwhich potentially results in a better transient response and thusis more favorable than voltage-mode control. There are only a fewpublications on how to design and implement a fully integrated dig-ital controller as the on-chip implementation is very challenging,especially for current-mode control. This paper addresses those de-sign challenges and considerations. One of the main challenges isto efficiently sample and quantize both the output voltage and in-ductor current of the buck converter for control purposes. A time-multiplex scheme is used for the control-loop which enables theconverter to work with a single ADC. A modified delay-lock-loopDPWM has been developed for minimizing the mismatch of thedelay-cells. This enhances the accuracy at high frequency to pre-vent limit-cycle. A new algorithm has also been proposed for im-plementing look-up-table digital compensators with 20% less chiparea. A converter with the fully integrated digitally controlled loop,including the single ADC, digital compensators and DPWM, hasbeen fabricated in a CMOS 0.35 m process with a chip area of1049 m 1533 m. Measurement results show that the buck con-verter has a load transient response of 20 s, which is one of thefastest compared to other state-of-the-art digitally controlled buckconverter.

Index Terms—Analog-digital conversion, buck converter, cur-rent-mode, digitally controlled, integrated circuit.

I. INTRODUCTION

B UCK converters are commonly used as efficient voltageregulators in most miniature portable consumer elec-

tronics like mobile phones, PDAs, and multimedia players.There is an increasing trend to use digital controllers overanalog ones to control the buck converter in those applications.Because of the ever-decreasing sizes of those devices, it isvery desirable to integrate the buck converter controllers withthe digital system that is being regulated [1]–[3]. The digitalcontrollers make this possible and easier. A typical productdevelopment cycle for consumer electronics devices is aboutsix months shorter than the IC suppliers’ cycle to deliverthe underlying circuitry for these products [4]. Therefore,the reprogrammability of the digital controllers can shortenthe development time by programming the digital controllersaccording to the specification for different products. The digital

Manuscript received July 14, 2010; revised December 20, 2010; accepted Jan-uary 18, 2011. Date of publication March 10, 2011; date of current version July27, 2011. This work was supported by the Research Grant Council of HongKong SAR Government, China, under project No. 617308. This paper was rec-ommended by Associate Editor E. Alarcon.

The authors are with the Department of Electronic and Computer Engi-neering, Hong Kong University of Science and Technology, Kowloon, HongKong (e-mail:[email protected]; e-mail:[email protected]).

Digital Object Identifier 10.1109/TCSI.2011.2112531

Fig. 1. Generic architecture of a digitally controlled current-mode buck con-verter.

controllers are also favorable because they are capable ofoperating at an ultralow quiescent power [5], [6].

Several digital current-mode controllers (DCMCs) for buckconverters have been successfully demonstrated in recent re-search. In [7], a FPGA-based peak-current-mode digital con-troller is demonstrated to control a nonisolated point-of-load(POL) converter with 20 A loading current. Similarly, [8] showsa FPGA-based average-current-mode digital controller for con-trolling a 10 A synchronous buck converter. These two DCMCsare designed for high-current applications with off-chip powerMOSFETs. In contrast, another paper [9] aims to demonstratea peak-current-mode digital controller for a 500 mA low-powerbuck converter used in battery-powered products.

The digitally controlled current-mode buck converter ismore favorable for portable consumer electronics if it is highlyintegrated as shown in Fig. 1. For example, the buck con-verter, including DCMC and power MOSFETs, should befully integrated into a single silicon chip. However, all theaforementioned papers only verify their digitally controlledcurrent-mode converters design through FPGAs/CPLD imple-mentation. There are different design considerations betweenFPGAs and fully IC implementations. Therefore, this paperaddresses the challenges and design considerations of imple-menting a fully integrated digitally controlled current-modebuck converter.

One of the main challenges to implementing the converter inFig. 1 is that two ADCs are required for quantizing the outputvoltage and the inductor current . Compared to the digitalvoltage-mode control, the extra ADC requires more chip areaand power to operate. The two-ADC architecture for DCMCs isoften used, as cited in [7], [8], [10]. Alternatively, other papers

1549-8328/$26.00 © 2011 IEEE

CHAN AND MOK: DESIGN AND IMPLEMENTATION OF FULLY INTEGRATED DIGITALLY CONTROLLED CURRENT-MODE BUCK CONVERTER 1981

[9], [11] have used a different approach to obtain the inductorcurrent information, but that still required one ADC and oneDAC. Based on this observation, it would be interesting to in-vestigate how to use only one ADC in the DCMC for quantizingboth the output voltage and the inductor current.

Another design challenge is to design a timing scheme suchthat the single ADC knows when to sample and quantize theoutput voltage and the inductor current. The timing scheme alsoneeds to make sure that the digitized signals can be sent to boththe current-loop and the voltage-loop compensators with theleast amount of delay to ensure the stability of the convertershown in Fig. 1.

Motivated by the above discussions, a fully integrated digi-tally controlled current-mode buck converter with a single time-multiplex (TM) ADC is proposed. The proposed converter usesa time-multiplex scheme (TMS) to demonstrate how the DCMCcontrols the buck converter by using a single TM-ADC for quan-tizing both the output voltage and the inductor current. A low-power and small chip area TM-ADC is designed for the TMSand integration purposes. This not only saves one ADC staticpower but also requires less chip area.

Since the proposed converter is designed with fully integratedcircuits, several design issues, which will not concerned theimplementation of FPGAs, will be addressed throughout thispaper. For example, the IC implementation of DPWM is verydifferent from that of the FPGAs. The former requires a fullcustom IC design while the latter requires the coding of delay-cells and time-constraints. The design consideration of thosetwo digital compensators shown in Fig. 1 is also different be-tween integrated circuits and FPGAs. The former focuses onreducing chip area while the latter focuses on reducing the gatecount. As a result, it is necessary to design area-efficient digitalcompensators in IC implementation.

The organization of this paper is as follows. Section II de-scribes the overall system architecture of the proposed converterand how the TMS works with the whole system and a singleTM-ADC. Design details of the TM-ADC will also be presentedin this section. In Section III, the design of the DPWM willbe discussed. Then, the design of voltage-loop and current-loopdigital compensators will be shown in Section IV. Experimentalresults of the proposed converter are shown in Section V. Fi-nally, conclusions are made in Section VI.

II. OVERALL SYSTEM ARCHITECTURE WITH TIME-MULTIPLEX

SCHEME AND TM-ADC

The proposed digitally controlled current-mode buck con-verter is shown in Fig. 2. There is one TM-ADC instead of twoADCs in the conventional approach as shown in Fig. 1. Theproposed buck converter is controlled by the DCMC, which in-cludes the DPWM, voltage-loop and current-loop digital com-pensators (DCs), TM-ADC, and 500 mA power MOSFETs. Theconverter requires no external component except for the LCfilter. The memory cells, which are used by the DCs with alook-up-table approach, are also integrated on chip.

A. Design of Time-Multiplex Scheme

The time-multiplex scheme (TMS) for the DCMC is depictedin Fig. 3. This scheme allows the DCMC to regulate the buck

Fig. 2. Block diagram of the digitally controlled current-mode buck converterwith a single TM-ADC.

converter by using a single TM-ADC to quantize both theoutput voltage and the inductor current through an on-chipcurrent sensor. To understand how the scheme works, considerstarting from the time at , the rising edge of triggersthe output voltage quantization ) and the(error difference between the reference voltage and the outputvoltage) is available after some conversion time . This

is then fed to the voltage-loop compensator forcalculating the current-command at the rising edgeof . At the same time, the falling edge of triggersthe inductor current quantization and the inductorcurrent information is available after some conver-sion time . Before the rising edge of at time , both

and are available for calculating the dutyratio . Lastly, the is obtained from the current-loopcompensator and the DPWM drives the power MOSFETswith the pulse width according to the . By using half of theswitching period for the voltage quantization and the other halffor current quantization, a single ADC is shown to be possiblefor current-mode control.

It is very important to note that has to be done be-fore because the must be available togetherwith for calculating the . Otherwise, the compen-sator will be idle and wait for to be calculatedfrom the by the compensator . This increases thecontrol-loop delay by one switching period and thus affects thestability of the converter.

Another design consideration of the TMS is to determinewhat kind of inductor current information is needed to be sam-pled for the current-mode control. For the current-mode controlused in this paper, only the magnitude of the change of the in-ductor current is needed to calculate the duty ratio [8].

Fig. 4 shows the sampling instant at an arbitrary point be-fore the current quantization. As long as the sampling instant forevery period is unchanged, the magnitude change of the inductorcurrent can be obtained. Therefore, the sampling instant can be


Fig. 3. Time-multiplex scheme for the DCMC.

Fig. 4. Timing diagram of the inductor current sampling.

set at any time before the current quantization . Inthis design, in order to simplify the sampling control, the samplepoint is taken at the beginning of each period as shown by thesignal in Fig. 4. Both the inductor current and the outputvoltage are sampled at the rising edge of . However, the timewhen they are quantized is different. The output voltage quanti-zation begins right after the output voltage is sampled while theinductor current quantization begins at the falling edge ofas explained before with Fig. 3.

The inductor current information is sensed by an on-chip cur-rent sensor used in [12], which is a high-side inductor currentsensor. In other words, only the input current through the p-typepower MOSFET is sensed. The sensed inductor current is thenheld by the sample-and-hold (S/H) circuit discussed in [13] untilit is quantized at the falling edge of the signal.

B. Design of TM-ADC

In order to ensure the TMS works properly, it is crucial thatthe single TM-ADC can quantize both the output voltage andthe inductor current within a switching period. In FPGA imple-mentation, the required ADCs may be built-in with the FPGAboard or external to it. Therefore, little or no function modifi-cation can be made to achieve time multiplexing. In contrast,

Fig. 5. Schematic of 4-bit time-multiplex ADC with an on-demand clock.

the TM-ADC, which is based on the successive approximation(SA) ADC reported in [14], can be fully custom-made to fit thisspecific application.

1) Operating Principle of TM-ADC: The schematic of the4-bit TM-ADC with an on-demand clock is depicted in Fig. 5.Although the TM-ADC is based on the same principle of suc-cessive approximation to do the analog-to-digital conversion, itsimplementation is different from [14], [15]. Some modificationshave been made for the design of the controller in this paper.One is that two set of reference voltages are needed for two dif-ferent phases of quantization. One (vhigh, vlow) is for outputvoltage quantization and the other (ihigh, ilow) is for inductorcurrent quantization. In this case, the successive approximationregister (SAR) needs to switch the references according to theTMS mentioned in Fig. 3. Since the upper and lowerbound reference voltages are used, the TM-ADC is ac-tually a “window” ADC [16], which means the ADC is onlylinear within the “window.” This kind of “window” ADC pro-vides a fine resolution while maintaining low power consump-tion.

Because of the bipolar supply used in [14], [15], [17], thoseSA-ADCs can obtain the digital code by comparing the sam-pled voltage to the virtual ground. However, bipolar supply isoften unavailable in portable consumer electronics, which usebatteries as the only source of power. This leads to another mod-ification of those SA-ADCs. The TM-ADC shown in Fig. 5 isimplemented using a single supply only. The generation of thedigital code is then done by comparing a predefined DC voltageat the node as shown in Fig. 5. To have a better under-standing of how the TM-ADC works with the predefined DCvoltage used at and the “window” imposed, Fig. 6(a)shows the simplified version of a 4-bit time-multiplex ADC atthe beginning of the voltage quantization phase.

The following describes how to generate the MSB of thesampled output voltage of the buck converter. When theTM-ADC samples the output voltage (i.e.,voltage of the buck converter), the switch is closed andthe voltage across all capacitors is given by

(1)


Fig. 6. Simplified version of 4-bit time-multiplex ADC: (a) at the beginningof the voltage quantization phase and (b) at the first comparison for generatingMSB.

Then, when the switch is opened, the lower plates ofall capacitors will connect to the reference and the voltage

is given by

(2)

Sub (1) into (2)

(3)

At this stage, the TM-ADC will undergo a first-comparisonbetween and in order to generate the MSB code ofthe sampled voltage. This is done by connecting the largest ca-pacitor (8C) to as shown in Fig. 6(b). The new voltagewill be given as

(4)

(5)

Lastly, if the output of the comparator is logic 1,which is the MSB code of the sampled voltage, this impliesis smaller than , i.e.,

(6)

(7)

(8)

Similarly, if is logic 0,

(9)

(10)

As we can see from (7), the actually cancels out.Therefore, the behavior of the TM-ADC will not be affected aslong as the is within the input range of the comparator(CMP) as shown in Fig. 5. The TM-ADC will continue toswitch the capacitors for comparison and generate the corre-sponding digital code of the sampled buck converter outputvoltage. The detailed operating principles of a generic SA ADCcan be found in [17].

The window ( and ) of the TM-ADC in thevoltage quantization phase defines the quantization leveland the output voltage of the buck converter. This is shown inthe following:

(11)

(12)

For example, if mV and V are required,then we have V and V.

The above discussion and derivation are for the voltage quan-tization phase while the operation of the current quantizationphase is the same as the voltage quantization. The difference isthat the and are used as references in the currentquantization. The current quantization level is determined bythe same (11) as the voltage quantization. In particular, the upperwindow could be designed for the maximum voltage gen-erated by the on-chip current sensor when the inductor currentis maximum (e.g., maximum loading current).

However, if one wants to fix a different current quantizationlevel , this can be done by designing the sensing scalingfactor of the on-chip current sensor to have the desired max-imum voltage under the maximum loading current. Thevalue is constrained by the flipped voltage follower buffer. Inthis case, the hardware-reuse makes the TM-ADC possible forquantizing both the voltage and the current.

2) On-Demand Clock and Its Synchronization: In order tostart and carry out each step in the successive approximation,the SAR requires an extra clock. However, the frequency ofthis extra clock signal needs to be synchronized with the buckconverter switching frequency. The synchronization here doesnot refer to the absolute frequency synchronization betweenthe extra clock frequency and the buck converter switchingfrequency. It means that the extra clock should provide theTM-ADC with a “working-clock” right after the rising/fallingedge of the signal as shown in Fig. 3. In this case, theTM-ADC can always start the first step of the successiveapproximation after the rising/falling edge of the signal.

The synchronization problem is resolved by incorporating anon-demand clock. The SAR actively enables the on-demandclock ( in Fig. 3) for successive approximation after therising/falling edge of the signal. After finishing either theoutput voltage or the inductor current quantization, the SARturns it off to save power as the clock is unnecessary when thesuccessive approximation has finished. In fact, the turning off ofthe extra clock is also necessary to reset the on-demand clock.

The timing diagram is shown in the enlarged part of Fig. 3.The and are the clock signal from the on-demandclock and the enabling pin of the on-demand clock, respectively.


Consider the period of , at the rising edge of the ,the SAR pulls up the pin and enables the on-demandclock. Then, it feeds a clock signal to the SAR. Once the clock isavailable, the SAR starts and carries out the successive approxi-mation, the steps of which are triggered by the falling edge of the

signal. Lastly, the e[n] is generated according to the outputvoltage. After the successive approximation is completed, theSAR pulls down the vosc en pin and disables the on-demandclock. This is also the purpose of resetting the clock. A sim-ilar procedure is repeated for the but the on-demandclock enabling time is at the falling edge of the .

The requirements of the accuracy of the frequency of theon-demand clock are not stringent. In theory, a 4-bit TM-ADCrequires five clock-cycles to complete either the voltage orcurrent phase of the analog-to-digital conversion. In practice,the TM-ADC requires five clock-cycles plus one reset cycleas illustrated in the enlarged part of Fig. 3. In other words, aslong as the on-demand clock feeds a 12 times or higher clockfrequency to the SAR, it should be sufficient. Therefore, theon-demand clock is implemented by a simple chain-inverter.Since the chain-inverter is an all-digital circuit, it consumeslittle power. For having enough design margins, the on-demandclock frequency is 21 times higher than the 3 MHz switchingfrequency of the buck converter. From the simulation results,the 63 MHz chain-inverter consumes 1.72 A/MHz at 3 Vsupply with the 0.35 m CMOS process. Although higherfrequency of the on-demand clock can be used, this requires afaster comparator for the TM-ADC. A faster comparator willinevitably increase the power consumption.

The TM-ADC operates at the frequency of 3 MHz, which isthe switching frequency of the buck converter, while the on-de-mand clock operates at 63 MHz. The total current consump-tion of the TM-ADC in this case is 33 A which is about 33

A/3 MHz A/MHz. The chip area of the TM-ADCis about 0.428 mm in the 0.35 m CMOS process. Table Ishows the comparison between the TM-ADC and the self-strobedelay-line (SS-DL) ADC [16] used in typical low-power digitalcontroller IC. From Table I, the TM-ADC has an advantage oflow current consumption (11 A/MHz). Although the chip areaof TM-ADC is larger, it can be justified that the technology usedin TM-ADC has a longer channel length. Improvement can bemade if a more advanced process is used.

The slower conversion time of TM-ADC can also be im-proved by using higher on-demand clock frequency fed to theSAR. Because the on-demand clock is the simple chain-inverter,a higher frequency can be easily obtained. However, a 100 nsconversion time is sufficient for the converter operating up to3 MHz. Given the same switching frequency of the buck con-verter, faster conversion time in TM-ADC is unnecessary andwill not help in reducing the control loop delay. This is be-cause the TM-ADC will idle anyway and wait for the next rising/falling edge of the signal for subsequent output voltage/in-ductor current quantization.

3) Flipped Voltage Follower Buffer for the TM-ADC: An-other design consideration of the TM-ADC is that a buffer isneeded to drive its input from the S/H circuit, which does nothave a large capacitive load driving capability. From Fig. 2,the signal is passed to a flipped voltage follower (FVF)

TABLE ICOMPARISON OF THE TM-ADC AND THE SS-DL ADC

Fig. 7. Schematic of the FVF.

[18], [19] before feeding the inductor current information to theTM-ADC. Fig. 7 shows the schematic of the FVF and there aretwo identical branches. The left branch acts as a bufferand connects to the input of the TM-ADC. However, thevoltage of the sensed inductor current will have a constant DCshift (approximately equals to the source-gate voltage of the

) after passing through the FVF. In other words, there isstill constant DC output voltage shift even when the buffer inputvoltage is zero. Therefore, the right branch is used toobtain the DC shift by connecting its gate to theground. Then, the is fed to the TM-ADC as a lowerbound of the inductor current quantization.

C. Design of On-Chip Power MOSFETs

To ensure the high power efficiency of the buck converter, thepower MOSFETs sizing design is important. As a general guide-line, it is assumed that the switch resistances of power MOS-FETs are 1% of the load resistance. Since the power MOSFETsare operating in the linear region for most of the time, we havethe following linear equations for the MOSFETs [20] to estimate


Fig. 8. Dead time circuit.

the switch resistance of the p-type power MOSFETand the n-type power MOSFET

(13)

(14)

where mobility of holes in (m /Vs), ofelectrons in (m /Vs), oxide thickness in (F/m ),

to source voltage in (V), voltageof the PMOS transistor in (V), and voltage ofthe NMOS transistor in (V).

By simulations, both the sizing of the n-type and p-type powerMOSFETs are optimized for a heavy load condition, i.e., 500mA loading current. After optimizing the switching resistanceof the power MOSFETs, a dead time circuit, that to precludeany shoot-through current, is also important for ensuring highpower efficiency. The dead time circuit makes sure that bothn-type and p-type power MOSFETs are not turned on at thesame time, i.e., there is a time that the both MOSFETs are off(dead time). Although some advanced dead time controls [21],[22] are available, a simple SR latch implementation has beenchosen for the controller in this paper as shown in Fig. 8. Thosetwo capacitors Cd are used to adjust the “dead time.”

III. DESIGN OF DIGITAL PULSE WIDTH MODULATOR

The main function of the DPWM is to convert a digital wordto an analog pulse with different pulse widths as shown

in Fig. 9 [23]. Conceptually, the DPWM is achieved by quan-tizing time into a number of discrete time slots of length .Then a particular slot is selected by the digital control inputword . The pulse width from the DPWM is then used todrive the power MOSFETs of the switching converter.

In this section, the on-chip implementation of DPWM will bepresented. First, a commonly used DPWM implementation willbe highlighted. It focuses on low power and chip area efficiency.Then, a modification of the DPWM will be discussed to improvethe conversion accuracy at higher operating frequency.

A. Common Low Power DPWM

Delay-line DPWM is commonly used in low-power digitalPWM controller [5], [6], [16], [24], [25] because of its low

Fig. 9. Architecture of the DPWM.

Fig. 10. Common low power DPWM.

power and small chip area. For example, [16] shows one of the8-bit delay-line DPWM implementations as shown in Fig. 10.This DPWM has the advantage of not requiring an externalclock and can be implemented on less than one-eighth of thearea needed for the conventional ring implementation.

The operating principle of the DPWM is to use two branchesof delay-line to quantize time into a number of discrete timeslots. One branch consists of fast-delay-cells and the other con-sists of slow-delay-cells. The slow-delay-cells quantize the timeinto coarse slots and then each coarse slot is further quantized byfast-delay-cells into a fine slot. Then a particular fine time slot isselected by the digital MUX according to the digital word .

The main disadvantage of this DPWM is that it is difficultto match two different types of delay cells, namely, those thatare fast and those that are slow. That is, for the 8-bit DPWMin [16], the delay time of one fast-delay-cell has to beexactly equal to 1/16 of the delay time of one slow-delay-cell

, i.e., . Matching all 16 fast-delay-cellsto one slow-delay-cell is very difficult to achieve monolithicallyby simply adjusting biasing current because of process variationand the parasitic layout.

B. Modified 8-Bit Delay-Line DPWM

To solve the matching problem in the delay cells, a modifiedarchitecture of the DPWM is developed as shown in Fig. 11.The digital duty ratio is from the current-loop digital com-pensator . Then is split into two halves. One half

is from the MSB to the middle bit of for con-trolling the MUX-A to select the slow-delay-cells. The otherhalf is from the middle bit minus one bit to the LSB


Fig. 11. Modified 8-bit delay-line DPWM.

Fig. 12. Operation of the DLL.

of the d[n] for controlling the MUX-B to select the fast-delay-cells.

For ensuring the requirement of , a delaylock loop (DLL) is added to lock the delay of one “ref-delay-cell” equal to that of 16 fast-delay-cells. The ref-delay-cell isactually the exact replica of one slow-delay-cell. A similar DLLtechnique in DPWM has been reported in [26]. However, as theimplementation of the DPWM is different from that in [26], sois the design of the DLL in this paper.

The operation details of operation of the DLL are summa-rized in Fig. 12. It is a standard DLL operation including phasefrequency detector (PFD) [22], charge pump (CP), and currentsink for correcting the delay time of the 16 fast-delay-cells. Thislocking mechanism will minimize the effect of process varia-tion on the propagation delay. As a result, the newly proposedDPWM can operate at higher frequency without losing its accu-racy.

IV. DESIGN OF DIGITAL COMPENSATORS

As mentioned in the introduction, the digital compensatorscould be implemented by coding the DSP/FPGA/microcon-troller. Their main disadvantages are high power consumptionand high cost. Therefore, it is not suitable for a low powerswitching converter application.

In contrast, the look-up-table (LUT) approach for imple-menting the digital compensators is more suitable for low-powerapplications. The LUT approach also has the advantage of asmall computation delay because it is a one-to-one mappingtable.

Fig. 13. Block diagram of LUT implementation of PID digital compensator.

A. Voltage-Loop Digital Compensator

Fig. 13 shows the look-up-table implementation of the PIDvoltage-loop digital compensator as described in [27]. The PIDcompensator block diagram is drawn according to the equationbelow:

(15)

The designs of the gain constant are well docu-mented in papers [28]–[31]. The corresponds to theduty ratio of the next switching cycle. However, theis actually the next current command signal as shownin Fig. 2. Therefore, can be rewritten as follows:

(15)

After those gain constants have been designed, Table A, B,and store the precalculated values of and

, respectively. Once the error signal is available,the is obtained by summing all the output of thosetables. In general, the lengths of the Table A, B and are equalto the number of all possible values of . For example, ifis a 4-bit signal, the lengths of Table A, B, and will be equalto .

One of the main drawbacks of using LUT is that there aremany storage elements; a large chip area is needed for those ta-bles. Therefore, it is necessary to make the table size as smallas possible. One solution is to reduce the length of those tables,thereby reducing the chip area. This is achieved by constructinga full-set of the table entries from a reduced-set of entries. Inother words, this is done by utilizing the linear combinationproperty of the entries. For instance, Table II lists all the pos-sible values of Table A by letting and the number of bitof .

There are 15 entries [Table II(a)] in the full-set of Table A.In the reduced-set table, the full set of Table A entries can begenerated by using only five entries as shown in Table II(b).The entry “70”, for example, can be calculated from the twoentries “10” and “80.” The rest of the entries can be obtainedin a similar way. The cost of this implementation is that threeextra subtractors are needed as shown in Fig. 14. As a result,although the entries of the tables have been reduced three times,the chip area reduction of the LUT is less than three times. Thefollowing estimates the total memory size before and after thetable entries’ reduction by using the number of bits of .

Before the tables’ reduction,

(16)

(17)


TABLE IIFULL-SET OF TABLE A GENERATION DEMONSTRATION (A) ORIGINAL FULL-SET

OF TABLE A, (B) REDUCED-SET OF TABLE A

Fig. 14. Block diagram of reduced-set LUT implementation of PID digitalcompensator.

Fig. 15. Chip area comparison of the: (a) original full-set of Table A and (b)reduced-set of Table A.

After the tables’ reduction,

(18)

(19)

Fig. 15 shows the layout of Table A, B, and C. The left oneis the full-set of tables while the right one is the reduced-set ta-bles. The memory structures used in the layout for comparisonare D-flip flop while other memory structures can be used toimplement the tables. It can be seen that the actual chip area isreduced from (612.2 m 497.2 m) - (234 m 110 m)= 0.2676 mm to 521 m 404 m mm , which

Fig. 16. Block diagram of the current control law.

is 21.4% reduction in chip area. This shows that the newly pro-posed algorithm can reduce the chip area to implement the LUTdigital compensators.

B. Current-Loop Digital Compensator

The current-loop digital compensator is based on the one-cycle predictive current control as derived in [8]. The currentcontrol law is restated as follows:

(20)

where is a constant, is the current command,is the sensed inductor current and D is the steady-state dutycycle. The steady-state duty cycle D is obtained by using amoving-average low-pass filter on d[n]. In z-domain, the blockdiagram is shown in Fig. 16. There is a parameter in the filterLP(z) to determine its low frequency pole. If the pole is too low,the steady state D takes a long time to settle. If the pole is toohigh, the D is not at steady state. The low frequency pole ofthe filter LP(z) is optimized by Matlab simulation. By choosing

, the hardware implementation of the filter issimply the number of shifts in the register and addi-tion operation [21].

As mentioned before, the current command is actu-ally from the voltage-loop digital compensator as stated in (15).In the z-domain, the compensator can be rewritten as thefollowing:

(21)

The constants and are the same constant as definedbefore in (15). Moreover, according to Fig. 16, the z-domaintransfer function of the current-loop digital compensatoris stated as the following:

(22)

In designing the gain of the whole system, precautions haveto be taken to prevent the limit cycle from happening. Onesuch precaution is to make sure that the gain of the DPWM islarger than that of the output voltage of the ADC [32]. Table IIIsummarizes the parameters used for simulation in the Matlab.Fig. 17 shows the loop gain simulation of the current-modebuck converter. It shows that the bandwidth of the converter isabout 200 kHz with a phase margin of about 73 .

Fig. 18 shows that the inductor current responses to the cur-rent command . The upper waveform is the switching nodebetween the n-type and the p-type power MOSFET. The middlewaveform is the inductor current while the lower waveform is


Fig. 17. Loop gain simulation of the current-mode buck converter.

TABLE IIIPARAMETERS USED IN MATLAB SIMULATION

Fig. 18. Inductor current response to the current command � ��.

the current command . It can be seen that the inductor cur-rent is responding to the current command and the current-loopis operating properly.

V. EXPERIMENTAL RESULTS

The digital current-mode controller of a buck converter is im-plemented with AustriaMicroSystems (AMS) 0.35 m CMOSprocess with a chip area of 1049 m 1533 m. The die photois shown in Fig. 19. It can be seen that the voltage-loop dig-ital compensator occupies a large chip area. The reason is that

Fig. 19. Die photo of the fully integrated digitally controlled current-modebuck converter with the single time-multiplex.

Fig. 20. Measurement setup.

the standard memory cells are not available in the AMS process.The look-up-table is then implemented with D-flip flops. There-fore, the chip area can be further reduced if the memory cells areused. Also, it is noted that a large chip area on the left hand sideof the die is used for testing purpose during the measurement.

A. Steady-State Output Voltage

The steady-state output voltage is obtained with the mea-surement setup shown in Fig. 20. The input voltage rangesfrom 2.5 V to 3 V with regulated at 1.5 V or 1.9 V fortesting. The switching frequency of the buck converter is about2.5 MHz. The ESR of the inductor and the capacitor are 11.2 m

and 10 m , respectively, which is quoted from the manufac-turer. Fig. 21 shows the measurement result of the steady-statedc-coupled output voltage and the inductor current . Thoseare measured under different input voltages. For example, thetop left graph of Fig. 21 is at the steady state response with

V, V and mA.The waveforms in Fig. 22 are captured under the same

measurement condition as shown in Fig. 21. The difference isthat the output voltage is measured with ac-coupled. The ripplevoltage is around 40 mV in all cases. The spikes in Fig. 22 arefrom the switching noise generated by the parasitic inductancein PCB. These closed-loop steady state measurement resultsshow that the buck converter can operate properly and remainstable with the single TM-ADC under different input/outputvoltage conditions. These also show that the buck converter can


Fig. 21. Steady state dc-coupled output voltage and inductor current.

Fig. 22. Steady state ac-coupled output voltage and inductor current.

operate properly without any limit-cycle oscillation with thesingle TM-ADC.

B. Load Transient

The load transient is obtained by applying a current stepchange at the output of the buck converter. For the case of

V, the current step is from 63 mA to 250 mA whilefor V, the step is from 50 mA to 250 mA. The currentstep is generated by N-type BJT transistor (2N3904). Therise time and fall time of the current step are about 1 s. Themeasurement set up is also shown in Fig. 20.

The step-up load transient response is captured in Fig. 23.For example, the top right graph shows the step-up transient atthe output voltage and inductor current withV, V. The current step is from 50 mA to 250mA. The in all the graphs correspond to the current step.Similarly, the current step-down transient response is in Fig. 24.

Fig. 23. Step-up load transient responses.

Fig. 24. Step-down load transient responses.

In both cases, the output voltage drop is about 200 mV and theresponse time is 20 s.

All these measurement results show that the buck converter isstable under different loading conditions. The concept of using asingle ADC for current-mode control has proven to be feasible.Table IV shows the comparison of different digital controllerICs for Buck converter. Both voltage-mode and current-modecurrent converters have been included. It can be observed thatthe voltage-mode converters generally have slower load tran-sient responses time than the current-mode converters.

In fact, the inductor value will also limit the transient responsetime because it limits how fast the loading current can rampup/down. Given the similar inductor value like 2.5 H in [9], thiswork has similar transient response time. Among the current-mode converters, the buck converter in this paper is among thefastest in terms of load transient responses.


TABLE IVCOMPARISON OF DIFFERENT DIGITAL CONTROLLER ICS FOR BUCK CONVERTER

Fig. 25. Power efficiency with different input voltages.

C. Power Efficiency

The plot of the power efficiency with different input voltagesis shown in Fig. 25. The power efficiency is measured with

the output voltage regulated at 1.9 V. It can be seen that thehighest power efficiency of the buck converter is close to 85%.

The plot of the power efficiency with different output voltagesis shown in Fig. 26. The power efficiency is measured with

the fixed input voltage at 2.5 V. The highest power efficiency isalso close to 85%.

The efficiency is relatively low compared with others in theTable IV. However, the 0.35 m process is relatively old com-pared with others. The 0.35 m process has higher parasitic thanthe advanced process like 40 nm or 0.13 m.

VI. CONCLUSION

The challenges and design considerations of implementinga fully integrated digitally controlled current-mode buck con-verter has been addressed and discussed. Throughout the de-sign of the converter, the implementation of the TM-ADC, theDLL DPWM and the chip-area reduction algorithm has beendiscussed.

Fig. 26. Power efficiency with different output voltages.

The buck converter is fabricated with a standard 0.35 mCMOS process. It consists of the DLL DPWM, voltage-loopand current-loop digital compensators, the TM-ADC, thememory cells and the 500 mA power MOSFETs. All of themare integrated in a single die with a chip area of 1049 m 1533

m. The converter requires no external component except forthe LC filter.

Measurement results show that the buck converter is stableunder different operation conditions. No limit-cycle occurs withthe use of a single TM-ADC. The 20 s load transient responsetime is comparable with the other digitally controlled buck con-verters. All of these proved that it is possible to use a singleTM-ADC for a stable and fast dual-loop digitally controlledconverter.

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Man Pun Chan (S’08) received the B.Eng. andM.Phil. degrees in electronic and computer engi-neering from the Hong Kong University of Scienceand Technology (HKUST) in 2006 and 2008, re-spectively. He is currently working toward the Ph.D.degree in electronic and computer engineering atHKUST, with the Integrated Power Electronics Lab(IPEL).

He was a part-time IC Design Engineer fromJan. 2005 to May 2006 in Lexiwave Technology(HK) Ltd. His current research interest is in digitally

controlled SMPC, low-power ADC and mix-signal design.Mr. Chan was the recipient of the STMicroelectronics Ltd Scholarship in

2005. He has won first prize both in the Student Paper Contest of the 2008IEEE International Conference on Electron Devices and Solid-State Circuits(EDSSC) and the 2010 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS).

Philip K. T. Mok (S’86–M’95–SM’02) received theB.A.Sc., M.A.Sc., and Ph.D. degrees in electricaland computer engineering from the University ofToronto, Toronto, ON, Canada, in 1986, 1989 and1995, respectively.

In January 1995, he joined the Department ofElectronic and Computer Engineering, Hong KongUniversity of Science and Technology, Hong Kong,China, where he is currently a Professor. His researchinterests include semiconductor devices, processingtechnologies and circuit designs for power elec-

tronics and telecommunications applications, with current emphasis on powermanagement integrated circuits, low-voltage analog integrated circuits, and RFintegrated circuits design.

Dr. Mok received the Henry G. Acres Medal, the W.S. Wilson Medal anda Teaching Assistant Award from the University of Toronto, and the TeachingExcellence Appreciation Award three times from The Hong Kong Universityof Science and Technology. He is also a corecipient of the Best Student PaperAward in the 2002 and 2009 IEEE Custom Integrated Circuits Conference. Inaddition, he has been a member of the International Technical Program Com-mittees of the IEEE International Solid-State Circuits Conference (ISSCC) from2005 to 2010 and he served as an Associate Editor for the IEEE TRANSACTIONS

ON CIRCUITS AND SYSTEMS—PART II: EXPRESS BRIEFS from 2005 to 2007, theIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS

from 2007 to 2009, and the IEEE JOURNAL OF SOLID-STATE CIRCUITS since2006.

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