Accelerated Analog Neuromorphic Hardware -...

Kirchhoff Institute for PhysicsJohannes SchemmelRuprecht-Karls-Universität Heidelberg 1

Accelerated AnalogNeuromorphic Hardware

Johannes Schemmel

Kirchhoff Institute for PhysicsChair of Prof. Karlheinz Meier

Ruprecht-Karls UniversityHeidelberg, Germany


Motivation

future computing based on biological information

processing

understanding biological information processing

modeling possibilities:

• numerical model

represents model parameters as binary numbers

• physical model :

analog Neuromorphic Hardware

represents model parameters as physical quantities :

→ voltage, current, charge

can becombined toform a hybrid system

need model system to test ideas


Physical Model Example : Continuous Time Integrating Membrane Model

DV [V] gleak [S] Cm [F] (gV)/C [V/s]

Biology(*) 10-2 10-8 10-10 100

VLSI 10-1 10-6 10-13 106

Consider a simple physical model for the neuron’s

cell membrane potential V:

( VEgdt

dVC leakleakm

Cm

R = 1/gleak

Eleak

V(t)

(*) from Brette/Gerstner, J. Neurophysiology, 2005

Inherent speed gap:106 Volt/second

→ accelerated neuron model


Measured Example Membrane Voltage Traces

# of Synaptic inputs : 12 4


More Neuronal Diversity : Adaptive-Exponential Integrate-and-Fire

• 180 nm CMOS• 24 calibration parameters stored on

analog floating gates


Single Spike Firing Modes of the AdEx VLSI Neuron

tonic spiking

transient spiking adaptation


Burst Firing Modes of the AdEx VLSI Neuron

regularbursting

initial burst


Spike-Time Comparison with Poisson Input


Six Groups of Neurons Firing in a Chain


Attractor Network


𝜈𝑘 = 𝑝 𝑧𝑘 = 1 =1

1 + exp(−𝑢𝑘)

Boltzman Machine with Neural Sampling

Büsing et al. (2011)

Petrovici & Bill et al. (2013)

Petrovici et al. (2015)


𝜈𝑘 = 𝑝 𝑧𝑘 = 1 =1






Using hardware-in-the-looptraining to matchtarget distribution:


𝜈𝑘 = 𝑝 𝑧𝑘 = 1 =1






Using hardware-in-the-looptraining to matchtarget distribution:


Aspects of Modelling Neurobiology : Diversity and Connectivity

Biology: CMOS based analog Neuromorphic hardware :

Diversity : a multitude of neuron morphologies and electorphysiologies

• heavily parameterized circuits necessary• need calibration for quantitative matchingAlso implemented in Heidelberg: multi-compartment back-propagating action potential dentridic spikes gap junctions between neighboring neuronsPlanned:• NMDA plateau potentials• calcium spikesNot yet clear how to do it:• gap junctions beween distant neurons

Connectivity : 1011 neurons, 1015 synapses in Human Brain

physical model of synapse is about 100 µm2

approx. 400 million synapses fit on a silicon wafer → 2.5 million wafer neededsimple simulator model needs O(1016) bytes

10.000 synapses per neuron on average

14k inputs per neuron demonstrated

Wafer-ScaleNeuro-

morphicHW

114.000 dynamic synapses

512 neurons (up to 14k inputs)

chip

-to

-ch

ip c

om

mu

nic

atio

n n

etw

ork


Wafer Modulewafer beneath heatsink power supplies

48 FPGA communication PCBs

host links

Neuromorphicchip

Machine Room

3/22/2016neuromorphic.eu


Aspects of Modelling Neurobiology : Time and Plasticity

Biology: Analog Neuromorphic Hardware :

Time : continuous time operation physical model

relevant timescales range from ms to years

accelerated model compresses years to hours and hours to seconds

precisely controlled delays programmable delay circuits needed → even more memory

Plasticity : grows from single precursor cell

programmable topology, large amounts of memory

genome codes for complex and diverse plasticity rules

flexible synaptic plasticity has to be integrated into synapse modelarea is limited → hybrid model necessary


Complexity of Synaptic Plasticity is Key to Biological Intelligence

Protein-protein interaction map (…) of

post-synaptic density

“Towards a quantitative model of the post-synaptic

proteome”

O Sorokina et.al., Mol. BioSyst., 2011,7, 2813–2823

Protein complex organization in the

postsynaptic density (PSD)

“Organization and dynamics of PDZ-domain-

related supramodules in the postsynaptic density”

W. Feng and M. Zhang, Nature Reviews NS,

10/2009


Start with Simple Model : Spike Time Dependent Plasticity

synapse strength decreases

long term depression

synapse strength increases

long term potentiation

presynaptic membrane potential

Dt = tpost – tpre

postsynaptic membrane potentialtime

Dt > 0 |Dt| < tcorrelated Dt < 0

extracellular

stimulation

intracellular

stimulation

Graphs taken from:

Theoretical

Neuroscience by P.

Dayan and L. Abbott,

2001

change in

excitatory

post-

synaptic

potential

long-term

depression

long-term

potentiation

Biological Evidence


An Example Using Spike-Time-Dependent-Plasticity

T. Pfeil, A.-C. Scherzer, J. Schemmel and K. Meier,

Neuromorphic Learning towards Nano Second Precision,

Proceedings of the 2013 International Joint Conference on

Neural Networks (IJCNN).

Dallas, TX, USA: IEEE Press, 2013, pp. 869-873.

Spikey USB basedneuromorphic system


Using Neuromorphic Hardware : From Networks to Experiments

Mappingimport pyNN.stage2 as pynn

pynn.setup()

neuronParams = {

'v_init' : -70.6,

'w_init' : 0.0,

[...]

}

pool0 = pynn.create(pynn.EIF_[...])

pool1 = pynn.create(pynn.EIF_[...])

[...]

pynn.connect(pool0, pool0, p=0.26, weight=0.5)

pynn.connect(pool1, pool0, p=0.16, weight=0.5)

[...]

pynn.run()

[...]

PyNN script(reordered connection matrix)

RoutingConfiguration/Evaluation(comparing connection matrix)


Hybrid Plasticity

Problem : millions of parameters

• network topology

• neuron sizes and parameters

• synaptic strengths

Current status : everything is pre-computed on host-computer

• requires precise calibration of hardware

• takes long time(much longer than running the experiment on the accelerated system)

Integrate flexible plasticity mechanisms : “Hybrid Plasticity”

• no calibration of synapses necessary

• plastic topology and delays

• learning replaces calibration

• combination of analog correlation measurement and digital Plasticity Processing Unit (PPU)


Second Generation Neuromorphic ASIC : HICANN-DLS

analog

network

core

bottom ppu

top ppu

digital

core

logic

fast ADC

vertical

layer1 repeaters

horizontal layer1

repeaters

SERDESchannel 0

output amplifier

main PLL

SERDESchannel 1

SERDESchannel 2

SERDESchannel 3

synthesized RTL

mixed full custom

analog outputs

TX data

TX clk

RX clk

RX data

extclk

JTAG and reset

TX dat

L1 top

L1 right

L1 left

L1 bot

synapse tl, tr, bl, br

new component : digital plasticity processing units (ppu)


2nd 65nm Hybrid Plasticity Prototype

plasticity processor

synapse array

neuron circuits

FPGA based controller board


Plasticity : Hybrid Scheme Provides Flexibility

• analog correlation measurement in synapses

• A/D conversion by parallel ADC

• digital Plasticity Processing Units→ full access to synapse

weights→ full access to

configuration data

SIMD Plasticity Processing Unit

ADC arrayparallel conversion of STDP readout


Concept of Hybrid Plasticity Operation


𝜔′− = 𝜔 − 𝑏−𝜔 exp −

∆𝑡

𝑐−

Measurement Results for Multiplicative STDP Rule

𝜔+′ = 𝜔 + 𝑏+ 𝜔max − 𝜔 exp −

Δ𝑡

𝑐+


Measurements Demonstrating Possible STDP Rules

Hebbian :Anti-Hebbian :

AsymmetricSensitivity :

Bistablelearning :

• very early results using only variations of the STDP PPU code

• PPU also supports : • supervised plasticity• reinforcement

learning• including neuron

firing rates in plasticity rules

• adding additional digital synaptic state variables

• anything you can code …

Publication currently under review:S. Friedmann, J. Schemmel et.al.:

“Demonstrating Hybrid Learning in a Flexible Neuromorphic Hardware System”

The research leading to these results has received funding from theEU FP7 Framework Programme under grant agreement nos.

269921 (BrainScaleS), 243914 (Brain-i-Nets) and 604102 (HBP).

This endeavor would not have been possible without the tireless commitment of all the involved students and

colleagues, which unfortunately are too many to name them all here individually.

Thank You!

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Accelerated Analog Neuromorphic Hardware -...

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