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ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
Fault-tolerant Multicore System on Fault-tolerant Multicore System on Network-on-ChipNetwork-on-Chip
Presenter: Parhelia
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P2
Motivation (1)Motivation (1) Challenge of future SoC: Performance/Technology Gap
Advanced architecture techniques are required!
Before 2002, ILP helped to close the gap successfully
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P3
Motivation (2)Motivation (2)
Trend: More Core, More better
1993, Pentium 1997, Pentium MMX
1997, Pentium II 1999, Pentium III 2001, Tualatin2002, Pentium 4
Northwood
2005, Pentium D 2006, Core 2 Duo (Conroe)
2006, Core 2 Quad(Kentisfield)
2007, TeraScale 80-core prototype
Single core with increased performance
Multicore processor with more and more cores!!
Key for Multicore:Interconnection
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P4
Motivation (3)Motivation (3)
Future on-chip communication for SoC IPs
OCN (On-Chip Network) is a novel and practical approach to interconnect SoC IPs
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P5
Fault-Tolerant NoC(1)Fault-Tolerant NoC(1)
Device size shrinking Erroneous in production
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P6
Fault-Tolerant NoC (2)Fault-Tolerant NoC (2)
Just like normal computer network :pUnreliable
OCNTraditional FT routing
CB
A
Partitioned Faulty Nodes
Fault block
Faulty node
CB
A
valid path
invalid path
Model a faulty node to multiple data paths Define relative FT routers architectures and FT routing algorithms.
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P7
Goal (1)Goal (1) Demonstrate FT NoC on real
application using FPGA GUI interface Visual demonstration
See performance degradation
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P8
Goal (2)Goal (2) Demonstrate FT NoC on real
parallel application Rendering engine
20-path Router Model
RealisticFT Router Architecture
FT Routing Algorithm
FT Mapping Algorithm
FPGA System PlatformsFPGA
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P9
What you will learn is…What you will learn is…
State-of-the-Art on-chip communication technology HW/SW co-design FPGA emulation concepts and experiences
PrerequisitePrerequisite Programming language (C/C++, GUI better) Concepts on digital logic design Creativity, smart-working
Contact InformationContact Information黃耿賢 [email protected]
Software / system simulation
許展誠 [email protected] Hardware design / FPGA Emulation
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
P10
ReferenceReference [1] L. Benini and G. De Micheli, “Networks on chips: a new SoC
paradigm,” on Computer, pp. 70-78, Vol. 35, Issue. 1, Jan. 2002. [2] http://techresearch.intel.com/articles/Tera-Scale/1449.htm [3] http://www.tilera.com/pdf/ProBrief_Tile64_Web.pdf [4] S. Murali,, N. Vijaykrishnan, M.J. Irwin, L. Benini, and G. De
Micheli, “Analysis of error recovery schemes for networks on chips,” IEEE Design & Test of Computers, pp.434-442, Volume 22, Issue 5, Sep. 2005.
[5] N. Genko, D. Atienza, G. De Micheli, J. M. Mendias, R. Hermida, and F. Catthoor, “A Complete Network-On-Chip Emulation Framework,” Proceedings of the conference on Design, Automation and Test in Europe (DATE’ 05), pp.246-251,
Vol.1, 2005.