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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE...

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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx FPGA Design with Xilinx ISE ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6
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Page 1: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

FPGA Design with XilinxFPGA Design with XilinxISEISE

Presenter: Shu-yen Lin

Advisor: Prof. An-Yeu Wu

2005/6/6

Page 2: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 2

OutlineOutline

Concepts of Xilinx FPGAXilinx FPGA ArchitectureIntroduction to ISECode GeneratorConstraints and ReportsConfigurationDemo and Lab

Page 3: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Concepts of Xilinx FPGAConcepts of Xilinx FPGA

Page 4: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 4

Electronic ComponentsElectronic Components

Page 5: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 5

FPGA BenefitsFPGA BenefitsFull-Custom

ICsCell-Based

ICsGate Arrays FPGA

Speed ●● ● ● ●

Integration Density ●● ● ● ●

High-Volume Device Cost ●● ●● ● ●

Low-Volume device Cost ● ●●

Time to Market ● ●●

Risk Reduction ●●

Future Modification ●●

Development Tool ● ● ● ●●

Educational Purpose ●●

Page 6: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 6

Full Xilinx Design SupportFull Xilinx Design Support

Page 7: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 7

Xilinx Products CPLDs and FPGAs

Page 8: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Xilinx FPGA ArchitectureXilinx FPGA Architecture

Page 9: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 9

The Conceptual CPLD ArchitectureThe Conceptual CPLD Architecture

Page 10: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 10

The Conceptual FPGA ArchitectureThe Conceptual FPGA Architecture

Field-programmable Re-programmable In-circuit design verification Rapid prototyping Fast time-to-market No IC-test & NRE cost H/W emulation instead of S/W

Page 11: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 11

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6)Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6)

Page 12: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 12

Logic and Routing - the CLB tile

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (2/6)Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (2/6)

Page 13: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 13

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)6)

Two slices in each CLB Each slice contains 2 LUT, 2 Register and 2 Carry Logic.

Logic and Routing – Simplified CLB Structure

Page 14: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 14

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)

Logic and Routing – Look-Up Tables (LUTs) Combinational logic is stored in Look-up Tables (LU

Ts) in a CLB. Capacity is limited by number of inputs, not complex

ity. Delay through CLB is constant.

Page 15: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 15

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (4/6)Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (4/6)

System Interface – Select IOTM

Supports multiple voltage and signal standards simultaneously Eliminate costly bus transceivers

Page 16: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 16

System Memory – Distributed RAM, Block RAM and External Memory

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (5/6)Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (5/6)

Page 17: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 17

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/6)6)

System clock management - DLLs Clock Mirror Multiplication

1 DLL for 2x Combine 2 DLL for 4x

Division Selectable division values - 1.5, 2, 2.5,

3, 4, 5, 8, or 16

Phase Shift 0, 90, 180, 270

Page 18: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 18

Spatran-3, VirtexII FPGA Architecture (1/7)Spatran-3, VirtexII FPGA Architecture (1/7)

Page 19: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 19

Spatran-3, VirtexII FPGA Architecture (2/7)Spatran-3, VirtexII FPGA Architecture (2/7) Logic and Routing - the CLB tile

Page 20: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 20

Spatran-3, VirtexII FPGA Architecture (3/7)Spatran-3, VirtexII FPGA Architecture (3/7)System Interface – Select IOTM 23 different

standards supported !

Page 21: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 21

Spatran-3, VirtexII FPGA Architecture (4/7)Spatran-3, VirtexII FPGA Architecture (4/7) System Memory –External Memory supports DDR memory

Page 22: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 22

Spatran-3, VirtexII FPGA Architecture (5/7)Spatran-3, VirtexII FPGA Architecture (5/7) System clock management – DCMs

Page 23: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 23

Spatran-3, VirtexII FPGA Architecture (6/7)Spatran-3, VirtexII FPGA Architecture (6/7) System clock management – DCMs

Page 24: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 24

Spatran-3, VirtexII FPGA Architecture (7/7)Spatran-3, VirtexII FPGA Architecture (7/7) Embedded multiplexer

Page 25: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 25

VirtexII Pro FPGA ArchitectureVirtexII Pro FPGA Architecture

Page 26: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 26

Programmable Logic EvolutionProgrammable Logic Evolution

Page 27: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Introduction to ISEIntroduction to ISE

Page 28: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 28

ISE PhilosophyISE Philosophy

ISE 6.1i Future Xilinx devices Proactive Timing Closure ECS & HDL Bencher & XST

Platform Unix: Solaris 2.7/2.8 PC: Win 2000/XP

Service Pack http://support.xilinx.com

ISE WebPage http://www.xilinx.com/ise

Page 29: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 29

Design Flow in ISE (1/2)Design Flow in ISE (1/2)

Design

Synthesis

Implement

Download

A & B = C

A

BC

LUT RegA

BC

CLB

AB

C

Specification

RTL model

Synthesis

APR

Download

Testbench

Pre-Synthesis Simulation

Post-Synthesis Simulation&

Static Timing Analysis

Post-Layout Simulation&

Static Timing Analysis

Page 30: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 30

Design Flow in ISE (2/2)Design Flow in ISE (2/2)

Page 31: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 31

Introduction to Projection Navigator Introduction to Projection Navigator (1/4)(1/4)

Page 32: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 32

Introduction to Projection Navigator (2/4)Introduction to Projection Navigator (2/4) Source Windows

Page 33: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 33

Introduction to Projection Navigator (3/4)Introduction to Projection Navigator (3/4)Processes for current source

Page 34: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 34

Introduction to Projection Navigator (4/4)Introduction to Projection Navigator (4/4) Processes for current source

Page 35: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 35

Create New ProjectCreate New Project

Page 36: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 36

Create New SourceCreate New Source

Page 37: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 37

HDL Source FileHDL Source File

Page 38: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 38

Text EntryText Entry

Page 39: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 39

Language TemplatesLanguage Templates

Page 40: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 40

Synthesis (1/4)Synthesis (1/4) XST

Page 41: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 41

Synthesis (2/4)Synthesis (2/4) XST Flow

Page 42: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 42

Synthesis (3/4)Synthesis (3/4) Synthesis Step

Page 43: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 43

Synthesis (4/4)Synthesis (4/4) RTL view

Page 44: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 44

Implementation (1/8)Implementation (1/8)

Translate - Merge multiple design files into a single netlistMap - Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs)Place & Route - Place components onto the chip, connect them, and extract timing data into reports

Page 45: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 45

Implementation (2/8)Implementation (2/8)

Page 46: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 46

NCFEDIF

EDIF2NGD

EDIF

EDIF2NGD

.NGO .NGO

NGDBUILD

.NGO

Core Generator

UCF

.NGO Native Generic Database

Logical DRCCheck-point

TranslateImplementation (3/8)Implementation (3/8)

Page 47: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 47

Optional Constraint File(File from UCF)

MDF

NCD

Optional Guide Files(Files from the last mapping)

NGD PCF

MAP

MDF

NCD PCF

MRP

NGM

MapImplementation (4/8)Implementation (4/8)

Page 48: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 48

Implementation (5/8)Implementation (5/8)

Map Property Trim Unconnected Signals

If you check this item, the mapping tool will remove the unconnected wire that let the tracing back become hardly.

Generate Detailed Map Report If more detailed report is needed, you can check it. (Recommending ch

eck it) Use Guide Design File (.ncd)

You can refer the last mapping solution so that you maybe get better solution.

Use RLOC Constraints Constraints of CLB (default check).

Pack I/O Registers/Latches into IOBs If the value chosen Default that pack the register nearby I/O into I/O blo

ck. You can also chose only for input or only for output or off.

Page 49: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 49

Optional Guide File

NCDNCD PCF

P&R

PAR

NCDDIR

PAR

PAR

NCD

PAR

NCD

PAR

NCD

PAR

NCD

Multi-PAR runSingle-PAR

run

Place and Route

Implementation (6/8)Implementation (6/8)

Page 50: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 50

Place and Route Property (1/2) Place & Route Effort Level (Overall)

Effort Level means the P&R effect result. Using the Higher get the better solution, but spend more time.

Starting Placer Cost Table (0-100) Specify a placement initialization value with which to begin P&R attem

pts. Each subsequent attempt is assigned an incremental value based on the placement initialization value.

Place and Route Mode Quick means without timing constraints; Route Only and Re-entrant Ro

ute mean P&R must have been run at last once to use this option.

Guide File Include the .ncd file.

Implementation (7/8)Implementation (7/8)

Page 51: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 51

Place and Route Property (2/2) Use Timing Constraints

Include the .ucf file.

Use Bonded I/Os If it is checked, signals will be connected to I/O pads.

Generate Detailed PAR Report Check the value to generate a detailed PAR report.

Generate Post-Place & Route Static Timing Report Check the value to generate post-place & route static timing report.

Generate Post-Place & Route Simulation Model Check it for generating required simulation files for ModelSim (*.v and *.

sdf).

Implementation (8/8)Implementation (8/8)

Page 52: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 52

Download (1/2)Download (1/2)

Page 53: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 53

Download (2/2)Download (2/2)

Page 54: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Code GeneratorCode Generator

Page 55: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 55

What are Cores?What are Cores?

Page 56: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 56

Benefits of Using CoresBenefits of Using Cores

Page 57: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 57

Invoking the CORE Generator GUIInvoking the CORE Generator GUI

Page 58: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 58

Xilinx Code Generator System GUIXilinx Code Generator System GUI

Page 59: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 59

Core Customize WindowCore Customize Window

Page 60: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 60

Core Data SheetCore Data Sheet

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pp. 61

Core Generator Design Flow Core Generator Design Flow

Page 62: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 62

Link with CodeGen IP (Verilog)Link with CodeGen IP (Verilog)

Page 63: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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Graduate Institute of Electronics Engineering, NTU

Constraints and ReportsConstraints and Reports

Page 64: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 64

TopicsTopics

Assign Package Pins (PACE)Assigning Pins

Create Timing ConstraintsThe PERIOD ConstraintsThe Pad-to-Pad ConstraintsThe OFFSET ConstraintsThe Constraints Editor

Read Report

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pp. 65

Constraints GUI (1/2)Constraints GUI (1/2)

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pp. 66

Constraints GUI (2/2)Constraints GUI (2/2)

Page 67: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 67

Assign Package Pins (1/6)Assign Package Pins (1/6)Start PACE Editor

Page 68: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 68

Assign Package Pins (2/6)Assign Package Pins (2/6)

PACE Editor GUI

Page 69: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 69

Assign Package Pins (3/6)Assign Package Pins (3/6)Method #1 to assign package pins

Page 70: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 70

Assign Package Pins (4/6)Assign Package Pins (4/6)Method #2 to assign package pins

Page 71: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 71

Assign Package Pins (5/6)Assign Package Pins (5/6)Method #3 to assign package pins

Page 72: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 72

Assign Package Pins (6/6)Assign Package Pins (6/6)

Method #4 to assign package pins

Use text editor to edit .ucf files

NET is port nameLOC assign pins to sp

ecific location

Page 73: ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.

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pp. 73

The PERIOD ConstraintThe PERIOD Constraint

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The Pad-to-Pad ConstraintThe Pad-to-Pad Constraint

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pp. 75

The OFFSET ConstraintThe OFFSET Constraint

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The Constraint Editor (1/3)The Constraint Editor (1/3)

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The Constraint Editor (2/3)The Constraint Editor (2/3) Enter PERIOD and Pad-to-Pad Constraint

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The Constraint Editor (3/3)The Constraint Editor (3/3) Enter OFFSET Constraint

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Read Report (1/12)Read Report (1/12) Create Report Files

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Read Report (2/12)Read Report (2/12)

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Read Report (3/12)Read Report (3/12) Example of MAP Report (1/2)

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pp. 82

Read Report (4/12)Read Report (4/12) Example of MAP Report (2/2)

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pp. 83

Read Report (5/12)Read Report (5/12)

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pp. 84

Read Report (6/12)Read Report (6/12) Example of PAR Report (1/2)

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Read Report (7/12)Read Report (7/12) Example of PAR Report (2/2)

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pp. 86

Read Report (8/12)Read Report (8/12)

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pp. 87

Read Report (9/12)Read Report (9/12) Example of Timing Report (1/4)

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pp. 88

Read Report (10/12)Read Report (10/12) Example of Timing Report (2/4)

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pp. 89

Read Report (11/12)Read Report (11/12) Example of Timing Report (3/4)

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pp. 90

Read Report (11/12)Read Report (11/12) Example of Timing Report (4/4)

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pp. 91

Post-layout SimulationPost-layout Simulation

Modelsim

Post layoutsimulation file

testbench

Result

glbl.v simprims.sdf file

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Graduate Institute of Electronics Engineering, NTU

ConfigurationConfiguration

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pp. 93

What is configuration?What is configuration?

Process for loading into the FPGA

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Configuration Mode (1/4)Configuration Mode (1/4)

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Configuration Mode (2/4)Configuration Mode (2/4) Serial Mode

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Configuration Mode (3/4)Configuration Mode (3/4)SelectMAP Mode

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Configuration Mode (4/4)Configuration Mode (4/4) JTAG or Boundary Scan

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pp. 98

IMACT (1/3)IMACT (1/3)

Must double clock “Generate Programming File” before programming FPGA

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IMACT (2/3)IMACT (2/3)

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IMACT (3/3)IMACT (3/3)


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