Abstract—In outdoor light-emitting diode (LED) lighting sys-tems, there are a lot of applications. Depending on the outputpower rating, the power stage to drive an LED can be classifiedinto single-stage and two-stage structures. The single-stage struc-ture is for low-power LED lighting applications. However, it isdifficult to apply at over 60–70 W of output power because of itslow efficiency and huge transformer at high power. On the otherhand, the two-stage structure is usually used for high power ap-plications. However, it is undesirable to cover wide output powerrange because of its poor power factor (PF) under the light loadcondition. To solve these problems, this paper proposes a new pulseduty cycle control method with pulse frequency modulation foran interleaved single-stage flyback ac–dc converter. The proposedconverter provides high efficiency under heavy loads with low acline condition and under light loads with high ac line condition.In addition, the proposed converter shows high PF and low to-tal harmonic distortion even when the output power is very low.As a result, a single LED ac–dc converter can cover wide powerrange for outdoor LED lighting applications. To verify the validityof the proposed converter, an 81-W prototype converter has beenimplemented and experimented on.
Index Terms—Frequency control, interleaved flyback, light-emitting diode (LED), power factor correction (PFC), single-stage,total harmonic distortion (THD).
I. INTRODUCTION
NOWADAYS, the use of high-brightness light-emittingdiode is increasing in a lot of outdoor lighting applications
such as street lights, floodlights, beacon lights, tunnel lights, andsecurity lights, because of its high luminous efficacy, ease todrive, the absence of a mercury problem and long lifetime. Theoutput power of these applications is usually around 10–200 W.Since outdoor lights are usually supplied by an ac source, theyhave to comply with the IEC61000-3-2 standard [1] regarding
Manuscript received June 8, 2012; revised August 31, 2012 and October 9,2012; accepted November 4, 2012. Date of current version January 18, 2013.This work was supported by the National Research Foundation of Korea fundedby the Korea Government (MEST) under Grant 2012-0000981. This work waspresented at the 27th Annual IEEE Proceedings of the Applied Power Electron-ics Conference and Exposition, Orlando, FL, Feb. 5 to 9, 2012. Recommendedfor publication by Associate Editor J. M. Alonso.
S. Moon and G.-W. Moon are with the Department of Electrical Engineering,Korea Advanced Institute of Science and Technology, Daejeon 305-701, Re-public of Korea (e-mail: [email protected]; [email protected]).
G.-B. Koo is with the Fairchild Korea Semiconductor, Ltd., Bucheon 420-711, Korea (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2229471
Fig. 1. Power stage of LED driver. (a) Single-stage structure. (b) Two-stagestructure.
harmonic content and power factor (PF). The PF is required thatis higher than 0.9, and the total harmonic content has to meet theIEC61000-3-2 Class C lighting equipment standard. Recently,the total harmonic distortion (THD) of less than 10% is requiredin the industry.
In outdoor lighting systems, according to the output power rat-ing, the power stage to drive an LED can be classified into single-stage [2]–[8] and two-stage structures. As shown in Fig. 1(a), thesingle-stage structure for an LED power supply unit combinesthe power factor correction (PFC) part and the dc–dc converterpart into one stage. As shown in Fig. 1(b), in the two-stagestructure, the first stage is the ac–dc converter for PFC and thesecond stage is the dc–dc converter for regulating the outputvoltage or current. A critical conduction mode (CRM) boostconverter is widely used for the first stage and forward, flyback,half- bridge and LLC converters are used for the second stagebecause they have high PF and efficiency. In two-stage struc-ture, two power stages can be controlled separately so that itis easy to optimize and it can handle high power applications.In addition, since the LED current ripple caused by the ac linesource is very small, there is no invisible flicker problem de-tected by digital devices such as digital cameras. However, thetwo-stage structure needs a large number of components andtwo kinds of control ICs so that it costs a lot and shows lowefficiency due to the two processes of the input power. Since theoutput voltage of the PFC circuit is around 400 Vdc , a very highvoltage rating electrolytic capacitor is required for the bulkycapacitor resulting in a reduction in both the lifetime and thereliability. Especially, in the CRM boost converter for PFC,it shows poor PF and THD under light load condition due tothe negative drain current for valley switching. Therefore, the
two-stage structure cannot cover the wide output power rangeof LED lighting applications.
On the other hand, the single-stage structure has a low com-ponent count, a low cost, a simple control circuit, and highefficiency. Since there is no high voltage rating electrolytic ca-pacitor for boost output voltage, single-stage has a long life andhigh reliability compared with two-stage structure. A CRM fly-back converter is widely used as the single-stage structure dueto its high efficiency by valley switching even if it still showspoor PF and THD under light load condition due to the valleyswitching of the CRM control method. On the other hand, aDCM flyback converter shows good PF and THD, but it has lowefficiency due to its high rms current. Most single-stage flybackconverters are hard to apply at over 60–70 W LED applications,because the flyback converter usually has low efficiency and ahuge transformer with high power applications. The single-stagestructure also cannot cover wide output power range. To handlehigh output power with the flyback topology, an interleavingcontrol method is a possible solution [9]–[15].
As shown in Fig. 2, the interleaving control method providessmall input and output filters, low voltage stress on the mainswitch and a low profile design when compared to noninter-leaving methods. While the CRM interleaved flyback converterhas high efficiency, but shows poor PF and THD under lightload condition, the discontinuous conduction mode (DCM) in-terleaved flyback converter has good PF and THD under lightload condition, but shows low efficiency due to its high rmscurrent. To achieve high efficiency and good PF and THD inwide output power range, this paper proposes a pulse duty cyclepulse frequency modulation (PDPFM) control method for aninterleaved single-stage flyback (ISSF) converter.
II. PROPOSED CONTROL METHOD
The proposed control method adopts DCM operation whichcan achieve high PF for wide output power range. In the pro-posed method, the interleaved DCM flyback converter is basi-cally controlled by frequency modulation, not pulsewidth mod-ulation (PWM). As shown in (1), the turn-ON time correspondsto the switching frequency to reduce the frequency variation and
Fig. 3. Key waveforms of the proposed control method.
to achieve high efficiency
Ton = m · fsw (1)
where m is a constant. For low conduction loss under heavy loadwith low ac line condition, the proposed method increases theswitching frequency and the turn-ON time. On the other hand, toreduce the switching loss under light load with high ac line, theproposed method decreases both the switching frequency andthe turn-ON time. Therefore, in Fig. 2, average output powerover half of the ac line period can be expressed as
Po =η · V 2
line · m · D · fSW
Lm1(2)
where Vline is the ac line voltage in rms, η is efficiency, D isduty cycle, and Lm1 equals Lm2 . Output power is controlled byduty cycle and switching frequency. As a result, the proposedconverter can achieve high PF and low THD by utilizing DCMoperation, and high efficiency due to frequency modulation inwide output power range.
A. Operation Principle
Fig. 3 shows the key waveforms of an interleaved DCM fly-back converter with the proposed method. The switching periodis subdivided into six modes. Since operation modes 1–3 aresimilar to modes 4–6, only the first three operation modes arepresented. The main equivalent circuits for the operation modesare shown in Fig. 4. To simplify the analysis of the circuit oper-ation, the following assumptions are made:
1) the leakage inductance of the transformer is neglected;2) the line frequency is much lower than the switching fre-
quency of the flyback converter so that the input voltageVin can be regarded as a constant during each switchingperiod;
MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK AC–DC CONVERTER 4053
3) the EMI filter capacitance Cfilter is greater than CIN , in-cluding the equivalent capacitance of the bridge diodes;
4) the magnetizing inductances Lm1 and Lm2 are identical;5) the line voltage Vline is positive. Thus, diodes D1 and D4
are conducting;6) the two switches, Q1 and Q2 , operate 180◦ out of phase.Mode 1 (t0–t1): As can be seen in Fig. 4(a), Q1 is turned ON
and the energy is built into the magnetizing inductor Lm1 , andthe energy stored in Lm2 is transferred to the output. The draincurrent IDS1 of Q1 increases with the slope of Vin / Lm1 , andthe diode current ID6 decreases with the slope of N 2Vo /Lm2 .This mode ends when ID6 decreases to zero.
Mode 2 (t1–t2): When ID6 equals zero, this mode begins. InFig. 4(b), the magnetizing inductor of T2 starts to resonate withthe output capacitor Coss2 of the switch Q2 . Because Q1 is still
ON, the diodes D1 and D4 are conducting. Thus, most of theresonance currents flow through D1 ,D4 , and the electromag-netic interference (EMI) filter. The resonance period TP 1 andIDS2 can be expressed as
TP 1 =2π
√Lm2 ·
(Cfilter +CIN) · Coss2
Cfilter +CIN +Coss2≈2π
√Lm2 · Coss2
(3)
IDS2 = − NVo√Lm2/Coss2
sin2π
TP 1(t − t1), t1 ≤ t < t2 (4)
where Cfilter is greater than CIN and Coss2 .Mode 3 (t2–t3): Mode 3 begins when Q1 is turned OFF. As
can be seen in Fig. 4(c), the diode current ID5 decreases with
4054 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
Fig. 5. Conventional and proposed control method. (a) PFM method at low line. (b) PWM method at low line. (c) Proposed method at low line. (d) PFM methodat high line. (e) PWM method at high line. (f) Proposed method at high line.
the slope of N 2Vo /Lm1 . Because Q1 is turned OFF, D1 andD4 are no longer conducting. Thus, the resonance current flowsthrough CIN and the resonance period TP 2 can be expressed as
TP 2 = 2π
√Lm2 ·
CIN · Coss2
CIN + Coss2≈ 2π
√Lm2 · Coss2 . (5)
If CIN is greater than Coss2 , the resonance period TP 2 isalmost the same as TP 1 .
In high ac line, the waveforms are similar except for theswitching period, the turn-ON time, and the duty cycle. Theswitching period Tsw2 increases and the turn-ON time and theduty cycle decreases to reduce the switching frequency variationand the switching loss in high ac line.
Fig. 5 shows the conventional pulse frequency modulation(PFM) method with constant duty cycle of 0.5, the constant fre-quency PWM method and the proposed method at low and highac lines. As shown in Fig. 5(a) and (d), the conventional PFMmethod shows the disadvantage of a large frequency variationbetween low and high ac lines. It causes severe switching loss at
high ac line. The frequency variation between the low and highlines is obtained as
ΔfPFM = flow ·
⎛⎝(
V in. h ig h
V in. l ow
)2
− 1
⎞⎠ (6)
where flow is the switching frequency at low line.The proposed method is basically controlled by the switching
frequency in DCM operation. However, unlike the conventionalPFM method, as shown in Fig. 5(c) and (f), the turn-ON timeand the duty cycle of the proposed method is varied with theswitching frequency. If the switching frequency increases, theturn-ON time and the duty cycle also increases, and vice versa.The frequency variation of the proposed method between lowand high lines is obtained as
Δfproposed = flow ·
⎛⎝
(V in
. h ig h
V in. l ow
· Dmin
Dmax
)2
− 1
⎞⎠ (7)
MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK AC–DC CONVERTER 4055
Fig. 6. Simple block diagram of the proposed control method.
where Dmin is the duty cycle at full load with high ac linecondition, Dmax is the duty cycle at full load with low ac linecondition and the value of Dmin over Dmax is less than unity.Thus, the proposed method reduces the switching frequencyvariation when compared to the conventional PFM method.
As shown in Fig. 5(b) and (c), the rms current of the proposedmethod is lower than that of the conventional PWM method inlow ac line so that the conduction loss of the proposed method isreduced. In high ac line, the switching frequency of the proposedmethod is lower than that of the conventional PWM method. Asa result, the switching loss of the proposed method is reduced.
Therefore, the proposed method can achieve high PF andlow THD by utilizing DCM operation, and it can achieve highefficiency due to the variable switching frequency, turn-ON timeand duty cycle. However, the peak current at high ac line ishigher than that of the conventional PWM method as shown inFig. 5(e) and (f). Therefore, the transformer size may increase.
B. Proposed Control Scheme
Figs. 6 and 7 show a simple block diagram for the proposedcontrol method of the interleaved DCM flyback converter andits key waveforms, respectively. In Fig. 6, the optotransistorreceives the output current information and draws current fromFB terminal. The current I1 is given by
I1 =V1
Rf min+
V1 − Vop
Rf max. (8)
The more the current I1 flows, the higher the switching fre-quency. At t00 , in Fig. 7, the switch M2 is turned ON. If thecurrent source I2 is much greater than the dependent currentsource aI1 , I2 discharges the capacitor C1 very quickly. Whenthe capacitor voltage VC 1 becomes V3 , the comparator COM3outputs high signal. Accordingly, SR1 is reset, SR2 is set andthe switch M3 is turned ON. As a result, M2 is turned OFF, theD flip–flop DFF1 outputs high signal, and the capacitor C2 isdischarged. Therefore, the signal of the gate driver1 VG1 outputshigh signal and Q1 is turned ON in Fig. 4. Then, C1 is charged
Fig. 7. Key waveforms of the block diagram.
by aI1 and C2 is charged by the current source I3 . When thecapacitor voltage VC 2 increases to VR1 , which is set by aI1and R1 at t11 , the comparator COM4 outputs high signal. As aresult, SR2 is reset. Then, VG1 becomes low and Q1 is turnedOFF. The turn-ON time of Q1 is obtained by
Ton = C2VR1
I3= C2
aI1 · R1
I3. (9)
After VG1 becomes low at t11 , C1 is still charged by aI1 .When VC 1 is equal to V2 at t22 , the comparator COM2 outputshigh signal. Thereby, SR1 is set. Then, M2 is turned ON again.For the next one cycle, VG1 remains low signal by DFF1, whichactivates AND2 and deactivates AND1. Then, VG2 goes to highand turns ON Q2 in Fig. 4. Therefore, Q1 and Q2 are turnedON by turns. The switching period TL of Q1 is twice the periodof the sawtooth signal VC 1 because of the interleaving controlmethod. The switching period is obtained by
TL = 2C1 ·V2 − V3
aI1. (10)
From (9) and (10), Ton can be expressed as
Ton = 2C1 · C2 · R1 ·V2 − V3
I3· fL = m · fL . (11)
Equation (11) shows that the turn-ON time is varied in pro-portion to the switching frequency. Therefore, the turn-ON timeand the switching frequency increase under heavy load in lowac line condition and decrease under light load in high ac linecondition. The right side of Fig. 7 shows the waveforms underheavy load condition. The turn-ON time and the switching fre-quency are increased. Table I is an example of the relationshipbetween the switching frequency and the turn-ON time.
4056 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
TABLE IEXAMPLE OF THE RELATIONSHIP OF FREQUENCY AND Ton
90Vac 265Vac
Load (%) Freq. (kHz) Ton (µs) Freq. (kHz) Ton (µs)
100 100 4.979 48.68 2.278
90 96.55 4.797 47.00 2.189
80 92.83 4.602 45.19 2.094
70 88.79 4.389 43.22 1.991
60 84.34 4.155 41.06 1.877
50 79.37 3.893 38.64 1.749
40 73.68 3.594 35.87 1.604
30 66.94 3.239 32.59 1.431
20 58.48 2.794 28.47 1.214
10 46.42 2.159 22.60 0.905
Fig. 8. Drain current of the DCM flyback converter.
III. ANALYSIS AND DESIGN CONSIDERATIONS
A. Input Current
Fig. 8 shows the drain current of the DCM flyback converter.The input voltage Vin(t) can be expressed as
Vin(t) =√
2Vac sin ωt (12)
where Vac is the ac line voltage in rms. Then, the instantaneouspeak current Ipk(t) is obtained by
Ipk(t) =√
2Vac sinωt
Lm· ton (13)
where Lm is the magnetizing inductance of the transformer.From (13), the instantaneous average input current Iave(t) isobtained by
Iave(t) =√
2Vac sinωt
2Lm· t2on
Tsw. (14)
The instantaneous average current follows a sinusoidal enve-lope. On the other hand, as shown in Fig. 9, the instantaneousaverage input current Iave(t) of the CRM flyback converter isgiven by
Iave(t) =√
2Vac sin ωt · ton
2Lm· 1
1 +√
2Va c sin ωtN Vo
(15)
where NVo is the reflected output voltage. The instantaneousaverage current has some distortion from a pure sinusoidal wave-form due to the denominator of the right-side term in (15). Thus,
Fig. 9. Drain current of the CRM flyback converter.
TABLE IICONDUCTION LOSS COMPARISON AT LOW AC LINE
the DCM flyback configuration results in better PF and THDwhen compared to the CRM flyback configuration.
B. Conduction Loss and Peak Current Comparison
In low ac line and heavy load condition, the conduction lossis dominant for the total power loss. To compare the proposedmethod with the conventional constant frequency DCM method,the following assumptions are made:
1) f1 = k·fsw and f2 = fsw /k, where fsw is the switchingfrequency of the conventional method, f1 and f2 are theswitching frequencies of the proposed method under fullload with low and high ac line conditions, respectively,and k is a constant;
2) the turn-ON time ton is reverse proportion to the switchingperiod Tsw .
In Fig. 8, the rms current of the drain during one switchingperiod can be calculated as
IDS.rms =
√1
Tsw
∫ to n
0
(Vin
Lmt
)2
dt =Vin
Lm· ton ·
√ton
3Tsw(16)
where Vin is almost constant during one switching period. Then,the instantaneous rms current can be expressed as
IDS.rms(t) =√
2Vac sin ωt
Lm· ton ·
√D
3. (17)
From (17), the rms current during half of the ac line period isobtained by
IDS.rms =
√2
Tac
∫ Ta c /2
0IDS.rms(t)2dt =
Vac
Lm· ton ·
√D
3.
(18)Table II shows conduction loss comparison between the con-
stant frequency DCM method and the proposed method under
MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK AC–DC CONVERTER 4057
Fig. 10. Peak current and conduction loss ratios with k.
full load with low ac line condition. It shows that the conductionloss of the proposed method is reduced by 1/
√k.
As shown in Fig. 5(b) and (e), the peak current of the conven-tional method in high ac line is the same as that in a low ac line.However, in the proposed method, the peak current in a high acline is given by
Ipk.high =√
k · Ipk (19)
where Ipk.high is peak current in the high ac line of the proposedmethod and Ipk is peak current in the conventional method. Theequation shows that the proposed method has the disadvantageof higher peak current. The peak current and the conductionloss ratios between the proposed and conventional methods areshown in Fig. 10. The more k increases, the lower the conductionloss and the higher the peak current become. Thus, k should bedesigned with a trade off between the conduction loss and thepeak current.
C. Transformer Design
In Fig. 8, the DCM single-stage flyback converter draws aninput power related to the drain peak current squared. Therefore,the instantaneous input power can be expressed as
Pin(t) =12Lm · I2
pk(t)fsw =V 2
ac · t2on · fsw
Lm· sin2 ωt. (20)
From (20), considering the efficiency η and interleaving op-eration, the average input power over half of the ac line periodis obtained by
Pin =Pout
η=
V 2ac · t2on · fsw
Lm. (21)
Therefore, the magnetizing inductance for the worst case canbe designed as
Lm ≤V 2
a c. l ow
· t2on · fsw · ηPout
(22)
where Vac.low is the low ac line voltage in rms.The turns ratio N is required to prevent current distortion due
to undesired continuous conduction mode operation around the
Fig. 11. Switch network.
peak ac line voltage. Thus, the turns ratio is designed by
N >
√2V a c
. l ow
Vo· Dmax
1 − Dmax. (23)
In the proposed converter, the IDS.peak in high ac line ishigher than that in low ac line. Thus, the minimum number ofturns for the primary side to avoid core saturation is given by
NminP >
Lm · IDS.peak@high line
Bsat · Ae× 106 (24)
where Bsat is the saturation flux density in tesla and Ae is theeffective cross-sectional area in mm2 .
IV. SMALL-SIGNAL MODELING AND STABILITY
Since the proposed converter operates in DCM, a small-signalDCM model is needed to prove stability. In this section, a small-signal model of the proposed converter is derived by the DCMswitch network [16], [17]. Because in the proposed controlmethod, two flyback converters operate in interleaving method,small-signal models of the converters are the same. Consideringthe upper side flyback converter of Fig. 2, the general two-switchnetwork is illustrated in Fig. 11. The averaged terminal voltagesand currents of the switch network in the DCM are obtained as
〈v1(t)〉ts (t) = 〈vin(t)〉ts (t)
〈v2(t)〉ts (t) = 〈vo(t)〉ts (t)
〈i1(t)〉ts (t) =d2
1(t)ts(t)2Lm1
· 〈v1(t)〉ts (t)
〈i2(t)〉ts (t) =d2
1(t)ts(t)2Lm1
·〈v1(t)〉2ts (t)
〈v2(t)〉ts (t)(25)
where d1(t) is duty cycle and ts(t) is switching period of Q1 . Inthe proposed control method, since not only d1(t), but also ts(t)is time varying, the averaged current have four variables. Theaveraged large-signal model of two-switch network in DCMis illustrated in Fig. 12. The averaged transistor is modeled asan effective resistor, and the averaged diode is modeled as apower source, equal to consumption in the effective resistor.However, the averaged switch network is nonlinear. Therefore,the small-signal modeling of the converter needs perturbationand linearization.
In the conventional pulsewidth pulse frequency modulationcontrol method [18]–[21] which changes both duty cycle andfrequency, there are two independent duty cycle and frequencyloops. Therefore, to obtain the small-signal switch networkequations, (25) should be expanded in a 4-D Taylor series. It
4058 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
Fig. 12. Averaged large-signal model.
is difficult and complicated. On the other hand, in the proposedcontrol method, from (1), duty cycle can be expressed by
d1(t) =m
t2s (t). (26)
The duty cycle is not independent but inverse proportionalto switching period squared. As a result, the proposed controlmethod seems to have single loop, and the small-signal switchnetwork can be expressed in a 3-D Taylor series as the equationof the conventional DCM flyback converter. So, the small-signalswitch network equations of i1 and i2 can be written by
∧i1 =
∧v1
r1+ j1
∧d +g1
∧v2
∧i2 = −
∧v2
r2+ j2
∧d +g2
∧v1 . (27)
The parameters r1 , j1 , g1 , r2 , j2 , and g2 can be found by Tay-lor expansion about quiescent operating point as follows:
〈i1(t)〉ts (t) =d
321 (t)
√m
2Lm1· 〈v1(t)〉ts (t)
= f1(〈v1(t)〉ts (t) , 〈v2(t)〉ts (t) , d1(t)
)I1 +
∧i1(t) = f1(V1 , V2 , D) +
∧v1
∂f1(v1 , V2 , D)∂v1
∣∣∣∣v1 =V1
+∧v2
∂f1(V1 , v2 , D)∂v2
∣∣∣∣v2 =V2
+∧d1(t)
∂f1(V1 , V2 , d)∂d
∣∣∣∣d1 =D
+ higher order nonlinear terms. (28)
〈i2(t)〉ts (t) =d
321 (t)
√m
2Lm1·〈v1(t)〉2ts (t)
〈v2(t)〉ts (t)
= f2(〈v1(t)〉ts (t) , 〈v2(t)〉ts (t) , d1(t)
)I2 +
∧i2(t) = f2(V1 , V2 , D) +
∧v1
∂f2(v1 , V2 , D)∂v1
∣∣∣∣v1 =V1
+∧v2
∂f2(V1 , v2 , D)∂v2
∣∣∣∣v2 =V2
+∧d1(t)
∂f2(V1 , V2 , d)∂d
∣∣∣∣d1 =D
Fig. 13. Small-signal model of the proposed converter.
+ higher order nonlinear terms. (29)
So, the first-order linear ac parameters r1 , j1 , g1 , r2 , j2 , andg2 are given by
r1 =2Lm1
D32√
m
g1 = 0
j1 =3√
D · m · V1
4Lm1. (30)
r2 =2Lm1 · V 2
2
D32√
m · V 21
g2 =D
32√
m · V1
Lm1 · V2
j2 =3√
D · m · V 21
4Lm1V2. (31)
As shown in Fig. 13, a small-signal model of the proposedconverter is obtained by replacing the MOSFET and diode withthe switch network model.
The control-to-output transfer function of the proposed con-verter has two poles and a right half-plane (RHP) zero. One polecaused by Co appears at low frequency. But the other pole dueto the Lm1 and a RHP zero occur at higher frequency aboutswitching frequency. Therefore, by low-frequency approxima-tion, the proposed converter regards as single-pole system. Inlow frequency, since Lm1 seems to be short, a low-frequency ap-proximation ac model is obtained as shown in Fig. 14. Therefore,the control-to-output transfer function Gvd(s) and the line-to-output transfer function Gvg (s) are obtained as
Gvd(s) =∧vo
∧d
∣∣∣∣∣ ∧v in =0
=j2(Ro ‖ r2)
1 + sωp
Gvg (s) =∧vo
∧vg
∣∣∣∣∣∧d=0
=g2(Ro ‖ r2)
1 + sωp
ωp =1
(Ro ‖ r2)Co. (32)
In (32), the control-to-output transfer function of the pro-posed converter has one pole at low frequency like conventionalDCM flyback converter, so that the converter can have enoughphase margin. It makes easy to build the compensation net-work. Usually, proportional and integral controller is enough for
MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK AC–DC CONVERTER 4059
Fig. 14. Low-frequency approximation ac model.
Fig. 15. Bode plot of the control-to-output transfer function, when Vin =90 Vac , Vo = 90 V, d1 = 0.4979, fs = 100 kHz, Lm 1 = 215 μH, Co =1410 μF, Ro = 100 Ω.
TABLE IIISPECIFICATIONS OF PROTOTYPE
Input voltage 90 ~ 265 Vac
Output voltage 9 ~ 90 Vdc
Output load current 900 mA
Output power 8.1 ~ 81 W
Switches (Q1, Q2) FQA13N80
Diodes (D5, D6) FFPF10U40S
LED unit 3 V, 300 mA
The proposed ISSF and 67 kHz ISSF
Magnetizing inductance (Lm1, Lm2) 215 µH
Turns ratio (Np : Ns) 29 : 14
The 67 kHz single-stage flyback
Magnetizing inductance (Lm1) 180 µH
Turns ratio (Np : Ns) 21 : 10
The two-stage boost-flyback
CRM boost inductance (L) 387 µH
Flyback magnetizing inductance (Lm1) 1452 µH
Turns ratio (Np : Ns) 49 : 25
Flyback switching frequency (fsw) 67 kHz
compensation. The Bode plot of Gvd(s) is illustrated in Fig. 15.In practice, the second pole caused by Lm1 and the RHP zero areplaced around several tens kilohertz. However, the bandwidthof the controller of the proposed system should be narrow to
Fig. 16. LED configuration.
Fig. 17. Waveforms with 265 Vac and full load condition.
achieve high power factor. Therefore, the second pole and RHPzero cannot affect the converter system.
V. EXPERIMENTAL RESULTS
A prototype of the proposed converter is implemented withthe specifications shown in Table III. For fair comparison,the inductance and turns ratio should similar among the con-verters. However, unfortunately, the converters have differenttopologies and control methods so that it is hard to designsimilar value. Though the proposed and conventional convertershave different inductance and turns ratio, they are designedoptimally. The LED units are configured as shown in Fig. 16.Since the number of LEDs in series varies according to LEDapplications, the range of output voltage is wide. Minimumoutput voltage is for low power applications such as the outdoorpot light and maximum output voltage is set for high powerapplication like the flood light. To evaluate the validity ofthe proposed converter, 67-kHz constant frequency single-stage DCM flyback converter, two-stage CRM boost-flyback
4060 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
Fig. 18. Experimental waveforms of the proposed converter. (a) 90 Vac fullload condition. (b) 265 Vac full load condition. (c) 90 Vac 10% load condition.(d) 265 Vac 10% load condition.
converter, and 67-kHz constant frequency ISSF converter arealso constructed and experimented on.
The interleaving operation of the proposed control method isillustrated in Fig. 17 with 265 Vac and full load condition. Fig. 18shows the experimental waveforms of the proposed converter.
Fig. 19. Efficiency, PF, and THD comparison at 90 Vac . (a) Efficiency.(b) PF. (c) THD.
Fig. 18(a) and (b) shows the waveforms of 90 Vac and 265 Vacunder the full load condition, respectively. The line current Ilineis a sinusoidal waveform and has same phase as the line voltageVline . The peak drain current IDS1 .peak at 265 Vac is higher thanthat at 90 Vac due to lower switching frequency. This needs tobe considered when the transformer is designed. Fig. 18(c) and(d) shows that the proposed converter still has the sinusoidalwaveform of Iline even if the load condition is very light.
Fig. 19 shows the efficiency, PF, and THD of the proposedISSF converter, constant frequency ISSF converter, single-stageDCM flyback converter, and two-stage CRM boost-flyback con-verter at 90 Vac . Under the 100% load condition, the proposedconverter shows higher efficiency than the other converters be-cause of the low rms current with high switching frequency. ThePF and THD are good in all of the converters due to the low
MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK AC–DC CONVERTER 4061
Fig. 20. Efficiency, PF, and THD comparison at 265 Vac . (a) Efficiency.(b) PF. (c) THD.
ac line voltage. Usually in low ac line, the input current is lessdistorted due to relatively high drain current.
Fig. 20 shows the efficiency, PF, and THD at 265 Vac . InFig. 20(a), the proposed converter shows higher efficiency thanother converters under light load condition due to lower switch-ing frequency. For the PF and THD, light load with high acline condition is the worst case due to the low drain current.Therefore, the converter for wide output power range shouldhave high PF and low THD under that condition. Fig. 20(b)and (c) show that the proposed converter has high PF and lowTHD under light load with high ac line condition. Thus, the pro-posed converter is suitable for wide output power range LEDapplications.
Fig. 21. LEDs current ripple.
Fig. 21 shows the current ripple of the LEDs. To reducethe invisible flicker problem, the current ripple caused by theline frequency should be low. The results show that the two-stage configuration is the best solution for the invisible flickerproblem and that there is no current ripple cancelation even ifthe interleaving control method is applied.
VI. CONCLUSION
The PDPFM control method for an ISSF converter has beenproposed in this paper. The proposed control method increasesthe switching frequency, the turn-ON time and the duty cycleunder heavy load with low ac line condition for low rms currentand it decreases under light load with high ac line condition forlow switching loss. Therefore, the proposed converter has highefficiency for wide input voltage and output load ranges. Fur-thermore, the proposed converter is operated in DCM so that itcan achieve high PF and low THD for wide output power range.The operational principles, design considerations, and small-signal modeling have been presented. Because the proposedconverter has higher peak current than the conventional convert-ers at high ac line, it should be considered when the transformeris designed. To verify the validity of the proposed converter, an81-W prototype was implemented and experimented on. Theresults showed that the proposed converter has high efficiency,high PF, and low THD. Therefore, the proposed converter isconsiderably suitable for wide output range LED applications.
REFERENCES
[1] “Electromagnetic compatibility(EMC),” Part 3, International StandardIEC61000-3-2, 2001.
[2] Y.-C. Chuang, Y.-L. Ke, H.-S. Chuang, and C.-C. He, “Single-stage power-factor-correction circuit with flyback converter to drive LEDs for lightingapplications,” in Proc. IEEE Ind. Appl. Soc. Annu. Meeting, 2010, pp. 1–9.
[3] R. Redl and L. Balogh, “Design considerations for single-stage isolatedpower-factor-corrected power supplies with fast regulation of the outputvoltage,” in Proc. IEEE Appl. Power Electron. Conf., 1995, vol. 1, pp. 454–458.
[4] L. Huber and M. M. Jovanovic, “Single-stage single-switch input-current-shaping technique with reduced switching loss,” IEEE Trans. Power Elec-tron., vol. 15, no. 4, pp. 681–687, Jul. 2000.
[5] K.-H. Liu and Y.-L. Lin, “Current waveform distortion in power convert-ers,” in Proc. IEEE Power Electron. Spec. Conf., 1989, pp. 825–829.
[6] D. Gacio, J. M. Alonso, A. J. Calleja, J. Garcia, and M. R. Secades,“A universal-input single-stage high-power-factor power supply for HB-LEDs based on integrated buck-flyback converter,” IEEE Trans. Ind. Elec-tron., vol. 58, no. 2, pp. 589–599, Feb. 2011.
4062 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
[7] J. A. Villarejo, J. Sebastian, F. Soto, and E. de Jodar, “Optimizing the de-sign of single-stage power-factor correctors,” IEEE Trans. Ind. Electron.,vol. 54, no. 3, pp. 1472–1482, Jun. 2007.
[8] V. F. Pires and J. F. Silva, “Single-stage double-buck topologies with highpower factor,” J. Power Electron., vol. 11, no. 5, pp. 655–661, Sep. 2011.
[9] F. Tao and F. C. Lee, “An interleaved single-stage power-factor-correctionelectronic ballast,” in Proc. IEEE Appl. Power Electron. Conf., 2000,vol. 1, pp. 617–623.
[10] J. Zhang, F. C. Lee, and M. M. Jovanovic, “A novel interleaveddiscontinuous-current-mode single-stage power-factor-correction tech-nique with universal-line input,” in Proc. IEEE Power Electron. Spec.Conf., 2001, vol. 2, pp. 1007–1012.
[11] D. Wang, X. He, and J. Shi, “Design and analysis of an interleaved flyback-forward boost converter with the current autobalance characteristic,” IEEETrans. Power Electron., vol. 25, no. 2, pp. 489–498, Feb. 2010.
[12] Y.-C. Hsieh, M.-R. Chen, and H.-L. Cheng, “An interleaved flyback con-verter featured with zero-voltage transition,” IEEE Trans. Power Electron.,vol. 26, no. 1, pp. 79–84, Jan. 2011.
[13] K. I. Hwu and Y. T. Yau, “An interleaved AC-DC converter based oncurrent tracking,” IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1456–1463, May 2009.
[14] H.-Y. Li, H.-C. Chen, and L.-K. Chang, “Analysis and design of a single-stage parallel AC-to DC converter,” IEEE Trans. Power Electron., vol. 24,no. 12, pp. 2989–3002, Dec. 2009.
[15] W. Wang, X. Zhang, and D. Xu, “Novel interleaved single-stage AC/DCconverter with a high power factor and high efficiency,” J. Power Electron.,vol. 11, no. 3, pp. 245–255, May 2011.
[16] V. Vorperian, “Simplified analysis of PWM converters using the modelof the PWM switch part I and II,” IEEE Trans. Aerosp. Electron. Syst.,vol. 26, no. 3, pp. 490–505, May 1990.
[17] J. Sun, D. M. Mitchell, M. Greuel, P. T. Krein, and R. M. Bass, “Aver-aged modeling of PWM converters operating in discontinuous conductionmode,” IEEE Trans. Power Electron., vol. 16, no. 4, pp. 482–492, Jul.2001.
[18] J. Sebastian and J. Uceda, “The double converter: A fully regulated two-output dc-dc converter,” IEEE Trans. Power Electron., vol. PE-2, no. 3,pp. 239–246, Jul. 1987.
[19] H. H. Seong, D. J. Kim, and G. H. Cho, “A new ZVS DC/DC converterwith fully regulated dual outputs,” in Proc. IEEE Power Electron. Spec.Conf., 1993, pp. 351–356.
[20] H. E. Tacca, “Single-switch two-output flyback-forward converter oper-ation,” IEEE Trans. Power Electron., vol. 13, no. 5, pp. 903–911, Sep.1998.
[21] Y. Chen and Y. Kang, “A fully regulated dual-output dc-dc converterwith special-connected two transformers (SCTTs) cell and complemen-tary pulse width modulation-PFM (CPWM-PFM),” IEEE Trans. PowerElectron., vol. 25, no. 5, pp. 1296–1309, May 2010.
[22] B. Tamyurek and D. A. Torrey, “A three-phase unity power factor single-stage AC-DC converter based on an interleaved flyback topology,” IEEETrans. Power Electron., vol. 26, no. 1, pp. 308–318, Jan. 2011.
[23] F. Yang, X. Ruan, Y. Yang, and Z. Ye, “Interleaved critical current modeboost PFC converter with couped inductor,” IEEE Trans. Power Electron.,vol. 26, no. 9, pp. 2404–2413, Sep. 2011.
[24] S. Park, Y. Park, S. Choi, W. Choi, and K. B. Lee, “Soft-switched inter-leaved boost converters for high step-up and high-power applications,”IEEE Trans. Power Electron., vol. 26, no. 10, pp. 2906–2914, Oct. 2011.
[25] Y. Hu, L. Huber, and M. M. Jovanovic, “Single-stage, universal-inputAC/DC LED driver with current-controlled variable PFC boost inductor,”IEEE Trans. Power Electron., vol. 27, no. 3, pp. 1579–1588, Mar. 2012.
[26] J. Turchi, “Power factor correction stages operated in critical conductionmode,” ON Semiconductor, Phoenix, AZ, Appl. Note no. AND8123/D,2003.
[27] C. P. Basso, Switch-Mode Power Supplies—SPICE Simulations and Prac-tical Designs. New York: McGraw-Hill, 2008.
[28] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics.Norwell, MA: Kluwer, 2001.
SangCheol Moon (S’10) was born in Jeju Island, Ko-rea, in 1979. He received the B.S. degree in electricalengineering from Ajou University, Suwon, Korea, in2005, and the M.S. degree in electrical engineeringfrom Korea Advanced Institute of Science and Tech-nology, Daejeon, Korea, in 2007, where he is cur-rently working toward the Ph.D. degree in electricalengineering.
In 2007, he joined Fairchild Semiconductor,Bucheon, Korea, as a System and Application Engi-neer. His research interests include power electronics
including analysis, modeling, control method, power factor correction, LEDs,and wireless power transfer circuit.
Gwan-Bon Koo was born in Seoul, Korea, in 1975.He received the B.S., M.S., and Ph.D. degrees in elec-trical engineering from the Korea Advanced Instituteof Science and Technology, Daejeon, Korea, in 1997,1999, and 2004, respectively.
He is currently a Principal Engineer with FairchildKorea Semiconductor, Ltd., Bucheon, Korea. His re-search interests include the areas of power electron-ics and control, including analysis, modeling, anddesign of high-performance power converters, soft-switching power converters, power factor correction,
and resonant converters. His research interests also include battery managementsystem, piezoelectric driver, and LED lighting system.
Gun-Woo Moon (S’92–M’00) received the M.S.and Ph.D. degrees in electrical engineering from theKorea Advanced Institute of Science and Technol-ogy (KAIST), Daejeon, Korea, in 1992 and 1996,respectively.
He is currently a Professor in the Department ofElectrical Engineering, KAIST. His research inter-ests include modeling, design, and control of powerconverters, soft-switching power converters, resonantinverters, distributed power systems, power factorcorrection, electric drive systems, driver circuits of
plasma display panels, and flexible ac transmission systems.Dr. Moon is a Member of the Korean Institute of Power Electronics, Korean
Institute of Electrical Engineers, Korea Institute of Telematics and Electronics,Korea Institute of Illumination Electronics and Industrial Equipment, and Soci-ety for Information Display.
