ACER ACER Aspire V5-531p

55

4

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3

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2

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1

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C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

Husk/Petra -4MCover Page

A3

1 103Thursday, September 06, 2012

DIS IVB Touch

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DIS IVB Touch

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DIS IVB Touch

ANNIE: ONLY FOR ANNIE solution.PSL: KBC795 PSL circuit for 10mW solution installed.10mW: External circuit for 10mW solution installed.65W: for 65W adaptor installed.90W: for 90W adaptor installed.

DY :None InstalledDIS:DIS installedDIS_Muxless :BOTH DIS or Muxless installedDIS_PX:BOTH DIS or PX installedDIS_PX_Muxless:DIS or PX or Muxless installed.Muxless: Muxless installed.(PX4.0)PX:MUX installed.(PX3.0)PX_Muxless:BOTH PX or Muxless installed.UMA:UMA installedUMA_Muxless:BOTH UMA or Muxless installedUMA_PX_Muxless:UMA or PX or Muxless installed

Intel PCH

UMA/Muxless Schematics DocumentIvy Bridge

Husk/Petra

55

4

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3

3

2

2

1

1

D D

C C

B B

A A

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Husk/Petra -4MBlock Diagram

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DIS IVB Touch

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DIS IVB Touch

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DIS IVB Touch

286925

69

PCIE x 1+ USB x 1

60 71LPC debug port

Nvidia N13P-GL16 lane/128bit/29x29mm

Project code : 91.4TU01.001PCB P/N : Revision : -4M

NCT 7718W

ALC271X

DMIx4

LAN

S

P

I

Flash ROM8MB

51HDMIHDMI

88,89,90,91

83.84,85,86,87

RTL8411

KBC

ThermalInt. KB

L

P

C

B

u

s

DDRIII1600/1333

Intel CPU17W/GT2 DDRIII 1333/1600 Channel A Slot 0

14

4,5,6,7,8,9,10,11,12,13

Husk and Petra Block Diagram (Optimus/UMA/co-lay)

Left Side:USB x 1

CAMERA 49

Mini-Card and BT802.11a/b/g

LVDS Intel

56

LCD

ODD

56

4 USB 3.0 / 14 USB 2.0/1.1 ports

High Definition Audio

SATA

SATA ports (6)

ACPI 1.1LPC I/F

HDD

SD/MMC

AzaliaCODEC

USB2.0 x 2

29

SPEAKER

COMBO

Internal Analog MIC

ETHERNET (10/100/1000Mb)

PCIE ports (8)

NPCE885

28

DDR3900MHz

1GByte

Fan

VRAM

27

49

17,18,19,20,21,22,23,24,25,26

PCIe x 16(Gen2_5Gb/s)

TouchPAD

FDIx4x2(UMA only)

AZALIA

65

31

(Muxless)

SMBus

PCIE x 1

Ivy BridgeSandy Bridge

PCH:HM70/77Panther Point

(USB2.0 + USB3.0)

(SATA3_6Gb/s)

62

74

BT+

40

OUTPUTSBQ24727

INPUTS

CHARGER

DCBATOUT

3D3V_AUX_S5

RT8223MGQW

DCBATOUT 5V_S5

OUTPUTS

3D3V_S5

SYSTEM DC/DC

INPUTS5V_AUX_S5

41

42~43ISL95836HRTZINPUTS

VCC_COREOUTPUTS

CPU DC/DC

DCBATOUT

VCC_GFXCORE

ISL95836HRTZ

DCBATOUTOUTPUTS

SYSTEM DC/DC

INPUTS44

1D05V_VTT

TPS51218DSCROUTPUTS

DCBATOUTINPUTS

SYSTEM DC/DC45

0D75V_S0

SYSTEM DC/DCRT8207LGQW

DDR_VREF_S3

OUTPUTS1D5V_S3

INPUTS

DCBATOUT

46

26

INPUTS

LDO

OUTPUTSRT9025-25ZSP

3D3V_S0 1D8V_S0

47

G978INPUTS OUTPUTS

LDO48

INPUTS

VGA

DCBATOUTOUTPUTS

ISL62882CHRTZ

VGA_CORE

92

1D05_VTT 0D85V_S0

INPUTS OUTPUTS

1D05V_VTT 1D05V_VGA_S0

1D5V_S3 1D5V_VGA_S0

Switches

263D3V_VGA_S03D3V_S0

93

PCB LAYERL1:TopL2:VCCL3:Signal

L4:SignalL5:GNDL6:Bottom

eDP

co-lay

USB2.0 x 261

Left Side:USB x 2

Feature Port(CRT+LAN)

MDI

50

DDRIII1600/1333

DDRIII 1333/1600 Channel A Slot 115

Touch Sensor49

RGB

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

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Husk/Petra -4MTable of Content

A3


DIS IVB Touch

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DIS IVB Touch

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DIS IVB Touch

PCIE Routing

LANE2

LANE3 Card Reader Onboard LANLANE4

Mini Card1(WLAN)SATA Table

PairSATA

Device

0

5

4

32

1

HDD1

ODD

N/AHDD2

N/A

ESATA

LANE1 Mini Card2(WWAN)

LANE5

LANE6

LANE7

LANE8 New Card

Intel GBE LAN

CFG[6:5]

CFG[7]

Processor Strapping

CFG[2]

Disabled - No Physical Display Port attached toEmbedded DisplayPort.CFG[4]

Pin Name Strap Description Configuration (Default value for each bit is 1 unless specified otherwise)

1:

Huron River Schematic Checklist Rev.0_7

0:PCI-Express StaticLane Reversal

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

DefaultValue

PCI-ExpressPort BifurcationStraps

11 : x16 - Device 1 functions 1 and 2 disabled10 : x8, x8 - Device 1 function 1 enabled ;function 2 disabled01 : Reserved - (Device 1 function 1 disabled ;function 2 enabled)00 : x8, x4, x4 - Device 1 functions 1 and 2enabled

PEG DEFER TRAINING

1

0

1

1:

0:Enabled - An external Display Port device isconnectd to the EMBEDDED display Port

11

1:0: PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

SPKRName Schematics Notes

HAD_DOCK_EN#/GPIO[33]

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

HDA_SYNC

Huron River Schematic Checklist Rev.0_7

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

GNT3#/GPIO55GNT2#/GPIO53GNT1#/GPIO51

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-downusing a 1k +/- 5% resistor. When this signal is sampled high at the rising edge ofRSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode isenabled.

PCH Strapping

SPI_MOSI

Internal weak Pull-down. Connect to Vcc3_3 with 8.2-k- 10-k weak pull-up resistor.

NV_ALE

Enable Danbury:

Disable Danbury:

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

GPIO15

GPIO8

Reboot option at power-upDefault Mode:No Reboot Mode with TCO Disabled:

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

Low (0) - Flash Descriptor Security will be overridden. Also,when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.High (1) - Security measure defined in the Flash Descriptor will be enabled.Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND asrequired by the functional strap, the signal should be pulled low through a weakpull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internalpull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset forstrapping functions.

GPIO27

Default = Do not connect (floating)High(1) = Enables the internal VccVRM to have a clean supply foranalog rails. No need to use on-board filter circuit.Low (0) = Disables the VccVRM. Need to use on-board filtercircuits for analog rails.

Voltage RailsVOLTAGE DESCRIPTION

ACTIVE INPOWER PLANE

CPU Core RailGraphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

3D3V_AUX_KBC

3.3V

DSW, Sx ON for supporting Deep Sleep states

S0

S3

All S states

WOL_EN

G3, Sx

5V_S03D3V_S01D8V_S01D5V_S01D05V_VTT0D85V_S00D75V_S0VCC_COREVCC_GFXCORE1D8V_VGA_S03D3V_VGA_S01V_VGA_S0

5V3.3V1.8V1.5V1.05V0.95 - 0.85V0.75V0.35V to 1.5V0.4 to 1.25V1.8V3.3V1V

5V1.5V0.75V

5V_USBX_S31D5V_S3DDR_VREF_S3

BT+DCBATOUT5V_S55V_AUX_S53D3V_S53D3V_AUX_S5

6V-14.1V6V-14.1V5V5V3.3V3.3V

3.3V3D3V_LAN_S5

3.3V

3D3V_AUX_S5

GNT[3:0]# functionality is not available on Mobile.Mobile: Used as GPIO onlyPull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with noconfidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentialityNote : This is an un-muxed signal.This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#.CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLK

Device

I C / SMBus Addresses2

EC SMBus 1BatteryCHARGER

EC SMBus 2PCHeDP

PCH SMBusSO-DIMMA (SPD)SO-DIMMB (SPD)Digital PotG-SensorMINI

BAT_SCL/BAT_SDA

SMBus ADDRESSES

HURON RIVER ORBAddress Hex Bus Ref Des

USB3.0

Dock

USB Table

13

EDP CAMERA

12

X

Mini Card1 (WLAN)

Fingerprint

X

New Card

USB Ext. port 2

10

0

11

USB Ext. port 1 (HS)

Pair

4

5

2

3

1

Device

67

89

BLUETOOTH

Touch Panel / 3G SIM

CARD READER

USB Ext. port 4 / E-SATA /USB CHARGER

CAMERA

Mini Card2 (WWAN) BAT_SCL/BAT_SDABAT_SCL/BAT_SDA

SML1_CLK/SML1_DATASML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK

PCH_SMBDATA/PCH_SMBCLK

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PEG_C_TXN3

PEG_C_TXN15

PEG_C_TXN10

PEG_C_TXN5

PEG_C_TXN0

PEG_C_TXN12

PEG_C_TXN7

PEG_C_TXN2

PEG_C_TXN14

PEG_C_TXN9

PEG_C_TXN4

PEG_C_TXN11

PEG_C_TXN6

PEG_C_TXN1

PEG_C_TXN13

PEG_C_TXN8

PEG_RXN5PEG_RXN4PEG_RXN3PEG_RXN2PEG_RXN1

PEG_RXP5

PEG_RXN0

PEG_RXP4PEG_RXP3PEG_RXP2PEG_RXP1PEG_RXP0

PEG_RXP15

PEG_RXN15PEG_RXN14

PEG_RXP14PEG_RXP13PEG_RXP12

PEG_RXN13PEG_RXN12

PEG_RXP11

PEG_RXN11

PEG_RXP10

PEG_RXN10

PEG_RXP9

PEG_RXN9

PEG_RXP8

PEG_RXN8

PEG_RXP7PEG_RXP6

PEG_RXN7PEG_RXN6

PEG_IRCOMP_R

PEG_C_TXP3

PEG_C_TXP15

PEG_C_TXP10

PEG_C_TXP5

PEG_C_TXP0

PEG_C_TXP12

PEG_C_TXP7

PEG_C_TXP2

PEG_C_TXP14

PEG_C_TXP9

PEG_C_TXP4

PEG_C_TXP11

PEG_C_TXP6

PEG_C_TXP1

PEG_C_TXP13

PEG_C_TXP8

PEG_TXN0PEG_TXN1PEG_TXN2PEG_TXN3PEG_TXN4PEG_TXN5PEG_TXN6PEG_TXN7PEG_TXN8PEG_TXN9PEG_TXN10PEG_TXN11PEG_TXN12PEG_TXN13PEG_TXN14PEG_TXN15

PEG_TXP15PEG_TXP14PEG_TXP13PEG_TXP12PEG_TXP11PEG_TXP10PEG_TXP9PEG_TXP8PEG_TXP7PEG_TXP6PEG_TXP5PEG_TXP4PEG_TXP3PEG_TXP2PEG_TXP1PEG_TXP0

DP_COMP

FDI_TXP4FDI_TXP5

DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3

DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3

DMI_RXN0DMI_RXN1DMI_RXN2DMI_RXN3

DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3

FDI_TXP6FDI_TXP7

FDI_TXN0FDI_TXN1

FDI_TXN3FDI_TXN4FDI_TXN5FDI_TXN6FDI_TXN7

FDI_TXN2

FDI_TXP0FDI_TXP1FDI_TXP2FDI_TXP3

DP_HPD#

1D05V_VTT_CPU

1D05V_VTT_CPU PEG_TXP[0..15] 83

PEG_TXN[0..15] 83

PEG_RXP[0..15] 83

PEG_RXN[0..15] 83

DMI_RXN[3:0]19

DMI_RXP[3:0]19

DMI_TXN[3:0]19

DMI_TXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019FDI_FSYNC119

FDI_INT19

FDI_LSYNC019FDI_LSYNC119

DP_HPD#49

DP_AUXP_CPU49DP_AUXN_CPU49

DP_TXP0_CPU49DP_TXP1_CPU49

DP_TXN0_CPU49DP_TXN1_CPU49

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Husk/Petra -4MCPU (PCIE/DMI/FDI)

A3


DIS IVB Touch

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DIS IVB Touch

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DIS IVB Touch

SSID = CPU

C408 SCD22U10V2KX-1GPMuxlessC408 SCD22U10V2KX-1GPMuxless1 2C409 SCD22U10V2KX-1GPMuxlessC409 SCD22U10V2KX-1GPMuxless1 2

C420 SCD22U10V2KX-1GPMuxlessC420 SCD22U10V2KX-1GPMuxless1 2


R403Do Not StuffDY

R403Do Not StuffDY

1

2






R40124D9R2F-L-GPR40124D9R2F-L-GP

1 2




R402 24D9R2F-L-GPR402 24D9R2F-L-GP1 2

P

C

I

E

X

P

R

E

S

S

-

-

G

R

A

P

H

I

C

S

DMI

Intel(R) FDI

eDP

1 OF 9CPU1A

IVY-BRIDGE-GP-NF

71.00IVY.A0U

P

C

I

E

X

P

R

E

S

S

-

-

G

R

A

P

H

I

C

S

DMI

Intel(R) FDI

eDP

1 OF 9CPU1A

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DMI_RX#0M2DMI_RX#1P6DMI_RX#2P1DMI_RX#3P10

DMI_RX0N3DMI_RX1P7DMI_RX2P3DMI_RX3P11

DMI_TX#0K1DMI_TX#1M8DMI_TX#2N4DMI_TX#3R2

DMI_TX0K3DMI_TX1M7

DMI_TX3T3DMI_TX2P4

FDI0_TX#0U7FDI0_TX#1W11FDI0_TX#2W1FDI0_TX#3AA6FDI1_TX#0W6FDI1_TX#1V4FDI1_TX#2Y2FDI1_TX#3AC9

FDI0_TX0U6FDI0_TX1W10FDI0_TX2W3FDI0_TX3AA7FDI1_TX0W7FDI1_TX1T4FDI1_TX2AA3FDI1_TX3AC8

FDI0_FSYNCAA11FDI1_FSYNCAC12

FDI_INTU11

FDI0_LSYNCAA10FDI1_LSYNCAG8

PEG_ICOMPI G3PEG_ICOMPO G1

PEG_RCOMPO G4

PEG_RX#0 H22PEG_RX#1 J21PEG_RX#2 B22PEG_RX#3 D21PEG_RX#4 A19PEG_RX#5 D17PEG_RX#6 B14PEG_RX#7 D13PEG_RX#8 A11PEG_RX#9 B10

PEG_RX#10 G8PEG_RX#11 A8PEG_RX#12 B6PEG_RX#13 H8PEG_RX#14 E5PEG_RX#15 K7

PEG_RX0 K22PEG_RX1 K19PEG_RX2 C21PEG_RX3 D19PEG_RX4 C19PEG_RX5 D16PEG_RX6 C13PEG_RX7 D12PEG_RX8 C11PEG_RX9 C9

PEG_RX10 F8PEG_RX11 C8PEG_RX12 C5PEG_RX13 H6PEG_RX14 F6PEG_RX15 K6

PEG_TX#0 G22PEG_TX#1 C23PEG_TX#2 D23PEG_TX#3 F21PEG_TX#4 H19PEG_TX#5 C17PEG_TX#6 K15PEG_TX#7 F17PEG_TX#8 F14PEG_TX#9 A15

PEG_TX#10 J14PEG_TX#11 H13PEG_TX#12 M10PEG_TX#13 F10PEG_TX#14 D9PEG_TX#15 J4

PEG_TX0 F22PEG_TX1 A23PEG_TX2 D24PEG_TX3 E21PEG_TX4 G19PEG_TX5 B18PEG_TX6 K17PEG_TX7 G17PEG_TX8 E14PEG_TX9 C15

PEG_TX10 K13PEG_TX11 G13PEG_TX12 K10PEG_TX13 G10PEG_TX14 D8PEG_TX15 K4

EDP_AUXAF4EDP_AUX#AG4

EDP_TX0AC1EDP_TX1AA4EDP_TX2AE10EDP_TX3AE6

EDP_COMPIOAF3

EDP_HPD#AG11EDP_ICOMPOAD2

EDP_TX#0AC3EDP_TX#1AC4EDP_TX#2AE11EDP_TX#3AE7


















55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XDP_DBRESET#

XDP_TDO

BUF_CPU_RST#

H_PROCHOT#

H_PROCHOT#_R

XDP_DBRESET#

BUF_CPU_RST#

XDP_TRST#XDP_TDO

SM_RCOMP_0SM_RCOMP_1SM_RCOMP_2

XDP_TRST#

1D05V_VTT_CPU

3D3V_S0

1D05V_VTT_CPU

H_PM_SYNC19

H_PECI22,27

CLK_EXP_P 20CLK_EXP_N 20

H_SNB_IVB#22

H_PROCHOT#27,42

H_THERMTRIP#22,36

H_CPUPWRGD22,36,97

VDDPWRGOOD37

PLT_RST#18,27,31,36,65,71,83,97

CLK_DP_P 20CLK_DP_N 20

SM_DRAMRST# 37

Title


Date: Sheet of


Husk/Petra -4M

CPU (THERMAL/CLOCK/PM )Custom


DIS IVB Touch

Title


Date: Sheet of


Husk/Petra -4M



DIS IVB Touch

Title


Date: Sheet of


Husk/Petra -4M



DIS IVB Touch

SSID = CPU

Signal Routing Guideline:SM_RCOMP keep routing length less than 500 mils.

R507 25D5R2F-GPR507 25D5R2F-GP1 2

RN503SRN1K5J-1-GPRN503SRN1K5J-1-GP1234 5

678

R508 200R2F-L-GPR508 200R2F-L-GP1 2

R50162R2J-GPR50162R2J-GP

1 2

RN501SRN51J-GPRN501SRN51J-GP

12 3

4

R51356R2J-L1-GP

R51356R2J-L1-GP1 2

C502SC47P50V2JN-3GPC502SC47P50V2JN-3GP

1

2 R5024K99R2F-L-GP

R5024K99R2F-L-GP1 2

C

L

O

C

K

S

MISC

THERMAL

PWR MANAGEMENT

D

D

R

3

M

I

S

C

J

T

A

G

&

B

P

M

2 OF 9CPU1B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

C

L

O

C

K

S

MISC

THERMAL

PWR MANAGEMENT

D

D

R

3

M

I

S

C

J

T

A

G

&

B

P

M

2 OF 9CPU1B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

SM_RCOMP1 BE43SM_RCOMP2 BG43

SM_DRAMRST# AT30

SM_RCOMP0 BF44

BCLK# H2BCLK J3

DPLL_REF_CLK# AG1DPLL_REF_CLK AG3

CATERR#C49

PECIA48

PROCHOT#C45

THERMTRIP#D45

SM_DRAMPWROKBE45

RESET#D44

PRDY# N53PREQ# N55

TCK L56TMS L55

TRST# J58

TDI M60TDO L59

DBR# K58

BPM#0 G58BPM#1 E55BPM#2 E59BPM#3 G55BPM#4 G59BPM#5 H60BPM#6 J59BPM#7 J61

PM_SYNCC48

PROC_DETECT#C57

PROC_SELECT#F49

UNCOREPWRGOODB46

R50310KR2J-L-GP

R50310KR2J-L-GP1 2

R506 140R2F-GPR506 140R2F-GP1 2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_A_DQS4M_A_DQS3

M_A_DQS5M_A_DQS6M_A_DQS7

M_A_DQS2M_A_DQS1M_A_DQS0

M_A_A7

M_A_A12

M_A_A14M_A_A13

M_A_A9

M_A_A15

M_A_A10

M_A_A0

M_A_A6

M_A_A8

M_A_A1M_A_A2M_A_A3M_A_A4M_A_A5

M_A_A11

M_A_DQS#4M_A_DQS#5M_A_DQS#6M_A_DQS#7

M_A_DQS#3M_A_DQS#2M_A_DQS#1M_A_DQS#0

M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_DQS#3M_B_DQS#2M_B_DQS#1M_B_DQS#0

M_B_DQS#7M_B_DQS#6M_B_DQS#5M_B_DQS#4

M_B_A5M_B_A6M_B_A7M_B_A8M_B_A9M_B_A10M_B_A11M_B_A12M_B_A13M_B_A14M_B_A15

M_B_A4M_B_A3M_B_A2M_B_A1M_B_A0

M_A_DQ[63:0]14M_B_DQ[63:0]15

M_A_DQS#[7:0] 14

M_A_A[15:0] 14

M_A_DQS[7:0] 14

M_A_DIM0_CKE0 14

M_A_DIM0_CKE1 14

M_A_DIM0_CS#0 14M_A_DIM0_CS#1 14

M_A_DIM0_ODT0 14M_A_DIM0_ODT1 14

M_A_DIM0_CLK_DDR0 14M_A_DIM0_CLK_DDR#0 14


M_B_A[15:0] 15

M_B_DQS[7:0] 15

M_B_DQS#[7:0] 15

M_B_DIM0_CKE0 15

M_B_DIM0_CKE1 15

M_B_DIM0_CS#0 15M_B_DIM0_CS#1 15

M_B_DIM0_ODT0 15M_B_DIM0_ODT1 15

M_B_DIM0_CLK_DDR0 15M_B_DIM0_CLK_DDR#0 15


M_A_BS014

M_A_CAS#14M_A_RAS#14M_A_WE#14

M_A_BS114M_A_BS214

M_B_CAS#15M_B_RAS#15M_B_WE#15

M_B_BS015M_B_BS115M_B_BS215

Title


Date: Sheet of


Husk/Petra -4MCPU (DDR)

A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

SSID = CPU

D

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A

3 OF 9CPU1C

IVY-BRIDGE-GP-NF

71.00IVY.A0U

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3 OF 9CPU1C

IVY-BRIDGE-GP-NF

71.00IVY.A0U

SA_CK0 AU36

SA_CK1 AT40

SA_CK#0 AV36

SA_CK#1 AU40

SA_CKE0 AY26

SA_CKE1 BB26

SA_CS#0 BB40SA_CS#1 BC41

SA_ODT0 AY40SA_ODT1 BA41

SA_DQS0 AJ11

SA_DQS#0 AL11

SA_DQS1 AR10

SA_DQS#1 AR8

SA_DQS2 AY11

SA_DQS#2 AV11

SA_DQS3 AU17SA_DQS4 AW45

SA_DQS#4 AV45

SA_DQS5 AV51

SA_DQS#5 AY51

SA_DQS6 AT56

SA_DQS#6 AT55

SA_DQS7 AK54

SA_DQS#7 AK55

SA_MA0 BG35SA_MA1 BB34SA_MA2 BE35SA_MA3 BD35SA_MA4 AT34SA_MA5 AU34SA_MA6 BB32SA_MA7 AT32SA_MA8 AY32SA_MA9 AV32

SA_MA10 BE37SA_MA11 BA30SA_MA12 BC30SA_MA13 AW41SA_MA14 AY28SA_MA15 AU26

SA_DQ0AG6SA_DQ1AJ6SA_DQ2AP11SA_DQ3AL6SA_DQ4AJ10SA_DQ5AJ8SA_DQ6AL8SA_DQ7AL7SA_DQ8AR11SA_DQ9AP6SA_DQ10AU6SA_DQ11AV9SA_DQ12AR6SA_DQ13AP8SA_DQ14AT13SA_DQ15AU13SA_DQ16BC7SA_DQ17BB7SA_DQ18BA13SA_DQ19BB11SA_DQ20BA7SA_DQ21BA9SA_DQ22BB9SA_DQ23AY13SA_DQ24AV14SA_DQ25AR14SA_DQ26AY17SA_DQ27AR19SA_DQ28BA14SA_DQ29AU14SA_DQ30BB14SA_DQ31BB17SA_DQ32BA45SA_DQ33AR43SA_DQ34AW48SA_DQ35BC48SA_DQ36BC45SA_DQ37AR45SA_DQ38AT48SA_DQ39AY48SA_DQ40BA49SA_DQ41AV49SA_DQ42BB51SA_DQ43AY53SA_DQ44BB49SA_DQ45AU49SA_DQ46BA53SA_DQ47BB55SA_DQ48BA55SA_DQ49AV56SA_DQ50AP50SA_DQ51AP53SA_DQ52AV54SA_DQ53AT54SA_DQ54AP56SA_DQ55AP52SA_DQ56AN57SA_DQ57AN53SA_DQ58AG56SA_DQ59AG53SA_DQ60AN55SA_DQ61AN52SA_DQ62AG55SA_DQ63AK56

SA_CAS#BE39SA_RAS#BD39SA_WE#AT41

SA_BS0BD37SA_BS1BF36SA_BS2BA28

SA_DQS#3 AT17

D

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Y

B

4 OF 9CPU1D

IVY-BRIDGE-GP-NF

71.00IVY.A0U

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4 OF 9CPU1D

IVY-BRIDGE-GP-NF

71.00IVY.A0U

SB_CK0 BA34

SB_CK1 BA36

SB_CK#0 AY34

SB_CK#1 BB36

SB_CKE0 AR22

SB_CKE1 BF27

SB_ODT0 AT43SB_ODT1 BG47

SB_DQS4 BE51

SB_DQS#4 BG51

SB_DQS5 BA61

SB_DQS#5 BA59

SB_DQS6 AR59

SB_DQS#6 AT60

SB_DQS7 AK61

SB_DQS#7 AK59

SB_DQS0 AM2

SB_DQS#0 AL3

SB_DQS1 AV1

SB_DQS#1 AV3

SB_DQS2 BE11

SB_DQS#2 BG11

SB_DQS3 BD18

SB_DQS#3 BD17

SB_MA0 BF32SB_MA1 BE33SB_MA2 BD33SB_MA3 AU30SB_MA4 BD30SB_MA5 AV30SB_MA6 BG30SB_MA7 BD29SB_MA8 BE30SB_MA9 BE28

SB_MA10 BD43SB_MA11 AT28SB_MA12 AV28SB_MA13 BD46SB_MA14 AT26SB_MA15 AU22

SB_DQ0AL4SB_DQ1AL1SB_DQ2AN3SB_DQ3AR4SB_DQ4AK4SB_DQ5AK3SB_DQ6AN4SB_DQ7AR1SB_DQ8AU4SB_DQ9AT2SB_DQ10AV4SB_DQ11BA4SB_DQ12AU3SB_DQ13AR3SB_DQ14AY2SB_DQ15BA3SB_DQ16BE9SB_DQ17BD9SB_DQ18BD13SB_DQ19BF12SB_DQ20BF8SB_DQ21BD10SB_DQ22BD14SB_DQ23BE13SB_DQ24BF16SB_DQ25BE17SB_DQ26BE18SB_DQ27BE21SB_DQ28BE14SB_DQ29BG14SB_DQ30BG18SB_DQ31BF19SB_DQ32BD50SB_DQ33BF48SB_DQ34BD53SB_DQ35BF52SB_DQ36BD49SB_DQ37BE49SB_DQ38BD54SB_DQ39BE53SB_DQ40BF56SB_DQ41BE57SB_DQ42BC59SB_DQ43AY60SB_DQ44BE54SB_DQ45BG54SB_DQ46BA58SB_DQ47AW59SB_DQ48AW58SB_DQ49AU58SB_DQ50AN61SB_DQ51AN59SB_DQ52AU59SB_DQ53AU61SB_DQ54AN58SB_DQ55AR58SB_DQ56AK58SB_DQ57AL58SB_DQ58AG58SB_DQ59AG59SB_DQ60AM60SB_DQ61AL59SB_DQ62AF61SB_DQ63AH60

SB_CS#0 BE41SB_CS#1 BE47

SB_CAS#AV43SB_RAS#BF40SB_WE#BD45

SB_BS0BG39SB_BS1BD42SB_BS2AT22

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFG2

CFG4CFG5CFG6

CFG5 CFG6

CFG0_TPCFG1_TP

CFG3_TP

CFG7

CFG7

CFG2

CFG4

Title


Date: Sheet of


Husk/Petra -4MCPU (RESERVED)

A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

SSID = CPU

0:Lane Reversed

1: Normal Operation; Lane # definition matches socket pin map definition

PEG Static Lane Reversal

CFG2

0:Enable

1:Disable

Enabl EDP function

CFG4

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled

PCIE Port Bifurcation Straps

1: PEG Train immediately following xxRESETB de assertionCFG7

PEG DEFER TRAINING

0: PEG Wait for BIOS for training

R7021KR2J-L2-GPMuxless

R7021KR2J-L2-GPMuxless

1

2

R704Do Not StuffDY

R704Do Not StuffDY

1

2

TP703Do Not Stuff TP703Do Not Stuff 1

R

E

S

E

R

V

E

D

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71.00IVY.A0U

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5 OF 9CPU1E

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71.00IVY.A0U

CFG0B50CFG1C51CFG2B54CFG3D53CFG4A51CFG5C53CFG6C55CFG7H49CFG8A55CFG9H51CFG10K49CFG11K53CFG12F53CFG13G53CFG14L51CFG15F51CFG16D52CFG17L53

DC_TEST_A4 A4

DC_TEST_A58 A58DC_TEST_A59 A59

DC_TEST_A61 A61

DC_TEST_BD1 BD1

DC_TEST_BD61 BD61

DC_TEST_BE1 BE1DC_TEST_BE3 BE3

DC_TEST_BE59 BE59DC_TEST_BE61 BE61

DC_TEST_BG1 BG1DC_TEST_BG3 BG3DC_TEST_BG4 BG4

DC_TEST_BG58 BG58DC_TEST_BG59 BG59DC_TEST_BG61 BG61

DC_TEST_C4 C4

DC_TEST_C59 C59

DC_TEST_C61 C61

DC_TEST_D1 D1DC_TEST_D3 D3

DC_TEST_D61 D61

VCC_VAL_SENSEH43VSS_VAL_SENSEK43

VAXG_VAL_SENSEH45VSSAXG_VAL_SENSEK45

VCC_DIE_SENSEF48

RSVD41 AH2RSVD42 AG13RSVD43 AM14RSVD44 AM15

RSVD8BA19RSVD9AV19RSVD10AT21RSVD11BB21RSVD12BB19RSVD13AY21RSVD14BA22RSVD15AY22RSVD16AU19RSVD17AU21RSVD18BD21RSVD19BD22RSVD20BD25RSVD21BD26RSVD22BG22RSVD23BE22RSVD24BG26RSVD25BE26RSVD26BF23RSVD27BE24

RSVD45 N50

RSVD30 N42RSVD31 L42RSVD32 L45RSVD33 L47

RSVD34 M13RSVD35 M14RSVD36 U14RSVD37 W14RSVD38 P13

RSVD39 AT49RSVD40 K24

RSVD6H48RSVD7K48

RSVD47G48

BCLK_ITP N59BCLK_ITP# N58

R7031KR2J-L2-GPEDP

R7031KR2J-L2-GPEDP

1

2

R706Do Not StuffDY

R706Do Not StuffDY

1

2

TP702Do Not Stuff TP702Do Not Stuff 1TP701Do Not Stuff TP701Do Not Stuff 1

R705Do Not StuffDY

R705Do Not StuffDY

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_CPU_SVIDCLKH_CPU_SVIDALRT#

H_VCCP_SEL_L

+V1.05S_VCCPQE

H_CPU_SVIDDAT

VCC_CORE

VCC_CORE

1D05V_VTT_CPU

VCC_CORE

1D05V_VTT_CPU

1D05V_VTT_CPU

1D05V_VTT 1D05V_VTT_CPU

3D3V_S5

1D05V_VTT_CPU

1D05V_VTT_CPU

1D05V_VTT_CPU

H_CPU_SVIDDAT 42

VR_SVID_ALERT# 42H_CPU_SVIDCLK 42

VSSSENSE 42VCCSENSE 42

VSSIO_SENSE 45VCCIO_SENSE 45

Title


Date: Sheet of


Husk/Petra -4MCPU (VCC_CORE)

Custom

8 103Monday, September 17, 2012

DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

SSID = CPU

ULV:17WIccmax:33AICC_TDC:25A

Iccmax:8.5AICC_TDC:8.5A

Place near processor

Place near processorR806

10R1F-GPDY

R80610R1F-GP

DY

1 2

C810SC10U6D3V5KX

-1GP

DY

C810SC10U6D3V5KX

-1GP

DY

1

2

C813SC1U6D3V2KX

-L-1

-GP

C813SC1U6D3V2KX

-L-1

-GP

1

2

C803SC2D2U6D3V2KX

-GP

DY

C803SC2D2U6D3V2KX

-GP

DY1

2

C805SC10U6D3V5KX

-1GP

DY

C805SC10U6D3V5KX

-1GP

DY

1

2

C818SC2D2U6D3V2KX

-GP

DY

C818SC2D2U6D3V2KX

-GP

DY

1

2

R810100KR2J-4-GPR810100KR2J-4-GP

1

2

R802100R2F-L1-GP-UR802100R2F-L1-GP-U

1

2

R80575R3J-L-GPR80575R3J-L-GP

1

2

PG806

GAP-CLOSE-PWR

PG806

GAP-CLOSE-PWR

1 2

C827SC10U6D3V5KX

-1GP

DY

C827SC10U6D3V5KX

-1GP

DY

1

2

C812SC1U6D3V2KX

-L-1

-GP

C812SC1U6D3V2KX

-L-1

-GP

1

2

C845SC10U6D3V5KX

-1GP

DY

C845SC10U6D3V5KX

-1GP

DY

1

2

C814SC1U6D3V2KX

-L-1

-GP

DY

C814SC1U6D3V2KX

-L-1

-GP

DY

1

2

PG801

GAP-CLOSE-PWR

PG801

GAP-CLOSE-PWR

1 2

C801SC2D2U6D3V2KX

-GP

DY

C801SC2D2U6D3V2KX

-GP

DY

1

2

R801100R2F-L1-GP-UR801100R2F-L1-GP-U

1

2

C806SC1U6D3V2KX

-L-1

-GP

C806SC1U6D3V2KX

-L-1

-GP

1

2

C819SC2D2U6D3V2KX

-GP

DY

C819SC2D2U6D3V2KX

-GP

DY

1

2

C807SC1U6D3V2KX

-L-1

-GP

DY

C807SC1U6D3V2KX

-L-1

-GP

DY

1

2

C811SC2D2U6D3V2KX

-GP

C811SC2D2U6D3V2KX

-GP

1

2

C832SC10U6D3V5KX

-1GP

C832SC10U6D3V5KX

-1GP

1

2

PG804

GAP-CLOSE-PWR

PG804

GAP-CLOSE-PWR

1 2

PG802

GAP-CLOSE-PWR

PG802

GAP-CLOSE-PWR

1 2

C835SC10U6D3V5KX

-1GP

DY

C835SC10U6D3V5KX

-1GP

DY

1

2

C825SC10U6D3V5KX

-1GP

C825SC10U6D3V5KX

-1GP

1

2

C834SC10U6D3V5KX

-1GP

C834SC10U6D3V5KX

-1GP

1

2

C824SC1U6D3V2KX

-L-1

-GP

C824SC1U6D3V2KX

-L-1

-GP

1

2

C808SC2D2U6D3V2KX

-GP

C808SC2D2U6D3V2KX

-GP

1

2

C829SC10U6D3V5KX

-1GP

DY

C829SC10U6D3V5KX

-1GP

DY

1

2

C804SC2D2U6D3V2KX

-GP

C804SC2D2U6D3V2KX

-GP

1

2

C833SC10U6D3V5KX

-1GP

C833SC10U6D3V5KX

-1GP

1

2

C831SC10U6D3V5KX

-1GP

DY

C831SC10U6D3V5KX

-1GP

DY

1

2

C838SC10U6D3V5KX

-1GP

DY

C838SC10U6D3V5KX

-1GP

DY

1

2

C817SC2D2U6D3V2KX

-GP

DY

C817SC2D2U6D3V2KX

-GP

DY

1

2

POWER

C

O

R

E

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U

P

P

L

Y

P

E

G

I

O

A

N

D

D

D

R

I

O

S

E

N

S

E

L

I

N

E

S

S

V

I

D

Q

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I

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R

A

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S

6 OF 9CPU1F

IVY-BRIDGE-GP-NF

71.00IVY.A0U

POWER

C

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U

P

P

L

Y

P

E

G

I

O

A

N

D

D

D

R

I

O

S

E

N

S

E

L

I

N

E

S

S

V

I

D

Q

U

I

E

T

R

A

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S

6 OF 9CPU1F

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VCC_SENSE F43VSS_SENSE G43

VIDALERT# A44VIDSCLK B43VIDSOUT C44

VSS_SENSE_VCCIO AN17

VCC1A26VCC2A29VCC3A31VCC4A34VCC5A35VCC6A38VCC7A39VCC8A42VCC9C26VCC10C27VCC11C32VCC12C34VCC13C37VCC14C39VCC15C42VCC16D27VCC17D32VCC18D34VCC19D37VCC20D39VCC21D42VCC22E26VCC23E28VCC24E32VCC25E34VCC26E37VCC27E38VCC28F25VCC29F26VCC30F28VCC31F32VCC32F34VCC33F37VCC34F38VCC35F42VCC36G42VCC37H25VCC38H26VCC39H28VCC40H29VCC41H32VCC42H34VCC43H35VCC44H37VCC45H38VCC46H40VCC47J25VCC48J26VCC49J28VCC50J29VCC51J32VCC52J34VCC53J35VCC54J37VCC55J38VCC56J40VCC57J42VCC58K26VCC59K27VCC60K29VCC61K32VCC62K34VCC63K35VCC64K37VCC66K39VCC67K42VCC68L25VCC69L28VCC70L33VCC71L36VCC72L40VCC73N26VCC74N30VCC75N34VCC76N38

VCCIO1 AF46VCCIO3 AG48VCCIO4 AG50VCCIO5 AG51VCCIO6 AJ17VCCIO7 AJ21VCCIO8 AJ25VCCIO9 AJ43

VCCIO10 AJ47VCCIO11 AK50VCCIO12 AK51VCCIO13 AL14VCCIO14 AL15VCCIO15 AL16VCCIO16 AL20VCCIO17 AL22VCCIO18 AL26VCCIO19 AL45VCCIO20 AL48VCCIO21 AM16VCCIO22 AM17VCCIO23 AM21VCCIO24 AM43VCCIO25 AM47VCCIO26 AN20VCCIO27 AN42VCCIO28 AN45VCCIO29 AN48

VCCIO30 AA14VCCIO31 AA15VCCIO32 AB17VCCIO33 AB20VCCIO34 AC13VCCIO35 AD16VCCIO36 AD18VCCIO37 AD21VCCIO38 AE14VCCIO39 AE15VCCIO40 AF16VCCIO41 AF18VCCIO42 AF20VCCIO43 AG15VCCIO44 AG16VCCIO45 AG17VCCIO46 AG20VCCIO47 AG21VCCIO48 AJ14VCCIO49 AJ15

VCCIO50 W16VCCIO51 W17

VCCPQE1 AM25VCCPQE2 AN22

VCCIO_SENSE AN16

VCCIO_SEL BC22

C826SC10U6D3V5KX

-1GP

DY

C826SC10U6D3V5KX

-1GP

DY

1

2

R8080R0402-PAD

R8080R0402-PAD1 2

C815SC2D2U6D3V2KX

-GP

C815SC2D2U6D3V2KX

-GP

1

2

R80710R1F-GPDY

R80710R1F-GPDY

1

2

C830SC10U6D3V5KX

-1GP

C830SC10U6D3V5KX

-1GP

1

2

C820SC2D2U6D3V2KX

-GP

DY

C820SC2D2U6D3V2KX

-GP

DY1

2

PG803

GAP-CLOSE-PWR

PG803

GAP-CLOSE-PWR

1 2

C844SC10U6D3V5KX

-1GP

DY

C844SC10U6D3V5KX

-1GP

DY

1

2

C839SC10U6D3V5KX

-1GP

DY

C839SC10U6D3V5KX

-1GP

DY

1

2

C816SC2D2U6D3V2KX

-GP

DY

C816SC2D2U6D3V2KX

-GP

DY

1

2

C823SC1U6D3V2KX

-L-1

-GP

C823SC1U6D3V2KX

-L-1

-GP

1

2

C822SC1U6D3V2KX

-L-1

-GP

DYC822SC1U6D3V2KX

-L-1

-GP

DY

1

2

C853SC1U6D3V2KX-L-1-GPC853SC1U6D3V2KX-L-1-GP

1

2

C840SC10U6D3V5KX

-1GP

C840SC10U6D3V5KX

-1GP

1

2

C828SC10U6D3V5KX

-1GP

C828SC10U6D3V5KX

-1GP

1

2

C836SC10U6D3V5KX

-1GP

C836SC10U6D3V5KX

-1GP

1

2

PG805

GAP-CLOSE-PWR

PG805

GAP-CLOSE-PWR

1 2

C802SC2D2U6D3V2KX

-GP

C802SC2D2U6D3V2KX

-GP

1

2

R80343R2J-GPR80343R2J-GP1 2

R804130R2F-1-GPR804130R2F-1-GP

1

2

C821SC1U6D3V2KX

-L-1

-GP

DY

C821SC1U6D3V2KX

-L-1

-GP

DY

1

2

C843SC10U6D3V5KX

-1GP

C843SC10U6D3V5KX

-1GP

1

2

C809SC1U6D3V2KX

-L-1

-GP

C809SC1U6D3V2KX

-L-1

-GP

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSS_AXG_SENSEVCC_AXG_SENSE

VCCSA_VID0VCCSA_VID1

M_VREF_DQ_DIMM1_CM_VREF_DQ_DIMM0_C

VCCSA_VID1VCCSA_VID0

TP_VDDQ_SENSETP_VDDQ_VSS

+1.5S_VCCD_Q

VCCSA_SENSE

+1.5S_VCCD_Q

VCC_GFXCORE

1D8V_S0

VCC_GFXCORE

0D85V_S0

1D05V_VTT_CPU1D05V_VTT_CPU

1D5V_S0

0D85V_S0

1D5V_S0

VCC_AXG_SENSE42VSS_AXG_SENSE42

+V_SM_VREF_CNT 37

M_VREF_DQ_DIMM0_C 37M_VREF_DQ_DIMM1_C 37

VCCSA_VID0 48VCCSA_VID1 48

Title


Date: Sheet of


Husk/Petra -4MCPU (VCC_GFXCORE)

Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

SSID = CPU

R906,R907 close to CPU

Routing Guideline:Power from DDR_VREF_S3 and +V_SM_VREF_CNTshould have 10 mils trace width.

R902 need be close to pin U10.

PROCESSOR DDR 1.5V QUIET RAIL (BGA only)

+V1.5S_VCCD_Q should be short to +V1.5S_VCCDDQ on board

Iccmax:18A(GT1)ICC_TDC:12A(GT1)

ICC_MAX:6A

ICC_MAX:1.2A

Iccmax:5A

BE7 and BG7 is NC ball in HR

C918SC1U6D3V2KX

-L-1

-GP

C918SC1U6D3V2KX

-L-1

-GP

1

2

RN902SRN1KJ-7-GPDY

RN902SRN1KJ-7-GPDY

12

3 4

C905SC10U6D3V5KX

-1GP

DY

C905SC10U6D3V5KX

-1GP

DY

1

2

R9090R0402-PAD

R9090R0402-PAD1 2

R91310KR2J-L-GP

R91310KR2J-L-GP

1

2

C919SC10U6D3V5KX

-1GP

C919SC10U6D3V5KX

-1GP

1

2

C909SC1U6D3V2KX

-L-1

-GP

DY

C909SC1U6D3V2KX

-L-1

-GP

DY

1

2

C923SC1U6D3V2KX-L-1-GPC923SC1U6D3V2KX-L-1-GP

1 2

TP901 TPAD14-OP-GPTP901 TPAD14-OP-GP1

POWER

G

R

A

P

H

I

C

S

D

D

R

3

-

1

.

5

V

R

A

I

L

S

1

.

8

V

R

A

I

L

S

E

N

S

E

L

I

N

E

S

S

A

R

A

I

L

S

E

N

S

E

L

I

N

E

S

Q

U

I

E

T

R

A

I

L

S

V

R

E

F

V

C

C

S

A

V

I

D

l

i

n

e

s

7 OF 9CPU1G

IVY-BRIDGE-GP-NF

71.00IVY.A0U

POWER

G

R

A

P

H

I

C

S

D

D

R

3

-

1

.

5

V

R

A

I

L

S

1

.

8

V

R

A

I

L

S

E

N

S

E

L

I

N

E

S

S

A

R

A

I

L

S

E

N

S

E

L

I

N

E

S

Q

U

I

E

T

R

A

I

L

S

V

R

E

F

V

C

C

S

A

V

I

D

l

i

n

e

s

7 OF 9CPU1G

IVY-BRIDGE-GP-NF

71.00IVY.A0U

SM_VREF AY43VAXG1AA46VAXG2AB47VAXG3AB50VAXG4AB51VAXG5AB52VAXG6AB53VAXG7AB55VAXG8AB56VAXG9AB58VAXG10AB59VAXG11AC61VAXG12AD47VAXG13AD48VAXG14AD50VAXG15AD51VAXG16AD52VAXG17AD53VAXG18AD55VAXG19AD56VAXG20AD58VAXG21AD59VAXG22AE46VAXG23N45VAXG24P47VAXG25P48VAXG26P50VAXG27P51VAXG28P52VAXG29P53VAXG30P55VAXG31P56VAXG32P61VAXG33T48VAXG34T58VAXG35T59VAXG36T61VAXG37U46VAXG38V47VAXG39V48VAXG40V50VAXG41V51VAXG42V52VAXG43V53VAXG44V55VAXG45V56VAXG46V58VAXG47V59VAXG48W50VAXG49W51VAXG50W52VAXG51W53VAXG52W55VAXG53W56VAXG54W61

VDDQ11 AM40VDDQ12 AN30VDDQ13 AN34VDDQ14 AN38VDDQ15 AR26

VDDQ1 AJ28VDDQ2 AJ33VDDQ3 AJ36VDDQ4 AJ40VDDQ5 AL30VDDQ6 AL34VDDQ7 AL38VDDQ8 AL42VDDQ9 AM33

VDDQ10 AM36

VCCPLL1BB3VCCPLL2BC1

VCCSA_SENSE U10

VCCSA_VID1 D49

VAXG55Y48VAXG56Y61

VCCPLL3BC4

VAXG_SENSEF45VSSAXG_SENSEG45

VCCSA1L17

VCCSA10R21

VCCSA12V16VCCSA13V17VCCSA14V18

VCCSA4N20VCCSA5N22VCCSA6P17

VCCSA9R18

VDDQ16 AR28VDDQ17 AR30VDDQ18 AR32VDDQ19 AR34VDDQ20 AR36VDDQ21 AR40VDDQ22 AV41VDDQ23 AW26VDDQ24 BA40VDDQ25 BB28VDDQ26 BG33

VCCSA11U15

VCCSA15V21VCCSA16W20

VCCSA2L21VCCSA3N16

VCCDQ1 AM28VCCDQ2 AN26

VCCSA7P20VCCSA8R16

VDDQ_SENSE BC43VSS_SENSE_VDDQ BA43

VCCSA_VID0 D48

SA_DIMM_VREFDQ BE7SB_DIMM_VREFDQ BG7

C915SC10U6D3V5KX-1GP

C915SC10U6D3V5KX-1GP

1

2

C912SC10U6D3V5KX

-1GP

DY

C912SC10U6D3V5KX

-1GP

DY

1

2

C910SC10U6D3V5KX

-1GP

C910SC10U6D3V5KX

-1GP

1

2

R90810KR2J-L-GP

DY

R90810KR2J-L-GP

DY

1

2

C922SC1U10V2KX-1GPC922SC1U10V2KX-1GP

1

2

TP902 TPAD14-OP-GPTP902 TPAD14-OP-GP1

C903SC10U6D3V5KX

-1GP

DY

C903SC10U6D3V5KX

-1GP

DY1

2

C921SC10U6D3V5KX

-1GP

DY

C921SC10U6D3V5KX

-1GP

DY

1

2

C913SC10U6D3V5KX

-1GP

DY

C913SC10U6D3V5KX

-1GP

DY

1

2

R91410KR2J-L-GPR91410KR2J-L-GP

1

2

R907100R2F-L1-GP-U

R907100R2F-L1-GP-U

1

2

C917SC1U6D3V2KX

-L-1

-GP

C917SC1U6D3V2KX

-L-1

-GP

1

2

C902SC10U6D3V5KX

-1GP

C902SC10U6D3V5KX

-1GP

1

2

R906100R2F-L1-GP-U

R906100R2F-L1-GP-U

1

2

C907SC1U6D3V2KX

-L-1

-GP

C907SC1U6D3V2KX

-L-1

-GP

1

2

C911SC10U6D3V5KX

-1GP

C911SC10U6D3V5KX

-1GP

1

2

C914SC1U6D3V2KX

-L-1

-GP

DY

C914SC1U6D3V2KX

-L-1

-GP

DY

1

2

C924SC1U6D3V2KX

-L-1

-GP

DY

C924SC1U6D3V2KX

-L-1

-GP

DY

1

2

C904SC10U6D3V5KX

-1GP

DY

C904SC10U6D3V5KX

-1GP

DY

1

2

C925SC1U6D3V2KX

-L-1

-GP

C925SC1U6D3V2KX

-L-1

-GP

1

2

C908SC10U6D3V5KX

-1GP

C908SC10U6D3V5KX

-1GP

1

2

C926SC1U6D3V2KX

-L-1

-GP

DY

C926SC1U6D3V2KX

-L-1

-GP

DY

1

2

R91210KR2J-L-GPDY

R91210KR2J-L-GPDY

1

2

C920SC10U6D3V5KX

-1GP

C920SC10U6D3V5KX

-1GP

1

2

C916SC1U6D3V2KX

-L-1

-GP

C916SC1U6D3V2KX

-L-1

-GP

1

2

R902100R2F-L1-GP-UR902100R2F-L1-GP-U

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Husk/Petra -4MCPU (VSS)

A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

SSID = CPU

VSS

9 OF 9

N

C

T

F

N

C

T

F

T

E

S

T

P

I

N

A

5

,

A

5

7

,

B

C

6

1

,

B

G

5

B

G

5

7

,

C

3

,

E

1

,

E

6

1

CPU1I

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS

9 OF 9

N

C

T

F

N

C

T

F

T

E

S

T

P

I

N

A

5

,

A

5

7

,

B

C

6

1

,

B

G

5

B

G

5

7

,

C

3

,

E

1

,

E

6

1

CPU1I

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS181BG17VSS182BG21VSS183BG24VSS184BG28VSS185BG37VSS186BG41VSS187BG45VSS188BG49VSS189BG53VSS190BG9VSS191C29VSS192C35VSS193C40VSS194D10VSS195D14VSS196D18VSS197D22VSS198D26VSS199D29VSS200D35VSS201D4VSS202D40VSS203D43VSS204D46VSS205D50VSS206D54VSS207D58VSS208D6VSS209E25VSS210E29VSS211E3VSS212E35VSS213E40VSS214F13VSS215F15VSS216F19VSS217F29VSS218F35VSS219F40VSS220F55VSS221G51VSS222G6VSS223G61VSS224H10VSS225H14VSS226H17VSS227H21VSS228H4VSS229H53VSS230H58VSS231J1VSS232J49VSS233J55VSS234K11VSS235K21VSS236K51VSS237K8VSS238L16VSS239L20VSS240L22VSS241L26VSS242L30VSS243L34VSS244L38VSS245L43VSS246L48

VSS268 P14VSS269 P16VSS270 P18VSS271 P21VSS272 P58VSS273 P59VSS274 P9VSS275 R17VSS276 R20VSS277 R4VSS278 R46VSS279 T1VSS280 T47VSS281 T50VSS282 T51VSS283 T52VSS284 T53VSS285 T55VSS286 T56VSS287 U13VSS288 U8VSS289 V20VSS290 V61

VSS_NCTF_1#A5 A5VSS_NCTF_2#A57 A57

VSS_NCTF_3#BC61 BC61VSS_NCTF_8#BG5 BG5

VSS_NCTF_9#BG57 BG57VSS_NCTF_10#C3 C3VSS_NCTF_13#E1 E1

VSS_NCTF_14#E61 E61

VSS250 M4VSS251 M58VSS252 M6VSS253 N1VSS254 N17VSS255 N21VSS256 N25VSS257 N28VSS258 N33VSS259 N36VSS260 N40VSS261 N43VSS262 N47VSS263 N48VSS264 N51VSS265 N52VSS266 N56VSS267 N61

VSS247L61VSS248M11

VSS291 W13VSS292 W15VSS293 W18VSS294 W21VSS295 W46VSS296 W8VSS297 Y4VSS298 Y47VSS299 Y58VSS300 Y59

VSS249M15VSS_NCTF_4 BD3VSS_NCTF_5 BD59VSS_NCTF_6 BE4VSS_NCTF_7 BE58

VSS_NCTF_11 C58VSS_NCTF_12 D59

VSS

8 OF 9CPU1H

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS

8 OF 9CPU1H

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS1A13VSS2A17VSS3A21VSS4A25VSS5A28VSS6A33VSS7A37VSS8A40VSS9A45VSS10A49VSS11A53VSS12A9VSS13AA1VSS14AA13VSS15AA50VSS16AA51VSS17AA52VSS18AA53VSS19AA55VSS20AA56VSS21AA8VSS22AB16VSS23AB18VSS24AB21VSS25AB48VSS26AB61VSS27AC10VSS28AC14VSS29AC46VSS30AC6VSS31AD17VSS32AD20VSS33AD4VSS34AD61VSS35AE13VSS36AE8VSS37AF1VSS38AF17VSS39AF21VSS40AF47VSS41AF48VSS42AF50VSS43AF51VSS44AF52VSS45AF53VSS46AF55VSS47AF56VSS48AF58VSS49AF59VSS50AG10VSS51AG14VSS52AG18VSS53AG47VSS54AG52VSS55AG61VSS56AG7VSS57AH4VSS58AH58VSS59AJ13VSS60AJ16VSS61AJ20VSS62AJ22VSS63AJ26VSS64AJ30VSS65AJ34VSS66AJ38VSS67AJ42VSS68AJ45VSS69AJ48VSS70AJ7VSS71AK1VSS72AK52VSS73AL10VSS74AL13VSS75AL17VSS76AL21VSS77AL25VSS78AL28VSS79AL33VSS80AL36VSS81AL40VSS82AL43VSS83AL47VSS84AL61VSS85AM13VSS86AM20VSS87AM22VSS88AM26VSS89AM30VSS90AM34

VSS91 AM38VSS92 AM4VSS93 AM42VSS94 AM45VSS95 AM48VSS96 AM58VSS97 AN1VSS98 AN21VSS99 AN25

VSS100 AN28VSS101 AN33VSS102 AN36VSS103 AN40VSS104 AN43VSS105 AN47VSS106 AN50VSS107 AN54VSS108 AP10VSS109 AP51VSS110 AP55VSS111 AP7VSS112 AR13VSS113 AR17VSS114 AR21VSS115 AR41VSS116 AR48VSS117 AR61VSS118 AR7VSS119 AT14VSS120 AT19VSS121 AT36VSS122 AT4VSS123 AT45VSS124 AT52VSS125 AT58VSS126 AU1VSS127 AU11VSS128 AU28VSS129 AU32VSS130 AU51VSS131 AU7VSS132 AV17VSS133 AV21VSS134 AV22VSS135 AV34VSS136 AV40VSS137 AV48VSS138 AV55VSS139 AW13VSS140 AW43VSS141 AW61VSS142 AW7VSS143 AY14VSS144 AY19VSS145 AY30VSS146 AY36VSS147 AY4VSS148 AY41VSS149 AY45VSS150 AY49VSS151 AY55VSS152 AY58VSS153 AY9VSS154 BA1VSS155 BA11VSS156 BA17VSS157 BA21VSS158 BA26VSS159 BA32VSS160 BA48VSS161 BA51VSS162 BB53VSS163 BC13VSS164 BC5VSS165 BC57VSS166 BD12VSS167 BD16VSS168 BD19VSS169 BD23VSS170 BD27VSS171 BD32VSS172 BD36VSS173 BD40VSS174 BD44VSS175 BD48VSS176 BD52VSS177 BD56VSS178 BD8VSS179 BE5VSS180 BG13

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Husk/Petra -4MXDP

A3


DIS IVB Touch

Title


Date: Sheet of


Husk/Petra -4MXDP

A3


DIS IVB Touch

Title


Date: Sheet of


Husk/Petra -4MXDP

A3


DIS IVB Touch

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Husk/Petra -4MReserved

A4


DIS IVB Touch

Title


Date: Sheet of



A4


DIS IVB Touch

Title


Date: Sheet of



A4


DIS IVB Touch

(Blanking)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of



A4


DIS IVB Touch

Title


Date: Sheet of



A4


DIS IVB Touch

Title


Date: Sheet of



A4


DIS IVB Touch

(Blanking)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_A1

M_A_DQS#0



M_A_DQS3

M_A_DQ0

M_A_DQS#5

M_A_A2



M_A_DQS4

M_A_A3

M_A_DQS#6



M_A_DQ1

M_A_A4

M_A_DQS5

M_A_DQS#7



M_A_DQS#1

M_A_A5

M_A_DQ2

M_A_DQS6


M_A_DQS0


M_A_A7M_A_A8M_A_A9M_A_A10M_A_A11

M_A_A6

M_A_DQ3

M_A_DQS#2

M_A_DQS7



M_A_DQS1

M_A_A13M_A_A14M_A_A15

M_A_A12


M_A_DQS#3

M_A_A0



M_A_DQS2

M_A_DQS#4

TS#_DIMM0_1

1D5V_S3

3D3V_S0

0D75V_S0

3D3V_S0

1D5V_S3

DDR_VREF_S3

0D75V_S0

DDR_VREF_S3 M_VREF_DQ_DIMM0

M_VREF_DQ_DIMM0

DDR3_DRAMRST#15,37

M_A_DIM0_ODT06M_A_DIM0_ODT16

M_A_BS26

M_A_BS06M_A_BS16

M_A_DQ[63:0]6

TS#_DIMM0_1 15

PCH_SMBCLK 15,20,69PCH_SMBDATA 15,20,69

M_A_WE# 6

M_A_DIM0_CS#0 6

M_A_CAS# 6

M_A_DIM0_CKE0 6M_A_DIM0_CKE1 6

M_A_DIM0_CS#1 6



M_A_RAS# 6M_A_A[15:0] 6

M_A_DQS#[7:0] 6M_A_DQS[7:0] 6

DDR_WR_VREF01_B4 37

Title


Date: Sheet of


Husk/Petra -4MDDR3-SODIMM1

Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

SSID = MEMORY

Thermal EVENT

Tracew should be at least 20 mils wide

R14050R3J-4-GP

IVB

R14050R3J-4-GP

IVB

12

C1416

SCD

1U10V2KX

-L1-G

PC

1416SC

D1U

10V2KX-L1

-GP

1

2

C1403

SC10U6D3V5KX

-1GP

C1403

SC10U6D3V5KX

-1GP

1

2

C1417

SCD

1U10V2KX

-L1-G

PC

1417SC

D1U

10V2KX-L1

-GP

1

2

C1401SCD1U10V2KX-L1-GPC1401SCD1U10V2KX-L1-GP

1

2


1

2


1

2

R1403

10KR2J-L-GP

R1403

10KR2J-L-GP

1 2

C1407

SC10U6D3V5KX

-1GP

C1407

SC10U6D3V5KX

-1GP

1

2

C1419

SC1U6D3V2KX

-L-1

-GP

C1419

SC1U6D3V2KX

-L-1

-GP

1

2

C1404

SC10U6D3V5KX

-1GP

C1404

SC10U6D3V5KX

-1GP

1

2

C1405

Do

Not

Stuff

DY

C1405

Do

Not

Stuff

DY

1

2

R1404Do Not Stuff

SNB

R1404Do Not Stuff

SNB12

DM1DDR3-204P-122-GP62.10017.Z512nd = 62.10017.M513rd = 62.10024.G21


A098A197A296A395A492A591A690A786A889A985A10/AP107A1184A1283A13119A1480A1578A16/BA279

BA0109BA1108

DQ05DQ17DQ215DQ317DQ44DQ56DQ616DQ718DQ821DQ923DQ1033DQ1135DQ1222DQ1324DQ1434DQ1536DQ1639DQ1741DQ1851DQ1953DQ2040DQ2142DQ2250DQ2352DQ2457DQ2559DQ2667DQ2769DQ2856DQ2958DQ3068DQ3170DQ32129DQ33131DQ34141DQ35143DQ36130DQ37132DQ38140DQ39142DQ40147DQ41149DQ42157DQ43159DQ44146DQ45148DQ46158DQ47160DQ48163DQ49165DQ50175DQ51177DQ52164DQ53166DQ54174DQ55176DQ56181DQ57183DQ58191DQ59193DQ60180DQ61182DQ62192DQ63194

DQS0#10DQS1#27DQS2#45DQS3#62DQS4#135DQS5#152DQS6#169DQS7#186

DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188

ODT0116ODT1120

VREF_DQ1

VSS 2

NP1 NP1NP2 NP2

RAS# 110WE# 113

CAS# 115

CS0# 114CS1# 121

CKE0 73CKE1 74

CK0 101CK0# 103

CK1 102CK1# 104

DM0 11DM1 28DM2 46DM3 63DM4 136DM5 153DM6 170DM7 187

SDA 200SCL 202

VDDSPD 199

SA0 197SA1 201

VREF_CA126

VDD18 124

NC#1 77NC#2 122

NC#/TEST 125

VDD3 81VDD4 82VDD5 87VDD6 88VDD7 93VDD8 94VDD9 99

VDD10 100

VDD13 111VDD14 112VDD15 117VDD16 118

VSS 3VSS 8VSS 9VSS 13VSS 14VSS 19VSS 20VSS 25VSS 26VSS 31VSS 32VSS 37VSS 38VSS 43VSS 44VSS 48VSS 49VSS 54VSS 55VSS 60VSS 61

VDD1 75

VSS 65VSS 66VSS 71VSS 72

VDD2 76

VDD11 105VDD12 106

VDD17 123

VSS 127VSS 128

VSS 134VSS 133


VSS 151VSS 150

VSS 155VSS 156VSS 161VSS 162VSS 167VSS 168

VSS 173VSS 172

VSS 179VSS 178

VSS 185VSS 184


RESET#30

EVENT# 198

VSS 205VSS 206

VTT1203VTT2204

C1421

SC1U6D3V2KX

-L-1

-GP

C1421

SC1U6D3V2KX

-L-1

-GP

1

2

C1406

SC10U6D3V5KX

-1GP

C1406

SC10U6D3V5KX

-1GP

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_B_A1

M_B_DQ42M_B_DQ41M_B_DQ40

M_B_DQS#0

M_B_DQ43


M_B_DQ15

M_B_DQS3

M_B_DQ0

M_B_A2

M_B_DQS#5


M_B_DQ47


M_B_DQS4

M_B_A3

M_B_DQS#6



SA1_DIM1

M_B_DQ1

M_B_A4

M_B_DQS5

M_B_DQS#7

M_B_DQ53M_B_DQ52

M_B_DQ24

M_B_DQ55M_B_DQ54


M_B_DQS#1

M_B_DQ2

M_B_A5

M_B_DQS6

M_B_DQ57M_B_DQ56

M_B_DQS0

M_B_DQ59M_B_DQ58


M_B_A7M_B_A6

M_B_A11M_B_A10M_B_A9M_B_A8

M_B_DQ3

M_B_DQS#2

M_B_DQS7


M_B_DQ33M_B_DQ32

M_B_DQ35M_B_DQ34

M_B_DQS1

M_B_A12

M_B_A15M_B_A14M_B_A13

M_B_DQ5M_B_DQ4

M_B_DQ7M_B_DQ6

M_B_DQS#3

M_B_A0


M_B_DQ8


M_B_DQS2

M_B_DQS#4

1D5V_S3

3D3V_S0

0D75V_S0

1D5V_S3

DDR_VREF_S3

0D75V_S0

M_VREF_DQ_DIMM1DDR_VREF_S3

M_VREF_DQ_DIMM1

DDR3_DRAMRST#14,37

M_B_BS06

M_B_BS26

M_B_BS16M_B_DQ[63:0]6

TS#_DIMM0_1 14

PCH_SMBCLK 14,20,69PCH_SMBDATA 14,20,69

M_B_A[15:0] 6

M_B_DQS[7:0] 6M_B_DQS#[7:0] 6

M_B_DIM0_ODT06M_B_DIM0_ODT16

M_B_WE# 6

M_B_DIM0_CS#0 6

M_B_CAS# 6

M_B_DIM0_CKE0 6M_B_DIM0_CKE1 6

M_B_DIM0_CS#1 6



M_B_RAS# 6

DDR_WR_VREF01_D1 37

Title


Date: Sheet of



Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

SSID = MEMORY



A098A197A296A395A492A591A690A786A889A985A10/AP107A1184A1283A13119A1480A1578A16/BA279

BA0109BA1108

DQ05DQ17DQ215DQ317DQ44DQ56DQ616DQ718DQ821DQ923DQ1033DQ1135DQ1222DQ1324DQ1434DQ1536DQ1639DQ1741DQ1851DQ1953DQ2040DQ2142DQ2250DQ2352DQ2457DQ2559DQ2667DQ2769DQ2856DQ2958DQ3068DQ3170DQ32129DQ33131DQ34141DQ35143DQ36130DQ37132DQ38140DQ39142DQ40147DQ41149DQ42157DQ43159DQ44146DQ45148DQ46158DQ47160DQ48163DQ49165DQ50175DQ51177DQ52164DQ53166DQ54174DQ55176DQ56181DQ57183DQ58191DQ59193DQ60180DQ61182DQ62192DQ63194

DQS0#10DQS1#27DQS2#45DQS3#62DQS4#135DQS5#152DQS6#169DQS7#186

DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188

ODT0116ODT1120

VREF_DQ1

VSS 2

NP1 NP1NP2 NP2

RAS# 110WE# 113

CAS# 115

CS0# 114CS1# 121

CKE0 73CKE1 74

CK0 101CK0# 103

CK1 102CK1# 104

DM0 11DM1 28DM2 46DM3 63DM4 136DM5 153DM6 170DM7 187

SDA 200SCL 202

VDDSPD 199

SA0 197SA1 201

VREF_CA126

VDD18 124

NC#1 77NC#2 122

NC#/TEST 125

VDD3 81VDD4 82VDD5 87VDD6 88VDD7 93VDD8 94VDD9 99

VDD10 100

VDD13 111VDD14 112VDD15 117VDD16 118

VSS 3VSS 8VSS 9VSS 13VSS 14VSS 19VSS 20VSS 25VSS 26VSS 31VSS 32VSS 37VSS 38VSS 43VSS 44VSS 48VSS 49VSS 54VSS 55VSS 60VSS 61

VDD1 75


VDD2 76

VDD11 105VDD12 106

VDD17 123

VSS 127VSS 128

VSS 134VSS 133


VSS 151VSS 150

VSS 155VSS 156VSS 161VSS 162VSS 167VSS 168

VSS 173VSS 172

VSS 179VSS 178

VSS 185VSS 184


RESET#30

EVENT# 198

VSS 205VSS 206

VTT1203VTT2204


1

2

C1507

SC10U6D3V5KX

-1GP

C1507

SC10U6D3V5KX

-1GP

1

2


1

2


1

2

C1503

Do

Not

StuffDY

C1503

Do

Not

StuffDY

1

2

C1519

SC1U6D3V2KX

-L-1

-GP

C1519

SC1U6D3V2KX

-L-1

-GP

1

2

R1502Do Not StuffSNB

R1502Do Not StuffSNB

12

C1513

SCD

1U10V2KX

-L1-G

PC

1513SC

D1U

10V2KX-L1

-GP

1

2

C1506

SC10U6D3V5KX

-1GP

C1506

SC10U6D3V5KX

-1GP

1

2

C1521

SC1U6D3V2KX

-L-1

-GP

C1521

SC1U6D3V2KX

-L-1

-GP

1

2

R15030R3J-4-GP

IVB

R15030R3J-4-GP

IVB

12

C1514

SCD

1U10V2KX

-L1-G

PC

1514SC

D1U

10V2KX-L1

-GP

1

2

C1505

SC10U6D3V5KX

-1GP

C1505

SC10U6D3V5KX

-1GP

1

2

C1504

Do

Not

StuffDY

C1504

Do

Not

StuffDY

1

2


12

C1509

SC10U6D3V5KX

-1GP

C1509

SC10U6D3V5KX

-1GP

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of



A4


DIS IVB Touch

Title


Date: Sheet of



A4


DIS IVB Touch

Title


Date: Sheet of



A4


DIS IVB Touch

(Blanking)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LVDS_IBG

DAC_IREF_R

LVDS_VREFHLVDS_VREFL

L_CTRL_DATAL_CTRL_CLK

LVDS_VDD_EN

CRT_RED

CRT_BLUE

L_BKLT_EN

CRT_GREEN

DDBP_DATA0DDBP_DATA0#

DDBP_DATA2#DDBP_DATA2

DDBP_CLK#

DDBP_DATA1#

DDBP_CLK

DDBP_DATA1

L_CTRL_DATAL_CTRL_CLK

LVDS_DDC_CLK_RLVDS_DDC_DATA_R

3D3V_S0

3D3V_S0

3D3V_S0

CRT_HSYNC50CRT_VSYNC50

LVDS_DDC_CLK_R49LVDS_DDC_DATA_R49

LVDSA_DATA049LVDSA_DATA149LVDSA_DATA249

LVDSA_DATA0#49LVDSA_DATA1#49LVDSA_DATA2#49

LVDSA_CLK#49LVDSA_CLK49

L_BKLT_CTRL49

LVDS_VDD_EN49L_BKLT_EN27

CRT_BLUE50CRT_GREEN50CRT_RED50

CRT_DDC_CLK50CRT_DDC_DATA50

HDMI_PCH_DET 51

PCH_HDMI_CLK 51PCH_HDMI_DATA 51

HDMI_DATA0_R 51HDMI_DATA0_R# 51

HDMI_CLK_R 51

HDMI_DATA1_R 51

HDMI_CLK_R# 51

HDMI_DATA1_R# 51HDMI_DATA2_R 51HDMI_DATA2_R# 51

Title


Date: Sheet of


Husk/Petra -4MPCH (LVDS/CRT/DDI)

A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

Place near PCH

RN1706SRN2K2J-1-GPRN1706SRN2K2J-1-GP

1 2

34

C1707 SCD1U10V2KX-L1-GPC1707 SCD1U10V2KX-L1-GP1 2


12 3

4


1 2

34


R17021KR2D-1-GP

R17021KR2D-1-GP

1

2


RN1702SRN100KJ-6-GPRN1702SRN100KJ-6-GP

12 3

4


RN1704SRN0J-6-GPRN1704SRN0J-6-GP

12 3

4

L

V

D

S

D

i

g

i

t

a

l

D

i

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p

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a

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C

R

T

4 OF 10PCH1D

PANTHER-GP-NF

71.PANTH.00U

L

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S

D

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a

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PANTHER-GP-NF

71.PANTH.00U

L_BKLTCTLP45

L_BKLTENJ47

L_CTRL_CLKT45L_CTRL_DATAP39

L_DDC_CLKT40L_DDC_DATAK47

L_VDD_ENM45

LVDSA_CLK#AK39LVDSA_CLKAK40

LVDSA_DATA#0AN48LVDSA_DATA#1AM47LVDSA_DATA#2AK47LVDSA_DATA#3AJ48

LVDSA_DATA0AN47LVDSA_DATA1AM49LVDSA_DATA2AK49LVDSA_DATA3AJ47

LVDSB_CLK#AF40LVDSB_CLKAF39

LVDSB_DATA#0AH45LVDSB_DATA#1AH47LVDSB_DATA#2AF49LVDSB_DATA#3AF45

LVDSB_DATA0AH43

DDPB_0N AV42

DDPB_1N AV45

LVD_VREFHAE48LVD_VREFLAE47

DDPD_2N BF42

DDPD_3N BJ42

DDPB_2N AU48

DDPB_3N AV47

DDPC_0N AY47

DDPC_1N AY43

DDPC_2N BA47

DDPC_3N BB47

DDPD_0N BB43

DDPD_1N BF44

DDPB_0P AV40

DDPB_1P AV46

DDPD_2P BE42

DDPD_3P BG42

DDPB_2P AU47

DDPB_3P AV49

LVDSB_DATA1AH49LVDSB_DATA2AF47LVDSB_DATA3AF43

LVD_IBGAF37LVD_VBGAF36

DDPC_1P AY45DDPC_0P AY49

DDPC_2P BA48

DDPC_3P BB49

DDPD_0P BB45

DDPD_1P BE44

CRT_BLUEN48

CRT_DDC_CLKT39CRT_DDC_DATAM40

CRT_GREENP49

CRT_HSYNCM47

CRT_IRTNT42

CRT_REDT49

CRT_VSYNCM49

DAC_IREFT43

SDVO_CTRLCLK P38SDVO_CTRLDATA M39

DDPC_CTRLCLK P46DDPC_CTRLDATA P42

DDPD_CTRLCLK M43DDPD_CTRLDATA M36

DDPB_AUXN AT49

DDPC_AUXN AP47

DDPD_AUXN AT45

DDPB_AUXP AT47

DDPC_AUXP AP49

DDPD_AUXP AT43

DDPB_HPD AT40

DDPC_HPD AT38

DDPD_HPD BH41

SDVO_TVCLKINP AP45SDVO_TVCLKINN AP43

SDVO_STALLP AM40SDVO_STALLN AM42

SDVO_INTP AP40SDVO_INTN AP39



R17012K37R2F-GP

R17012K37R2F-GP

1

2


RN1705SRN150F-1-GPRN1705SRN150F-1-GP

1234

5 6 7 8


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TP_IN#

CLK_PCI_LPC_R

INT_PIRQF#INT_PIRQE#

CLK_PCI_FB_RCLK_PCI_KBC_R

INT_PIRQB#INT_PIRQC#INT_PIRQD#

INT_PIRQA#

DGPU_PWM_SELECT#

USB_RBIAS

PCH_TOUCH_ENINT_PIRQC#

DGPU_SELECT#

DGPU_PWR_EN#DGPU_HOLD_RST#

CLK_PCI_LPC

INT_PIRQF#INT_PIRQB# INT_PIRQA#

INT_PIRQE#

INT_PIRQD#

OC_PWR

PCH_TOUCH_EN

3D3V_S0

3D3V_S0

3D3V_S5

CLK_PCI_FB20CLK_PCI_KBC27

PLT_RST#5,27,31,36,65,71,83,97

USB_PN9 61USB_PP9 61


DGPU_HOLD_RST#83

DGPU_PWR_EN#27,93

SATA_ODD_DA#56

CLK_PCI_LPC71

USB30_TN262

USB30_TP262

USB30_RN262

USB30_RP262



TP_IN#69



TOUCH_EN27,49

Title


Date: Sheet of


Husk/Petra -4MPCH (PCI/USB/NVRAM)

Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

Reserved 0111

BOOT BIOS Strap

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 1 Reserved

SPI(Default)

SSID = PCH

0 0 LPC

USB Table

1312

may not be available

Mini Card1 (WLAN+BT)

USB2.0 Ext. port 310

0

11

USB3.0/USB2.0 Ext. port 2

Pair

45

23

1

Device

67

89

may not be available

CCD

USB2.0 Ext. port 1

Touch panel

-4

-4

EC1801Do Not StuffDYEC1801Do Not StuffDY

1

2

R

S

V

D

P

C

I

U

S

B

5 OF 10PCH1E

PANTHER-GP-NF

71.PANTH.00U

R

S

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D

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B

5 OF 10PCH1E

PANTHER-GP-NF

71.PANTH.00U

RSVD23 AV5

RSVD1 AY7RSVD2 AV7RSVD3 AU3RSVD4 BG4

RSVD5 AT10RSVD6 BC8

RSVD7 AU2RSVD8 AT4

RSVD17 BB5RSVD18 BB3RSVD19 BB7RSVD20 BE8RSVD21 BD4RSVD22 BF6

RSVD9 AT3RSVD10 AT1RSVD11 AY3RSVD12 AT5RSVD13 AV3RSVD14 AV1RSVD15 BB1RSVD16 BA3

RSVD25 AT8RSVD24 AV10

RSVD26 AY5RSVD27 BA2

RSVD28 AT12RSVD29 BF3

PIRQA#K40PIRQB#K38PIRQC#H38PIRQD#G38

REQ1#/GPIO50C46REQ2#/GPIO52C44REQ3#/GPIO54E40

GNT1#/GPIO51D47GNT2#/GPIO53E42GNT3#/GPIO55F46

PIRQE#/GPIO2G42PIRQF#/GPIO3G40PIRQG#/GPIO4C42PIRQH#/GPIO5D44

USBP0N C24USBP0P A24USBP1N C25USBP1P B25USBP2N C26USBP2P A26USBP3N K28USBP3P H28USBP4N E28USBP4P D28USBP5N C28USBP5P A28USBP6N C29USBP6P B29USBP7N N28USBP7P M28USBP8N L30USBP8P K30USBP9N G30USBP9P E30

USBP10N C30USBP10P A30USBP11N L32USBP11P K32USBP12N G32USBP12P E32USBP13N C32USBP13P A32

PME#K10

CLKOUT_PCI0H49CLKOUT_PCI1H43CLKOUT_PCI2J48

USBRBIAS# C33

USBRBIAS B33

OC0#/GPIO59 A14OC1#/GPIO40 K20OC2#/GPIO41 B17OC3#/GPIO42 C16OC4#/GPIO43 L16OC5#/GPIO9 A16

OC6#/GPIO10 D14OC7#/GPIO14 C14CLKOUT_PCI4H40

CLKOUT_PCI3K42

PLTRST#C6

TP1BG26TP2BJ26TP3BH25

TP6AH38TP7AH37TP8AK43TP9AK45

TP16Y13TP17K24TP18L24TP19AB46TP20AB45

TP21B21TP22M20TP23AY16

USB3RN1BE28USB3RN2BC30USB3RN3BE32USB3RN4BJ32USB3RP1BC28USB3RP2BE30USB3RP3BF32USB3RP4BG32USB3TN1AV26USB3TN2BB26USB3TN3AU28USB3TN4AY30USB3TP1AU26USB3TP2AY26USB3TP3AV28USB3TP4AW30

TP4BJ16TP5BG16

TP15AM5TP14AM4TP13AH12TP12H3TP11N30TP10C18

TP24BG46

R1813 Do Not StuffR1813 Do Not Stuff1 2

RN1801SRN8K2J-2-GP-URN1801SRN8K2J-2-GP-U

12345 6

78910

R1804 22R2J-2-GPR1804 22R2J-2-GP1 2



1

2

R1805 22R2J-2-GPR1805 22R2J-2-GP1 2


RN1803

SRN10KJ-L-GP

RN1803

SRN10KJ-L-GP

12 3

4

R1801 Do Not StuffDY

R1801 Do Not StuffDY

1 2

R1806 22R2J-2-GPR1806 22R2J-2-GP1 2

R181122D6R2F-L1-GPR181122D6R2F-L1-GP

1 2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BATLOW#

PM_CLKRUN#

RBIAS_CPY

SUS_PWR_ACK_R

DSWODVREN

PM_RSMRST#

BATLOW#PM_RI#AC_PRESENT

SUS_PWR_ACK#

DSWODVREN

SYS_RESET#

PCH_DPWROKPM_RSMRST#

DMI_COMP_R

PM_RI#

SUS_PWR_ACK_R

PM_RSMRST#

3V_5V_POK_#

PWROK

PM_RSMRST#

PCIE_WAKE#

PWROK

SYS_PWROK

SUS_PWR_ACK#

SLLP_SUS#_TP

PCIE_WAKE#

RTC_AUX_S5

3D3V_S5

1D05V_VTT

3D3V_S0

3D3V_S0

RTC_AUX_S5

3D3V_AUX_S5

DMI_RXP[3:0]4DMI_RXN[3:0]4

PM_SLP_S4# 27,46

PM_CLKRUN# 27

H_PM_SYNC 5

PM_SLP_S3# 27,29,36,37,47

PCH_SUSCLK_KBC 27

DMI_RXP04

S0_PWR_GOOD27

PM_PWRBTN#27,97

DMI_RXP34DMI_RXP24DMI_RXP14

DMI_TXN14DMI_TXN04

DMI_TXP04

DMI_TXN34DMI_TXN24

DMI_TXP34DMI_TXP24DMI_TXP14

DMI_RXN04

PM_DRAM_PWRGD37

AC_PRESENT27

DMI_RXN34DMI_RXN24DMI_RXN14

FDI_LSYNC0 4

FDI_FSYNC1 4

FDI_TXP0 4

FDI_TXN0 4

FDI_INT 4

FDI_TXP6 4

FDI_TXP4 4

FDI_TXN6 4

FDI_TXP5 4

FDI_TXP2 4

FDI_TXN4 4

FDI_TXN7 4

FDI_TXP7 4

FDI_TXN5 4

FDI_TXN2 4FDI_TXN3 4

FDI_LSYNC1 4

FDI_FSYNC0 4

FDI_TXP1 4

FDI_TXP3 4

FDI_TXN1 4

RSMRST#_KBC 27

3V_5V_POK 41

DMI_TXP[3:0]4DMI_TXN[3:0]4

FDI_TXP[7:0] 4

SYS_PWROK36

FDI_TXN[7:0] 4

Title


Date: Sheet of


Husk/Petra -4MPCH (DM I/FDI/PM)

A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

Title


Date: Sheet of



A3


DIS IVB Touch

Signal Routing Guideline:DMI_ZCOMP keep W=4 mils androuting length less than 500mils.DMI_IRCOMP keep W=4 mils androuting length less than 500mils.

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

SSID = PCH

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

R1904100KR2J-4-GP

R1904100KR2J-4-GP1 2

R192210KR2J-L-GP

R192210KR2J-L-GP

12

R1902 750R2F-GPR1902 750R2F-GP1 2

R1901 49D9R2F-GPR1901 49D9R2F-GP1 2

R19121KR2J-L2-GP

R19121KR2J-L2-GP1 2


12345

678

R192110KR2J-L-GP

R192110KR2J-L-GP

12

R190510KR2J-L-GP

R190510KR2J-L-GP1 2

R1908100KR2J-4-GPR1908100KR2J-4-GP

12

R19198K2R2J-3-GPR19198K2R2J-3-GP

1 2

Q19012N7002KDW-GP84.2N702.A3F2nd = 84.DM601.03F3rd = 84.2N702.F3F

Q19012N7002KDW-GP84.2N702.A3F2nd = 84.DM601.03F3rd = 84.2N702.F3F

1

2

34

5

6

R1926Do Not Stuff

DYR1926

Do Not Stuff

DY1 2

D

M

I

F

D

I

S

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P

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3 OF 10PCH1C

PANTHER-GP-NF

71.PANTH.00U

D

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3 OF 10PCH1C

PANTHER-GP-NF

71.PANTH.00U

DMI0RXNBC24DMI1RXNBE20DMI2RXNBG18DMI3RXNBG20

DMI0RXPBE24DMI1RXPBC20DMI2RXPBJ18DMI3RXPBJ20

DMI0TXNAW24DMI1TXNAW20DMI2TXNBB18DMI3TXNAV18

DMI0TXPAY24DMI1TXPAY20DMI2TXPAY18DMI3TXPAU18

DMI_ZCOMPBJ24

DMI_IRCOMPBG25

FDI_RXN0 BJ14FDI_RXN1 AY14FDI_RXN2 BE14FDI_RXN3 BH13FDI_RXN4 BC12FDI_RXN5 BJ12FDI_RXN6 BG10FDI_RXN7 BG9

FDI_RXP0 BG14FDI_RXP1 BB14FDI_RXP2 BF14FDI_RXP3 BG13FDI_RXP4 BE12FDI_RXP5 BG12FDI_RXP6 BJ10FDI_RXP7 BH9

FDI_FSYNC0 AV12

FDI_FSYNC1 BC10

FDI_LSYNC0 AV14

FDI_LSYNC1 BB10

FDI_INT AW16

PMSYNCH AP14

SLP_SUS# G16

SLP_S3# F4

SLP_S4# H4

SLP_S5#/GPIO63 D10

SYS_RESET#K3

SYS_PWROKP12

PWRBTN#E20

RI#A10

WAKE# B9

SUS_STAT#/GPIO61 G8

SUSCLK/GPIO62 N14

ACPRESENT/GPIO31H20

BATLOW#/GPIO72E10

PWROKL22

CLKRUN#/GPIO32 N3

SUSWARN#/SUSPWRDNACK/GPIO30K16

RSMRST#C21

DRAMPWROKB13

SLP_LAN#/GPIO29 K14

APWROKL10

DPWROK E22

DMI2RBIASBH21

SLP_A# G10

DSWVRMEN A18

SUSACK#C12

R1918 Do Not StuffDYR1918 Do Not StuffDY1 2

TP1904 Do Not StuffTP1904 Do Not Stuff1

R1910Do Not StuffR1910Do Not Stuff1 2


1

2

R1911Do Not Stuff

DY

R1911Do Not Stuff

DY

1 2

R1924Do Not StuffR1924Do Not Stuff

12

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP1 2

R1909100KR2J-4-GP

R1909100KR2J-4-GP

12

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XTAL25_IN

PCIE_CLK_REQ6#

CLK_BUF_EXP_NCLK_BUF_EXP_P

XTAL25_OUT

CLK_BUF_CKSSCD_P

XTAL25_IN

XTAL25_OUT

PCH_GPIO74

DGPU_PRSNT#

PEG_B_CLKRQ#

PCIE_CLK_REQ1#

CLK_BUF_CKSSCD_NCLK_BUF_CKSSCD_PCLK_BUF_REF14

CLK_BUF_EXP_NCLK_BUF_EXP_P

CLK_BUF_DOT96_NCLK_BUF_DOT96_P

PCIE_CLK_REQ4#

XCLK_RCOMP

CLK_BUF_REF14

SMB_DATA

SML0_CLK

PCIE_TXP4_CPCIE_TXN4_C

CLK_BUF_DOT96_PCLK_BUF_DOT96_N

CLK_BUF_CKSSCD_N

SMB_CLK

SML0_DATA

PCIE_CLK_REQ7#

SMB_CLK

SMB_DATA

CLK_BUF_CPYCLK_NCLK_BUF_CPYCLK_P

DGPU_PRSNT#

PCIE_CLK_REQ1#

SMB_CLK

DRAMRST_CNTRL_PCH

SMB_DATA

SML0_DATASML0_CLK

SML1_DATASML1_CLK

PCIE_CLK_REQ4#

CLK_PCIE_WLAN_REQ#

PCH_GPIO74

PCIE_CLK_REQ5#

PEG_B_CLKRQ#PCIE_CLK_REQ7#

EC_SWI#

CLKOUT_DP_N_CCLKOUT_DP_P_C

PCIE_TXP3_CPCIE_TXN3_C

PCIE_CLK_REQ5#

PCIE_CLK_REQ6#

PCIE_CLK_REQ0#

PCIE_CLK_REQ0#

PCIE_CLK_LAN_REQ#1D05V_VTT

3D3V_S0

3D3V_S0 3D3V_S0

3D3V_S0

3D3V_S5

3D3V_S5

3D3V_S0

PCIE_RXN465PCIE_RXP465

PCIE_TXN465PCIE_TXP465

CLK_PCI_FB 18

PCH_SMBDATA 14,15,69

PCH_SMBCLK 14,15,69

CLK_PCIE_VGA# 83CLK_PCIE_VGA 83

SML1_DATA 27,28,49,86

SML1_CLK 27,28,49,86

PEG_CLKREQ# 83

DRAMRST_CNTRL_PCH 37

EC_SWI# 27

UMA_DIS# 22

PCIE_CLK_WLAN65PCIE_CLK_WLAN#65

CLK_PCIE_WLAN_REQ#65

CLK_EXP_N 5CLK_EXP_P 5

CLK_DP_P 5CLK_DP_N 5

PCIE_RXN331PCIE_RXP331

PCIE_TXN331PCIE_TXP331

PCIE_CLK_LAN#31PCIE_CLK_LAN31

PCIE_CLK_LAN_REQ#31

Title


Date: Sheet of


Husk/Petra -4MPCH (PCI-E/SMBUS/CLOCK/CL)

Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

Title


Date: Sheet of



Custom


DIS IVB Touch

SSID = PCH

UMA_DIS#;DGPU_PRSNT#UMA: 1 1DIS :0 1Muxless : 1 0PX:0 0

WLAN

need very close to PCH

WLAN

PCIECLKRQ1# and PCIECLKRQ2# Support S0 power only

Lan

LAN

R2013Do Not StuffUMA

R2013Do Not StuffUMA

1

2

RN2009SRN10KJ-L3-GPRN2009SRN10KJ-L3-GP

12345 6

78910


RN2008

SRN10KJ-L-GP

RN2008

SRN10KJ-L-GP

12 3

4


123

4

RN2018

SRN10KJ-L-GP

RN2018

SRN10KJ-L-GP

12 3

4

R201210KR2J-L-GP

R201210KR2J-L-GP

1

2

R201110KR2J-L-GPMuxless

R201110KR2J-L-GPMuxless

1

2

RN2017SRN0J-6-GP

EDP

RN2017SRN0J-6-GP

EDP12 3

4


R2010Do Not Stuff

DY

R2010Do Not Stuff

DY

1

2

R200790D9R2F-1-GP

R200790D9R2F-1-GP1 2


1234 5

678

RN2006SRN10KJ-L-GPRN2006SRN10KJ-L-GP

12

Date post:	13-Sep-2015
Category:	Documents
Upload:	ricardo-olivares
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ACER ACER Aspire V5-531p

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