5
4
3
2
1
Eiger Block DiagramD
Project code: 91.4Z501.001 PCB P/N : 48.4Z501.001 REVISION :
07246- -1PCB STACKUPTOP
SYSTEM DC/DCTPS51125INPUTS 43 OUTPUTS5V_S5 DCBATOUT
CLK GEN.ICS 9LPRS365BKLFT3
Mobile CPUPenryn4, 5
THERMAL EMC210223
3D3V_S5
D
SYSTEM DC/DCTPS51124INPUTSDCBATOUT 1D8V_S3 1D05V_S0
45
DDR2 DIMM1667/800 MHz12
HOST BUS 667/800MHz
667/800/[email protected]
CRT
Port Replicator
17 15
VCC S S GND BOTTOM
OUTPUTS
CantigaAGTL+ CPU I/F DDR Memory I/F INTEGRATED GRAHPICS LVDS,
CRT I/F
LCD
DDR2 DIMM2667/800 MHz13C
HDMI18
RT90261D8V_S3
44DDR_VREF_S0 DDR_VREF_S3
667/800MHz
PCIex166,7,8,9,10,11
INT.MIC35
X4 DMI 400MHz
MXM CONN30
RT9018A1D8V_S3 1D5V_S0
44C
C-Link0
Line In35
CodecALC888S VC 33
AZALIA
ICH9M6 PCIe ports PCI/PCI BRIDGE ACPI 2.0 4 SATA 12 USB 2.0/1.1
ports ETHERNET (10/100/1000MbE) High Definition Audio LPC I/F
Serial Peripheral I/F Matrix Storage Technology(DO) Active
Managemnet Technology(DO)
G9131
44
PCIex1 PCIex1
CardReader JMicro 27 JMB385
MS/MS Pro/xD /MMC/SD5 in 1
27
3D3V_S0
2D5V_S0
MIC In35
LAN Giga LAN88E8071 28
TXFM29
RJ4529
GFXCORE DC/DCISL6263 INPUTSDCBATOUT
46 OUTPUTS VGFXCORE0.7~1.25V
PCIex1 PCIex1 PCIex1
New card31
35B
OP AMPG1431Q 34
PWR SW G577BR91U31
Mini CardKedron a/b/g/n
INT.SPKR35
32 32
CPU DC/DCISL6266A INPUTSDCBATOUT
B
Line Out (SPDIF)
OP AMP G1412 34 MODEM MDC Card25 19,20,21,22
Mini CardKedron a/b/g/n
42
OUTPUTS VCC_CORE_S00.35~1.5V
LPC BUS BIOS USB SPI SATABlue Tooth (USB) eSATA 24 ODD SATA 2425
Winbond W25X80 8M Bits
RJ11
KBCCamera (USB) 15 USB 4 Port
LPC37
CHARGERBQ24745 INPUTS 38DCBATOUT
ENE331036 Launch Buttom 14
DEBUG CONN 37
47 OUTPUTS BT+ DCBATOUTA
BIOS/DASH 2Mb 37A
HDD SATA
26
SATA24
Touch Pad 36Finger Printer
INT. KB 36
CIR36UMA
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date: Document
Number
BLOCK DIAGRAM Eiger1
Rev
-1Sheet 1 of 50
Tuesday, April 01, 2008
5
4
3
2
A
Bpage 92
C
ICH9M Functional Strap Definitions Rev.1.5 ICH9 EDS 642879Signal
HDA_SDOUT Usage/When Sampled XOR Chain Entrance/ PCIE Port Config1
bit1, Rising Edge of PWROK PCIE config1 bit0, Rising Edge of PWROK.
PCIE config2 bit2, Rising Edge of PWROK. Reserved ESI Strap (Server
Only) Rising Edge of PWROK Comment
ICH9M Integrated Pull-up and Pull-down ResistorsCL_CLK[1:0]
CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK
HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC
GLAN_DOCK# GPIO[20] GPIO[49] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0]
LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED#SPI_CS1#/GPIO58/CLGPIO6
GNT[3:0]#/GPIO[55,53,51]
Cantiga chipset and ICH9M I/O controller Hub strapping
configurationRev.1.5Pin Name CFG[2:0]
D
E
ICH9 EDS 642879
Montevina Platform Design guide 22339page 218 Configuration 000
= FSB1067 011 = FSB667 010 = FSB800 others = Reserved
0.5
Allows entrance to XOR Chain testing when TP3 pulled low.When
TP3 not pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers: offset 224h). This signal has weak
internal pull-down This signal has a weak internal pull-down. Sets
bit0 of RPC.PC(Config Registers:Offset 224h) This signal has a weak
internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset
0224h) This signal should not be pulled high. ESI compatible mode
is for server platforms only. This signal should not be pulled low
for desttop and mobile. Sampled low:Top-Block Swap mode(inverts A16
for all cycles targeting FWH BIOS space). Note: Software will not
be able to clear the Top-Swap bit until the system is rebooted
without GNT3# being pulled down. Controllable via Boot BIOS
Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is
MSB, 01-SPI, 10-PCI, 11-LPC. Sample low: the Integrated TPM will be
disabled. Sample high: the MCH TPM enable strap is sampled low and
the TPM Disable bit is clear, the Integrated TPM will be
enable.
SIGNAL
Resistor Type/ValuePULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN
20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN
20K PULL-DOWN 20K PULL-DOWN 20KThe pull-up or pull-down active when
configured for native GLAN_DOCK# functionality and determined by
LAN controller
Strap Description FSB Frequency Select
CL_DATA[1:0]
4
HDA_SYNC GNT2#/ GPIO53 GPIO20 GNT1#/ GPIO51
CFG[4:3] CFG8 CFG[15:14] CFG[18:17] CFG5 CFG6
Reserved
4
DMI x2 Select iTPM Host Interface Intel Management engine Crypto
strap
0 = DMI x2 1 = DMI x4 (Default) 0= The iTPM Host Interface is
enabled(Note2) 1=The iTPM Host Interface is disalbed(default) 0 =
Transport Layer Security (TLS) cipher suite with no confidentiality
1 = TLS cipher suite with confidentiality (default) 0 = Reverse
Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane
Numbered in order 0 = Enable (Note 3) 1= Disabled (default) 00 10
01 11 = = = = Reserve XOR mode Enabled ALLZ mode Enabled (Note 3)
Disabled (default)
GNT3#/ GPIO55
Top-Block Swap Override. Rising Edge of PWROK.
CFG7
CFG9
PCIE Graphics Lane
GNT0#: SPI_CS1#/ GPIO58 SPI_MOSI
Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.
Integrated TPM Enable, Rising Edge of CLPWROK
PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K
PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP
20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K
PULL-DOWN 15KL_DDC_DATA Local Flat Panel (LFP) Present
SDVO_CTRLDATA SDVO Present CFG20 CFG19 DMI Lane Reversal CFG16 FSB
Dynamic ODT CFG10 CFG[13:12] PCIE Loopback enable XOR/ALL
3GPIO49
DMI Termination Voltage, The signal is required to be low for
desktop Rising Edge of PWROK. applications and required to be high
for mobile applications. PCI Express Lane Reversal. Rising Edge of
PWROK. No Reboot. Rising Edge of PWROK. Signal has weak internal
pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) If
sampled high, the system is strapped to the "No Reboot" mode(ICH9
will disable the TCO Timer system reboot feature). The status is
readable via the NO REBOOT bit. This signal should not be pull low
unless using XOR Chain testing. Sampled low:the Flash Descriptor
Security will be overridden. If high,the security measures will be
in effect.This should only be enabled in manufacturing environments
using an external pull-up resister.
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) 0 =
Normal operation(Default): Lane Numbered in Order
3
SATALED# SPKR
1 = Reverse Lanes DMI x4 mode[MCH ->
ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH ->
ICH]:(3->0,2->1) Digital Display Port (SDVO/DP/iHDMI)
Concurrent with PCIe 0 = Only Digital Display Port or PCIE is
operational (Default) 1 =Digital display Port and PCIe are operting
simulataneously via the PEG port 0 =No SDVO Card Present (Default)
1 = SDVO Card Present 0 = LFP Disabled (Default) 1= LFP Card
Present; PCIE disabled
SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]
TP3
XOR Chain Entrance. Rising Edge of PWROK. Flash Descriptor
Security Override Strap Rising Edge of PWROK
GPIO33/ HDA_DOCK _EN#
2
SMBusSMBC_Therm SMBD_Therm
Media Board
NOTE: 1. All strap signals are sampled with respect to the
leading edge of the (G)MCH Power OK (PWROK) signal. 2. iTPM can be
disabled by a 'Soft-Strap' option in the Flash-decriptor section of
the Firmware. This 'Soft-Strap' is activated only after enabling
iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be
enabled at any time.
2
Thermal MXM
USB TableUSB
KBC
BAT_SCL BAT_SDA
PCIE RoutingLANE1 LANE2 LANE3 LANE4 LANE5 LAN MARVELL 88E8071
MiniCard WLAN MiniCard WWAN/TV JMB385 Card Reader NewCard NC
Pair 0 1 2 3 4 5 6 7 8 9 10 11
Device USB1 USB4 USB2 USB5(DOCK) USB3 Bluetooth FP MINIC1 WEBCAM
NEW1 MINIC2 NCSMBC_ICH
BATTERY
CHARGER
1
LANE6
ICH9M
SO-DIMM
UMA
1
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
9LPRS365BKLFT DDRSize A3 Date:
ReferenceDocument Number Tuesday, April 01, 2008 Rev
Eiger
-1Sheet 2 of 50
A
B
C
D
E
3D3V_S0 3D3V_S0 R20 R57 R35 3D3V_CLKGEN_S0
3D3V_S0
1
2
3D3V_48MPW R_S0
3D3V_CLKPLL_S0
2 1 1 1C106 SCD1U16V2ZY-2GP C104 SCD1U16V2ZY-2GP C75
1
1
1
1
1
1
1
1
1
1
1
1
Do Not Stuff
C46 Do Not Stuff
C34
EC15 Do Not Stuff Do Not Stuff
C84
C108 SC4D7U10V5ZY-3GP
C70
C102 Do Not Stuff
C47 SC4D7U10V5ZY-3GP
C67 SCD1U16V2ZY-2GP
C38 SCD1U16V2ZY-2GP
C53 SCD1U16V2ZY-2GP
1
1 Do Not Stuff
2 1 Do Not Stuff C105SCD1U16V2ZY-2GP
C36 Do Not Stuff Do Not Stuff
SC1U16V3ZY-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY2
DY2
2
2
2
2
2
2
2
2
2
2
2
2
2
DY
DY
4
2
4
3D3V_CLKGEN_S0
SBPCLK_ICH CLK_ICH14
1
EMI near R12
2
DY
near R16
2
C29 Do Not Stuff
EMI
EMIC51 SC5P50V2CN-2GP 3D3V_48MPW R_S0
1
1C31 Do Not Stuff
CLK48_ICH
3D3V_CLKPLL_S0
near R194 16 9 46 62 23 19 27 43 52 33 56
DY
2
U9
VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3
C45 SC27P50V2JN-2-GP GEN_XTAL_IN 1 2
VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO
CL=20pF0.2pFR24 R34 X1 X-14D31818M-35GP
2 1
DY
1 Do Not StuffGEN_XTAL_OUT
CPUT0 CPUC0 CPUT1_F CPUC1_F CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8
61 60 58 57 54 53 51 50 48 47 41 42 40 39 37 38 34 35 31 32 28
29 24 25 20 21DREFSSCLK_1 DREFSSCLK#_1 DREFCLK_1 DREFCLK#_1
CLK_PCIE_PEG_1 CLK_PCIE_PEG_1#
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6
CLK_PCIE_LAN 28 CLK_PCIE_LAN# 28 CLK_PCIE_NEW 31 CLK_PCIE_NEW # 31
CLK_PCIE_ICH 20 CLK_PCIE_ICH# 20
CPU NB LAN New Card SB DMI MXM JMB385 MINI2 NB CLK MINI1 SB SATA
NB CLK NB CLK (96 MHz)3
82.30005.891 82.30005.951C35 1
2 Do Not Stuff
3 2
X1 X2
2
1GEN_XTAL_OUT_R
2
SC27P50V2JN-2-GP3
20 4,7
CLK48_ICH CPU_SEL0
R37 R38
2 2
1 33R2J-2-GP 1 2K2R2J-2-GP
CLK48
17
USB_48MHZ/FSLA SRCT7/CR#_F SRCC7/CR#_E PCI_STOP# CPU_STOP# SRCT6
SRCC6 SRCT10 SRCC10 SRCT11/CR#_H SRCC11/CR#_G SRCT9 SRCC9
PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN
SRCT4 SRCC4 SRCT3/CR#_C SRCC3/CR#_D SRCT2/SATAT SRCC2/SATAC
FSLB/TEST_MODE REF0/FSLC/TEST_SEL NC#55 GND GNDSRC GNDSRC GNDSRC
GNDCPU GND GND48 GNDPCI GNDREF 27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2 SRCT0/DOTT_96 SRCC0/DOTC_96
3D3V_S0
EMI near X1
1D8V_S3 RN66
20 PM_STPPCI# 20 PM_STPCPU#
45 44
1
C742 Do Not Stuff
PCLKCLK1 PCLKCLK0
4 3
1 2Do Not Stuff
12,13,22 SMBC_ICH 12,13,22 SMBD_ICH
7 6 63
SCLK SDATA CK_PWRGD/PD#
2 1
3 4
RN17 Do Not Stuff
DIS
CLK_PCIE_PEG 30 CLK_PCIE_PEG# 30
2
DY
DY3D3V_S0 RN63 20 7
2 R36
DY
20 CLK_PW RGD 1 Do Not Stuff R26 1 R123 1 R31
CLK_PCIE_CARDREADER 27 CLK_PCIE_CARDREADER# 27 CLK_PCIE_MINI2 32
CLK_PCIE_MINI2# 32 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 CLK_PCIE_MINI1
32 CLK_PCIE_MINI1# 32 CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19
SATACLKREQ# CLK_MCH_OE# 37 36 20 PCLK_FW H PCLK_KBC PCLK_ICH
DY DY
2 Do Not Stuff 2 Do Not Stuff 1 33R2J-2-GP 4 3
8 7 6 5
1 2 3 4SRN10KJ-6-GP
PCLKCLK2 PCLKCLK4 PCLKCLK5
2 1 2
PCLKCLK0 PCLKCLK1 PCLKCLK2 PCLKCLK3 PCLKCLK4 PCLKCLK5
8 10 11 12 13 14
RN4
SRN33J-5-GP-U
PCLK_KBC
4,7 4,7
CPU_SEL1 CPU_SEL2 CLK_ICH14
R27 R25
2 2
1 10KR2J-3-GP CPU_SEL2_R 1 33R2J-2-GP
64 5 55
UMA2 1 2 1 3 4 3 4
EMI near R112
2
C30 Do Not Stuff
20
RN7 SRN0J-6-GP RN5 SRN0J-6-GP
DREFSSCLK 7 DREFSSCLK# 7 DREFCLK 7 DREFCLK# 7
1
DY
GND
2
UMA
ICS9LPRS365BKLFT setting table PIN NAME DESCRIPTION
PCI0/CR#_AByte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A
enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2
pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A
controls SRC2 pair Byte 5, bit 5 0 = PCI1 enabled (default) 1=
CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1
or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair 0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed 3.3V PCI clock
output
18 15 1
22 30 36 49 59 26
71.00875.C03 71.09365.A03 ICS9LPRS365BKLFT-GP
65
RTM875N-606-VD-GRT-GP
SEL2 SEL1 SEL0 FSC FSB FSA PIN NAME SRCC3/CR#_D SRCC7/CR#_E
DESCRIPTIONByte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D
enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4
pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D
controls SRC4 pair Byte 6, bit 7 0 = SRC7# enabled (default) 1=
CR#_F controls SRC6 Byte 6, bit 6 0 = SRC7 enabled (default) 1=
CR#_F controls SRC8 Byte 6, bit 5 0 = SRC11# enabled (default) 1=
CR#_G controls SRC9 Title Byte 6, bit 4 0 = SRC11 enabled (default)
1= CR#_H controls SRC10 UMA
CPU100M 133M 166M 200M 266M
FSBX 533M 667M 800M 1066M1
PCI1/CR#_B PCI2/TME PCI31
1 0 0 0 0
0 0 1 1 0
1 1 1 0 0
PCI4/27M_SEL PCI_F5/ITP_EN SRCT3/CR#_C
0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as
DOT96# 1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21
as SRC-0# 0 =SRC8/SRC8# 1 = ITP/ITP# Byte 5, bit 3 0 = SRC3 enabled
(default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C
controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0
pair (default), 1= CR#_C controls SRC2 pair
SRCT7/CR#_F SRCC11/CR#_G SRCT11/CR#_H
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Clock GeneratorDocument Number Rev
Size Date:
EigerTuesday, April 01, 2008 SheetE
-13 of 50
A
B
C
D
A
B
C
D
E
6
H_A#[35..3]
H_A#[35..3] H_DINV#[3..0] H_DSTBN#[3..0] U49A 1 OF 4 H_A#3 H_A#4
H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14
H_A#15 H_A#16 TP21 Do Not Stuff H_DSTBP#[3..0] H_DINV#[3..0]
H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] 64
6 6 6
4
6 6
H_ADSTB#0 H_REQ#[4..0]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2
U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5
C4 D5 C6 B4 A3
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16#
ADSTB0# REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22#
A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35#
ADSTB1# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD#M4 RSVD#N5
RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6
KEY_NC
ADS# BNR# BPRI#
H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1
AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20XDP_BPM#0 XDP_BPM#1 XDP_BPM#2
XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS
XDP_TRST# XDP_DBRESET# H_RS#0 H_RS#1 H_RS#2
H_ADS# H_BNR# H_BPRI#
6 6 6
1D05V_S0 H_D#[63..0]
ADDR GROUP 0
CONTROL
DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2#
TRDY# HIT# HITM#
H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ#0 6 H_IERR# H_INIT# 19
1
R100 56R2J-4-GP
Place testpoint on H_IERR# with a GND 0.1" away
2
TP29 Do Not Stuff
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19
H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28
H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_LOCK# 6 H_CPURST# 6,49 H_RS#[2..0]
U49B 2 OF 4 6 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7
H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 6 6 6
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20
H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29
H_D#30 H_D#31 6 6 6 H_DSTBN#1 H_DSTBP#1 H_DINV#1
H_TRDY# H_HIT# H_HITM# TP7 TP5 TP6 TP11 TP9 TP10 TP8 TP15 TP12
TP14 TP13 TP25
6 6 6 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not
Stuff Do Not Stuff Do Not Stuff Do Not Stuff1D05V_S0 Do Not Stuff
Do Not Stuff Do Not Stuff Do Not Stuff R98 68R2-GP H_THERMDA
XDP/ITP SIGNALS
3
Side Band Non GTL6 19 19 19 19 19 19 19 H_ADSTB#1 H_A20M#
H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# Do Not Stuff TP19 Do
Not Stuff TP18 Do Not Stuff TP17 Do Not Stuff TP16 Do Not Stuff
TP27 Do Not Stuff TP31 Do Not Stuff TP24 Do Not Stuff TP28 Do Not
Stuff TP26 Do Not Stuff TP22 Do Not Stuff TP32
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST#
DBR#
DYH_THERMDC
2
C144 Do Not Stuff
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23
J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25
T25 N25 L26 M26 N24
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14#
D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23#
D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL0 BSEL1 BSEL2
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44#
D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53#
D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3#
DINV3# COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP#
PSI#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24
AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25
AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5
D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40
H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 6
H_DSTBP#2 6 H_DINV#2 6 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53
H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62
H_D#63 H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3
R67 R59 R53 R54
DATA GRP2
DATA GRP0
1
2
THERMTRIP#
C7
PM_THRMTRIP-A# 7,19,23,40
HCLK
BCLK0 BCLK1
A22 A21
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 PM_THRMTRIP# should connect to
ICH9 and MCH without T-ing ( No stub) Layout Note: "CPU_GTLREF0"
0.5" max length.
1D05V_S0
2
RSVD_CPU_1 RSVD_CPU_2 RSVD_CPU_3 RSVD_CPU_4 RSVD_CPU_5
RSVD_CPU_6 RSVD_CPU_7 RSVD_CPU_8 RSVD_CPU_9 RSVD_CPU_10
RSVD_CPU_11
M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 B1
RESERVED
R327 1KR2F-3-GP
1
2
CPU_GTLREF0
DATA GRP3
1
1
BGA479-SKT-8-GP-U2
2
2
ADDR GROUP 11D05V_S0
3
THERMALPROCHOT# THRMDA THRMDC D21 A24 B25CPU_PROCHOT# H_THERMDA
23 H_THERMDC 23
1
DY1 R99 2 Do Not StuffCPU_PROCHOT#_R 42
DATA GRP1
62.10053.401 62.10079.001
ICH ICH
R330 2KR2F-3-GP
DY
Do Not Stuff TP23 C407 Do Not Stuff Do Not Stuff Do Not Stuff
TP3 Do Not Stuff TP112 3,7 3,7 3,7 CPU_SEL0 CPU_SEL1 CPU_SEL2
AD26 TEST1 C23 TEST2 D25 RSVD_CPU_12 C24 TEST4 AF26 RSVD_CPU_13
AF1 RSVD_CPU_14 A26 B22 B23 C21
MISC
1 1 1 1
2 2 2 2
27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
2
H_DPRSTP# 7,19,42 H_DPSLP# 19 H_DPW R# 6 H_PW RGD 19,40,49
H_CPUSLP# 6 PSI# 42
BGA479-SKT-8-GP-U2
Follow Demo CircuitXDP_TMS XDP_TDI XDP_BPM#5 R321 1 R320 1 R324
1
62.10053.401 62.10079.001
2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 1 R92 1 R393 2
C402
DY DY
2 TEST1 Do Not Stuff 2TEST2 Do Not Stuff
Net "TEST4" as short as possible, make sure "TEST4" routing is
reference to GND and away other noisy signals
Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace
length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_CPURST# XDP_TCK1
R106 1 R323 1 R322 1
DY
2 Do Not Stuff 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP
TEST4 1 Do Not Stuff
XDP_TRST#
DY3D3V_S0 UMA1
All place within 2" to CPUXDP_DBRESET# R101
1
DY
2 Do Not Stuff1D05V_S0 Title
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
XDP_TDO R58
1
DY
2 Do Not StuffSize Date: Document Number Tuesday, April 01,
2008
CPU (1 of 2)Rev
Eiger
-1SheetE
4
of
50
A
B
C
D
A
B
C
D
E
VCC_CORE VCC_CORE VCC_CORE4
VCC_CORE
U49D
4 OF 4
1 4
VCC_CORE
1
1
1
1
1
1
1
C71
C134 Do Not Stuff
C135 Do Not Stuff Do Not Stuff
C77
C78 Do Not Stuff
C138 Do Not Stuff
C143 Do Not Stuff
1
U49C 3 OF 4
C76 Do Not Stuff
3
2
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18
B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10
E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9
AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15
AB17 AB18
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCCP VCCP VCCP VCCA VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6
VCCSENSE VSSSENSE
2
2
2
2
2
2
2
2
G5
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26
AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
VCCP_1D05
1
2Do Not Stuff
DY
DY
1
C128 SCD1U10V2KX-4GP
1
C111 SCD1U10V2KX-4GP
2
2
layout note: "1D5V_VCCA_S0" as short as possible1D5V_S0
1D5V_VCCA_S0 L12
1 1H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
VCC_SENSE_CPU VSS_SENSE_CPU H_VID[6..0] VCC_CORE 42 C490
SCD01U16V2KX-3GP
2
1
C496 SC10U6D3V5MX-3GP
HCB1608KF121T30-GP
68.00230.041
2
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14
AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12
AF14 AF15 AF17 AF18 AF20
TC1 ST900U2D5VM-1-GP
77.E9071.011 NECTP1 Do Not Stuff
77.E9071.001
CAP
CAP CAP
CAP
DY
DY
DY
DY
VCC_CORE
C136 Do Not Stuff
C113 Do Not Stuff
C147 Do Not Stuff
C396 Do Not Stuff
C440 Do Not Stuff
C428 Do Not Stuff Do Not Stuff
C431 Do Not Stuff Do Not Stuff
C427 Do Not Stuff Do Not Stuff
C59 Do Not Stuff Do Not Stuff
C398 Do Not Stuff Do Not Stuff
C117 Do Not Stuff
C395 Do Not Stuff
C114 Do Not Stuff
C116 Do Not Stuff
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
1D05V_S0
C115 SCD1U10V2KX-4GP
C112 SCD1U10V2KX-4GP
C118 Do Not Stuff
C122 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
C124 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
C94 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
C103 Do Not Stuff Do Not Stuff
C101 SC4D7U6D3V3KX-GP
C500 SC4D7U6D3V3KX-GP
1D05V_S0
R319 100R2F-L1-GP-U G105 1 G107 1
2 Do Not Stuff 2 Do Not Stuff
VCC_SENSE 42 VSS_SENSE 42
BGA479-SKT-8-GP-U2
62.10053.401 62.10079.0012
R318 100R2F-L1-GP-U Layout Note: VCCSENSE and VSSSENSE lines
should be of equal length.
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5
C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3
E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4
G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24
M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22
V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19
AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8
AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22
AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13
AF16 AF19 AF21 A25 AF25
4
Do Not Stuff
Do Not Stuff Do Not Stuff
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2 3 1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
1
1
1
1
1
1
1
1
1
2
2
1
2
Do Not Stuff TP4
2
1
Do Not Stuff TP2 TP30 Do Not Stuff
1
Layout Note: Provide a test point (with no stub) to connect a
differential probe between VCCSENSE and VSSSENSE at the location
where the two 54.9ohm resistors terminate the 55 ohm transmission
line.
TP113 Do Not Stuff TP109 Do Not Stuff
BGA479-SKT-8-GP-U2
62.10053.401 62.10079.0011
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (2 of 2)Size Date:A B C D
Document Number Tuesday, April 01, 2008
Rev
Eiger
-1SheetE
5
of
50
5
4
3
2
1
U54A 4 H_D#[63..0] H_D#[63..0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4
H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14
H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23
H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32
H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41
H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50
H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59
H_D#60 H_D#61 H_D#62 H_D#63
1 OF 10 H_A#[35..3]
D
H_SWING routing Trace width and Spacing use 10 / 20 mil H_SWING
Resistors and Capacitors close MCH 500 mil ( MAX )1
1D05V_S0
R446 221R2F-2-GP
H_SW ING C550 SCD1U10V2KX-4GP
R442 100R2F-L1-GP-U
C
H_RCOMP routing Trace width and Spacing use 10 / 20 mil1 R439 2
24D9R2F-L-GPH_RCOMP
Place them near to the chip ( < 0.5")
B
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6
M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8
Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14
AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8
H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16
H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24
H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32
H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40
H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48
H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56
H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11
H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19
H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27
H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER#
H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK#
H_TRDY#
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19
J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12
H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21
H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30
H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4
H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3 H_DPW R# 4 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4
H_TRDY# 4
H_A#[35..3]
4
D
2
2
1
2
1
C
HOST
H_DINV#[3..0]
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1
H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1
H_RS#_2
J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6
F12 C8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#[3..0] H_DSTBN#0
H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#[3..0] H_DSTBP#0 H_DSTBP#1
H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0
H_RS#1 H_RS#2
H_DINV#[3..0]
4
H_DSTBN#[3..0]
4
H_DSTBP#[3..0]
4
B
1D05V_S0
H_REQ#[4..0]
4
2
H_SW ING H_RCOMP R453 1KR2F-3-GP 4,49 H_CPURST# 4 H_CPUSLP#
H_AVREF SCD1U16V2ZY-2GP
C5 E3 C12 E11 A11 B11
H_SWING H_RCOMP H_CPURST# H_CPUSLP# H_AVREF H_DVREF
H_RS#[2..0]
4
1
1
1
C561 CANTIGA-GM-GP-U-NF
2
R448 2KR2F-3-GP
71.CNTIG.00U
71.CNTIG.D1UUMAA
A
2
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2
Document Number Tuesday, April 01, 2008
Cantiga (1 of 6) EigerSheet1
Rev
-16 of 50
5
4
3
2
1
U54B RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33
RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12
RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35
RESERVED#T24
2 OF 10 U54C 3 OF 10 1D05V_S0
DDR CLK/ CONTROL/COMPENSATION
1D8V_S3
R471 1KR2F-3-GP 2
SM_RCOMP_VOH 1 1D
C586
1
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24
B31 B2 M1 AY21
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0
SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1
SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP
SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT
SM_DRAMRST#
AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17
AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36
BF17 BC36 B38 A38 E41 F41 F43 E43
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0
M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3
M_CS0# M_CS1# M_CS2# M_CS3# M_ODT0 M_ODT1 M_ODT2 M_ODT3 M_RCOMPP
M_RCOMPN SM_RCOMP_VOH SM_RCOMP_VOL 12 12 13 13 12 12 13 13 12 12 13
13
12 12 13 13 12 12 13 13
15 L_BKLTCTL 36 GMCH_BL_ON Do Not Stuff TP73 Do Not Stuff TP75
15 CLK_DDC_EDID 15 DAT_DDC_EDID 15 GMCH_LCDVDD_ON R178 2
L_BKLTCTL GMCH_BL_ON LCTLA_CLK LCTLB_DATA CLK_DDC_EDID
DAT_DDC_EDID
L32 G32 M32 M33 K33 J33
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK
L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL
LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0
LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1
LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2
LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
LVDSB_DATA_3
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3
PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9
PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6
PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13
PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3
PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9
PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6
PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13
PEG_TX_14 PEG_TX_15
T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43
AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42
AD36 AC48 AD40
PEG_CMP 2 R166 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4
PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11
PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXP0 PEG_RXP1 PEG_RXP2
PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9
PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 1 DIS 1
DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1
DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1
DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 49D9R2F-GP
Close to GMCH as 500 mils.PEG_RXN[15..0] 30
1
C587 SC2D2U6D3V3MX-1-GP SM_RCOMP_VOL
R470 3K01R2F-3-GP 2
2
2
SCD01U16V2KX-3GP
RESERVED#B31 RESERVED#B2 RESERVED#M1 RESERVED#AY21
GMCH_LCDVDD_ON M29 LIBG C44 L_LVBG B43 E37 GMCH_LVDS_VREF E38 1
0R2J-2-GP C41 15 GMCH_TXACLKC40 UMA 15 GMCH_TXACLK+ B37 15
GMCH_TXBCLKA37 15 GMCH_TXBCLK+ Do Not Stuff TP81 15 GMCH_TXAOUT015
GMCH_TXAOUT115 GMCH_TXAOUT215 GMCH_TXAOUT0+ 15 GMCH_TXAOUT1+ 15
GMCH_TXAOUT2+ H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42
G38 F37 K37
D
RSVD
LVDS
1
1
C579
1
C580 SC2D2U6D3V3MX-1-GP BG23 BF23 BH18 BF18
2
2
RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18
DDR_VREF_S3 15 GMCH_TXBOUT015 GMCH_TXBOUT115 GMCH_TXBOUT215
GMCH_TXBOUT0+ 15 GMCH_TXBOUT1+ 15 GMCH_TXBOUT2+
layout take note
1
DDR2 : connect to GNDSM_REXT R456 1 TP_SM_DRAMRST# DREFCLK
DREFCLK# DREFSSCLK DREFSSCLK# 2 499R2F-2-GP TP76Do Not Stuff
DREFCLK 3 DREFCLK# 3 DREFSSCLK 3 DREFSSCLK# 3 CLK_MCH_3GPLL
CLK_MCH_3GPLL# 3 3
C258 SCD1U10V2KX-4GP
1D8V_S3
DDR2 : Leave as NC
2
GRAPHICS
R466 1KR2F-3-GP 2
SCD01U16V2KX-3GP
PEG_RXP[15..0]
30
PCI-EXPRESS
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
PEG_CLK PEG_CLK#
PEG_TXN[15..0] C261 C266 C268 C264 C281 C247 C278 C248 C276 C250
C273 C272 C253 C256 C254 C271 C262 C265 C267 C263 C280 C246 C279
C249 C277 C251 C274 C275 C252 C257 C255 C270 Do Not Stuff Do Not
Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not
Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not
Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not
Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not
Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not
Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not
Stuff PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5
PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12
PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3
PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10
PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
PEG_TXP[15..0]
30
CLK
R463 80D6R2F-L-GP 2 M_RCOMPP M_RCOMPN 1
TVA_DAC TVB_DAC TVC_DAC
F25 H25 K25 H24
TVA_DAC TVB_DAC TVC_DAC TV_RTN
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 3,4 3,4 3,4 R531 2 1 Do
Not Stuff CFG6 CPU_SEL0 CPU_SEL1 CPU_SEL2 T25 R25 P25 P20 P24 C25
N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 CFG_0
CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11
CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35
AE44 AF46 AH43
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2
DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1
DMI_RXP2 DMI_RXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
20 20 20 20
C31 E32
R460 80D6R2F-L-GP 2C
TV_DCONSEL_0 TV_DCONSEL_1
DMI_TXP0 20 DMI_TXP1 20 DMI_TXP2 20 DMI_TXP3 20 DMI_RXN0
DMI_RXN1 DMI_RXN2 DMI_RXN3 20 20 20 20 38 GMCH_BLUE GMCH_BLUE
GMCH_GREEN GMCH_RED E28 G28 J28 G29 17 GMCH_DDCCLK 17 GMCH_DDCDATA
17 17 GMCH_HSYNC GMCH_VSYNC 2 1 3 4 RN14 SRN33J-5-GP-U GMCH_DDCCLK
GMCH_DDCDATA GMCH_HS GMCH_VS H32 J32 J29 E29 L29 CRT_BLUE CRT_GREEN
CRT_RED
J41 GTXN0 M46 GTXN1 M47 GTXN2 M40 GTXN3 M42 GTXN4 R48 GTXN5 N38
GTXN6 T40 GTXN7 U37 GTXN8 U40 GTXN9 Y40 GTXN10 AA46 GTXN11 AA37
GTXN12 AA40 GTXN13 AD43 GTXN14 AC46 GTXN15 J42 GTXP0 L46 GTXP1 M48
GTXP2 M39 GTXP3 M43 GTXP4 R47 GTXP5 N37 GTXP6 T39 GTXP7 U36 GTXP8
U39 GTXP9 Y39 GTXP10 Y46 GTXP11 AA36 GTXP12 AA39 GTXP13 AD42 GTXP14
AD46 GTXP15
1
TV
C
30
DMI
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1
DMI_TXP_2 DMI_TXP_3
38 GMCH_GREEN 38 GMCH_RED
CFG
3D3V_S0
DYR525 R175 1 2 Do Not Stuff CFG20 2 1 Do Not Stuff CFG9
DMI_RXP0 20 DMI_RXP1 20 DMI_RXP2 20 DMI_RXP3 20
VGA
CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF
CRT_VSYNC
DYCFG20
DY
GRAPHICS VID
SB
20 PM_SYNC# 4,19,42 H_DPRSTP# 20,23,42 VGATE_PWRGD 20,23 PWROK
20,27,28,30,31,32,36,37 R186 Do Not Stuff 1 DY 2 2 Do Not Stuff 2 1
R122 100R2J-2-GP C155 SC100P50V2JN-3GP 1
R187 1 PLT_RST1#
PM_SYNC# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PWROK_GD RSTIN#
PM_THRMTRIP-A# PM_DPRSLPVR
R29 B7 N33 P32 AT40 AT11 T20 R32
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN#
THERMTRIP# DPRSLPVR
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID[4..0]
46
UMA1 R516
UMA 2
CRT_IREF 1K02R2F-1-GP
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
GTXN0 GTXN1 GTXN2 GTXN3
1 UMA 1 UMA 1 UMA 1 UMA 1 UMA 1 UMA 1 UMA 1 UMA
2 2 2 2
C646 C641 C639 C643
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
HDMI_DATA2- 18 HDMI_DATA1- 18 HDMI_DATA0- 18 HDMI_CLK- 18
HDMI_DATA2+ 18 HDMI_DATA1+ 18 HDMI_DATA0+ 18 HDMI_CLK+ 18
HDMI_DETECT# 18
2
PM
GFX_VR_EN
C34
GFXVR_EN
GFXVR_EN 46
1D05V_S0 R185 1KR2F-3-GP 1
FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm
TO level shifter
GTXP0 GTXP1 GTXP2 GTXP3
2 C645 2 C642 2 C640 2 C644
SB4,19,23,40B
MISC
DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ#
ICH_SYNC# TSATN#
R605 2
1 Do Not Stuff GMCH_HDMI_CLK 18 GMCH_HDMI_DATA 18 CLK_MCH_OE# 3
MCH_ICH_SYNC# 20
SCD1U10V2KX-4GP 2
PM_THRMTRIP-A# 20,42 PM_DPRSLPVR
HDA
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6
BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46
NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3
NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
ME
AH37 AH36 AN36 CLPWROK_MCH 1 R189 2 Do Not Stuff AJ35 AH34
MCH_CLVREF
CL_CLK0 20 CL_DATA0 20 PWROK 20,23 CL_RST#0 20
CRT_IREF routing Trace width use 20 mil
PEG_RXP3
UMA
1 R176
2 0R2J-2-GP
GMCH_BL_ON 1
UMA1 2 R165 100KR2J-1-GP
2
For HDMI port CN28 M28 G36 E36 K36 H36 B12
3D3V_S0
C245
DY
R184 511R2F-2-GP 2
SBRN83 GMCH_BLUE GMCH_GREEN GMCH_RED 4 3 2 1 5 6 7 8
SRN150J-1-GP
1
GMCH_LCDVDD_ON 1 2 R164 100KR2J-1-GPB
UMA
NC
FOR Cantiga:500 ohm Teenah: 392 ohm
LIBG
UMA1 2 R183 2K37R2F-GP RN65
MCH_TSATN#
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
B28 B30 B29 C29 A28
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
1 2 R511 1 2 1
TP67 Do Not Stuff RN10 4 3
UMAACZ_BIT_CLK_R 19 ACZ_RST#_R 19 ACZ_SDIN3 19 ACZ_SDATAOUT_R 19
ACZ_SYNC_R 19
UMA_66.R0036.A8L:DIS FOR Discrete,change to 0 ohm
66.R0036.A8LRN64 DREFCLK DREFCLK# DREFSSCLK DREFSSCLK# 4 3 2 1 Do
Not Stuff 5 6 7 8
CRT_IREF GMCH_HS GMCH_VS
SRN33J-5-GP-U UMA 2 0R2J-2-GP RN8 3 4 SRN33J-5-GP-U
1 2 3 4
8 7 6 5 Do Not Stuff
DIS
CANTIGA-GM-GP-U-NF
UMA
DISR159 TVA_DAC 1 2 75R2J-1-GP 3D3V_S0
71.CNTIG.00U
UMA_63.R0034.1DL:DISLCTLA_CLK LCTLB_DATA 4 3
RN33 1 2 SRN10KJ-5-GP
Pin Name CFG20
Strap Description Digital DisplayPort (SDVO/DP/HDMI) Concurrent
with PCIE
Configuration Low = Only digital DisplayPort (SDVO/DP/HDMI) or
PCIE is operational (default)
3D3V_S0 1
1D05V_S0 TVB_DAC 1 1
R158 2 75R2J-1-GP R458 56R2J-4-GP R160 TVC_DAC 1 2
75R2J-1-GP
UMA_63.R0034.1DL:DIS
UMA
R524 10KR2J-3-GP 2 CLK_MCH_OE# MCH_TSATN# 2
RN55
A
High = Digital DisplayPort (SDVO/DP/HDMI) and PCIE are operating
simultaneously via the PEG port
UMA_63.R0034.1DL:DIS
PM_EXTTS#0 PM_EXTTS#1
4 3
1 2 SRN10KJ-5-GP
GFXVR_EN
FOR Discrete,change to 0 ohm 63.R0034.1DLR526 100KR2J-1-GP
A
2
1
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga (2 of 6)Size Date:5 4 3 2
Document Number
Rev
EigerTuesday, April 01, 20081
-1Sheet 7 of 50
5
4
3
2
1
U54D 12 M_A_DQ[63..0] M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2
M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10
M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17
M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24
M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31
M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38
M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45
M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52
M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59
M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
4 OF 10
U54E
5 OF 10
D
C
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41
AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38
AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12
BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5
AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7
SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14
SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21
SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28
SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35
SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42
SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49
SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56
SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE#
BD21 BG18 AT25 BB20 BD20 AY20
13 M_B_DQ[63..0] M_A_BS#0 12 M_A_BS#1 12 M_A_BS#2 12 M_A_RAS# 12
M_A_CAS# 12 M_A_W E# 12
M_A_DM[7..0]
M_A_DQS[7..0] M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4
M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3
M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3
M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12
M_A_A13 M_A_A14
SYSTEM
DDR
B
DDR
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7
SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26
BH17 AY25
M_A_A[14..0] 12
SYSTEM
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6
SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4
SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12
BD8 AU9 AM8
M_A_DQS[7..0] 12
B
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6
SA_DM_7
A
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6
M_A_DM7
M_A_DM[7..0] 12
M_A_DQS#[7..0]
M_A_DQS#[7..0] 12
M_A_A[14..0]
M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5
M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13
M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20
M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27
M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34
M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41
M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48
M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55
M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62
M_B_DQ63
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47
AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38
BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7
BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1
AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7
SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14
SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21
SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28
SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35
SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42
SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49
SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56
SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE#
BC16 BB17 BB33 AU17 BG16 BF14
M_B_BS#0 13 M_B_BS#1 13 M_B_BS#2 13 M_B_RAS# 13 M_B_CAS# 13
M_B_W E# 13D
M_B_DM[7..0]
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6
SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4
SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3
SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11
SB_MA_12 SB_MA_13 SB_MA_14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2
AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 AV17 BA25 BC25 AU25
AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
M_B_DQS[7..0] M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5
M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4
M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4
M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13
M_B_A14
M_B_DM[7..0] 13
M_B_DQS[7..0] 13
MEMORY
MEMORY
M_B_DQS#[7..0]
M_B_DQS#[7..0] 13
M_B_A[14..0]
M_B_A[14..0] 13
C
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
B
71.CNTIG.00U
71.CNTIG.00U
A
A
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga (3 of 6)Size Date:5 4 3 2
Document Number Tuesday, April 01, 2008
Rev
Eiger
-1Sheet1
8
of
50
5
4
3
2
1
7 OF 10 1D8V_S3 AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32
AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29
BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29
BA36 BB24 BD16 BB21 AW16 AW13 AT13 VCC_GFXCORE Y26 AE25 AB25 AA25
AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21
AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15
AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 VCC_AXG VCC_AXG
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
U54G
VCC_GFXCORE R161
D
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM/NC
VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
C
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_AXG_NCTF
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21
U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19
AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17
W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16
W16 V16 U16
1
2 Do Not Stuff 1D05V_S0 U54F 6 OF 10
DISAG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33
AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26
AH25 AG25 AF25 AG24 AJ23 AH23 AF23 2 VCC_GMCH_35 T32 VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
1
1
1
1
1 2
C509 SC10U6D3V5MX-3GP
C150 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
C149 SC10U6D3V5MX-3GP
C502 SCD1U10V2KX-4GP
C503 SCD1U10V2KX-4GP
2
2
2
VCC_GFXCORE
2
D
POWER
1
1
1
1
1
1
1
1
1
C157 SC10U6D3V5MX-3GP
C505 SC10U6D3V5MX-3GP
C522 SC10U6D3V5MX-3GP
C151 SC10U6D3V5MX-3GP
C215 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
C200 SC1U10V3ZY-6GP
C213 SCD1U10V2KX-4GP
C203 SCD1U10V2KX-4GP
TC17 2 2 Do Not Stuff
Coupling CAP 370 mils from the Edge
79.22719.20L DY UMA
VCC SM
UMA
UMA
UMA
UMA
UMA
UMA
UMA
1
C510 SC10U6D3V5MX-3GP
1
C501 SCD1U10V2KX-4GP
Place on the Edge
Coupling CAP2
2
VCC CORE
2
2
2
2
2
2
2
POWER
VCC GFX NCTF
1D05V_S0 VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_NCTF VCC_NCTF VCC_NCTF AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32
AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30
Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29
AL28 AK28 AL26 AK26 AK25 AK24 AK23
Coupling CAPG26 1 Do Not Stuff
C
Place CAP where LVDS and DDR2 taps
FOR VCC SM1D8V_S3
C225 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP 2 2
C220 SCD1U10V2KX-4GP 2
C240 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2
C219 SCD1U10V2KX-4GP 2
TC19 2 Do Not Stuff
C226 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP 2
C229 SC10U6D3V5MX-3GP 2
C230 SC10U6D3V5MX-3GP
DY
VCC GFX
Place on the Edge
VCC SM LF
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
VCC_SM_LF
AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21
SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH 1 1 1
1 1 1 C563 C154 C534 C578 C284 C244 1 C243 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP
SCD22U10V2KX-1GP SCD47U16V3ZY-3GP SC1U10V3KX-3GP SC1U10V3KX-3GP
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
B
VCC NCTF
1
1
1
1
1
1
1
1
77.C3371.10L
46 VCC_AXG_SENSE 46 VSS_AXG_SENSE
2
2
2
2
2
2
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
place near Cantiga
A
2
AJ14 AH14
VCC_AXG_SENSE VSS_AXG_SENSE
B
A
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga (4 of 6)Size Date:5 4 3 2
Document Number
Rev
EigerTuesday, April 01, 20081
-1Sheet 9 of 50
5
4
3
2
1
5V_S0
Imax = 300 mAU55
3D3V_S0_DAC 3D3V_S0_DAC R162 2 1 0R3-0-U-GP 1D05V_S0
73mA1C612
3D3V_CRTDAC_S0 C218
U54H
8 OF 10 SC4D7U6D3V3KX-GP C228 SC4D7U6D3V3KX-GP C236
852mASC4D7U6D3V3KX-GP C232 SCD47U6D3V2KX-GP SCD47U6D3V2KX-GP
C164 Do Not Stuff C161
SC2D2U6D3V3MX-1-GP C227
1 2 3 1
VIN GND EN/EN#
VOUT NC#4
1
1
1
1
4BC2 SC1U16V3ZY-GP
UMAC241 SC22U16V0KX-1GP
UMA2
UMA2
G909-330T1U-GP BC1 SC1U16V3ZY-GP
D
UMA1D05V_S0
UMA
2
1 0R3-0-U-GP
3 4
R497
5mA1C613 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
VCCA_DAC_BG VSSA_DAC_BG
CRT
74.00909.03F 74.09198.G7F UMA
1
UMA 3D3V_S0_DAC
2
B27 A26M_VCCA_DAC_BG
VCCA_CRT_DAC VCCA_CRT_DAC
A25 B25
UMA2
DIS2 11D8V_TXLVDS_S3
M_VCCA_DPLLB M_VCCA_HPLL M_VCCA_MPLL
L48 AD1 AE1 J48
VCCA_DPLLB VCCA_HPLL VCCA_MPLL VCCA_LVDS
VTT
UMA
RN16 Do Not Stuff
M_VCCA_DPLLA
F47
VCCA_DPLLA
PLL
RN78
65mA4 3 2 1M_VCCA_DPLLA
5 6 7 8
1
UMA2
UMA2
2
UMA
VSSA_LVDS
83.00054.Z81
R196
M_VCCA_DPLLB
1
65mA1 4 31D05V_S0 RN15 Do Not Stuff R153
1
2Do Not Stuff
VCCA_PEG_BG C283 Do Not Stuff
AD48
VCCA_PEG_BG
2
C285 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
C282 SCD1U10V2KX-4GP
UMA2
UMA2
1Do Not Stuff
2 1
480mA1 1C153 C159 C187 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP Do Not
Stuff
DY
A PEG
1
1D05V_S0
1D05V_RUN_PEGPLL AA48 1D05V_SM
VCCA_PEG_PLL VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
VCCA_SM VCCA_SM VCCA_SM
322mASC1U10V3KX-3GP C199 SC10U6D3V5MX-3GP C572 C572
1
1
1
1D05V_S0
C181
C192
2
1
2
2
2
2
R433 Do Not Stuff
1
1
1
1
120ohm 100MHz2L13 1 2 FCM1608KF-1-GP
68.00217.161
C529
1
L14 1 2 FCM1608KF-1-GP
24mAM_VCCA_HPLL SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP C530
1D05V_S0 R154
24mA2SC10U6D3V5MX-3GP SCD1U10V2KX-4GP C208 C204 C211 Do Not
Stuff 1D05V_SM_CK
1Do Not Stuff
A SM
2
1D05V_SUS_MCH_PLL2
2
2
C
DY
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
1 2
1
DIS
2
SRN0J-11-GP
A LVDS
1D5V_S0
C288 SC1KP50V2KX-1GP
2BAT54-5-GP
10R2J-2-GP
1
C260 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
C259 SCD1U10V2KX-4GP
UMA
13.2mA J47
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VTT VTT VTT VTT VTT VTT VTT VTT VTT
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3
U3 V2 U2 T2 V1 U1
1
1
1 2
2
2
2
2
2
2
2
1
5
SCD01U16V2KX-3GP
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
DY
D
1D05V_S0 D28
1 31D05V_HV_S0 2
3D3V_S0 R529
R528
3D3V_HV_S0
1
1
1
2
1Do Not Stuff C635 SCD1U10V2KX-4GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP SC1U10V3KX-3GP
POWER
C
1D8V_SUS_SM_CK
AXF
M_VCCA_MPLL 3D3V_S0_DAC
1
139.2mAUMA
DY
A CK
120ohm 100MHz
68.00217.161
2
2
C528
DY
C535
L1
1
1
1D05V_S0B
2
2
1
1
L18
50mA1D5V_S0 R180
TV
HV
1 2 FCM1608CF-221T02-GP
2
HDA
220ohm 100MHz2
68.00217.521 68.00084.A81
1
C637 SCD1U10V2KX-4GP
1
PEG
1
1
1
1
2
2
2
1D5VRUN_QDAC
2
1 1Do Not Stuff SCD1U10V2KX-4GP
1D5VRUN_TVDAC C210
L28 AF1
VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS VCCD_LVDS
DMI
157.2mA1 1C163 SCD1U10V2KX-4GP C242 SCD1U10V2KX-4GP
VCCD_QDAC
1D05V_RUN_PEGPLL AA47
VCC_DMI VCC_DMI VCC_DMI VCC_DMI
AH48 AF48 AH47 AG47
2
1D5V_S0
R483
58.7mA
1D05V_SUS_MCH_PLL2
DIS
2
1D5VRUN_TVDAC
M25
VCCD_TVDAC
D TV/CRT
UMA
1
UMA C628SCD1U10V2KX-4GP
1
2
2 0R2J-2-GP
VCC_HDA
A32
VCC_HDA
1D05V_S0
R520 Do Not Stuff
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
V48 U48 V47 U47 U46
1782mASC4D7U6D3V3KX-GP C537
2
50mA
VCC_HV VCC_HV VCC_HV
2
1D05V_RUN_PEGPLL
DIS2 1 R478 Do Not Stuff
B24 A24
VCC_TX_LVDS VCCA_TV_DAC VCCA_TV_DAC
K47 C35 B35 A35
3D3V_HV_S0
1
68.00214.101 68.00206.041 180ohm 100MHz
C609 SCD1U10V2KX-4GP
C607
1
2 HCB1608K-181T20GP
3D3VTVDAC SCD01U16V2KX-3GP
SM CK
AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23
AL23
UMA
UMA
VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK
VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF
VCC_AXF VCC_AXF VCC_AXF
B22 B21 A21
2
2
2
200mASCD1U10V2KX-4GP C194
R151
1D8V_S3
2
1Do Not Stuff
2
2
1 R152
2 1D8V_SUS_SM_CK_RC 1R2F-GP
1
1
1
2
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
BF21 BH20 BG20 BF20
C184 SC10U6D3V5MX-3GP 1D8V_TXLVDS_S3 1D8V_S3
2
1
1
VTTLF
LVDS
2
2
2
L2
1
1
2 HCB1608K-181T20GP
1D5VRUN_QDAC 1D8V_S3 R163 Do Not Stuff C710 SCD01U16V2KX-3GP
VTTLF VTTLF VTTLF
68.00214.101 68.00206.041A
1
CANTIGA-GM-GP-U-NF
C221 SCD1U10V2KX-4GP
R168
71.CNTIG.00U1D8V_SUS_DLVDS
1 2
1 2
1 2
180ohm 100MHz
DY2
2
2
1 10R3-0-U-GP
2
M38 L37
2
A8 L1 AB2
VTTLF1 VTTLF2 VTTLF3 SCD47U6D3V2KX-GP C531 SCD47U6D3V2KX-GP C162
SCD47U6D3V2KX-GP C167
1
UMA
C620 SCD1U10V2KX-4GP
1
C621 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
2
2
SB
2
1
Do Not Stuff Do Not Stuff
SCD1U10V2KX-4GP
119mASC1KP50V2KX-1GP C269 SC1U10V3KX-3GP C286
UMA2 R198 1 0R3-0-U-GPB
79mA
106mA
UMA
UMA
R194 Do Not Stuff
DIS
SC22U6D3V5MX-2GP SCD1U10V2KX-4GP C238 C239
SC22U6D3V5MX-2GP SC10U6D3V5MX-3GP C515 C216
SC10U6D3V5MX-3GP C520
1D05V_S0 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP C527
456mA
60.3mA
A
UMA
UMA
R169 Do Not Stuff
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
DIS
Cantiga (5 of 6)Size Date: Document Number Tuesday, April 01,
2008 Rev
Eiger
-1Sheet1
10
of
50
5
4
3
2
5
4
3
2
1
U54J U54I 9 OF 10
10 OF 10
D
C
B
A
AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47
L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44
AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42
AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41
T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39
L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38
BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34
AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33
P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28
BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28
C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25
AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24
AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20
BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17
AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15
W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13
BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11
G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9
BH8 BB8 AV8 AT8
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6
AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2
AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24
U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19
AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45
C46 D47 B47 A46 F48 E48 C48 B48Title TP149 TP121 TP150 TP122 TP123
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not
Stuff
D
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
C
B
NCTF TEST PIN: A3,C1,A48,BH1,BH48
VSS SCB
NCTF_VSS_SCB#BH48 NCTF_VSS_SCB#BH1 NCTF_VSS_SCB#A48
NCTF_VSS_SCB#C1 NCTF_VSS_SCB#A3 NC#E1 NC#D2 NC#C3 NC#B4 NC#A5 NC#A6
NC#A43 NC#A44 NC#B45 NC#C46 NC#D47 NC#B47 NC#A46 NC#F48 NC#E48
NC#C48 NC#B48
NC
VSS NCTF
A
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
71.CNTIG.00U
Cantiga (6 of 6)Size Date: Document Number Tuesday, April 01,
2008 Rev
Eiger
-1Sheet1
11
of
50
5
4
3
2
A
B
C
D
E
DDR_VREF_S34
PARALLEL TERMINATIONRN32 8 7 6 5 1 2 3 4 SRN56J-5-GP RN22 8 7 6
5 1 2 3 4 SRN56J-5-GP RN26 8 7 6 5 1 2 3 4 SRN56J-5-GP RN19 8 7 6 5
1 2 3 4 SRN56J-5-GP RN28 8 7 6 5 1 2 3 4 SRN56J-5-GP M_A_A9 M_A_A14
M_A_A5 M_A_A3 M_A_CAS# M_ODT1 M_CS1# M_A_BS#1 M_A_A0 M_A_A2 M_A_A4
M_A_A13 M_ODT0 M_CS0# M_A_RAS# M_A_A12 M_CKE0 M_A_BS#2 M_A_A8
8
M_A_A[14..0]
DM2 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7
M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 102
101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 M_A_DQ0
M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8
M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15
M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22
M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29
M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36
M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43
M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50
M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57
M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#0
M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6
M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5
M_A_DQS6 M_A_DQS7 7 7 M_ODT0 M_ODT1 5 7 17 19 4 6 14 16 23 25 35 37
20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125
135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173
175 158 160 174 176 179 181 189 191 180 182 192 194 11 29 49 68 129
146 167 186 13 31 51 70 131 148 169 188 114 119 1 2 C290 202
SCD1U16V2ZY-2GP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13
A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22
DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35
DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48
DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61
DQ62 DQ63 /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 DQS0 DQS1
DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF VSS GND
SKT-SODIMM20022U2GP /RAS /WE /CAS /CS0 /CS1 CKE0 CKE1 CK0 /CK0 CK1
/CK1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL VDDSPD SA0 SA1 NC#50
NC#69 NC#83 NC#120 NC#163/TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS GND 108 109 113 110 115 79 80 30 32
164 166 10 26 52 67 130 147 170 185 195 197 199 198 200 50 69 83
120 163 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21
24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121
122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168
171 172 177 178 183 184 187 190 193 196 201 1 C145 Do Not Stuff
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_RAS# 8 M_A_WE# 8 M_A_CAS# 8 M_CS0# 7 M_CS1# 7 M_CKE0 7 M_CKE1 7
M_CLK_DDR0 7 M_CLK_DDR#0 7 M_CLK_DDR1 7 M_CLK_DDR#1 7
M_A_DM[7..0]
Put decap near power(0.9V) and pull-up resistor
4
Do Not Stuff TP72 8 8 8 M_A_BS#2 M_A_BS#0 M_A_BS#1
8
8 M_A_DQ[63..0]
SMBD_ICH SMBC_ICH
3,13,22 3,13,22
3D3V_S0
3
RN30 8 7 6 5 1 2 3 4 SRN56J-5-GP RN23 8 7 6 5 1 2 3 4
SRN56J-5-GP M_A_BS#0 M_A_A1 M_A_A10 M_A_WE# M_A_A6 M_A_A7 M_A_A11
M_CKE1
REVERSE TYPE
2
DY
3
1D8V_S3
Decoupling CapacitorDDR_VREF_S3
1D8V_S3
Place these Caps near DM11 1 1 C231 C196 C186 C177 1
SC2D2U6D3V3MX-1-GP 2 C224
1
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
Put decap near power(0.9V) and pull-up resistor1 1 1 1 1 1 1 1 1
C198 C172 C209 C237 C234 C179 C178 C217 C182 1 C171 SCD1U16V2ZY-2GP
Do Not Stuff Do Not Stuff SCD1U16V2ZY-2GP Do Not Stuff Do Not Stuff
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
2
1
C189
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DY
DY
DY
DY
8 M_A_DQS[7..0]
DDR_VREF_S3_1
1
C289
DY
2
Do Not Stuff
2
1
62.10017.691 62.10017.911
High 5.2mm
1
2
SCD1U16V2ZY-2GP
2
DY
DY
DY
1
1
1
8 M_A_DQS#[7..0]
C214
C205
C173
1 Do Not Stuff
C175
Do Not Stuff
Do Not Stuff
Do Not Stuff1
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:A B C D
Document Number Tuesday, April 01, 2008
DDR2 Socket 0 (DM1) EigerE
Rev
-1Sheet 12 of 50
A
B
C
D
E
DM1 8 DDR_VREF_S34
M_B_A[14..0]
PARALLEL TERMINATIONRN27 8 7 6 5 1 2 3 4 M_B_A8 M_B_A9
M_B_A5
Put decap near power(0.9V) and pull-up resistor
8 7 6 5
SRN56J-5-GP RN31 1 M_CKE3 2 M_B_A12 3 M_B_BS#2 4 M_CKE2
SRN56J-5-GP RN24 1 M_B_A3 2 M_B_A1 3 M_B_A10 4 M_B_WE# SRN56J-5-GP
RN21 1 2 3 4 SRN56J-5-GP RN25 M_B_BS#1 M_B_A2 M_B_A0 M_B_A4
Do Not Stuff TP70
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8
M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
8 8 8
M_B_BS#2 M_B_BS#0 M_B_BS#1 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3
M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11
M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18
M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25
M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32
M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39
M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46
M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53
M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60
M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3
M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2
M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 7 7 M_ODT2 M_ODT3
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58
61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151
153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191
180 182 192 194 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169
188 114 119 1 2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13
DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26
DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52
DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1#
DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5
DQS6 DQS7 OTD0 OTD1 VREF VSS GND MH1 DDR2-200P-23-GP-U1
RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2
DM3 DM4 DM5 DM6 DM7 SDA SCL VDDSPD SA0 SA1 NC#50 NC#69 NC#83 NC#120
NC#163/TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS GND MH2
108 109 113 110 115 79 80 30 32 164 166 10 26 52 67 130 147 170
185 195 197 199 198 200 50 69 83 120 163 81 82 87 88 95 96 103 104
111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48
53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144
145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190
193 196 201 MH2 DDRB_SA0 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4
M_B_DM5 M_B_DM6 M_B_DM7
M_B_RAS# 8 M_B_WE# 8 M_B_CAS# 8 M_CS2# 7 M_CS3# 7 M_CKE2 7
M_CKE3 7 M_CLK_DDR2 7 M_CLK_DDR#2 7 M_CLK_DDR3 7 M_CLK_DDR#3 7
M_B_DM[7..0]4
8
8 7 6 5
8 M_B_DQ[63..0]
8 7 6 5
M_B_A13 M_ODT2 M_ODT3 M_B_RAS#
SMBD_ICH SMBC_ICH
3,12,22 3,12,22
3D3V_S0
2
2 R97 10KR2J-3-GP
1 Do Not Stuff C146
REVERSE TYPE
8 7 6 5
1 2 3 4 SRN56J-5-GP RN29
DY
3
8 7 6 5
1 2 3 4 SRN56J-5-GP RN20
M_B_A14 M_B_A11 M_B_A7 M_B_A6
1
3
1D8V_S3
8 7 6 5
1 2 3 4 SRN56J-5-GP
M_B_BS#0 M_B_CAS# M_CS3# M_CS2#
1D8V_S3
Place these Caps near DM21 1 1 1 C170 SC2D2U6D3V3MX-1-GP C174
SC2D2U6D3V3MX-1-GP C233 SC2D2U6D3V3MX-1-GP C222 SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP 1 2 C197 SC2D2U6D3V3MX-1-GP
Decoupling CapacitorDDR_VREF_S32
Put decap near power(0.9V) and pull-up resistorC188 C207 C201
C195 C193 C235 C223 C176 C190 C206 8 M_B_DQS#[7..0] SCD1U16V2ZY-2GP
1 1 1 1 1 1 1 1 1 1
2
2
2
2
2
1
C185
SCD1U16V2ZY-2GP
Do Not Stuff
Do Not Stuff
Do Not Stuff Do Not Stuff
SCD1U16V2ZY-2GP
Do Not Stuff
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
2
2
2
1
1
1
DY
DY
DY
DY
C212 Do Not Stuff
C183 Do Not Stuff
C202 Do Not Stuff
1
C191 Do Not Stuff Do Not Stuff
2
2
2
8 M_B_DQS[7..0]
DY
DY
DY
DY
DDR_VREF_S3_1
1
C291 Do Not Stuff
1
DY
C292 SCD1U16V2ZY-2GP 202 MH1
2
2
62.10017.A71 62.10017.B51
High 9.2mm
1
2
1
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
DDR2 Socket 1 (DM2)Size Date:A B C D
Document Number
Rev
EigerTuesday, April 01, 2008E
-1Sheet 13 of 50
5
4
3
2
1
5V_S0 Do Not Stuff Do Not Stuff Do Not Stuff C436 C436
EC60
5V_S0
1
1
TP233 Do Not Stuff TP234 Do Not Stuff
DY2 2
-1MLAUNCH1 15
DYRP1
D
3D3V_S0
8 7 6 5
1 2 3 4
INTERNET# W IRELESS_BTN# BT_BTN# MAIL# EC64 Do Not Stuff
3D3V_S0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 16ACES-CON14-1-GP
3D3V_S5
SRN10KJ-6-GP
36 LID_CLOSE#
DY
1
LID_CLOSE# BT_LED# W LAN_LED# INTERNET# W IRELESS_BTN# BT_BTN#
MAIL#
SB
LID_CLOSE# BT_LED# W LAN_LED# INTERNET# W IRELESS_BTN# BT_BTN#
MAIL#
TP188 TP189 TP186 TP187 TP192 TP190 TP191
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
Do Not Stuff Do Not Stuff
D
2
36 36 36 36
INTERNET# W IRELESS_BTN# BT_BTN# MAIL#
20.K0276.014 20.K0227.014BT_LED# EC63
DY1 2 Do Not Stuff32 W LAN_LED#_MC R365
W LAN_LED# EC65
DY1 2 Do Not Stuff
1 2 33R2J-2-GP
W LAN_LED#
C
D
C
INTERNET# EC16
DY1 2 Do Not Stuff
36 W LAN_TEST_LED
G S
Q24 2N7002E-1-GP
84.2N702.E31
W IRELESS_BTN# EC17
DY1 2 Do Not StuffBT_LED# EC18
CQ23 DDTC143ZUA-7-F-GP R1
MAIL# EC19
DY1 2 Do Not Stuff
E36 BT_LED
BT_BTN#
DY1 2 Do Not Stuff
B
B
R2
B
A
UMA
A
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
LAUNCHSize Date:5 4 3 2
Document Number Tuesday, April 01, 2008
Rev
Eiger
-1Sheet1
14
of
50
LCD/INVERTER/CCD CONNSC10U10V5ZY-1GP LCDVDD
Inverter Pin Pin Symbol Vin Vin Brightness BLON GND GND1
RN45 LVDS_TXBOUT0LVDS_TXBOUT0+ LVDS_TXBOUT1LVDS_TXBOUT1+
1
20 20
USBPN8 USBPP8 3D3V_S0
41 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42
C6
1
LCD2
C11
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
DY2 2
SBBLON_OUT
5V_S0
LCD_EDID_CLK LCD_EDID_DAT CCD_PW R BRIGHTNESS_CN BLON_OUT1
1R28
233R2J-2-GP F2
-1DCBATOUT
1 1 1
2
PW R_INVERTER
DMIC_DAT_RC DMIC_CLK_RC LVDS_TXBCLK+ LVDS_TXBCLKLVDS_TXBOUT2+
LVDS_TXBOUT2LVDS_TXBOUT1+ LVDS_TXBOUT1LVDS_TXBOUT0+
LVDS_TXBOUT0LVDS_TXACLK+ LVDS_TXACLKLVDS_TXAOUT2+
LVDS_TXAOUT2LVDS_TXAOUT1+ LVDS_TXAOUT1LVDS_TXAOUT0+
LVDS_TXAOUT0-
2
C8 DY Do Not Stuff Do Not Stuff
1 2 3 4 5 6
1 2 3 4
UMA
8 7 6 5
GMCH_TXBOUT0GMCH_TXBOUT0+ GMCH_TXBOUT1GMCH_TXBOUT1+
7 7 7 7
SRN0J-7-GP RN42 LVDS_TXBOUT2LVDS_TXBOUT2+
LVDS_TXBCLKLVDS_TXBCLK+
SB
1 2 3 4
UMA
8 7 6 5
GMCH_TXBOUT2- 7 GMCH_TXBOUT2+ 7 GMCH_TXBCLK- 7 GMCH_TXBCLK+
7
SRN0J-7-GP RN48 LVDS_TXAOUT0LVDS_TXAOUT0+
LVDS_TXAOUT1LVDS_TXAOUT1+
CCD Pin Pin 1 2 3 4 5 Symbol CCD_PWR USBUSB+ GND GND
1 2 3 4
UMA
8 7 6 5
GMCH_TXAOUT0GMCH_TXAOUT0+ GMCH_TXAOUT1GMCH_TXAOUT1+
7 7 7 7
SRN0J-7-GP RN46 LVDS_TXAOUT2LVDS_TXAOUT2+
LVDS_TXACLKLVDS_TXACLK+
POLYSW -1D1A24V-GP EC7 ACES-CONN40A-2GP Do Not Stuff Do Not
Stuff
C14
1 2 3 4
UMA
8 7 6 5
GMCH_TXAOUT2- 7 GMCH_TXAOUT2+ 7 GMCH_TXACLK- 7 GMCH_TXACLK+
7
1
SRN22-3-GP
2
2
1
SC10U25V6KX-1GP
DY
20.F0993.040 20.F1048.040
2
2
SRN0J-7-GP RN41
-1EMI
33 33
DMIC_DAT DMIC_CLK
DMIC_DAT DMIC_CLK
RN67
1 2
4 3
DMIC_DAT_RC DMIC_CLK_RC C713 SC22P50V2JN-4GP C712
SC22P50V2JN-4GP
LVDS_TXBCLK+ LVDS_TXBCLKLVDS_TXBOUT2+ LVDS_TXBOUT2-
1 2 3 4
DIS
8 7 6 5
G72_TXBCLK+ G72_TXBCLKG72_TXBOUT2+ G72_TXBOUT2-
30 30 30 30
Do Not Stuff RN44 LVDS_TXBOUT1+ LVDS_TXBOUT1LVDS_TXBOUT0+
LVDS_TXBOUT0-
USBPP8
USBPN8
EMI2
1
1
2
2
C461 Do Not Stuff
C462 Do Not Stuff
DY
R7 1 Do Not Stuff R10 1 0R2J-2-GP
1 2 3 4
DIS
8 7 6 5
G72_TXBOUT1+ G72_TXBOUT1G72_TXBOUT0+ G72_TXBOUT0-
30 30 30 30
L_BKLTCTL 7 LVDS_TXACLK+ LVDS_TXACLKLVDS_TXAOUT2+
LVDS_TXAOUT2-
Do Not Stuff RN47
DY
DYBRIGHTNESS_CN
2Do Not Stuff 2 1 Do Not Stuff 2 1
-1M
BRIGHTNESS 36 BLON_OUT 36
BLON_OUT
1 2 3 4
DIS
8 7 6 5
G72_TXACLK+ G72_TXACLKG72_TXAOUT2+ G72_TXAOUT2-
30 30 30 30
C10
C13
1
Do Not Stuff R9 10KR2J-3-GP 10KR2J-3-GP RN49 LVDS_TXAOUT1+
LVDS_TXAOUT1LVDS_TXAOUT0+ LVDS_TXAOUT03D3V_S0
DY
DY
1 2 3 4
DIS
8 7 6 5
G72_TXAOUT1+ G72_TXAOUT1G72_TXAOUT0+ G72_TXAOUT0-
30 30 30 30
2
Do Not Stuff
UMA7 GMCH_LCDVDD_ON R3
LCDVDD
1
2
U1 0R2J-2-GP
DIS30 LCDVDD_ON R2
Layout 40 mil2LCDVDD_ON_1 Do Not Stuff
1
1 2 3 4
IN#1 OUT EN GND
1
R4 10KR2J-3-GP
2
2
G5281RC1U-GP
C12 SC1U10V3ZY-6GP
74.05281.093
2
1 2SRN2K2J-1-GP RN1
C5
C7
GND IN#8 IN#7 IN#6 IN#5
2
1
1
1
9 8 7 6 5
3D3V_S0
SC1U10V3ZY-6GP SC1U10V3ZY-6GP
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
4 3
30 LCD_EDID_CLK 30 LCD_EDID_DAT
LCD_EDID_CLK LCD_EDID_DAT
F1 CCD_PW R
1C3 Do Not Stuff
2FUSE-1A6V-2-GP
3D3V_S0 7 CLK_DDC_EDID 7 DAT_DDC_EDID
1
C4
1
2 1
3 4
RN13 SRN0J-6-GP
SC4D7U10V5ZY-3GP
69.50007.721 69.50007.981
2
2
UMA
UMA
DY
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
LCD CONNSize Date: Document Number Tuesday, April 01, 2008
Rev
Eiger
-1Sheet 15 of 50
5
4
3
2
1
Q33 DDTC143ZUA-7-F-GP
84.00143.D1K
CR1 R1
ER2
5V_S0
B
D
36 FRONT_PW RLED PW RLED#_DB
R598
LED1
3D3V_S5
D
1R597
FRONT_PW RLED#_R 2 330R2J-3-GP STDBY_LED#_R 2 270R2F-GP
3
2
3D3V_S0
TP235 Do Not Stuff TP236 Do Not Stuff
-1M4LED-OB-2-GP
STDBY_LED#_BD
1
1
SC
Q32 DDTC143ZUA-7-F-GP
C
E
83.19223.A703D3V_S0 Media_CLK_C Media_DATA_C MEDIA_INT#
SBTP179 Do Not Stuff TP180 Do Not Stuff TP181 Do Not Stuff
R2
84.00143.D1K
B
R1 MEDIA1
DY1C576
936 STDBY_LED DC_BATFULL#
1 2 3 4 5 6 7 8 10LED2 R595 3D3V_S5 PTW O-CON8-GP
2Do Not Stuff Media_CLK_C Media_DATA_C RN84
1 2
4 3SRN22-3-GP
SMBC_Therm 18,23,30,36 SMBD_Therm 18,23,30,36 MEDIA_INT# 36C
C
Q30 DDTC143ZUA-7-F-GP
C
E
84.00143.D1K
SCBR1
3D3V_S5
1
36 DC_BATFULL
R596 CHARGE_LED#
2
1
C
E
LED-YG-50-GP
Q31 DDTC143ZUA-7-F-GP
83.19223.B702
Do Not Stuff 3D3V_AUX_S5 DY R124
DY
2
CHARGE_LED#_R 2 270R2F-GP
4
1
2
1
EC73
Do Not Stuff
R118
Do Not Stuff
1
R2
EC74
1
DC_BATFULL#_R 2 270R2F-GP
3
2
20.K0286.008 20.K0238.008
DY
R2
84.00143.D1K
10R2J-2-GP
B
R1
MEDIA BOARD3D3V_AUX_S5
36 CHARGE_LED
5V_S5
C491 Do Not Stuff
1 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16ACES-CON14-1-GP
2
PW RCN1B
DY15V_S0B
2
KBC_PW RBTN#_CN NUM_LED# 36 CAP_LED# 36 MEDIA_LED# 19
DY1
2
C486 Do Not Stuff
1
R255 10KR2J-3-GP R253 KBC_PW RBTN#_CN G70 Do Not Stuff
1
2Do Not Stuff
KBC_PW RBTN# 36
PW RLED#_DB STDBY_LED#_BD L-line_LED#
1L-line_LED#
2
20.K0276.014 20.K0227.014
Do Not Stuff Q12 DDTC143ZUA-7-F-GP
A
KBC_PW RBTN#_CN NUM_LED# CAP_LED# MEDIA_LED# PW RLED#_DB
STDBY_LED#_BD L-line_LED#
TP193 TP194 TP195 TP196 TP198 TP197 TP199
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
Do Not Stuff Do Not Stuff
L-line_LED# KBC_PW RBTN#_CN NUM_LED# CAP_LED#
B
EC66 EC72 EC71 EC70
1 1 1 1
2 Do Not Stuff 2 Do Not Stuff DY 2 Not Stuff Do DY 2 Not Stuff
Do
84.00143.D1K
C
SB
E
MEDIA_LED# PW RLED#_DB STDBY_LED#_BD
EC69 EC68 EC67
1 1 1
DY 2 Do DY 2 Not Stuff Do DY 2 Not Stuff
2R2 R1
C347 SCD1U16V2ZY-2GP
UMA
A
DY DY
36
L-line_LED
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title
5V_S5
TP237 Do Not Stuff TP239 Do Not Stuff TP238 Do Not Stuff Size
Date:
-1M5
5V_S0
Power & Media BoardDocument Number Tuesday, April 01, 2008
Rev
Eiger
-1Sheet1
16
of
50
4
3
2
A
B
C
D
E
Hsync & Vsync level shiftLayout Note: Place these resistors
close to the CRT-out connector 38 CRT_R_SYS 5V_S0
Ferrite bead impedance: 10 [email protected] 2 FCB1608CF-GP
CRT_R
1
SB1438 DOCK_IN_CRT#
68.00230.021 68.00119.0814
2
C412 SCD1U16V2ZY-2GP
38 CRT_G_SYS
1
L10 2 FCB1608CF-GP
CRT_G RN77 30 CRT_HSYNC 30 CRT_VSYNC CRT_B
68.00230.021 68.00119.08138 CRT_B_SYS
2 1
DIS
3 4
HSYNC_4
1
4
2 14
3U46A TSAHCT125PW -GP
CRT_HSYNC1
4
7
1 4 3 2 1 1 1 1Do Not Stuff Do Not Stuff C484 C475 C456 Do Not
Stuff RN85 SRN150J-1-GP
1
1
SC15P50V2JN-2-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
68.00230.021 68.00119.081
C485
C476
1
L9 2 FCB1608CF-GP
C457
7 GMCH_HSYNC 7 GMCH_VSYNC
Do Not Stuff RN61 2 3 UMA 4 1
73.74125.L126CRT_VSYNC1
VSYNC_4
5
1
1
SRN0J-6-GP
DYC432 Do Not Stuff
DY7C423 Do Not Stuff
2
2
2
2
2
2
DY5 6 7 8
DY
DY
U46B TSAHCT125PW -GP
-1
73.74125.L12
2
5V_S0 D21
SB5V_S0 Do Not Stuff
2
3
CRT_G 3
D
Layout Note: * Must be a ground return path between this ground
and the ground on the VGA connector. Pi-filter & 150 Ohm
pull-down resistors should be as close as to CRT CONN. RGB will hit
75 Ohm first, pi-filter, then CRT CONN.
CRT_R 3
DY1
Do Not Stuff 83.00099.K11
2
R356 100KR2J-1-GP
2
For Dock CRT
5V_S03
1
14Do Not Stuff
2
DY1D17
Do Not Stuff 83.00099.K11DOCK_IN_CRT#
HSYNC_4 Q20 2N7002E-1-GP
9 14 13
10
D19
DOCK_IN_CRT_2#
8U46C TSAHCT125PW -GP
HSYNC_5
38
84.2N702.E31S 2VSYNC_4 Do Not Stuff
7
G
73.74125.L1211VSYNC_5 38
12
CRT_B 3
DY1
Do Not Stuff 83.00099.K11
7
U46D TSAHCT125PW -GP
73.74125.L12
CRT I/F & CONNECTOR2
DDC_CLK & DATA level shift5V_S0 3D3V_S02
3D3V_S0 5V_CRT_S0
5V_CRT_S0
1
D14 CH551H-30PT-GP
83.R5003.H8HCRT1 F3
RN43 SRN2K2J-1-GP
FUSE-1D1A6V-4GP-U
8 7 6 5RN40 SRN2KJ-2-GP
9C451 SCD01U16V2KX-3GP CRT_R CRT_G CRT_B
VCC_CRT CRT_R CRT_G CRT_B JVGA_VS JVGA_HS DDCCLK_ID3
DDCDATA_ID1VIDEO-15-78-GP-U1
NP1 NP2 NC#11 NC#4 GND GND GND GND GND GND GND
NP1 NP2 11 4
3 4
1
2
5V_CRT_DDC
2 1
1 2 3 14 13
69.50007.691 69.50007.9411 2 3 4U45
2
SBCRT_IN#_R DAT_DDC1_5 38
1
CRT_VSYNC1 CRT_HSYNC1 CLK_DDC1_5 DAT_DDC1_5 C419
SC100P50V2JN-3GP
C445 SC18P50V2JN-1-GP
1
C444 SC18P50V2JN-1-GP
1
C471
15 12
5 6 7 8 10 16 17
7 GMCH_DDCDATA 7 GMCH_DDCCLK
2 1
UMARN71
3 4
RN9 SRN0J-6-GP
4 5 6
3 2 12N7002KDW -GP
2
1
30 CRT_DDCDATA 30 CRT_DDCCLK
2
2 1
DIS
3 4
DAT_DDC1_5_Q CLK_DDC1_5_Q
84.00512.03F
SDCLK_DDC1_5 38
2
SC100P50V2JN-3GP
20.20717.015 20.20722.015
1
SC EMI2
R354
1 1
CRT_IN#_R C439 Do Not Stuff
D15
5V_S0
2 1470R2J-2-GP C166 Do Not Stuff
36,38
CRT_DEC#
3 1Do Not Stuff
DY 83.00099.K11
DY
DY
6 1 7 2 8 3 9 4 10 5C
2
Do Not Stuff
UMA
1
Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C. Title Size Date: Document
Number
2
2
CRT Connector EigerSheetE
Rev
-117 of 50
Tuesday, April 01, 2008
A
B
D
5
4
3
2
1
5V_S0 5V_S0
2
Type AEC20 2 C524 2 Do 1 Not Stuff HDMI1
2
3D3V_SO_PS8122_3 3D3V_SO_PS8122_2 3D3V_SO_PS8122_1 RN60
SRN1K5J-GP
EC22
1
DY DY
1
Do Not Stuff
EC21 Do Not Stuff
DY1 2
4 3
2
1
2
2
1
2
1
1
+5V_POWER TMDS_DATA0+ TMDS_DATA0TMDS_DATA1+
TMDS_DATA1TMDS_DATA2+ TMDS_DATA2-
SCL SDA CEC DDC/CEC_GROUNG HOT_PLUG_DETECT RESERVED#14
D
TMDS_TX0+_MB TMDS_TX0-_MB TMDS_TX1+_MB TMDS_TX1-_MB TMDS_TX2+_MB
TMDS_TX2-_MB
7 9 4 6 1 3 8 5 2
SC13 17 19 14HDMI_CEC HDMI_HPD_MB 5V_S0 TP125 Do Not Stuff
1
SC1U16V3ZY-GP 1
18
15 16
TMDS_SCL TMDS_SDA
C549 SCD1U16V2ZY-2GP
C169 C559 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C400 SCD01U50V2KX-1GP
2C408 SCD01U50V2KX-1GP
D
SC1
TMDS_D
