Acer Aspire 6530 ZK3

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ZK3 BLOCK DIAGRAMDDRII-SODIMM1PG 7,8D

CPU_CORE1 CPU_CORE2 CPU VDDNB_CORE HOST 200MHz +NB_CORE +1.35V_VDDHTTX +2.5V +1.5V +1.2V +1.1V_NB

CPU COREPG 35

PCB STACK UPLAYER 1 : TOP LAYER 2 : GND LAYER 3 : IN1 LAYER 4 : IN2 LAYER 5 : VCC LAYER 6 : BOT

01D

AMD S1g2DDR II 667 MHZ

CPU_CLK NBGFX_CLK NBGPP_CLK SBLINK_CLK

NB CORE (1.0~1.2V)PG 36

CLOCK GENERATORICS9LPRS476AKLFT SLG8SP628VTR RTM880N-795

PCIE 100MHz USB 48MHz REF 14MHz

Griffin Processor

+2.5V +1.5V +1.2VPG 38

DDRII-SODIMM2PG 7,8 (638 S1g2 socket) PG 4,5,6

PG 3

Daughter BoardMMB Board

HDMIPG 20

HT_LINK PCI-E, 1X (port2)

AR8121(Giga)

RJ45

+1.2V_S5 +1.8VSUS +1.8V+SMDDR_VTERM

LVDSPG 19

HDMI LVDS(2ch)

PG 21

PG 22

RX780/RS780M/RS780MC21mm X 21mm, 528pin BGA

PCI-E, 1X (port0) USB2.0 (P3) PCI-E, 1X (port1)

Mini Card (WLAN) PG 23

+1.8VSUS SMDDR VTERM 3V/5V

USB BoardPG 37

CRT LVDS HDMIC

MXM Module

PG 18

SATA - HDD1

SATA - HDD2

www.kythuatvitinh.comCRTPG 19 MINI CARD (TV) NEW CARD PG 23

PCI-E X16

PG 9,10,11,12

PCI-E, 1X (port3) USB2.0 (P6)SBSRC_CLK

A_LINK (X4)

PG 27

+3VPCU +3V_S5 +3VSUS +3V +5VPCU +5V

Touch Pad board

Touch Pad board (with Fingerprinter)

C

PG 34

USB2.0 (P2/3) USB2.0 (P0) USB2.0 (P1)

USB2.0 MINI CARD Ports X2PG 23 PG 30 PG 30 PG 30 PG 30

SATA0

(MB)

PG 24

USB2.0 (P11) USB2.0 (P9) USB2.0 (P8)

CCD

USB2.0 I/O Ports X1(MB) (DB)

SATA1

SB700

PG 19

FingerprintPG 31

USB2.0 I/O Ports X1 USB2.0 I/O Ports X1(DB)

PG 24

Card ReaderPG 28

USB2.0 (P7) USB2.0 (P4) PG 22

SATA - ODDPG 24B

SATA4 USB2.0 (P5) SATA2 USB2.0 (P10) Azalia

Bluetooth DOCKINGPG 31

USB2.0 I/O Ports X2(DB)B

E - SATAPG 30

21mm X 21mm, 528pin BGA

4.5W(Ext) 4.3W(Int)

Azalia Audio CodecALC888PORT-A PORT-B PG 25

MDC CONN PCI ROUTING TABLEDevice IDSEL#OZ129 AD17

PG 13,14,15,16,17InterruptINTE#

MDC Board

RJ11

REQ#/GNT#REQ0# / GNT0#

PG 25 LPC

Speaker Amplifier G1441R51U

PG 26

ECA

5

Digitally signed by dd DN: cn=dd, o=dd, ou=dd, [email protected] com, c=US Date: 2009.11.29 07:52:53 +07'00'

WPCE775 PG 32 SPI VR PG 23 FAN PG 314

H.P/ SPDIF PG 26

MIC JACK PG 26

INT. MIC PG 26

INT. S.P. PG 26A

KeyboardPG 31

Flash ROM PG 32

Touch Pad PG 31

Quanta Computer Inc.CIRPG 323

Kill SWPG 322

PROJECT : ZK3Size Document Number

BLOCK DIAGRAMDate: Monday, August 18, 20081

Rev 1A of 43

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02BD3G Power On SequenceFrom AC,Battery VIN +5VPCU +3VPCU From PWM SYS_HWPG(PCU) From Power Button NBSWON# From EC S5_ON +5V_S5 +3V_S5 +1.2V_S5 >10ms RSMRST# From EC >100ms From EC DNBSWON# From SB PCIE_WAKE# From SB to EC SUSB#,SUSC# SUSON From EC SUSON +3VSUS +1.8VSUS SMDDR_VREF SMDDR_VTERM From PWM HWPG_1.8V (SUS) MAINON From EC MAINON +5V +3V +2.5V +1.8V +1.5V +NB_CORE +1.1V_NB +1.35V_VDDHTTX From PWM HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN) HWPG_1.2_NB From EC VRON CPU_CORE0, CPU_CORE1, CPU VDDNB_CORE, +1.2V From PWM VRM_PWRGD (CPU) HWPG ECPWROK SB_PWRGD NB_PWRGD CPU_PWRGD PLTRST# PCIRST# CPU_LDT_RST# CPU_LDT_STOP#Items 1 2 3 4 5 6 7 8 9 FunctionCIR HDMI port HDMI transmitter HDMI-CEC Discrete VGA UMA New Card RJ11 v

BOM naming ruleBTOv v v v

[email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected]

DescriptionD

D

Silicon image SiI 1392/1932 Renesas R8C/1B External VGA stuff Internal VGA stuff

C

www.kythuatvitinh.comModem RJ45-10/100 RJ45-1000 Marvell 8040T(10/100) Marvell 8055(Giga)

10 11 12 13 14 15 16 17

Option for RJ45-10/100 and RJ45-1000 TV

[email protected]@ [email protected] [email protected] [email protected]

Option for 8040/8055

C

v

Cardbus

FM transmitter

v

Mainstream ID LED Low cost ID LED CCD INT MIC AMD Hyper Flash North bridge(690MC/RS780MC) North bridge(RX780) PowerXpress PowerXpress with UMA SKU PowerXpress with Discrete VGA SKU Power player/Power Shift v v

[email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected]@ [email protected]@ [email protected] Only for AMD platform Only for AMD platform Only for AMD platformB

From EC

0ns~30ns 99ms~108ms

18 19 20 21 22 23 24 25

From From From FromB

SB SB SB SB

Only for AMD platform Only for AMD platform Only for AMD platform Only for AMD platform

*Note: EC will sampling SUSB# & SUSC# every 5ms.

EC SMBUS TableBattery EC775 SDATA1/SCLK1(+3VPCU) Mini-card(WL) New Card HDMI EC775 SDATA2/SCLK2(+3VPCU) EC775 SDATA3/SCLK3(+3VPCU) CPU thermal Sensor EC EEPROM VGA thermal Sensor Touch Sensor HDMI CEC

AMD SB700 SMBUS TableCLK GEN SB700 SDATA0/SCLK0(+3V)A

V V V V+3VPCU +3V +3VPCU +3V

RAM

Mini Card (HD-Decoder)

V

V

V

V

V V

V+3VPCU

VA

SB700 SDATA1/SCLK1(+3V_S5) SB700 SDATA2/SCLK2(+3V_S5) Power Reserve MOS ckt +3V +3V +3V +3V (Atheros) +3V

EC775 SDATA4/SCLK4(+3VPCU) Power +5VPCU

+3V_S5

Reserve MOS ckt

X

V

X

V

X

V

V

V

V

V

V

V Quanta Computer Inc.PROJECT : ZK3Size Document Number

SYSTEM INFORMATIONDate:5 4 3 2

Rev 1A 43

Monday, August 18, 20081

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CLK_GEN_SLG8SP628+3V L46 BK1608HS600 C595D

03+1.2V L47 BK1608HS600 C593 0.1U/10V_4 C620 0.1U/10V_4 C589 0.1U/10V_4 C599 0.1U/10V_4 C616 0.1U/10V_4 C598 0.1U/10V_4 C591 0.1U/10V_4 C587 22U/6.3V_8 C604 0.1U/10V_4 C592 0.1U/10V_4 C617 0.1U/10V_4 C594 0.1U/10V_4 C625 0.1U/10V_4 C590 0.1U/10V_4D

+3V_CLK_VDD

+1.2V_CLK_VDDIO

C588 22U/6.3V_8

0.1U/10V_4

ICS9LPRS480 SLG8SP628 RTM880N-796U29

P/N : P/N : AL8SP628000 P/N : AL000880000

Clock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose.

Place within 0.5" of CLKGEN4 16 26 35 40 48 55 56 63 11 17 25 34 47 1 7 10 18 24 33 43 46 52 60 61 62 2 3CLK_PD#

R528 *261/F_4 CPUCLKP CPUCLKN

C

2

R522 *10K_4 CLKREQ3#

www.kythuatvitinh.com+3V +3V_CLK_48 +3V_CLK_VDD L51

1

BK1608HS600

2

C615 2.2U/6.3V_6

VDDDOT VDDSRC VDDATIG VDDSB_SRC VDDSATA VDDCPU VDDHTT VDDREF VDD48

CPUK8_0T CPUK8_0C ATIG0T ATIG0C ATIG1T ATIG1C

50 49 30 29 28 27 37 36 32 31 22 21 20 19 15 14 13 12 9 8 42 41 6 5 54 53 64 59 58 57

CPUCLKP_R CPUCLKN_R

RP43

1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3

2 0X2 4

CPUCLKP (4) CPUCLKN (4)

To CPU

NBGFX_CLKP_R NBGFX_CLKN_R MXM_REFCLKP_R MXM_REFCLKN_R

RP44 RP45

2 0X2 4 2 [email protected] 4 2 0X2 4 2 0X2 4 2 4 2 4 2 4 2 4 2 4

NBGFX_CLKP NBGFX_CLKN CLK_MXM CLK_MXM#

RS780/RX780 for VGATo NB

NBGFX_CLKP (11) NBGFX_CLKN (11) To MXM

CLK_MXM (18) CLK_MXM# (18)

+1.2V_CLK_VDDIO

+3V

Q45 *RHU002N06

+3V_CLK_VDD

R254

*0_6

VDDSRC_IO0 VDDSRC_IO1 VDDATIG_IO VDDSB_SRC_IO VDDCPU_IO GND48 GNDDOT GNDSRC0 GNDSRC1 GNDATIG GNDSB_SRC GNDSATA GNDCPU GNDHTT GNDREF X1 X2 SMBCLK SMBDAT PD# CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#

SB_SRC0T SB_SRC0C SB_SRC1T SB_SRC1C SRC0T SRC0C SRC1T SRC1C SRC2T SRC2C SRC3T SRC3C SRC4T SRC4C

SBLINK_CLKP_R SBLINK_CLKN_R SBSRC_CLKP_R SBSRC_CLKN_R

RP41 RP42

SBLINK_CLKP SBLINK_CLKN SBSRC_CLKP SBSRC_CLKN

SBLINK_CLKP (11) SBLINK_CLKN (11) SBSRC_CLKP (13) SBSRC_CLKN (13)

C

To NB To SB

1

3

CLKREQ_TV# (23)

QFN64

+3V

RP47 NBGPP_CLKP_R NBGPP_CLKN_R CLK_PCIE_NEW_R RP48 CLK_PCIE_NEW#_R CLK_PCIE_MINI_R RP49 CLK_PCIE_MINI#_R CLK_PCIE_MINI2_R RP51 CLK_PCIE_MINI2#_R RP50 CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

*0X2 0X2 0X2 0X2 0X2

NBGPP_CLKP NBGPP_CLKN

RX780 onlyTo NB

CLK_PCIE_NEW_C CLK_PCIE_NEW_C# CLK_PCIE_MINI1 CLK_PCIE_MINI1# CLK_PCIE_TV CLK_PCIE_TV# CLK_PCIE_LAN CLK_PCIE_LAN#

NBGPP_CLKP (11) NBGPP_CLKN (11)

CLK_PCIE_NEW_C (27) To New Card CLK_PCIE_NEW_C# (27) CLK_PCIE_MINI1 (23) To Mini PCIE Slot CLK_PCIE_MINI1# (23) CLK_PCIE_TV (23) To Mini PCIE Slot CLK_PCIE_TV# (23) CLK_PCIE_LAN (21) To LAN Controller CLK_PCIE_LAN# (21)

2

R521 *10K_4 CLKREQ2#

Q44 *RHU002N06 CG_XIN CG_XOUT

1

3

CLKREQ_WLAN#

(23)

SRC6T/SATAT SRC6C/SATAC SRC7T/27M_SS SRC7C/27M_NS HTT0T/66M HTT0C/66M 48MHz_0 REF0/SEL_HTT66 REF1/SEL_SATA REF2/SEL_27 TGND0 TGND1 TGND2 TGND3 TGND4 TGND5 TGND6 TGND7 TGND8 TGND9

T140 T138 T145 T144 NBHT_REFCLKP_R RP46 NBHT_REFCLKN_R

B:(10/25) Add WLAN & LAN CLKREQ circuit (BOI request)

(7,14,20,21,23,27) PCLK_SMB (7,14,20,21,23,27) PDAT_SMB

1 3R548 R547

2 0X2 422_4 22_4

NBHT_REFCLKP NBHT_REFCLKN

NBHT_REFCLKP NBHT_REFCLKN CLK_Card48 (28) CLK_48M_USB (14)

(11) (11)

To NB

51 23 45 44 39 38

CLK_48M_USB_R

CLK_48M_USB

To SB

B

T142 (14,27) NEW_CLKREQ# T139

NEW_CLKREQ# CLKREQ2# CLKREQ3#

SEL_HTT66 SEL_SATA SEL_27

R536 R535

Ra Rb

B

158/F_4 90.9/F_4

EXT_NB_OSC

EXT_NB_OSC (11)

To NB

NB CLOCK INPUT TABLENB CLOCKS RX780 100M DIFF 100M DIFF 14M SE (1.8V) NC 100M DIFF 100M DIFF 100M DIFF RS780 100M DIFF 100M DIFF 14M SE (1.1V) vref 100M DIFF(IN/OUT)*NC or 100M DIFF OUTPUT

C606

33p/50V_4 SLG8SP628

C600 *10p/50V_4

C624 *10p/50V_4

RX780 1.8V Ra Rb 82.5R 130R

RS780 1.1V 158R 90.9R

1+3V_CLK_VDD R523 R530 8.2K_4 8.2K_4 NEW_CLKREQ# CLK_PD# 33p/50V_4 C611

2 2

CG_XIN Y6 14.318MHZ

65 66 67 68 69 70 71 72 73 74

HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N

10/17 Add 10p for EMI issue (Suggestion by Seligo)

1

1

2

CG_XOUT

GFX_REFCLK GPP_REFCLK GPPSB_REFCLK

RES CHIP 130 1/16W +-1%(0402)L-F -->CS11302FB15 RES CHIP 158 1/16W +-1%(0402) -->CS11582FB00 RES CHIP 90.9 1/16W +-1%(0402) -->CS09092FB15 RES CHIP 82.5 1/16W +-1%(0402) -->CS08252FB11

100M DIFF

CLOCKS name NBGFX_CLKP NBGFX_CLKN MXM_REFCLKP MXM_REFCLKN NBGPP_CLKP NBGPP_CLKN

RX780 RP1001 STUFF

RS780 RP1001 STUFF

Clock pin function to NB for VGA reference clock

+3V_CLK_VDD SEL_HTT66 R537 8.2K_4 R640 R641 *110/F_4 *75/F_4 CLK_14M_SB (13)

(For SB A13)SEL_SATA SEL_HTT66 SEL_27 1 SEL_HTT66 66 MHz 3.3V single ended HTT clock 100 MHz differential HTT clock 100 MHz non-spreading differential SRC clock 100 MHz spreading differential SRC clock 27MHz and 27M SS outputs 100 MHz SRC clock Size Document Number

RP66 STUFF

RP66 NC

to M82-S external reference clock -RX780 only

A

A

RP1005 STUFF

RP1005 NC

to NB for RX780 for PCIEX2 interface reference clock only RS780 is internal share with AC-LINK clock,RS780 not need to NB for AC-LINK reference clock

R539 *8.2K_4

R540 8.2K_4

R534 8.2K_4 SEL_SATA

0* 1*

SBLINK_CLKP SBLINK_CLKN

RP1003 STUFF

RP1003 STUFF

0 1 SEL_27 0* * default

Quanta Computer Inc.PROJECT : ZK3CLOCK GENERATOR_SLG8SP628Date:2

Rev 1A 43

Monday, August 18, 20081

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BLM21PG221SN1D +2.5V +1.2V R379 R373 0_8 0_8 +1.2V_VLDT U27A C462 C461 C463 C464D

+CPUVDDA L20 C202 LS0805-100M-N 10U/6.3V_8 C190 4.7U/6.3V_6

W/S= 15 mil/20milC177 C188 0.22U/6.3V_4 C189 3300p/50V_4 100U/6.3_3528 (3) (3)

CPU_LDT_RST# CPU_LDT_STOP#

300_4 300_4 300_4 300_4 C498 *0.1U/10V_4

R454 R166 R434 R443

+1.8V

CPU CLKCPUCLKP CPUCLKN CPUCLKP CPUCLKN +CPUVDDA W/S= 15 mil/20mil +CPUVDDA +CPUVDDA CPUCLKIN CPUCLKIN# CPU_LDT_RST# CPU_PWRGD CPU_LDT_STOP# CPU_LDT_REQ#_CPU CPU_SIC CPU_SID CPU_ALERT R154 R152 CPU_HTREF0 44.2/F_4 44.2/F_4 CPU_HTREF1 place them to CPU within 1.5" CPU_LDT_REQ#_CPU CPU_PWRGD U27D F8 F9 A9 A8 B7 A7 F10 C6 AF4 AF5 AE6 R6 P6 F6 E6 Y6 AB6 CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI T94 CPUTEST23 G10 AA9 AC9 AD9 AF9 AD7 VDDA1 VDDA2 CLKIN_H CLKIN_L RESET_L PWROK LDTSTOP_L LDTREQ_L SIC SID ALERT_L HT_REF0 HT_REF1 VDD0_FB_H VDD0_FB_L VDD1_FB_H VDD1_FB_L DBRDY TMS TCK TRST_L TDI TEST23 TEST18 TEST19 VDDIO_FB_H VDDIO_FB_L VDDNB_FB_H VDDNB_FB_L DBREQ_L TDO TEST28_H TEST28_L TEST17 TEST16 TEST15 TEST14 TEST7 TEST10 TEST8 W9 Y9 H6 G6 E10 CPU_DBREQ# AE9 CPU_TDO J7 H8 D7 E7 F7 C7 C3 K8 C4 C9 C8 CPUTEST28H CPUTEST28L CPUTEST17 CPUTEST16 CPUTEST15 CPUTEST14 VDDIO_FB_H VDDIO_FB_L VDDIO_FB_H VDDIO_FB_L CPU_VDDNB_FB_H CPU_VDDNB_FB_L T40 T97 T22 T16 (35) (35) KEY1 KEY2 SVC SVD M11 W18 A6 A4 CPU_SVC_R CPU_SVD_R +1.8V

+1.2V_VLDT

04D

AMD Suggestion 3/29 modify Keep trace from resisor to CPU within 0.6"keep trace from caps to CPU within 1.2"4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 180p/50V_4 +1.2V_VLDT +1.2V_VLDT +1.2V_VLDT +1.2V_VLDT +1.2V_VLDT +1.2V_VLDT +1.2V_VLDT +1.2V_VLDT 4.7U/6.3V_6 0.22U/6.3V_4 180p/50V_4 C460 C466 C465 CPUCLKIN CPUCLKP CPUCLKN R456 C519 C514 169/F_4 CPUCLKIN#

1/30 leakage issue , change +1.8Vsus to +1.8V

D1 D2 D3 D4 E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 J3 J2 J5 K5

VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3

HT LINK

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

AE2 AE3 AE4 AE5 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3 Y1 W1 Y4 Y3 R2 R3 T5 R5

3900p/25V_4 3900p/25V_4

(9) HT_NB_CPU_CAD_H[15..0] (9) HT_NB_CPU_CAD_L[15..0] (9) HT_NB_CPU_CLK_H[1..0] (9) HT_NB_CPU_CLK_L[1..0] (9) HT_NB_CPU_CTL_H[1..0] (9) HT_NB_CPU_CTL_L[1..0] (9) HT_CPU_NB_CAD_H[15..0] (9) HT_CPU_NB_CAD_L[15..0] (9) HT_CPU_NB_CLK_H[1..0] (9) HT_CPU_NB_CLK_L[1..0] (9) HT_CPU_NB_CTL_H[1..0] (9) HT_CPU_NB_CTL_L[1..0]

HT_NB_CPU_CAD_H[15..0] HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CLK_L[1..0] HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CTL_L[1..0] HT_CPU_NB_CAD_H[15..0] HT_CPU_NB_CAD_L[15..0] HT_CPU_NB_CLK_H[1..0]

C

+1.2V_VLDT

R377 R376

*51_4 *51_4

www.kythuatvitinh.comHT_CPU_NB_CLK_L[1..0] HT_CPU_NB_CTL_H[1..0]

HT_CPU_NB_CTL_L[1..0]

HT_NB_CPU_CAD_H0 HT_NB_CPU_CAD_L0 HT_NB_CPU_CAD_H1 HT_NB_CPU_CAD_L1 HT_NB_CPU_CAD_H2 HT_NB_CPU_CAD_L2 HT_NB_CPU_CAD_H3 HT_NB_CPU_CAD_L3 HT_NB_CPU_CAD_H4 HT_NB_CPU_CAD_L4 HT_NB_CPU_CAD_H5 HT_NB_CPU_CAD_L5 HT_NB_CPU_CAD_H6 HT_NB_CPU_CAD_L6 HT_NB_CPU_CAD_H7 HT_NB_CPU_CAD_L7 HT_NB_CPU_CAD_H8 HT_NB_CPU_CAD_L8 HT_NB_CPU_CAD_H9 HT_NB_CPU_CAD_L9 HT_NB_CPU_CAD_H10 HT_NB_CPU_CAD_L10 HT_NB_CPU_CAD_H11 HT_NB_CPU_CAD_L11 HT_NB_CPU_CAD_H12 HT_NB_CPU_CAD_L12 HT_NB_CPU_CAD_H13 HT_NB_CPU_CAD_L13 HT_NB_CPU_CAD_H14 HT_NB_CPU_CAD_L14 HT_NB_CPU_CAD_H15 HT_NB_CPU_CAD_L15 HT_NB_CPU_CLK_H0 HT_NB_CPU_CLK_L0 HT_NB_CPU_CLK_H1 HT_NB_CPU_CLK_L1 HT_NB_CPU_CTL_H0 HT_NB_CPU_CTL_L0 HT_NB_CPU_CTL_H1 HT_NB_CPU_CTL_L1

L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1

L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15

HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H2 HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H3 HT_CPU_NB_CAD_L3 HT_CPU_NB_CAD_H4 HT_CPU_NB_CAD_L4 HT_CPU_NB_CAD_H5 HT_CPU_NB_CAD_L5 HT_CPU_NB_CAD_H6 HT_CPU_NB_CAD_L6 HT_CPU_NB_CAD_H7 HT_CPU_NB_CAD_L7 HT_CPU_NB_CAD_H8 HT_CPU_NB_CAD_L8 HT_CPU_NB_CAD_H9 HT_CPU_NB_CAD_L9 HT_CPU_NB_CAD_H10 HT_CPU_NB_CAD_L10 HT_CPU_NB_CAD_H11 HT_CPU_NB_CAD_L11 HT_CPU_NB_CAD_H12 HT_CPU_NB_CAD_L12 HT_CPU_NB_CAD_H13 HT_CPU_NB_CAD_L13 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H15 HT_CPU_NB_CAD_L15 HT_CPU_NB_CLK_H0 HT_CPU_NB_CLK_L0 HT_CPU_NB_CLK_H1 HT_CPU_NB_CLK_L1 HT_CPU_NB_CTL_H0 HT_CPU_NB_CTL_L0 HT_CPU_NB_CTL_H1 HT_CPU_NB_CTL_L1

10/9 AMD suggest 1. pull up CPU_PWRGD to +1.8SUS 2. pop R5563 pull up to +1.8SUS

(13) CPU_LDT_RST# (13) CPU_PWRGD (11,13) CPU_LDT_STOP#

THERMTRIP_L PROCHOT_L MEMHOT_L THERMDC THERMDA

AF6 AC7 AA8 W7 W8

CPU_THERMTRIP_L# CPU_PROCHOT_L# CPU_MEMHOT_L# CPU_THERMDC CPU_THERMDA R113 R110 0_4 H_THERMDC 0_4 H_THERMDA

SideBand Temp sense I2C

+1.2V_VLDT

(35) CPU_VDD0_FB_H (35) CPU_VDD0_FB_L (35) CPU_VDD1_FB_H (35) CPU_VDD1_FB_L T21 T20 T15 T96 T95

AMD Suggestion 3/29 modify

*300_4 *300_4

R159 R145

CPUTEST18 CPUTEST19

H10 G9 E9 E8

+1.8VSUS

R160 R151

510/F_4 510/F_4

CPUTEST25H CPUTEST25L

TEST25_H TEST25_L TEST21 TEST20 TEST24 TEST22 TEST12 TEST27 TEST9 TEST6

T29 T26 *300_4 *300_4

R150 R157

L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1

+1.8VSUS

300_4 *300_4 300_4 *300_4 *300_4

R139 R410 R402 R408 R140

R416

*300_4

CPUTEST21 CPUTEST20 CPUTEST24 CPUTEST22 CPUTEST12 CPUTEST27

AB8 AF7 AE7 AE8 AC8 AF8

N1 P1 P3 P4

L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1

L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1

AMD Suggestion 3/29 modify

R409

0_4

C2 AA6 A3 A5 B3 B5 C1

TEST29_H TEST29_L RSVD10 RSVD9 RSVD8 RSVD7 RSVD6

CPUTEST29H CPUTEST29L

T34 T33

C

HT_NB_CPU_CTL_H1 HT_NB_CPU_CTL_L1

SOCKET_638_PIN

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5

H18 H19 AA7 D5 C5

SOCKET_638_PIN

CNTR_VREF C522 +3V R458 20K/F_4 R445 0.1U/10V_4 34.8K/F_4 CNTR_VREF 2

CNTR_VREF +3V

10/9 AMD suggest remove MOS and connect directlyCNTR_VREF

+1.8VSUS

2/4 pull up R691 CPU_BDREQ# to avoid noise cause system shut down+1.8VSUS

HDT Connector

R463 1K/F_4 2

R386 390_4

R391 390_4

R395 1K/F_4

R168 300_4 CPU_DBREQ#

Q41 CPU_LDT_REQ#_CPU 1

*BSS138_NL/SOT23 3

CPU_LDT_REQ#

(11)

CPU_LDT_RST#

1

CPU_LDT_RST_HTPA# 3 Q42 BSS138_NL/SOT23

T104

(14) SB_SCLK3

SB_SCLK3

R387

*0_4

CPU_SIC

1

R439 C489 *100p/50V_4

0_6 C504 *100p/50V_4

2

G1 *SHORT_ PAD1

(14) SB_SDATA3

SB_SDATA3

R392

*0_4 Q30 1

CPU_SID

2

THERM_ALERT#_R

3 *BSS138_NL/SOT23

CPU_ALERTB

for debug onlyB

+1.8VSUS 3

1/31 leakage issue ,add R687, no stuff R686+1.8VSUS +1.8VSUS R155 R142 10K/F_4 2 300_4 3

VFIX MODEQ33 +1.8VSUS R349 FDV301N *10K_4 D37 *BAS316 CPU_SVC_R CPU_SVD_R CPU_PWRGD R420 R438 R440 R430 R444 R435 R422 R448 1K/F_4 1K/F_4 0_4 0_4 0_4 *220_4 *220_4 *220_4 +3V

3/19 double checkQ16 MMBT3904 CPU_MEMHOT# 1 +3V (32) CPU_MEMHOT# (14,32) 1 R369 1K_4 +1.8VSUS 2 R396 300_4 R362 100K_6 HWPG 2

Serial VIDCPU_SVC CPU_SVD CPU_PWRGD_SVID_REG CPU_SVC (35) CPU_SVD (35) CPU_PWRGD_SVID_REG (35)

VID Override CircuitVoltage Output

SVC

SVD

CPU_MEMHOT_L# R433 R437 10K/F_4

+1.8VSUS +1.8VSUS

R429 2 300_4 Q40 *10K_4

0 0 1 1

0 1 0 1

1.4V 1.2V 1.0V 0.8V

CPU Thermal monitor3 R360 *0_6 CPU_THERMTRIP# SYS_SHDN# (34,39) (14) +3V Q11 RHU002N06 1 +3V 2 R107 10K_4 R112 10K_4

CPU_PROCHOT_L#

1

3 MMBT3904 0_4

EC_PROCHOT# CPU_PROCHOT_SB# (13)

(32)

CPU_THERMTRIP_L#

1 Q32 MMBT3904

2/19 change G781 to G786P81UR105 200_6 LM86VCC C101 0.1U/10V_4 U10 Q13 RHU002N06 1 +3V 2 H_THERMDA 8 7 6 4 2 R365 *8.2K_4 (15) THERM_ALERT# 3 *2N7002E-LF +3V (31) CPUFAN#_ON R119 Q31 10K_4 1 R117 *10K_4 THERM_ALERT#_R SCLK SDA ALERT# OVERT# G786P81U VCC DXP DXN GND 1 2 3 5 C105 2200p/50V_4 H_THERMDC R118 *0_4

R436

3/19 double check

(32) ABCLK

3

A

(32) ABDATA

3 +3V

2/18 G781 reverse R718 0 ohm for A Griffin CPU

ADDRESS: 98H

MAX6657,G781P8,W83L771G Layout Note:Routing 10:10 mils and away from noise source with ground gard2

Quanta Computer Inc.PROJECT : ZK3S1g2 HT, CTL I/F 1/3Rev 1A of 43

10/30 change to G781

Size Date:

Document Number Monday, August 18, 20081

Sheet

4

5

4

3

A

B

C

D

E

+SMDDR_VTERM

U27B

+SMDDR_VTERM MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9

PLACE THEM CLOSE TO CPU WITHIN 1"

D10 C10 B10 AD10R431 R432 39.2/F_4 M_ZP 39.2/F_4 M_ZN

VTT1 VTT2 VTT3 VTT4 MEMZP MEMZN

W 10 AC10 AB10 AA10 A10 Y10CPU_VTT_SENSE

+1.8VSUS

(7) MEM_MB_DATA[0..63] +SMDDR_VREF

Processor Memory InterfaceU27C MEM:DATA MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63 MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

05MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63 MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7 MEM_MA_DATA[0..63] (7)4

750 mAR192 2K/F_4 CPU_VTT_SENSE (37)

+1.8VSUS T464

AF10 AE10

R173 *0_4

Reserved

VTT_SENSE MEMVREF RSVD_M2 MB0_ODT0 MB0_ODT1 MB1_ODT0 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 MB_CKE0 MB_CKE1 MB_CLK_H5 MB_CLK_L5 MB_CLK_H1 MB_CLK_L1 MB_CLK_H7 MB_CLK_L7 MB_CLK_H4 MB_CLK_L4

MEM_MA_RESET# H16

RSVD_M1 MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 MA_CKE0 MA_CKE1 MA_CLK_H5 MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4 MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

W 17 MEMVREF_CPU B18 MEM_MB_RESET# W 26 W 23 Y26 MEM_MB1_ODT0 V26 W 25 U22 J25 H26 P22 R22 A17 A18 AF18 AF17 R26 R25 P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W 24 J23 J24 R24 U26 J26 U25 U24 U23CPU_MB_CLK_H5 CPU_MB_CLK_HL5 T113 R179 MEM_MB0_ODT0 (7,8) 2K/F_4 MEM_MB0_ODT1 (7,8) T82 MEM_MB0_CS#0 (7,8) MEM_MB0_CS#1 (7,8) T76 MEM_MB_CKE0 (7,8) MEM_MB_CKE1 (7,8) T83 T80 MEM_MB_CLK1_P (7) MEM_MB_CLK1_N (7) MEM_MB_CLK7_P (7) MEM_MB_CLK7_N (7) T75 T84 MEM_MB_ADD[0..15] C218 0.1U/10V_4 C210 1000p/50V_4

(7,8) MEM_MA0_ODT0 (7,8) MEM_MA0_ODT1 T85 T86 (7,8) MEM_MA0_CS#0 (7,8) MEM_MA0_CS#1 T81 T77 (7,8) MEM_MA_CKE0 (7,8) MEM_MA_CKE1 T73 T78 MEM_MA_CLK1_P MEM_MA_CLK1_N MEM_MA_CLK7_P MEM_MA_CLK7_N T79 T74 (7,8) MEM_MA_ADD[0..15] (7) (7) (7) (7)

MEM_MA1_ODT0 MEM_MA1_ODT1

T19 V22 U21 V19 T20 U19 U20 V20 J22 J20

CPU_MA1_CS_L0 CPU_MA1_CS_L1

CPU_MA_CLK_H5 CPU_MA_CLK_L5

3

www.kythuatvitinh.comCPU_MB_CLK_H4 CPU_MB_CLK_L4 MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

N19 N20 E16 F16 Y16 AA16 CPU_MA_CLK_H4 P19 CPU_MA_CLK_L4 P20 N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19 R20 R23 J21 R19 T22 T24

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

(7,8)

(7,8) MEM_MA_BANK0 (7,8) MEM_MA_BANK1 (7,8) MEM_MA_BANK2 (7,8) MEM_MA_RAS# (7,8) MEM_MA_CAS# (7,8) MEM_MA_WE#

MA_BANK0 MA_BANK1 MA_BANK2 MA_RAS_L MA_CAS_L MA_W E_LSOCKET_638_PIN

MB_BANK0 MB_BANK1 MB_BANK2 MB_RAS_L MB_CAS_L MB_W E_L

MEM_MB_BANK0 (7,8) MEM_MB_BANK1 (7,8) MEM_MB_BANK2 (7,8) MEM_MB_RAS# (7,8) MEM_MB_CAS# (7,8) MEM_MB_WE# (7,8)

C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11 A12 B16 A22 E25 AB26 AE22 AC16 AD12 C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W 22 W 21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W 16 W 14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W 11 AB14 AA14 AB12 AA12 E12 C15 E19 F24 AC24 Y19 AB16 Y13 G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W 15 W 12 W 13

3

2

+SMDDR_VTERM

Place close to socketC499 4.7U/6.3V_6 C507 4.7U/6.3V_6 C533 4.7U/6.3V_6 C200 0.22U/6.3V_4 C530 0.22U/6.3V_4 C511 0.22U/6.3V_4

(7) MEM_MB_DM[0..7]

MEM_MA_DM[0..7]

(7)2

C534 4.7U/6.3V_6

C199 0.22U/6.3V_4

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

+SMDDR_VTERM

C520 C201 1000p/50V_4 1000p/50V_4

C529 1000p/50V_4

C176 1000p/50V_4

C185 180p/50V_4

C171 180p/50V_4

C517 180p/50V_4

C528 180p/50V_4

Close to CPU within 1500 milsMEM_MA_CLK7_P MEM_MB_CLK7_P C544 1.5p/50V_4 MEM_MA_CLK7_N MEM_MB_CLK7_N MEM_MA_CLK1_P MEM_MB_CLK1_P C545 1.5p/50V_4 MEM_MA_CLK1_N MEM_MB_CLK1_N C557 1.5p/50V_4 C532 1.5p/50V_4

(7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7)

MEM_MB_DQS0_P MEM_MB_DQS0_N MEM_MB_DQS1_P MEM_MB_DQS1_N MEM_MB_DQS2_P MEM_MB_DQS2_N MEM_MB_DQS3_P MEM_MB_DQS3_N MEM_MB_DQS4_P MEM_MB_DQS4_N MEM_MB_DQS5_P MEM_MB_DQS5_N MEM_MB_DQS6_P MEM_MB_DQS6_N MEM_MB_DQS7_P MEM_MB_DQS7_N

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7SOCKET_638_PIN

MEM_MA_DQS0_P MEM_MA_DQS0_N MEM_MA_DQS1_P MEM_MA_DQS1_N MEM_MA_DQS2_P MEM_MA_DQS2_N MEM_MA_DQS3_P MEM_MA_DQS3_N MEM_MA_DQS4_P MEM_MA_DQS4_N MEM_MA_DQS5_P MEM_MA_DQS5_N MEM_MA_DQS6_P MEM_MA_DQS6_N MEM_MA_DQS7_P MEM_MA_DQS7_N

(7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7)

1

1

Quanta Computer Inc.PROJECT : ZK3Size Date: Document Number

S1G2 DDRII MEMORY I/F 2/3Monday, August 18, 2008E

Rev 1A 43

Sheet

5

of

A

B

C

D

5

4

3

2

1

U27F U27E

CPU_CORE0

CPU_CORE1

D

CPU VDDNB_CORE

G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11 K16 M16 P16 T16 V16

3A

VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23 VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12

+1.8VSUS

C

www.kythuatvitinh.com+1.8VSUS C220 22U/6.3V_8 C221 C219 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 C243 C228 22U/6.3V_8 C229 C245 0.22U/6.3V_4 0.22U/6.3V_4 C203 180p/50V_4 C233 180p/50V_4

VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2 Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

2A

H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17

VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13

SOCKET_638_PIN

AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129

J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

CPU_CORE0

06BOTTOM SIDE DECOUPLINGC181 22U/6.3V_8 C167 22U/6.3V_8 C158 22U/6.3V_8 C147 0.22U/6.3V_4 C143 0.01U/16V_4 C193 180p/50V_4D

C148 22U/6.3V_8

CPU_CORE1

C151 22U/6.3V_8

C179 22U/6.3V_8

C150 22U/6.3V_8

C149 22U/6.3V_8

C194 0.22U/6.3V_4

C163 C196 0.01U/16V_4 180p/50V_4

C157 0.01U/16V_4

CPU VDDNB_CORE

+1.8VSUS

C

DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.8VSUS

C272 4.7U/6.3V_6 +1.8VSUS

C261 4.7U/6.3V_6

C284 4.7U/6.3V_6

C274 4.7U/6.3V_6

C273 0.22U/6.3V_4

C267 0.22U/6.3V_4

C264 C260 C263 C262 0.22U/6.3V_4 0.22U/6.3V_4 0.01U/16V_4 0.01U/16V_4

C266 180p/50V_4

SOCKET_638_PINB B

PROCESSOR POWER AND GROUND

A

A

Quanta Computer Inc.PROJECT : ZK3Size Date:5 4 3 2

Document Number

S1G2 PWR & GND 3/3Monday, August 18, 2008 Sheet1

Rev 1A of 43

6

5

4

3

2

1

+1.8VSUS 81 82 87 88 95 96 103 104 111 112 117 118 (5,8) MEM_MA_ADD[0..15] MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0 BA1 BA2 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 CN26 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 50 69 83 120 163 MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA35 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA52 MEM_MA_DATA49 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA53 MEM_MA_DATA48 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA61 MEM_MA_DATA60 MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA[0..63] (5)(5,8) MEM_MB_ADD[0..15] MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15 MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2 MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

+1.8VSUS 81 82 87 88 95 96 103 104 111 112 117 118 CN29 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 50 69 83 120 163 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA45 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA44 MEM_MB_DATA41 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA60 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA61 MEM_MB_DATA57 MEM_MB_DATA62 MEM_MB_DATA63 MEM_MB_DATA[0..63] (5)

D

(5,8) MEM_MA_BANK[0..2]

(5,8) MEM_MB_BANK[0..2]

102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 107 106 85 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 30 32 164 166 79 80 108 113 109 110 115 114 119

VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0 BA1 BA2 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11

07D

(5) MEM_MA_DM[0..7]

MEM_MA_BANK0 107 MEM_MA_BANK1 106 MEM_MA_BANK2 85 MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 30 32 164 166 79 80 108 113 109 110 115 114 119 DIM1_SA0 DIM1_SA1 198 200 195 197 199 C339 0.1U/10V_4 1 2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54

(5) MEM_MB_DM[0..7]

(5) (5) (5) (5) (5) (5) (5) (5)C

MEM_MA_DQS0_P MEM_MA_DQS1_P MEM_MA_DQS2_P MEM_MA_DQS3_P MEM_MA_DQS4_P MEM_MA_DQS5_P MEM_MA_DQS6_P MEM_MA_DQS7_P

(5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5)

MEM_MA_DQS0_N MEM_MA_DQS1_N MEM_MA_DQS2_N MEM_MA_DQS3_N MEM_MA_DQS4_N MEM_MA_DQS5_N MEM_MA_DQS6_N MEM_MA_DQS7_N

www.kythuatvitinh.comDQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 CK0 CK0 CK1 CK1 CKE0 CKE1 RAS CAS WE S0 S1 ODT0 ODT1 SA0 SA1 SDA SCL VDDspd VREF VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) MEM_MB_DQS0_P MEM_MB_DQS1_P MEM_MB_DQS2_P MEM_MB_DQS3_P MEM_MB_DQS4_P MEM_MB_DQS5_P MEM_MB_DQS6_P MEM_MB_DQS7_P DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 CK0 CK0 CK1 CK1 CKE0 CKE1 RAS CAS WE S0 S1 ODT0 ODT1 SA0 SA1 SDA SCL VDDspd VREF VSS0 VSS1 VSS2 o VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 MEM_MB_DQS0_N MEM_MB_DQS1_N MEM_MB_DQS2_N MEM_MB_DQS3_N MEM_MB_DQS4_N MEM_MB_DQS5_N MEM_MB_DQS6_N MEM_MB_DQS7_N (5) (5) (5) (5) MEM_MB_CLK1_P MEM_MB_CLK1_N MEM_MB_CLK7_P MEM_MB_CLK7_N (5,8) MEM_MB_CKE0 (5,8) MEM_MB_CKE1 (5,8) MEM_MB_RAS# (5,8) MEM_MB_CAS# (5,8) MEM_MB_WE# (5,8) MEM_MB0_CS#0 (5,8) MEM_MB0_CS#1 (5,8) MEM_MB0_ODT0 (5,8) MEM_MB0_ODT1 T148 T146 T147 +3V VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 196 193 190 187 184 183 178 177 172 171 168 165 162 161 156 155 150 149 145 144 139 138 133 +0.9VSMVREF_DIMM C324 2.2U/6.3V_6 C321 0.1U/10V_4 DIM2_SA0 DIM2_SA1 PDAT_SMB PCLK_SMB C340 0.1U/10V_4 C319 1000p/50V_4

C

MEM_MA_CLK1_P MEM_MA_CLK1_N MEM_MA_CLK7_P MEM_MA_CLK7_N

(5,8) MEM_MA_CKE0 (5,8) MEM_MA_CKE1 (5,8) (5,8) (5,8) (5,8) (5,8) MEM_MA_RAS# MEM_MA_CAS# MEM_MA_WE# MEM_MA0_CS#0 MEM_MA0_CS#1

SO-DIMM

(5,8) MEM_MA0_ODT0 (5,8) MEM_MA0_ODT1

B

(3,14,20,21,23,27) PDAT_SMB (3,14,20,21,23,27) PCLK_SMB +3V

PDAT_SMB PCLK_SMB

NC1 NC2 NC3 NC4 NC/TEST

MEMHOT_SODIMM#_1 MEM_MA_RESET#1 MEM_MA_NC5

SO-DIMM

198 200 195 197 199 1 2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54

NC1 NC2 NC3 NC4 NC/TEST

MEMHOT_SODIMM#_2 MEM_MB_RESET#2 MEM_MB_NC5

T87 T141 T143B

+0.9VSMVREF_DIMM

C320 C322 1000p/50V_4 C323 0.1U/10V_4 2.2U/6.3V_6

+1.8VSUS

+SMDDR_VREF

+0.9VSMVREF_DIMM

R263 2K/F_4

VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33

VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33

R261

*0_4

+0.9VSMVREF_DIMM

VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34

196 193 190 187 184 183 178 177 172 171 168 165 162 161 156 155 150 149 145 144 139 138 133 DDR SO-DIMM SOCKET 1.8VA

59 60 65 66 71 72 77 78 121 122 127 128 132

A

Only for reservedDDR SO-DIMM SOCKET 1.8V

R262 2K/F_4

59 60 65 66 71 72 77 78 121 122 127 128 132 DIM2_SA0 DIM2_SA1 R260 R259

H=9.2

H=5.2R571 R576 10K/F_4 10K/F_4 DIM1_SA0 DIM1_SA1

1/18 Change CN23 footprint from DDR-C-1734071-200P to DDR-C-1734071-200P-BD3A (SMT open issue)

10K/F_4 10K/F_4

+3V


SMbus address A2

SMbus address A05 4 3 2

DDR2 SODIMMS: A/B CHANNELMonday, August 18, 20081

Rev 1A 43

Sheet

7

of

5

4

3

2

1

(5,7) MEM_MA_ADD[0..15] (5,7) MEM_MA_BANK[0..2]

MEM_MA_ADD[0..15] MEM_MA_BANK[0..2]

(5,7) MEM_MB_ADD[0..15] (5,7) MEM_MB_BANK[0..2]

MEM_MB_ADD[0..15] MEM_MB_BANK[0..2]

08+SMDDR_VTERM C316 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 +1.8VSUS +1.8VSUS +1.8VSUS +1.8VSUS +1.8VSUS +1.8VSUSD

+SMDDR_VTERM MEM_MA_BANK2 MEM_MA_ADD12 MEM_MA_CKE0 MEM_MA_ADD9 MEM_MA_ADD5 MEM_MA_ADD8 MEM_MA_ADD3 MEM_MA_ADD1 MEM_MA_BANK0 MEM_MA_ADD10 MEM_MA_WE# MEM_MA_CAS# MEM_MA0_ODT1 MEM_MA0_CS#1 MEM_MA_ADD15 MEM_MA_CKE1 RP29 RP30 RP31 RP32 RP33 RP27 RP28 RP34

D

(5,7) MEM_MA_CKE0

(5,7) (5,7) (5,7) (5,7)

MEM_MA_WE# MEM_MA_CAS# MEM_MA0_ODT1 MEM_MA0_CS#1

(5,7) MEM_MA_CKE1

4 2 4 2 4 2 4 2 2 4 4 2 2 4 4 2 2 4 2 4 4 2 4 2 2 4 4 2

3 1 3 1 3 1 3 1 1 3 3 1 1 3 3 1

47_4P2R_4 C288 47_4P2R_4 C309 47_4P2R_4 C315 47_4P2R_4 C338 47_4P2R_4 C313 47_4P2R_4 C331 47_4P2R_4 C317 47_4P2R_4 C348 C286 C327 C311 C347 C356 C349 C289 C310 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 +1.8VSUS 0.1U/10V_4 0.1U/10V_4 +1.8VSUS 0.1U/10V_4 0.1U/10V_4 +1.8VSUS 0.1U/10V_4 0.1U/10V_4 +1.8VSUS

(5,7) MEM_MB_CKE0

(5,7) (5,7) (5,7) (5,7) (5,7)

MEM_MB_WE# MEM_MB_CAS# MEM_MB0_ODT1 MEM_MB0_CS#1 MEM_MB_CKE1

MEM_MB_CKE0 MEM_MB_BANK2 MEM_MB_ADD12 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD5 MEM_MB_ADD3 MEM_MB_ADD1 MEM_MB_ADD10 MEM_MB_BANK0 MEM_MB_WE# MEM_MB_CAS# MEM_MB0_ODT1 MEM_MB0_CS#1 MEM_MB_CKE1 MEM_MB_ADD15 MEM_MB_ADD11 MEM_MB_ADD14 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD2 MEM_MB_ADD4

RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP20 RP21 RP22 RP23 RP24 RP25 RP26

4 2 4 2 4 2 4 2 2 4 2 4 4 2 2 4 4 2 4 2 4 2 2 4 2 4 4 2

3 1 3 1 3 1 3 1 1 3 1 3 3 1 1 3

47_4P2R_4 47_4P2R_4 C328 47_4P2R_4 C314 47_4P2R_4 C293 47_4P2R_4 C312 47_4P2R_4 C292 47_4P2R_4 C357 47_4P2R_4 C290 C355 C291

C

www.kythuatvitinh.comC354 C307 C318 C346 C287 C308 MEM_MA_ADD2 MEM_MA_ADD4 RP37

MEM_MA_ADD14 RP35 MEM_MA_ADD6 MEM_MA_ADD11 RP36 MEM_MA_ADD7

1 47_4P2R_4 3 1 47_4P2R_4 3 3 47_4P2R_4 1 3 47_4P2R_4 1 1 47_4P2R_4 3 3 47_4P2R_4 1

+1.8VSUS

3 47_4P2R_4 1 3 47_4P2R_4 1 3 47_4P2R_4 1 1 47_4P2R_4 3 1 47_4P2R_4 3 3 47_4P2R_4 1

+1.8VSUS

MEM_MA_BANK1 RP40 MEM_MA_ADD0 MEM_MA0_CS#0 RP38 MEM_MA_RAS# MEM_MA_ADD13 RP39 MEM_MA0_ODT0

+1.8VSUS

MEM_MB_BANK1 MEM_MB_ADD0 MEM_MB0_CS#0 MEM_MB_RAS#

+1.8VSUS

(5,7) MEM_MA0_CS#0 (5,7) MEM_MA_RAS#

(5,7) MEM_MB0_CS#0 (5,7) MEM_MB_RAS#

+1.8VSUS

+1.8VSUS

(5,7) MEM_MB0_ODT0

(5,7) MEM_MA0_ODT0

MEM_MB0_ODT0 MEM_MB_ADD13

C

PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH+1.8VSUS +1.8VSUS

PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH

C278 0.1U/10V_4

C282 0.1U/10V_4

C276 0.1U/10V_4

C281 0.1U/10V_4

C283 0.1U/10V_4

C285 0.1U/10V_4

C294 0.1U/10V_4

C326 0.1U/10V_4

C352 0.1U/10V_4

C353 0.1U/10V_4

C330 0.1U/10V_4

C275 0.1U/10V_4

PLACE CLOSE TO SOCKET( PER EMI/EMC)

PLACE CLOSE TO SOCKET( PER EMI/EMC)

B

B

A

A


Document Number

DDR2 SODIMMS TERMINATIONSMonday, August 18, 2008 Sheet1

Rev 1A 43

8

of

5

4

3

2

1

U26A HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H2 HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H3 HT_CPU_NB_CAD_L3 HT_CPU_NB_CAD_H4 HT_CPU_NB_CAD_L4 HT_CPU_NB_CAD_H5 HT_CPU_NB_CAD_L5 HT_CPU_NB_CAD_H6 HT_CPU_NB_CAD_L6 HT_CPU_NB_CAD_H7 HT_CPU_NB_CAD_L7 HT_CPU_NB_CAD_H8 HT_CPU_NB_CAD_L8 HT_CPU_NB_CAD_H9 HT_CPU_NB_CAD_L9 HT_CPU_NB_CAD_H10 HT_CPU_NB_CAD_L10 HT_CPU_NB_CAD_H11 HT_CPU_NB_CAD_L11 HT_CPU_NB_CAD_H12 HT_CPU_NB_CAD_L12 HT_CPU_NB_CAD_H13 HT_CPU_NB_CAD_L13 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H15 HT_CPU_NB_CAD_L15 HT_CPU_NB_CLK_H0 HT_CPU_NB_CLK_L0 HT_CPU_NB_CLK_H1 HT_CPU_NB_CLK_L1 HT_CPU_NB_CTL_H0 HT_CPU_NB_CTL_L0 HT_CPU_NB_CTL_H1 HT_CPU_NB_CTL_L1 301/F_4

HYPER TRANSPORT CPU I/F

D

Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25 AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W 21 W 20 V21 V20 U20 U21 U19 U18 T22 T23 AB23 AA22 M22 M23 R21 R20

HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N

PART 1 OF 6

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22 F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18 H24 H25 L21 L20

HT_NB_CPU_CAD_H0 HT_NB_CPU_CAD_L0 HT_NB_CPU_CAD_H1 HT_NB_CPU_CAD_L1 HT_NB_CPU_CAD_H2 HT_NB_CPU_CAD_L2 HT_NB_CPU_CAD_H3 HT_NB_CPU_CAD_L3 HT_NB_CPU_CAD_H4 HT_NB_CPU_CAD_L4 HT_NB_CPU_CAD_H5 HT_NB_CPU_CAD_L5 HT_NB_CPU_CAD_H6 HT_NB_CPU_CAD_L6 HT_NB_CPU_CAD_H7 HT_NB_CPU_CAD_L7 HT_NB_CPU_CAD_H8 HT_NB_CPU_CAD_L8 HT_NB_CPU_CAD_H9 HT_NB_CPU_CAD_L9 HT_NB_CPU_CAD_H10 HT_NB_CPU_CAD_L10 HT_NB_CPU_CAD_H11 HT_NB_CPU_CAD_L11 HT_NB_CPU_CAD_H12 HT_NB_CPU_CAD_L12 HT_NB_CPU_CAD_H13 HT_NB_CPU_CAD_L13 HT_NB_CPU_CAD_H14 HT_NB_CPU_CAD_L14 HT_NB_CPU_CAD_H15 HT_NB_CPU_CAD_L15 HT_NB_CPU_CLK_H0 HT_NB_CPU_CLK_L0 HT_NB_CPU_CLK_H1 HT_NB_CPU_CLK_L1 HT_NB_CPU_CTL_H0 HT_NB_CPU_CTL_L0 HT_NB_CPU_CTL_H1 HT_NB_CPU_CTL_L1 HT_TXCALP R461 HT_TXCALN

HT_CPU_NB_CAD_H[15..0] HT_CPU_NB_CAD_L[15..0] HT_CPU_NB_CLK_H[1..0] HT_CPU_NB_CLK_L[1..0] HT_CPU_NB_CTL_H[1..0] HT_CPU_NB_CTL_L[1..0] HT_NB_CPU_CAD_H[15..0] HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CLK_L[1..0] HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CTL_L[1..0]

HT_CPU_NB_CAD_H[15..0] HT_CPU_NB_CAD_L[15..0] HT_CPU_NB_CLK_H[1..0] HT_CPU_NB_CLK_L[1..0] HT_CPU_NB_CTL_H[1..0] HT_CPU_NB_CTL_L[1..0] HT_NB_CPU_CAD_H[15..0] HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CLK_L[1..0] HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CTL_L[1..0]

(4) (4) (4) (4) (4) (4)

08D

(4) (4) (4) (4) (4) (4)

C

www.kythuatvitinh.comHT_TXCALP HT_TXCALN HT_RXCALP HT_RXCALNHT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N HT_RXCALP HT_RXCALN HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N

HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N

11/4 modify

signals

RS780

RX780 RES CHIP 1.21K 1/16W +-1%(0402) P/N : CS21212FB18

R641 300 ohm 1%

R641 1.21k ohm 1%

R655

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

M24 M25 P19 R18 B24 B25

R655 300 ohm 1%

R655 1.21k ohm 1%

RES CHIP 300 1/16W +-1%(0402) P/N : CS13002FB00

C

R641

R460

HT_RXCALP HT_RXCALN

C23 A24

HT_TXCALP HT_TXCALN

301/F_4

RS780(RX780)

A12 version RS780M AJ067400T05 100-CK2612(216-0674008-00) RS780MC AJ067400T06 100-CK2613(216-0674010-00) RX781 AJ067400T10 100-CK2642(215-0674024) SB700 AJA12FG0T18 100-CK2614(218S7EALA12FG)U26D

This block is for UMA RS780 only , RX780 can remove all component

A13 version RS780M AJ067400T18 100-CK2699(216-0674022) RS780MC AJ067400T20 100-CK2704(216-0674024) RX781 AJ067400T21 100-CK2706(215-0674034) A12 version SB700 AJA12FG0T18B

PAR 4 OF 6AB12 AE16 V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14 Y14 AD16 AE17 AD17 W 12 Y12 AD18 AB13 AB18 V14 V15 W 14 AE12 AD12 MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC) MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC) MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC) MEM_DQ12(NC) MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC) MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS1P(NC) MEM_DQS1N(NC) MEM_DM0(NC) MEM_DM1/DVO_D8(NC) IOPLLVDD18(NC) IOPLLVDD(NC) IOPLLVSS(NC) MEM_COMPP(NC) MEM_COMPN(NC)RS780(RX780)

SBD_MEM/DVO_I/F

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21 Y17 W 18 AD20 AE21 W 17 AE19 AE23 AE24 AD23 AE18+1.8_IOPLLVDD18_NB +1.1V_IOPLLVDD R371 R370 *0_6 *0_6 +1.8V +1.1V_NB

B

MEM_RASb(NC) MEM_CASb(NC) MEM_W Eb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC) MEM_CKP(NC) MEM_CKN(NC)

2/1 R480,R479 no stuff when RS780M without side port / RX781

without Side-Port NU 4/8IOPLLVDD- memory PLL not applicable to RX780

MEM_VREF(NC)

A

A


Document Number

RS740/RS780-HT LINK I/F 1/5Monday, August 18, 2008 Sheet1

Rev 1A 43

9

of

5

4

3

2

1

U26B PEG_RXP15 PEG_RXN15 PEG_RXP14 PEG_RXN14 PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12 PEG_RXP11 PEG_RXN11 PEG_RXP10 PEG_RXN10 PEG_RXP9 PEG_RXN9 PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0 D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6 M8 L8 P7 M7 P5 M5 R8 P8 R6 R5 P4 P3 T4 T3 GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N

PART 2 OF 6

D

C

T9 T10 (27) PCIE_RXP1 (27) PCIE_RXN1 (23) PCIE_RXP2 (23) PCIE_RXN2 (23) PCIE_RXP3 (23) PCIE_RXN3 (21) GLAN_RXP (21) GLAN_RXN

(13) (13) (13) (13) (13) (13) (13) (13)

PCIE_SB_NB_RX0P PCIE_SB_NB_RX0N PCIE_SB_NB_RX1P PCIE_SB_NB_RX1N PCIE_SB_NB_RX2P PCIE_SB_NB_RX2N PCIE_SB_NB_RX3P PCIE_SB_NB_RX3N

www.kythuatvitinh.comPCIE_RXP1 PCIE_RXN1 PCIE_RXP2 PCIE_RXN2 PCIE_RXP3 PCIE_RXN3 GLAN_RXP GLAN_RXN AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

C_PEG_TXP15 C_PEG_TXN15 C_PEG_TXP14 C_PEG_TXN14 C_PEG_TXP13 C_PEG_TXN13 C_PEG_TXP12 C_PEG_TXN12 C_PEG_TXP11 C_PEG_TXN11 C_PEG_TXP10 C_PEG_TXN10 C_PEG_TXP9 C_PEG_TXN9 C_PEG_TXP8 C_PEG_TXN8 C_PEG_TXP7 C_PEG_TXN7 C_PEG_TXP6 C_PEG_TXN6 C_PEG_TXP5 C_PEG_TXN5 C_PEG_TXP4 C_PEG_TXN4 C_PEG_TXP3 C_PEG_TXN3 C_PEG_TXP2 C_PEG_TXN2 C_PEG_TXP1 C_PEG_TXN1 C_PEG_TXP0 C_PEG_TXN0

C565 C568 C561 C563 C556 C560 C543 C549 C538 C542 C535 C537 C525 C527 C518 C523 C512 C516 C506 C509 C496 C502 C492 C494 C490 C491 C486 C488 C483 C485 C476 C477

[email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4

PEG_TXP15 PEG_TXN15 PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12 PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8 PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5 PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0

(18) PEG_RXN[15:0] (18) PEG_RXP[15:0]

PEG_RXN[15:0] PEG_RXP[15:0]

PEG_TXN[15:0] PEG_TXP[15:0]

PEG_TXN[15:0] (18) PEG_TXP[15:0] (18)

9D

Close to North Bridge

BTOClose to North BridgeC251 C253 C242 C247 C232 C241 C223 C226 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 INT_HDMITXP2 (20) INT_HDMITXN2 (20) INT_HDMITXP1 (20) INT_HDMITXN1 (20) INT_HDMITXP0 (20) INT_HDMITXN0 (20) INT_HDMITXP3 (20) INT_HDMITXN3 (20)

PCIE I/F GFX

C_PEG_TXP15 C_PEG_TXN15 C_PEG_TXP14 C_PEG_TXN14 C_PEG_TXP13 C_PEG_TXN13 C_PEG_TXP12 C_PEG_TXN12

To HDMI CONN

PCIE I/F GPP

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2 AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5 AC8 AB8

PCIE_TXP1_C PCIE_TXN1_C PCIE_TXP2_C PCIE_TXN2_C PCIE_TXP3_C PCIE_TXN3_C PCIE_TXP4_C PCIE_TXN4_C

C112 C115 C104 C100 C106 C107 C124 C120

0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4

T11 T12

PCIE_TXP1 (27) PCIE_TXN1 (27) PCIE_TXP2 (23) PCIE_TXN2 (23) PCIE_TXP3 (23) PCIE_TXN3 (23) GLAN_TXP (21) GLAN_TXN (21)

TO EPRESS CARD TO WLAN TO MINI CARD TO PCIE-LAN

NOTE:

RS780MC no support Graphic / HDMI

C

AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5

PCIE I/F SB

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

A_TX0P_C A_TX0N_C A_TX1P_C A_TX1N_C A_TX2P_C A_TX2N_C A_TX3P_C A_TX3N_C

C445 C446 C450 C449 C451 C452 C448 C447

0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4

PCIE_NB_SB_TX0P PCIE_NB_SB_TX0N PCIE_NB_SB_TX1P PCIE_NB_SB_TX1N PCIE_NB_SB_TX2P PCIE_NB_SB_TX2N PCIE_NB_SB_TX3P PCIE_NB_SB_TX3N +1.1V_NB

(13) (13) (13) (13) (13) (13) (13) (13)

PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)

NB_PCIECALRP NB_PCIECALRN

R101 R100

1.27K/F_4 2K/F_4

RS780(RX780)11/4 modifyRX780/RS740/RS780 difference table (PCIE LINK)RS740 NB_PCIECALRP GPP4B

RS780 Display Port Support (muxed on GFX)GFX_TX0,TX1,TX2 and TX3

RX780/RS780 1.27K (GND) GPP4 GFX_TX4,TX5,TX6 and TX7 DP1 GPP5 AUX1 and HPD1B

562R (GND) NC NC

DP0 AUX0 and HPD0

GPP5

A

A


Document Number

RS740/RS780-PCIE I/F 2/5Monday, August 18, 2008 Sheet1

Rev 1A of 43

10

5

4

3

2

1

U26C

RX780: Powered from the 1.8-V and driven by SB600 LDT_RST#, SB700 LDT_RST# or A_RST#. RS780: Powered from the 3.3-V and driven by SB600 LDT_RST#, SB700 LDT_RST# or A_RST#.

rail or rail or

+3V_AVDD_NB +1.8V_AVDDDI_NB +1.8V_AVDDQ_NB

F12 E12 F14 G15 H15 H14 E17 F17 F15

AVDD1(NC) AVDD2(NC) AVDDDI(NC) AVSSDI(NC) AVDDQ(NC) AVSSQ(NC) C_Pr(DFT_GPIO5) Y(DFT_GPIO2) COMP_Pb(DFT_GPIO4) RED(DFT_GPIO0) REDb(NC) GREEN(DFT_GPIO1) GREENb(NC) BLUE(DFT_GPIO3) BLUEb(NC) DAC_HSYNC(PWM_GPIO4) DAC_VSYNC(PWM_GPIO6) DAC_SDA(PCE_TCALRN) DAC_SCL(PCE_RCALRN) DAC_RSET(PWM_GPIO1)

PART 3 OF 6

CRT/TVOUT

TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC) TXOUT_L2N(DBG_GPIO0) TXOUT_L3P(NC) TXOUT_L3N(DBG_GPIO2)

A22 B22 A21 B21 B20 A20 A19 B19 B18 A18 A17 B17 D20 D21 D18 D19 B16 A16 D16 D17 A13 B13 A15 B15 A14 B14 C14 D15 C16 C18 C20 E20 C22

INT_TXLOUT0+ (18) INT_TXLOUT0- (18) INT_TXLOUT1+ (18) INT_TXLOUT1- (18) INT_TXLOUT2+ (18) INT_TXLOUT2- (18) T111 T106 INT_TXUOUT0+ (18) INT_TXUOUT0- (18) INT_TXUOUT1+ (18) INT_TXUOUT1- (18) INT_TXUOUT2+ (18) INT_TXUOUT2- (18) T110 T105 INT_TXLCLKOUT+ (18) INT_TXLCLKOUT- (18) INT_TXUCLKOUT+ (18) INT_TXUCLKOUT- (18) +1.8V_VDDLTP18_NB +1.8V_VDDLT_18_NB +3V_VDLT33_NB

11D

RS780(13) NB_PLTRST#D

(18) INT_CRT_RED NB_PLTRST# (18) INT_CRT_GRN (18) INT_CRT_BLU

INT_CRT_RED R183 R181 R182 [email protected]/F_4 INT_CRT_GRN [email protected]/F_4 INT_CRT_BLU [email protected]/F_4 INT_HSYNC INT_VSYNC INT_CRT_DDCDAT INT_CRT_DDCCLK R163 [email protected]/F_6 DAC_RSET_NB +1.1V_PLLVDD +1.8V_PLLVDD18

North Bridge RESET

G18 G17 E18 F18 E19 F19 A11 B11 E8 F8 G14 A12 D14 B12 H17 D7 E7 D8 A10 C10 C12 C25 C24

TXOUT_U0P(NC) TXOUT_U0N(NC) TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2) TXOUT_U2P(NC) TXOUT_U2N(NC) TXOUT_U3P(PCIE_RESET_GPIO5) TXOUT_U3N(NC) TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3) TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1) VDDLTP18(NC) VSSLTP18(NC)

RX780+1.1V_NB R177 R178 *2.2K_4 *2.2K_4 INT_CRT_DDCDAT INT_CRT_DDCCLK

(18) INT_HSYNC (18) INT_VSYNC (18) INT_CRT_DDCDAT (18) INT_CRT_DDCCLK

PLL PWR LVTM

PLLVDD(NC) PLLVDD18(NC) PLLVSS(NC) VDDA18HTPLL VDDA18PCIEPLL1 VDDA18PCIEPLL2 SYSRESETb POWERGOOD LDTSTOPb ALLOW_LDTSTOP HT_REFCLKP HT_REFCLKN

+1.8V_VDDA18HTPLL +1.8V_VDDA18PCIEPLL 10/9 add 2K pull up to DDCDAT /DDCCLK for RX780 NB_PLTRST# NB_PWRGD_IN NB_LDT_STOP# NB_ALLOW_LDTSTOP NBHT_REFCLKP NBHT_REFCLKN 0_4 0_4

VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC) VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)

11/4 no stuff for RS780M/MC/RX781

(17) NB_PWRGD_IN

C

12/22 stuff R48 2.2K for power play

STRP_DATA

R191

www.kythuatvitinh.com(3) NBHT_REFCLKP (3) NBHT_REFCLKN

I

PM

11/01 exchange LVDS_PWM /LVDS_BLONINT_LVDS_DIGON (19) L_BKLT_CTRL (19) INT_LVDS_BLON (19)

+1.1V_NB

4.7K_4 R184

4.7K_4 R200

I

CLOCKs

(3) EXT_NB_OSC

R210 R194

NB_REFCLK_P NB_REFCLK_N

E11 F11 T2 T1

REFCLK_P/OSCIN(OSCIN) REFCLK_N(PWM_GPIO3) GFX_REFCLKP GFX_REFCLKN

NBGFX_CLKP NBGFX_CLKN

I/O I/O

LVDS_DIGON(PCE_TCALRP) LVDS_BLON(PCE_RCALRP) LVDS_ENA_BL(PWM_GPIO2)

E9 F7 G12

(3) (3) (3) (3) (3) (3)

NBGFX_CLKP NBGFX_CLKN NBGPP_CLKP NBGPP_CLKN SBLINK_CLKP SBLINK_CLKN

NBGPP_CLKP NBGPP_CLKN

U1 U2

GPP_REFCLKP GPP_REFCLKN

SBLINK_CLKP SBLINK_CLKN

C

V4 V3 A9 B9 B8 A8 B7 A7

GPPSB_REFCLKP(SB_REFCLKP) GPPSB_REFCLKN(SB_REFCLKN) I2C_DATA I2C_CLK DDC_DATA/AUX0N(NC) DDC_CLK/AUX0P(NC) AUX1P(NC) AUX1N(NC) STRP_DATA RSVD AUX_CAL(NC)

*10K/F_4

+3V

R196

2.2K_4

(19) INT_LVDS_EDIDDATA (19) INT_LVDS_EDIDCLK (20) SDVO_CTRLDATA (20) SDVO_CTRLCLK

INT_LVDS_EDIDDATA INT_LVDS_EDIDCLK IV_HDMI_DDCDATA IV_HDMI_DDCCLK T108 T109

MIS.

TMDS_HPD(NC) HPD(NC)

D9 D10 D12

TMDS_HPD0 TMDS_HPD1

R205 [email protected]_4 0_4

TMDS_HPD#

(20)

T39

RS740_DFT_GPIO1

TVCLKIN(PWM_GPIO5)

SUS_STAT#_NB R_NB_THRMDA R_NB_THRMDC

R211

SUS_STAT# (14)

(36) +NB_CORE_ON

R201

0_4 STRP_DATA

B10 G11

THERMALDIODE_P THERMALDIODE_N TESTMODE

AE8 AD8

T89 T90

D13 TEST_EN R203 1.82K/F_4

R252 *3K_4

selects Loading of straps from EPROM 1 : use default vaule , default 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RX780 --RS780_AUX_CAL RS780 -- SUS_ATAT

T107

RS780_AUX_CAL

C8

RS780(RX780)

RX780RS780_AUX_CAL R468 *3K_4 +3V L23 BLM18PG221SN1D

BLM18PG221SN1D +3V_AVDD_NB +1.1V_NB +1.1V_PLLVDD L22 C192 2.2U/6.3V_6 +1.8V

1/17 RX781 connect to GND C104,C110,C646,C98,C136,C103,C118 change to CS00003J951

AVDD-DAC Analog not applicable to RX780

BLM18PG221SN1D

C172 10U/6.3V_6

B

Enables Debug Bus acess through memory T/O pads and GPIO. 1 : Enable RX780 , Default 0 : Disable RX780

RX780 Reserved only

PLLVDD - Graphics PLL not applicable to RX780

+1.8V_VDDLTP18_NB L44 C173 2.2U/6.3V_6

+1.8V +1.8V L27 BLM18PG221SN1D C236 10U/6.3V_8 +1.8V_PLLVDD18 R197 0_6 +1.8V_AVDDDI_NB C162 2.2U/6.3V_6 BLM18PG221SN1D

VDDLTP18 - LVDS or DVI/HDMI PLL not applicable to RX780B

AVDDI-DAC Digital not applicable to RX780L24

BLM21PG221SN1D +1.8V_VDDLT_18_NB

C175 22U/6.3V_8

C215

C207 0.1U/10V_4

1/17 RX781 no stuff them L2,L12,C124,L52,R76,L17,L51,L10,C115VDDLT18 - LVDS or DVI/HDMI digital not applicable to RX780R218 *0_6 +VDDG_NB R217 *0_6

Enables Debug Bus acess through memory T/O pads and GPIO. 1 : Enable RS780 , Default 0 : Disable RS780 (RS780 use VSYNC#)

PLLVDD18 - Graphics PLL not applicable to RX780

+1.8V_AVDDQ_NB L29 C246 2.2U/6.3V_6

4.7U/6.3V_6

RS780INT_VSYNC R462 R465 3K_4 *3K_4

AVDDQ-DAC Bandgap Reference not applicable to RX780

11/4 no stuff for RS780M/MC+3V

+1.8V

VDDA18PCIEPLL -PCIE PLL

1/31 voltage leakage issue remove Q5,Q3,R83,R80,R97 stuff R88,R77Q18 *BSS138_NL/SOT23

RX780 +1.8V+1.8V +VDDG_NB +3V

Indicates if memory Side port is available or not 0: available RS780 , Default 1: Not available RS780 ( RS780 use HSYNC#)

RS780INT_HSYNC R464 R467 3K_4 *3K_4 +3V

L28 BLM18PG221SN1D

20mils width +1.8V_VDDA18PCIEPLL R215 *4.7K_4 3 NB_LDT_STOP# 2

RS780

C240 2.2U/6.3V_6

(4,13) CPU_LDT_STOP#

1

L43 +3V *BLM21PG221SN1D +3V_VDLT33_NB C540 *2.2U/6.3V_6A

R219

0_4 +VDDG_NB +1.8V R209 *4.7K_4 NB_ALLOW_LDTSTOP

VDDA18HTPLL -HT LINK PLLA

RS780

10/19 RS780M Databook rev 1.01 define High disable

L26 BLM18PG221SN1D

20mils width +1.8V_VDDA18HTPLL Q17 *BSS138_NL/SOT23 C225 2.2U/6.3V_6 (4) CPU_LDT_REQ# R214 0_4 1

VDDLT33 - LVDS or DVI/HDMI ANALOG RS740 only

2

3

Quanta Computer Inc.(13) ALLOW_LDTSTOP R208 0_4 Size Date:5 4 3 2

RS780

PROJECT : ZK3Document Number

RS740/RS780-SYSTEM I/F 3/5Monday, August 18, 20081

Rev 1A 43

Sheet

11

of

5

4

3

2

1

U26F

RX780/RS780 POWER DIFFERENCE TABLEPIN NAME VDDHT VDDHTRX VDDHTTX VDDA18PCIE VDDG18 VDD18_MEM

12RS780+1.1V +3.3V +1.8V +1.8V +1.1V +1.8V +1.8V +1.8V +1.8V +1.8V NCD

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

RX780+1.1V +1.1V +1.2V +1.8V +1.8V NC +1.1V +1.1V NC NC NC

RS780+1.1V +1.1V +1.2V +1.8V +1.8V +1.8V +1.1V +1.1V +1.8V/1.5V +3.3V +1.8V

PIN NAME IOPLLVDD AVDD AVDDDI AVDDQ PLLVDD PLLVDD18 VDDA18PCIEPLL VDDA18HTPLL VDDLTP18 VDDLT18 VDDLT33

RX780NC NC NC NC NC NC +1.8V +1.8V NC NC NC

D

PART 6/6

VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34

A25 D23 E22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19 W22 W24 W25 Y21 AD25

L12 M14 N13 P12 P15 R11 R14 T12 U14 U11 U15 V12 W11 W15 AC12 AA14 Y18 AB11 AB15 AB17 AB19 AE20 AB21 K11

C

VDDHT - HT LINK digital I/O for RX780/RS780

VDDHTRX - HT LINK RX I/O for RX780/RS780

www.kythuatvitinh.com+1.1V_NB

+1.1V 2A for RS780ML8 BLM21PG221SN1D

0.6A

C99 330U/2.5_3528

0.45A

L45 BLM21PG221SN1D C559 330U/2.5_3528 C153 0.1U/10V_4

+1.2V 2A for RS780M+SB700L39 +1.2V BLM21PG221SN1D

0.5AC456 4.7U/6.3V_6 C135 0.1U/10V_4 C110 0.1U/10V_4

12/14 del L15 stuff L36 for A12

B

+1.8V 1A for RS780M+SB700+1.8V BLM21PG221SN1D L9

POWER

+1.35V for A1-1 chip bug , A1-2 can remove

VDDHTTX - HT LINK TX I/O for RX780/RS780

600mAC108 4.7U/6.3V_6 C111 4.7U/6.3V_6 C117 0.1U/10V_4 C113 0.1U/10V_4

VDDA18PCIE PCIE TX stage I/O for RX780/RS780

VDD18 - RS780 I/O transform

+1.8V

+1.8V

VDD18_MEM For UMA RS780 only Not applicable to RX780 memory I/O transformA

5

GROUND GROUNDU26E +1.1V_VDDHT C141 0.1U/10V_4 C131 0.1U/10V_4 C98 0.1U/10V_4

VDDPCIE VDDC VDD_MEM VDDG33 IOPLLVDD18

VDDPCIE - PCIE-E Main power0_8 +1.1V_NB

C

J17 K16 L16 M16 P16 R16 T16 H18 G19 F20 E21 D22 B23 A23

VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

PART 5/6

+1.1V_VDDHTRX C553 0.1U/10V_4 C548 0.1U/10V_4

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7 VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13 VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15 VDDG18_1(VDD18_1) VDDG18_2(VDD18_2) VDD18_MEM1(NC) VDD18_MEM2(NC)RS780(RX780)

+1.2V_VDDHTTX C116 0.1U/10V_4 C128 0.1U/10V_4

AE25 AD24 AC23 AB22 AA21 Y20 W 19 V18 U17 T17 R17 P17 M17 J10 P10 K10 M10 L10 W9 H9 T10 R10 Y9 AA9 AB9 AD9 AE9 U10 F9 G9 AE11 AD11

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8 VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

+1.1V_VDD_PCIE

0.7A

R96

C103 0.1U/10V_4

C142 0.1U/10V_4

C125 1U/10V_4

C187 1U/10V_4

C169 4.7U/6.3V_6

2/13 EMI stuff C804~C807 for +NB_CORE

VDDC - Core Logic power

+1.8V_VDDA18PCIE C134 0.1U/10V_4 C122 0.1U/10V_4

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16 AE10 AA11 Y11 AD10 AB10 AC10 H11 H12

7A+NB_CORE C123 0.1U/10V_4 C145 0.1U/10V_4 C114 0.1U/10V_4 C118 C444 0.1U/10V_4 10U/6.3V_8 C87 0.1U/10V_4 C459 0.1U/10V_4 C455 0.1U/10V_4 C453 0.1U/10V_4

B

C130 0.1U/10V_4

C140 0.1U/10V_4

C129 0.1U/10V_4

C443 10U/6.3V_8

10/18 follow AMD design guide 1.0 VDD_MEM For UMA RS780 only Not applicable to RX780 memory I/O transformR103 R102 *0_6 0_6 +1.8V

1.8V(0.15A)+1.8V_VDD_MEM

R180

0_6

0.005AC161 1U/10V_4 +1.8V_VDDG18_NB +1.8V_VDD18_MEM

VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC) VDDG33_1(NC) VDDG33_2(NC)

R372

0_6

0.005AC458 *1U/10V_4

+3V_VDDG33 C156 0.1U/10V_4

R195 C217 0.1U/10V_4

RS780 0_6

3.3V(0.03A)+3V

VDD33 - 3.3V I/O Not applicable to RX780

1/17 RX781 no stuff them R484A

1/17 RX781 connect to GND C616 change to CS00002JB38

Quanta Computer Inc.PROJECT : ZK3Size Date:4 3 2

Document Number

RS740/RS780-POWER5/5Monday, August 18, 2008 Sheet1

Rev 1A of 43

12

5

4

3

2

1

2/4 reserve C800 PLTRST#R514 R491 33_4 33_4 U28A *0.1U/10V_4 (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) PCIE_SB_NB_RX0P PCIE_SB_NB_RX0N PCIE_SB_NB_RX1P PCIE_SB_NB_RX1N PCIE_SB_NB_RX2P PCIE_SB_NB_RX2N PCIE_SB_NB_RX3P PCIE_SB_NB_RX3N PCIE_NB_SB_TX0P PCIE_NB_SB_TX0N PCIE_NB_SB_TX1P PCIE_NB_SB_TX1N PCIE_NB_SB_TX2P PCIE_NB_SB_TX2N PCIE_NB_SB_TX3P PCIE_NB_SB_TX3N R424 R423 C479 C480 C474 C473 C481 C482 C471 C472 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 A_RST#_SB A_RX0P_C A_RX0N_C A_RX1P_C A_RX1N_C A_RX2P_C A_RX2N_C A_RX3P_C A_RX3N_C

C576 PLTRST#

(11) NB_PLTRST# (18,21,23,27,28,32) PLTRST#

13N2 V23 V22 V24 V25 U25 U24 T23 T22 U22 U21 U19 V19 R20 R21 R18 R17 T25 T24

SB700A_RST# PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_CALRP PCIE_CALRN PCIE_PVDD PCIE_PVSS

PCI CLKS

Part 1 of 5

D

To RS780

PLACE THESE PCIE AC COUPLING CAPS CLOSE TO U600

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5/GPIO41

P4 P3 P1 P2 T4 T3

PCI_CLK0_R PCI_CLK2_R PCI_CLK3_R PCI_CLK4_R PCI_CLK5_R R506 R508 R234 R485

T71 22_4 22_4 22_4 22_4 T59 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 (17) (17) (17) (17)

A11 default PCICLK5 A12 default GPIO41PE_GPIO1 R228 R227 SB_GPIO65 R216 8.2K_4 *8.2K_4 10K_4

D

+3V

PCIE_NB_SB_TX0P PCIE_NB_SB_TX0N PCIE_NB_SB_TX1P PCIE_NB_SB_TX1N PCIE_NB_SB_TX2P PCIE_NB_SB_TX2N PCIE_NB_SB_TX3P PCIE_NB_SB_TX3N 562/F_4 2.05K/F_4 PCIE_CALRP_SB PCIE_CALRN_SB

PCI EXPRESS INTERFACE

PCIRST# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1# REQ2# REQ3#/GPIO70 REQ4#/GPIO71 GNT0# GNT1# GNT2# GNT3#/GPIO72 GNT4#/GPIO73 CLKRUN# LOCK# INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36 LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/GNT5#/GPIO68 BMREQ#/REQ5#/GPIO65 SERIRQ RTCCLK INTRUDER_ALERT# VBAT

N1

PCIRST#_L

R520

33_4

PCIRST#

PCIRST# (23)

2

C

A_RST#_SB

R281 1K_4

K23 K22

PCI INTERFACE

www.kythuatvitinh.com+1.2V L13 BLM18PG221SN1D +1.2V_PCIE_PVDD

+1.2V_PCIE_VDDR

P24 P25

PCIE_PVDD-- PCIE PLL POWER

40mA

C484 10U/6.3V_8

C155 1U/10V_4

B test

(3) SBSRC_CLKP (3) SBSRC_CLKN

SBSRC_CLKP SBSRC_CLKN

N25 N24

PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN NB_DISP_CLKP NB_DISP_CLKN NB_HT_CLKP NB_HT_CLKN

T98 T18 T93 T92 T35 T19 T91 T36 T38 T41 T27 T31 T17 T25

NB_DISP_CLKP NB_DISP_CLKN NB_HT_CLKP NB_HT_CLKN CPU_HT_CLKP CPU_HT_CLKN

M24 M25 P17 M18 M23 M22 J19 J18 L20 L19 M19 M20 N22 P22 L18

100MHZ

CPU_HT_CLKP CPU_HT_CLKN SLT_GFX_CLKP SLT_GFX_CLKN GPP_CLK0P GPP_CLK0N GPP_CLK1P GPP_CLK1N GPP_CLK2P GPP_CLK2N GPP_CLK3P GPP_CLK3N 25M_48M_66M_OSC 25M_X1

SLT_GFX_CLKP SLT_GFX_CLKN GPP_CLK0P GPP_CLK0N GPP_CLK1P GPP_CLK1N GPP_CLK2P GPP_CLK2N GPP_CLK3P GPP_CLK3N

CLOCK GENERATOR

B

T32 T13 RTC_X1 Y5 T23

3

2(3) CLK_14M_SB R642 *0_4

U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 AD23 Y2 AD24 AA2 AD25 AB4 AD26 AA1 AD27 AB3 AD28 AB2 AD29 AC1 AD30 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 PORT_C# T49 AB6 AD2 T125 AE4 T124 AD5 AC6 PE_GPIO1 T123 AE5 CLKRUN#_R AD6 LOCK# V5 AD3 AC4 AE2 AE3 G22 E22 H24 H23 J25 J24 H25 H22 AB8 AD7 V15 C3 C2 B2INTE# INTF# INTG# INTH#

All the PCI bus has build-in Pull-UP/Down resistors

Maybe can remove

RTCD47

VCCRTC

+3VPCU

CH500H-40

D46 CH500H-40

1

C605

C607

G3

1U/10V_4

R532 1K_6

*SHORT_PAD R543

0.1U/10V_4C

AD23 AD24 AD25 AD26 AD27 AD28

(17) (17) (17) (17) (17) (17)

0_4

T156 T157

CN34

1 2

1 2RTC_BAT 53261-0210-2P-L DFHD02MS784

+5VPCU

R571+R667 = (5V - 0.2V-2V)/0.2mA = 14kR524 Q47 VCCRTC_33 MMBT3904 1 16K/F_4

R529 68.1K/F_4 T119 T127 R531 T56 150K/F_6 R476 0_4 CLKRUN# (32) T129B

J21

4R483

132.768KHZ

RTC_X2

(For SB A13)T30

T58 T126 R148 R427 22_4 22_4 LAD0 LAD1 LAD2 LAD3 LFRAME# T28 T61 T50 SERIRQ (32) (23,32) (23,32) (23,32) (23,32) (23,32)

T128

J20

25M_X2

*20M_6

R499 C570 18p/50V_4

20M_6 C579 18p/50V_4 RTC_X2 +1.8V R141 *1K_4

X1

RTC XTAL

RTC_X1

A3

B3

X2

LPC_CLK0 LPC_CLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0#_SB LDRQ1#_SB SB_GPIO65 SERIRQ

PCLK_DEBUG (17,23) PCLK_591 (17,32)

4/14 R527, change from 2k to 0. R524 change from 2K to 16K R529,change from 6.8k to 68.1k R531 change form 15k to 150k

A

(11) ALLOW_LDTSTOP (4) CPU_PROCHOT_SB# (4) CPU_PWRGD (4,11) CPU_LDT_STOP# (4) CPU_LDT_RST#

RTC

CPU

ALLOW_LDTSTOP CPU_PROCHOT_SB# CPU_PWRGD CPU_LDT_STOP# CPU_LDT_RST#

F23 F24 F22 G25 G24

ALLOW _LDTSTP PROCHOT# LDT_PG LDT_STP# LDT_RST#SB700

LPC

RTC_CLK INTRUDER_ALERT# R242 C255 0.1U/10V_4

RTC_CLK (17) T132 510_4 VCCRTC VCCRTCA

1/31 voltage leakage remove R349

IC CTRL(528P) SB700 A11(218S7EALA11FG) P/N : AJALA110T00


Document Number

2

SB700-PCIE/PCI/CPU/LPC 1/4Monday, August 18, 2008 Sheet1

Rev 1A 43

13

of

5

4

3

2

1

+3V_S5 R487 R241 R245

NC only ,Can't be install*2.2K_4 *2.2K_4 *2.2K_4 SB_TEST0

11/01 chagne +3VSUS to +3V_S5SB_TEST1 SB_TEST2 (32) SUSB# (32) SUSC# (32) DNBSWON# (17) SB_PWRGD_IN (11) SUS_STAT# T136 T135 T51 RI# SLP_S2 SUSB# SUSC# DNBSWON# SB_PWRGD_IN SUS_STAT# SB_TEST2 SB_TEST1 SB_TEST0 GATEA20 RCIN# EC_SCI# KBSMI# SYS_RST# PCIE_WAKE# SWI# CPU_THERMTRIP# WD_PWRGD RSMRST# E1 E2 H7 F5 G1 H2 H1 K3 H5 H4 H3 Y15 W15 K4 K24 F1 J2 H6 F2 J6 W14 D3

U28D

14SB700Part 4 of 5C8 G8 CLK_48M_USB USB_RCOMP_SB R204 CLK_48M_USB (3) 11.8K/F_6 R212 *10_6 USB_FSD13P USB_FSD13N E6 E7 F7 E8 H11 J10 E11 F11 A11 B11 C10 D10 G11 H12 E12 E14 USB_FSD13P USB_FSD13N USB_FDS12P USB_FSD12N T53 T55 T54 T48 USBP11+ (23) USBP11- (23) USBP10+ (31) USBP10- (31) USBP9+ (28) USBP9- (28) USBP8+ (27) USBP8- (27) USBP7+ (31) USBP7- (31) USBP6+ (22) USBP6- (22) USBP5+ (30) USBP5- (30) USBP4+ (30) USBP4- (30) USBP3+ (30) USBP3- (30) USBP2+ (19) USBP2- (19) USBP1+ (23) USBP1- (23) USBP0+ (30) USBP0- (30)D

+3V_S5D

R501 +3V SCL0/SDATA0 R451 R447

*10K/F_4 SWI#

10/31 add newcard DET#

is 3V tolerance AMD datasheet define it2.2K_4 2.2K_4 PCLK_SMB PDAT_SMB

Clock gen /DDR2 /MINI CARD/NEW CARD

(32) (32) (32) (32)

GATEA20 RCIN# EC_SCI# KBSMI# T133

(21,23,32) PCIE_WAKE# T131 (4) CPU_THERMTRIP# (17) WD_PWRGD

PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S2/GPM9# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST2 TEST1 TEST0 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8# BLINK/GPM6# SMBALERT#/THRMTRIP#/GEVENT2# NB_PWRGD RSMRST#

CLK_48M_USB

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

USB MISC

USB_RCOMP

USB 1.1

USB_FSD12P USB_FSD12N USB_HSD11P USB_HSD11N USB_HSD10P USB_HSD10N USB_HSD9P USB_HSD9N USB_HSD8P USB_HSD8N

C249 *10p/50V_4

for EMI To TV To Finger Printer To CARD READER To New Card DOCKING

+3V_S5

SCL1/SDATA1 is 3V/S5 tolerance AMD datasheet define itR502 R503 2.2K_4 2.2K_4 SB_SMBCLK1 SB_SMBDATA1

(32)

RSMRST#

+3V_S5

USB 2.0

SCL2/SDATA2 is 3V/S5 tolerance AMD datasheet define itR426 R394 2.2K_4 2.2K_4 SB_SCLK2 SB_SDATA2

+3VC

3/19 Without Side-port NUR488 G2 2 *4.7K_4 SUS_STAT#

*SHORT_ PAD1

www.kythuatvitinh.comT103 (3,27) NEW_CLKREQ# T14 (25) PCSPK (3,7,20,21,23,27) PCLK_SMB (3,7,20,21,23,27) PDAT_SMB (18) PE_RESET_MXM# T44 T134 T37 T52 R455 R457 R170 USB_HSD6P USB_HSD6N USB_HSD5P USB_HSD5N USB_HSD4P USB_HSD4N USB_HSD3P USB_HSD3N USB_HSD2P USB_HSD2N USB_HSD1P USB_HSD1N USB_HSD0P USB_HSD0N

T100 T99 T42

G-sensor SATA_IS1 SATA2_HOTPLUG 0_4 0_4 0_4 PCLK_SMB PDAT_SMB SB_SMBCLK1 SB_SMBDATA1 DDC1_SCL_GPIO9 DDC1_SDA_GPIO8 LOW_DET

AE18 AD18 AA19 W17 V17 W20 W21 AA18 W18 K1 K2 AA20 Y18 C1 Y19 G5

SATA_IS0#/GPIO10 CLK_REQ3#/SATA_IS1#/GPIO6 SMARTVOLT/SATA_IS2#/GPIO4 CLK_REQ0#/SATA_IS3#/GPIO0 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# SCL1/GPOC2# SDA1/GPOC3# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 LLB#/GPIO66 SHUTDOWN#/GPIO5 DDR3_RST#/GEVENT7#

USB_HSD7P USB_HSD7N

To Bluetooth

C12 D12 B12 A12

To M/B USB To M/B USB

GPIO

G12 G14 H14 H15 A13 B13 B14 A14

To M/B USB/ESATA To Camera To WLAN

C

10/26 modify it 11/06 check itD42 1

1

SYS_RST#

(4,32) CPU_MEMHOT#

CH501H-40PT 2

USB OC

T114 T112 (32) USBOC#3 T62 (27) (30) NEW_DET# USBOC#0

CPU_MEMHOT#_IN GPM5# *BAS316 R207

D41

1/31 NEW_DET# change from GEVEN5# to GPM1#

0_4

B9 B8 A8 A9 E5 F8 E4

To AzaliaACZ_SDOUT R519 R251 33_4 33_4 C268

12/7 add D57,D58 to avoid voltage leakageACZ_SDOUT_MDC (25) ACZ_SDOUT_AUDIO (25) *10p/50V_4 (17) ACZ_RST# T137 T69 T66

HD AUDIO

D26 *BAS316 ACZ_BCLK ACZ_SDOUT ACZ_SDIN0_R ACZ_SDIN1_R ACZ_SDIN2_R ACZ_SYNC ACZ_RST# R238 R489 R240

USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GPM5# USB_OC4#/IR_RX0/GPM4# USB_OC3#/IR_RX1/GPM3# USB_OC2#/GPM2# USB_OC1#/GPM1# USB_OC0#/GPM0# AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO42 AZ_SDIN1/GPIO43 AZ_SDIN2/GPIO44 AZ_SDIN3/GPIO46 AZ_SYNC AZ_RST# AZ_DOCK_RST#/GPM8#

To M/B USB

ACZ_SYNC

R517 R244

33_4 33_4 C271

ACZ_SYNC_MDC (25) ACZ_SYNC_AUDIO (25) *10p/50V_4

HD audio interface is 3.3V voltage

INTEGRATED uC

M1 M2 J7 J8 L8 M3 L6 M4 L5

IMC_GPIO8 IMC_GPIO9 IMC_PWM0/IMC_GPIO10 SCL2/IMC_GPIO11 SDA2/IMC_GPIO12 SCL3_LV/IMC_GPIO13 SDA3_LV/IMC_GPIO14 IMC_PWM1/IMC_GPIO15 IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17 IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25 IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41

A18 B18 F21 D21 F19 E20 E21 E19 D19 E18 G20 G21 D25 D24 C25 C24 B25 C23 B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18

10/18SB_SCLK2 SB_SDATA2 SB_SCLK3 SB_SDATA3 SB_GPIO16 SB_GPIO17 SB_GPIO16 (17) SB_GPIO17 (17)

USB swap for layout route

SB_SCLK3 (4) SB_SDATA3 (4)

SPI/LPC define

*10K_4

*10K_4

*10K_4

B

B

C583 R511 R248 BK1005HM121-T_4 BK1005HM121-T_4 C270 R505 R490 R246 *10K_4 33_4 33_4

22p/50V_4

ACZ_BCLK

22p/50V_4

+1.8V

R428 *10K_4

ACZ_RST#

ACZ_RST#_MDC (25) ACZ_RST#_AUDIO (25,26)

AMD Suggestion 3/29 modify From 20K change to 10K

D22 E24 E25 D23

IMC_GPIO4 IMC_GPIO5 IMC_GPIO6 IMC_GPIO7

ACZ_SDIN1_R ACZ_SDIN0_R

R269 R623

22_4 22_4

ACZ_SDIN1 (25) ACZ_SDIN0 (25)

SB700

+3V

12/21EMI change R241from 33 to BK1005HM121-T stff C309 22p +3VR171 R165

A

10K_4 LOW_DET R167 *1K_4 LOW_DET

10K_4 SATA2_HOTPLUG

INTEGRATED uC

BIT_CLK_MDC (25) BIT_CLK_AUDIO (25)

H19 H20 H21 F25

IMC_GPIO0 IMC_GPIO1 SPI_CS2#/IMC_GPIO2 IDE_RST#/F_RST#/IMC_GPO3

A

High : Main Strem Low : Low Cost


SB700-ACPI/GPIO/USB 2/4Monday, August 18, 20081

Rev 1A of 43

Sheet

14

5

4

3

2

5

4

3

2

1

SATA PORT 0,1,2,3 can support AHCI mode

PLACE SATA AC COUPLING CAPS CLOSE TO SB700

15U28B

SATA1D

(24) SATA_TXP0 (24) SATA_TXN0

C567 C564

0.01U/16V_4 0.01U/16V_4

SATA_TXP0_R SATA_TXN0_R C206 C212 0.01U/16V_4 0.01U/16V_4

AD9 AE9SATA_RXN0_C AB10 SATA_RXP0_C AC10

SB700SATA_TX0P SATA_TX0N SATA_RX0N SATA_RX0P SATA_TX1P SATA_TX1N SATA_RX1N SATA_RX1P SATA_TX2P SATA_TX2N SATA_RX2N SATA_RX2P SATA_TX3P SATA_TX3N SATA_RX3N SATA_RX3P SATA_TX4P SATA_TX4N

MB ID Selection TableIDE_IORDY IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_DACK# IDE_DRQ IDE_IOR# IDE_IOW # IDE_CS1# IDE_CS3# IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30 AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24 AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23

Part 2 of 5

Board ID NEW CARD CARD BUS CCFL Panel LED Panel W/ MXM W/O MXM W/ S-VIDEO W/O S-VIDEO W/ HDMI W/O HDMI

ID4

ID3

ID2

ID1

ID0 H LD

(24) SATA_RXN0 (24) SATA_RXP0

SATA2


C562 C558

0.01U/16V_4 0.01U/16V_4

SATA_TXP1_R SATA_TXN1_R C547 C552 0.01U/16V_4 0.01U/16V_4

AE10 AD10SATA_RXN1_C AD11 SATA_RXP1_C AE11

H L H L H L H L



C551 C546

0.01U/16V_4 0.01U/16V_4

SATA_RXN2_C AE12 SATA_RXP2_C AD12

SERIAL ATA

2/22 change SATA ODD from port3 to port4 (solve ODD post detect fail)

AD13 AE13 AB14 AC14 AE14 AD14 AD15 AE15 AB16 AC16 AE16 AD16 V12 Y12

ATA 66/100/133

E-SATA


C238 C239

0.01U/16V_4 0.01U/16V_4

SATA_TXP2_R SATA_TXN2_R

AB12 AC12

ODD

C

www.kythuatvitinh.com(24) SATA_TXP4 (24) SATA_TXN4 C541 C536 0.01U/16V_4 0.01U/16V_4 SATA_TXP4_R SATA_TXN4_R (24) SATA_RXN4 (24) SATA_RXP4 C526 C531 0.01U/16V_4 0.01U/16V_4 T45 T43 SATA_RXN4_C SATA_RXP4_C SATA_TXP5_C SATA_TXN5_C

MB IDBOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4

+3V

SATA_RX4N SATA_RX4P SATA_TX5P SATA_TX5N

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4

R441 R125 R138 R135 R130

*1K_4 *1K_4

R442 R124 R137 R134 R129

10K_4 10K_4

[email protected]_4 *1K_4 *1K_4

[email protected]_4 10K_4 10K_4

R193

1K/F_4

SATA_RBIAS_PN SATA_X1 SATA_X2

SATA_CAL SATA_X1 SATA_X2

SPI ROM

SATA PORT 4,5 are only support IDE mode

R361

T101 T102

SATA_RXN5_C SATA_RXP5_C

SATA_RX5N SATA_RX5P

SPI_DI/GPIO12 SPI_DO/GPIO11 SPI_CLK/GPIO47 SPI_HOLD#/GPIO31 SPI_CS#/GPIO32 LAN_RST#/GPIO13 ROM_RST#/GPIO14

G6 D2 D1 F4 F3

C

U15 J1 M8 M5 M7 P5 P8 R8 C6 B6 A6 A5 B5 A4 B4 C4 D4 D5 D6 A7 B7

ROM_RST#

PLACE SATA_CAL RES VERY CLOSE TO BALL OF SB700

AA12 W 11 AA11 W 12

T47 T130

Mount R441 and Unmout R442 for non IR SKU

(29)

SATA_LED#

SATA_LED#

SATA_ACT#/GPIO67

FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49

SB_GPIO3 SB_GPIO48 SB_GPIO49 SB_FANTACH0 SB_FANTACH1 PORT_80_PWR_DWN TEMPIN0 TEMPIN1 MB_THRMDA_SB TEMPIN3_GPIO64 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7

T151 T152 MXM_PRESENT# (18) T70 T72 T67 T121 T117 T116 THERM_ALERT# (4)

PLVDD_SATA-R361 IS 1K 1% FOR 25MHz SATA PLL XTAL, 4.99K 1% FOR 100MHz POWER

+1.2V_PLLVDD_SATA +3V_XTLVDD_SATA

PLLVDD_SATA XTLVDD_SATA

SATA PWR

NOTE:

FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52 TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63 TEMPIN3/TALERT#/GPIO64 VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60

10/18 AMD suggest to connect to GND

INTERNAL CLOCK

XTLVDD_SATA-- SATA crystal powerC183 SATA_X1 27p/50V_4

HW MONITOR

0_4 R477 T122 T120 T57 T60 T63 T64 T115 T118

2

Y2 25MHZ R169 10M_6 SATA_X2

B

C182 22p/50V_4

1

+3V

B

AVDDSB700

F6 G7

5mA

AVDD--H/W monitor Analog powerL31 0_6

+3V_VDD_HWM C256 0.1U/10V_4

AVSS

C257 EMI FILTER CHIP BLM18PG221SN1D(220,1.4A) 2.2U/6.3V_6

+1.2V

( 1.2V @ 60mA) +1.2V_PLLVDD_SATA1

77mA

2/13 EMI stuff C375,C366 for SB HW MONITOR

L30 BLM18PG221SN1D

2

C237 2.2U/6.3V_6

C231 0.1U/10V_4

C248 22U/6.3V_8

+3V

1mA( 3.3V @ 1.2mA)+3V_XTLVDD_SATA

L25 BLM18PG221SN1DA A

C214 1U/10V_4

Place near ball


SB700-SATA/IDE/HWM/SPI 3/4Monday, August 18, 2008 Sheet1

Rev 1A 43

15

of

5

4

3

2

5

4

3

2

1

PLACE ALL THE DECOUPLING CAPS ON THIS SHEET CLOSE TO SB AS POSSIBLE. VDD-- S/B CORE power+3.3V_SB_R +3V R509 2 0_8 1 U28C +1.2V_VCC_SB_R

12/14 del R234 stuff R235 for A12

16SB700VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24 P23 R16 R19 T17 U18 U20 V18 V20 V21 W 19 W 22 W 24 W 25 L17D

VDDQ--3.3V I/O power

0.8A1

100u/6.3V_3528

PCI/GPIO I/O

2

2

2

2

2

2

2

2

2

2

2

2

D

2

C574 10U/6.3V_8

C244 1U/10V_4

C250 1U/10V_4

C230 1U/10V_4

C234 1U/10V_4

C180 1U/10V_4

C252 1U/10V_4

CORE S0

C577

+

1.8V : FLASH MEMORY MODE(DEFAULT) 3.3V: IDE MODE+VDD33_18

L9 M9 T15 U9 U16 U17 V8 W7 Y6 AA4 AB5 AB21

SB700VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12

1

Part 3 of 5

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

L15 M12 M14 N13 P12 P14 R11 R15 T16

604mA1 1 1 1 1

2

R162 1 0_8

+1.2V

U28E

1

1

1

1

1

1

C205 C224 C195 0.1U/10V_4 0.1U/10V_4 1U/10V_4

C204 1U/10V_4

C216 10U/6.3V_8

+1.2V_CKVDD

CKVDD_1.2V-- Internal clock Generator I/O power

IDE/FLSH I/O

+1.8V +3V

R146 R147

2 2

1 *0_8 1 1 1 1 1 1 0_8

0.45A

CLKGEN I/O

Y20 AA21 AA22 AE25

10/18 change to +1.8V

2

2

2

2

2

2

2

2

0.1U/50V_6

0.1U/50V_6

2008-MAR CHECK LIST CHANGE TO 3V because no IDE devicePCIE_VDDR--PCIE I/O power

+1.2V

A-LINK I/O

1

1

1

1

1

1

BLM18PG221SN1D

2

2

2

2

2

2

1

1

3.3V_S5 I/O

+1.2V_AVDD_SATA

AVDD_SATA--SATA phy power

+1.2V

L42

0.2A

SATA I/O

1

1

1

1

BLM18PG221SN1D

CORE S5

2

2

2

2

C539 22U/6.3V_8

C208 0.1U/10V_4

C222 0.1U/10V_4

C227 1U/10V_4

C213 1U/10V_4

AA14 AB18 AA15 AA17 AC18 AD17 AE17

AVDD_SATA_1 AVDD_SATA_4 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7

+1.2VALW_R

S5_1.2V--1.2V standby powerR249 2 0_6 1 +1.2V_S5

S5_1.2V_1 S5_1.2V_2

1

USB_PHY_1.2V_1 USB_PHY_1.2V_2+3V_AVDD_USB

A10 B10

0.2A+1.2V_USB_PHY_R

Date post:	14-Oct-2014
Category:	Documents
Author:	jose-a-lachiondo
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