Achieving Multipurpose Space Imaging with theARTEMIS Reconfigurable Payload Processor

Ian A. Troxel, Matthew Fehringer, Michael T. ChenowethSEAKR Engineering, Inc.6221 S. Racine CircleCentennial, CO 80111

303.790.8499{ian.troxel, matt.fehringer, mike.chenoweth}@seakr.com

Abstract The components that comprise the AdvancedResponsive Tactically Effective Military ImagingSpectrometer (ARTEMIS) payload processor, to bedeployed on the AFRL TacSat-3 satellite, provide a flexibleand high-performance platform upon which space imagingapplications can be deployed. The payload system consistsof an FPGA camera interface and processing board as wellas a G4-based single board computer among othercomponents. The combination of FPGA and general-purpose processor provides resources attuned to strike abalance between compute-intensive sensor data extractionprocessing and administrative tasks such as healthmonitoring and information downlink. This paper providesa description of the system design and highlights thesystem's performance and flexibility. 1 2

TABLE OF CONTENTS

1. INTRODUCTION................................ 12. ARTEMIS PROCESSOR ARCHITECTURE .............23. ARTEMIS PROCESSOR FLEXIBILITY ..................4

4.TACSAT-3 MISSION OVERVIEW...........................55. CONCLUSIONS................................ 7REFERENCES ........ ......................... 7BIOGRAPHIES ........ ........................ 7

1. INTRODUCTION

NASA and other space agencies have identified the need toimprove the processing capabilities onboard remote spaceplatforms to support the complexity of future spaceexploration missions [1]. Increasing amounts of datacollected coupled with limited downlink speeds makes theneed to process data in-situ critical. The US Air Force alsorecognizes the coming "data crunch" and sees increasingspacecraft processing performance as vital to the success offuture missions [2]. In addition to the need to improve rawcomputational performance, both military and civilian spaceagencies have determined spacecraft flexibility is key tomeeting divergent mission objectives with minimal cost andrisk. Multiuse payloads can support the needs of multipleusers while reducing non-recurring engineering andincreasing mission survivability.

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To meet flexibility and resilience objectives, someresearchers have chosen to develop adaptable software thatexecutes on fixed hardware resources. For example, power-aware computing is a straightforward software managementapproach whereby the prioritized processing requirementsof applications are matched against component power usageand reserves to optimize performance/Watt [3]. Thisapproach provides a simple means for multiple applicationsto share hardware resources but lacks flexibility and faulttolerance.

Environmentally Adaptive Fault Tolerant Computing [4] isanother software-based approach recently developed thatfocuses on mission fault tolerance along with resourcemanagement. The middleware deployed on these systemsmeasures and predicts the radiation environment in whichthe spacecraft is traveling, prioritizes mission requirementsbased on this data, and then deploys applications in amanner that optimizes fault tolerance versus performance[5]. While this approach provides an improvement insystem flexibility, board- and device-level hardwareredundancy was necessary to achieve an acceptable level offault tolerance in the deployed system [6]. A mixture ofsoftware mechanisms and hardware redundancy is likely tobe the best overall solution for most programs but limitingthe scope to which hardware is replicated is critical toavoiding unnecessary increases in weight, power, bulk, etc.

Several related projects have proposed new techniques thatallow spacecraft to adapt to emergent and changing missionrequirements by providing hardware flexibility and faulttolerance with limited redundancy. The so called FlexibleMission Spacecraft (FMS) concept has been proposed as ameans to reduce design re-engineering by promoting systemflexibility with minimal redundancy [7]. Some proposedFMS solutions focus on building plug-and-play subsystems[8] while others focus within the processing subsystem.The Adaptive Avionics Experiment (AAE) project, led byAFRL, focuses on the responsive space mission byproposing a design that includes a collection of signalprocessors whose input can be dynamically changed toreceive data from one of several sensor suites [9]. Genericsensor interfaces provide a means to easily tailor the basearchitecture to a specific mission's sensors. Though thesystem did not have a successful flight, the AAE designserved as a good first step toward an FMS in support ofresponsive space missions.

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Building on the AAE design, the Advanced ResponsiveTactically Effective Military Imaging Spectrometer(ARTEMIS) is another payload processing system that isdesigned for the FSM mission. ARTEMIS processorsupports application independent processing by couplingcompute-intensive Field-Programmable Gate Arrays(FPGAs) with a powerful PowerPC-based general-purposeprocessor. ARTEMIS' adaptable architecture providesflexibility when tailoring the system design to meet theneeds of various missions and allows for in-situreconfigurability to vastly improve system fault tolerance.The ARTEMIS payload is scheduled to launch on theAFRL TacSat-3 mission in 2008.

This paper outlines the ARTEMIS payload processor andhighlights its performance and flexibility. The organizationof the remainder of the paper is as follows. Section 2describes the ARTEMIS architecture and Section 3highlights the flexibility of the ARTEMIS processor. Adiscussion of plans to deploy ARTEMIS on the upcomingTacSat-3 mission is given in Section 4 and Section 5concludes the paper.

2. ARTEMIS PROCESSOR ARCHITECTURE

The ARTEMIS processor is an AFRL funded project thatseeks to develop a general-purpose signal processingplatform that pushes the boundaries of payloadperformance, adaptability and survivability.

The key system objectives proposed by the programinclude:

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Support scalable processing from 9 to 400 GFLOPSOn-orbit system reconfigurabilityIncorporation of open standardsSEE and TID tolerantFlexible I/0 architecture to ease mission tailoringUser interface supporting rapid development

The main components of the ARTEMIS processor systemarchitecture are shown in Figure 1. Interfaces betweencomponents within the ARTEMIS processor include powerplane, Compact Peripheral Component Interconnect (cPCI)and Spacewire for command and data handling instructions(C&DH), and high speed serial to support fast dataprocessing. The ARTEMIS processor interacts with otherspacecraft components via several external interfacesincluding SV 28V power, Spacewire and RS422 forspacecraft C&DH, Gigabit Ethernet (GigE) for uplinkcommands and downlink data, and sensor connections thatcan interface via a wide array of standards using adaptablemezzanine connectors. Several custom interfaces have beendeveloped and interfaced through the adaptable sensorconnector including LVDS camera links for a HyperspectralImager (HSI) and a High Resolution Imager (HRI), otherdigital interfaces for a mass data storage board, and a focusmechanism, as well as an analog input for a position sensor.The ability to support such a wide array of devices istestament to the versatility of the adaptable sensorconnector.

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Figure 1 - ARTEMIS Processor System Architecture

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Four types of boards compose the ATERMIS processorsystem including a power supply, a Universal Power Switch(UPS), a G4-based single-board computer (G4-SBC), and aResponsive Avionics Reconfigurable Computer (RA-RCC)board. The power supply receives the space vehicle 28Vpower and outputs regulated +3.3V, +5V, +15V, and -15Vas required by the other boards in the system. The UPStakes in the space vehicle 28V power and receivescommands via the SEAKR Serial Bus to switch the powerto redundant payload power planes and individual payloadsensor components such as cameras. Power switchingcommands are passed from the G4-SBC to the RA-RCC viathe cPCI bus. The RA-RCC then passes the commands tothe UPS via the SEAKR Serial Bus. Redundant powersupplies and UPSs can be included if required by amission's fault tolerance requirements. The total powerbudget for the ARTEMIS processor and sensors is 47W.

The G4-SBC manages external interfaces to the spacecraftand up/down links, controls system configuration andorchestrates data processing. A block diagram of the G4-SBC board architecture is shown in Figure 2. The boardconsists of the Freescale MPC7457 processor with 32KB ofLI cache, 256 KB of L2 cache and an internal Alta-Veccoprocessor; a PC107A memory controller and PCI bridge;a support FPGA that provides Error Detection andCorrection (EDAC) protected interfaces to three types ofmemory and an RS422 LVDS interface; cPCI andSpaceWire interfaces; and a GigE PMC interface. The G4-SBC provides 600 DMIP sustained performance, 256 MBof SDRAM, 1GB of Flash memory, greater than 3OKradradiation tolerance and consumes a maximum of 15W.

The G4-SBC receives commands from the SpaceWire orRS422 interface and controls the rest of the system.

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The primary functions of the RA-RCC are to control thepayload sensor functionality, perform on-board processingof the sensor data, and to control power switching of thesensors and nonvolatile mass data storage. The RA-RCCboard architecture is shown in Figure 3.

Figure 3 - Responsive Avionics Reconfigurable Computer (RA_RCC) Board Architecture

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The board contains four FPGAs including one ActelRTAX2000 and three Xilinx V4 LX160 coprocessors(COPs). The radiation tolerant Actel provides a PCI-to-PCIbridge between the back plane and the local PCI businterconnecting three COP FPGAs. The Actel also controlsconfiguration management and scrubbing of the COPs viathe SelectMap interface as well as the 4Gb bank of triple-redundant Flash memory used for configuration programstorage and a 512Mb bank of triple redundant SDRAM usedfor system configuration management. The Actel alsocontrols the serial bus interface for the UPS card whichcontrols the power state of the payload sensors.

Each COP controls and has access to a 256MB bank ofReed-Solomon EDAC protected DDR2-SDRAM availablefor processing applications. The COPs also interface toadaptable high-speed mezzanine interfaces that can connectthem to sensors, or additional memory or systeminterconnections. At present, the ARTEMIS processorconnects to a 16GB bank of Reed-Solomon EDACprotected NAND Flash, two camera links for cameracontrol and receipt of the high rate image data, current drivefor opto-isolator control lines for the focus mechanismstepper motor controller, and analog position telemetry fromthe focus mechanism via mezzanine cards as previouslydescribed. Also, custom LVDS I/0 interfaces areimplemented between the COPs to improve inter-processorcommunication. Due to the flexibility of FPGAs, all ofthese interfaces may be enabled or disabled as required bythe mission without changing board hardware layouts.These adaptable interfaces provide a cost-effective way tocustomize the ARTEMIS core components for a wide rangeof missions.

The COP FPGAs also provide front-end signal processingand/or payload processing in conjunction with the G4-SBC.FPGAs provide a fabric upon which a variety of high-performance signal processing algorithms can be deployed.Libraries of predefined functions are available or thedeveloper can build custom functionality as required.

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The flexible nature of these devices allow the system toadapt to late developing requirements or changing on-orbitconditions such as algorithm updates and degraded moderequirements due to catastrophic hardware failure.

3. ARTEMIS PROCESSOR FLEXIBILITY

Figure 4 shows several of the many I/0 options the RA-RCC flexible mezzanine interconnect provides. Any one ofthe COPs can be connected to one or more mission-specificdevices via tailored mezzanine cards and interface logicdeveloped for the COP. The setup shown in Figure 4Ashows one setup option whereby each COP is independentlyinterfaced to one or more dedicated resources. This setupprovides a simple design but does not guard againstmechanical failures on the input channels unless someexternal redundancy mechanism is employed. A secondoption (Figure 4B) provides maximum redundancy andflexibility with all sensor inputs available to be switched toany of the COPs. This setup provides the ability to fullybypass a hardware failure with a COP or mezzanine cardinterface. Due to the reconfigurable nature of FPGAs, logicresources need not be wasted within the COPs to supporteach potential interface at all times. In-situ reconfigurationcan occur on an as needed basis to support degraded modes.This option also facilitates fully replicated processing ofinput data.

Another option (Figure 4C) provides a hybrid between thetwo previous approaches supporting a mixture ofredundancy as mission requirements dictate. Figure 4Dshows another option where physical separation betweenredundant interfaces can be achieved with the use of anadditional mezzanine card (or other means ofinterconnection). In this configuration the two COPs on theends are physically isolated while the center COP cansupport redundancy or additional processing in either I/0domain.

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Figure 5 - Select COP Application Fault Tolerance Options

The use of high performance yet radiation susceptibleXilinx FPGAs as processing elements on the RA-RCCrequires the use of period configuration scrubbing and otherSingle-Event Effects (SEE) mitigation techniques. The use

of Triple Module Redundancy (TMR) with a radiationhardened voter is a common method deployed in aerospace

systems but the flexible design of the RA-RCC provides thedesigner with some interesting options to consider (Figure5). Using the flexible mezzanine I/0 connectors, a faulttolerant voter could be deployed as shown in Figure 5A.For this option it is assumed that the voter would beintegrated into one or more mezzanine cards such as thoseshown in Figure 4B-4D in a manner in which it doesn'tinterfere with the I/0 interfaces to payload sensors. Thismezzanine approach allows the designer to choose an optionthat is most appropriate for their algorithm rather thanrequiring the voter to be designed on the RA-RCC.

Other mitigation options exist that do not require the use ofa mezzanine connector. Figure 5B shows an optionwhereby a radiation immune (i.e. triplicated) voter is placedon one of the COPs. The output data from each of the threeCOPs would be passed to the COP with the voter forverification. An alternative approach to the centralizedvoter is to have voters distributed in each of the devices(Figure 5D). This approach provides the benefits of havingimproved fault tolerance due to redundant voters which alsoprovides the option to save COP resources by not requiringeach individual voter to be radiation immune. However,this approach requires more data to be shared between thedevices because each voter needs a copy of data from allother devices.

Figure 5C provides another TMR strategy known as

selective TMR in which critical parts of an application are

triplicated within the FPGA such that an external voter isnot required [10]. Unlike the other options presented inFigure 5, all three COPs are not required to performredundant computation and can work on separateapplications or separate stages within the same application.The key to this strategy is to identify the critical controlpaths, data and other algorithm features to which TMRcoverage can be applied such that the algorithm's faulttolerance is at an acceptable level. It should be noted thatthe flexibility of the RA-RCC allows applications to bedynamically switched between options if desired due tochanges in the radiation environment or mission objectivesor due to system failures. Such flexibility greatly improvessystem fault tolerance and reduces overall project risk.

4. TACSAT-3 MISSION OVERVIEW

The Tactical Satellite (TacSat) program is a joint AFRL andNRL demonstration program whose main goal is to developthe capability to field inexpensive space systems in time ofcrisis to augment and reconstitute existing capabilities or

perform entirely new tactical theater support missions [11].Some of the key criteria that will define success for theTacSat program in meeting the needs of responsive space

missions are to deploy low cost ($20 million or less)mission-specific spacecraft rapidly (i.e. activated on orbitwithin six days of call up) and provide between six totwelve months of reliable mission operations [12].

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The TacSat- 1 mission took the first step toward improvingresponsive space capability and also expanded SIPRNET tospace and the TacSat-2 mission provided a space-basedcommon data link for tactical communications [13]. TacSat-3 will expand the program's capabilities by deploying astandard component interconnect bus, demonstrating initialcomponent plug and play ability and including a land-focusedHyperspectral imaging (HSI) payload [14]. The ARTEMISpayload will provide the HSI sensor and applicationprocessing capability for the TacSat-3 mission scheduled tolaunch in 2008. Future TacSat missions will focus onimproving payload capabilities, extending dwelling time inLEO and link to other satellite programs such as T-SAT.

The HSI payload onboard TacSat-3 consists of a telescope,an imaging spectrometer, and a high resolution imager thatcombine to produce raw high resolution images. Thispayload unit is captured by the ATEMIS Sensor box inFigure 6. The HSI data collected from the sensor isprocessed by the Sensor Processor shown in Figure 6 whichconsists of one ARTEMIS payload processor as shown inFigure 1. HSI allows for spectral match indication andidentification which provides anomaly detection within agiven scene that allows the warfighter to distinguish man-made materials from natural materials among other benefits.A fundamental capability of the ARTEMIS payload is toautonomously process HSI data and produce tacticallyrelevant data for dissemination directly to the warfighter inthe form of text or imagery as the situation requires.

The goals of achieving responsive space capabilitiesmotivated all aspects of the ARTEMIS sensor and processorpayload development. Design trades were carefullyevaluated at each step with cost and schedule impacts offoremost consideration. The resulting sensor maintainstechnical performance while containing costs even with arapid development schedule of twelve months [14].

ARTEMIS provides a foundation for high-performance andflexible payload system design that meets the TacSatdevelopment program's responsive space objectives. Aninnovative aspect used to control cost and schedule is todecouple payload processing capabilities from thespacecraft sensors. As previously described, the ARTEMISprocessor employs mezzanine connectors with flexiblehardware interfacing to connect sensors to processingresources. Also, by decoupling the sensor from theprocessor, the ARTEMIS payload can be deployed ondivergent spacecraft architectures without redesigning thesensors - only a re-spin of the processor board toaccommodate any additional interfaces (e.g. VMEbackplane) is required. Also, this decoupling allows for asmooth transition when future versions of the processing orsensor boards are developed. Such flexibility will allowfuture missions to quickly augment sensors and processingcapabilities around the core payload architecture deployedon TacSat-3. The ARTEMIS payload processor is a keytechnology to enabling the responsive space mission and isactively being investigated for additional mission.

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5. CONCLUSIONS

The Advanced Responsive Tactically Effective MilitaryImaging Spectrometer (ARTEMIS) payload processor wasmotivated and described. Various means by which theARTEMIS processor design improves system faulttolerance and flexibility and the system's ability to meet thechallenges of the responsive space mission weredemonstrated. Key features described include the flexiblemezzanine interface that decouples the payload sensors andprocessors. This flexibility enables smooth transitionsbetween successive generations of sensor and processorcomponents. The mezzanine connectors also provide for avariety of fault tolerant I/0 interconnect and radiationmitigation strategies as outlined in Section 3. The means bywhich ARTEMIS autonomously provides HyperspectralImaging intelligence to the warfighter from the TacSat-3spacecraft and the mission's importance were brieflyoutlined in Section 4. Upgrades and additional deploymentof the ARTEMIS payload processor are being activelypursued.

REFERENCES

[1] NASA, "2006 NASA Strategic Plan," NP-2006-02-423-HQ, NASA Headquarters, Washington D.C., February2006.

[2] US Air Force, "Strategic Master Plan FY06 and Beyond,"US Air Force Space Command, Peterson AFB, CO,October 2003.

[3] P. Shriver, S. Briles, J. Harikumar and M. Gokhale, "APower-Aware Approach to Processing Payload Design,"Proc. Government Microcircuit Applications and CriticalTechnology Conference, Tampa, FL, March 31-April 3,2003.

[4] D. Brenner, J. Ramos, G. Galica and C. Walter,"Environmentally Adaptive Fault Tolerant Computing,"IEEE Aerospace Conference, Big Sky, Montana, March5-12, 2005.

[5] I. Troxel and A. George, "Adaptable and AutonomicManagement System for Dependable AerospaceComputing," Journal of Autonomic and TrustedComputing (JoATC) Special Issue on Autonomic andTrusted Computing Systems and Applications (acceptedand in press).

[6] J. Samson, J. Ramos, I. Troxel, R. Subramaniyan, A.Jacobs, J. Greco, G. Cieslewski, J. Curreri, M. Fischer, E.Grobelny, A. George, V. Aggarwal, M. Patel and R.Some, "High-Performance, Dependable Multiprocessor,"Proc. IEEEIAIAA Aerospace Conference, Big Sky, MT,March 4-11, 2006.

[7] J. Bystroff, "System Architecting Challenges of ChangingMissions for a Flexible Mission Spacecraft," Proc. AIAAResponsive Space Conference, Los Angeles, CA, April,24-27, 2006.

[8] B. Jackson and K. Epstein, "A ReconfigurableMultifunctional Architecture Approach for Next-Generation Nanosatellite Design," Proc. IEEE AerospaceConference, Big Sky, MT, March 18-25, 2000.

[9] D. Lanza, J. Lyke, P. Zetocha, D. Fronterhouse and D.Melanson, "Responsive Space through Adaptive Avionics,"Proc. AIAA Responsive Space Conference, Los Angeles, CA,April 19-22, 2004.

[10] P. Samudrala, J. Ramos and S. Katkoori, "SelectiveTriple Modular Redundancy for SEU Mitigation in FPGAs,"Proc. International Conference on Military Application ofProgrammable Logic Devices (MAPLD), Washington, D.C.,September 9-11, 2003.

[11] J. Raymond, P. Stadter, C. Reed, E. Finnegan, M.Hurley, C. Merk, T. Kawecki and C. Gamer, "A TacSatUpdate and the ORS/JWS Standard Bus," Proc. AIAAResponsive Space Conference, Los Angeles, CA, April25-28, 2006.

[12] S. Straight and T. Davis, "Tactical Satellite 3:Requirements Development for Responsive SpaceMissions," Proc. Space Systems Engineering Conference(SSEC), Atlanta, GA, November 8-11, 2005.

[13] T. Duffey and M. Hurley, "Operationally ResponsiveTactical Microsatellites," Journal of Naval Research,2005.

[14] T. Davis and S. Straight, "Development of the TacticalSatellite 3 for Responsive Space Missions," Proc. AIAAResponsive Space Conference, Los Angeles, CA, April24-27, 2006.

BIOGRAPHIES

Ian A. Troxel is the Future SystemsArchitect at SEAKR Engineering, Inc. Ianreceived his Ph.D. in Electrical andComputer Engineering from the University

of Florida in 2006, where his graduate research focused ondeveloping fault tolerance and application management

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services for embedded space systems. Ian's researchinterests include fault tolerance strategies for next-generation processor systems, developing characterizationmethods for radiation acceptance testing of advancedprocessors and the design of optical interconnects forembedded space platforms.

Matthew J. Fehringer is a Program Manager at SEAKREngineering, Inc. Matt received his Bachelor's Degree inElectrical Engineering from the South Dakota School ofMines in 1990. While with SEAKR, he has managed thedevelopment and production of solid state data recorders,non-volatile memory components and systems, mission dataformatting products, and the ARTEMIS Sensor Processor.

Micheal T. Chenoweth is a hardware design engineer atSEAKR Engineering, Inc. Mike received his Masters inElectrical Engineering from the Colorado School of Minesin 1998, where his graduate research focused on developingan electromagnetic acoustic transducer and wavelet analysissystem for the non-destructive diagnosis of powersubstation ground grids. Mike is the technical lead for theARTEMIS processor.

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