Active Clamp and Reset Technique Enhances Forward ...

Ocl 94

Active Clamp and Reset Technique

Enhances Forward Converter Performance

Achieve Zero Voltage Transitions (ZVT),

Higher Efficiency, Higher Frequency Switchingand Reduced EMIIRFI

Bill Andreycak

Introduction:

The buck derived forward converter is one of the

nwst popular switchnwde topologies, second only to

the infanwusflyback converter. High input to output

step down or up in voltage is easily achieved by

using the appropriate transformer turns ratio.

Galvanic isolation is frequently added between the

supply and load ..grounds" for increased safety and

protection or to supply power to an isolated load.

F or these and other reasons, the forward converter

has become a cost effective solution to many power

management needs. With its continuing prolifera-

tion, new opportunities emerge for nwre efficient

operation, higher switching frequencies, reduced

EMl/RFl and extended duty cycle operation. This

paper presents an innovative technique to properly

clamp and reset the forward converter's main

transformer while achieving low loss, zero voltage

transitions of the power switch under wide duty

cycle variations without the excessive voltage stress

otherwise seen.

verter utilizes a much lower peak current than it'sflyback counterpart. This is advantageous with lowvoltage inputs, where even at 50 Watts, the peakprimary current reaches tens of amps.

The conventional forward converter uses a singlepower switch, a definite advantage over the twoswitches used in the half bridge or four required bya full bridge converter. Also, the forward's switchis "low" side referenced for simplified interface tothe PWM controller, although a two transistorvariety was also common and similar to one half ofa full bridge. But by-and-large, the single switchtype is the most predominant in use today. Mostoff-line designs operate over a universal 85 V AC to265 V AC input range, although some 110!220 V ACmodels still incorporate jumpers to accommodateboth inputs. Forwards are extremely popular in DCto DC conversion, especially in Telecommunica-tions and distributed DC bus applications. Manyutilize peak current mode control and limit the dutycycle to 50% maximum, although the recent trendhas been towards "stretching" this to 70% to effi-ciently accommodate a wider input range.

General ApplicationsForward converters offer a cost effective solution

to fill the void created between the low powerflyback converter and the more complex high powerbridge types. Typically, this span covers mostapplications between 125 and 1000 Watts, but theexact level depends on a number of variablesincluding input voltage and its range. Using contin-uous inductor current operation, the forward con-

Conventional Forward Converters:First generation forward converter designs were

limited to operate below a 50% maximum dutycycle to insure proper reset of the main transformer,preventing potential saturation problems. A separate"reset" winding was incorporated in the maintransformer to provide a convenient route for

3-1Active Clamp/Reset Enhances Converter Performance

over a worldwide AC input voltage span hardlyresults in an efficient power supply design at anyset of line and load conditions since numerouscompromises must be considered. It does, however,recycle the energy stored in the transformer'smagnetizing inductance back to the primary sideinput capacitor, somewhat of a redeeming factor.The associated schematic and operational wave-forms are displayed in Figures 1 and 2.

"RCD" Type Forward Converter:It wasn't long before the conventional adaptation

of the forward converter gave rise to the secondgeneration converters using a different clamp andreset technique which enabled stretching the dutycycles above the 50% barrier. Commonly referredto as the "RCD" type for its Resistor, Capacitor andDiode, these components are used to develop avarying clamp voltage into which the magnetizingenergy is dissipatively discharged. However, usinga high clamp voltage with an amplitude greater thantwice the input supply will facilitate maximum dutycycles which can stretch beyond the 50% milestone,particularly useful in wide range input supply

designs. Note that there are two penalties tobe paid with this adaptation: high voltagestress on the semiconductors and powerlosses from the resistor in the clamp circuit-These sacrifices must be evaluated alongwith any potential gains from reduced prima-ry currents and transformer cost (no resetwinding) when comparing the RCD to theconventional forward design alternative.Generally, the RCD is the preferred choicefor wide input ranges, especially low voltageinput designs where a higher clamp/resetvoltage still yields manageable low voltagesemiconductors. These RCD type designsfrequently require an iteration (or a few)more than their predecessors, with much ofthe development efforts spent on optimizingthe clamp network over all operating condi-

...tions. They, too, tend to suffer from lessthan optimal efficiency at any line or load,just like their predecessor. Nevertheless, theRCD forward converter designs are verypopular and can be made fairly efficient and

Fig 1. -Conventional Forward Converter

clamping the reset voltage amplitude to the inputsupply source. These two safeguards would guaran-tee proper operation and reset over all line and loadconditions. However, a penalty is incurred dueentirely to the limited maximum duty cycle. Alower transformer turns ratio results, which trans-lates into a higher primary current than otherwisenecessary .Designing for operation over a wideinput voltage range exaggerates the difficulty withthis approach. Very narrow duty cycles are neces-sary at high line to meet the 50% maximum dutycycle clamping at low line conditions. Operation

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DUTY- 25% 50%

Fig 2. -Conventional FolWard Converter Waveforms

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cost effective, but there's always room for improve-

ment. The schematic and associated operating

waveforms for this variety are shown in Figure 3

and Figure 4 respectively.

Design Tradeoffs with the RCD Forward: As

shown by the waveforms of Figure 4, a high

voltage exists across the power supply switch

during reset of the RCD forward converter, espe-

cially in an extended duty cycle (>50% maximum)application. A good example of this is a power

supply designed to operate with universal AC inputs

from 85 V AC at low line to 265 V AC at high line.

Fig 3. -RCD Forward Converter For the sake of this example, the maximum duty

cycle will be limited to 75% at low line to keep

.: ...: .: semiconductor ratings reasonable. The resul-

ON i i i ~ -t- ~ ~ ~ tant duty cycle needed to achieve regulation

OFF .-! ! I l-1-. T ..L of the output (constant volt seconds applied)

: ~ : : : ~ : ~ indicates that a 50% duty cycle is reached at

400 [ [ j ~ !...f.. 127 V AC, and a 25% duty cycle is needed

~ ~ ~ ~ ~ : at high line.300 : : ,..: : : j ~ ~ In order to insure reset of the main trans-

i : ~ !...~.. former, the applied volt-second product must

...~~:~... ~ :...l.. be equal to the reset volt-second product

: ~ 1 ~ ~ according to the following relationships:

Vin-D = Vreset-(l-D)

Vreset = Vin(min)-Dmax / (l-Dmax)

Vds = Vin + Vreset

vGS

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200

100 -

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.200

-300

t .

t :bMaximum Drain-Source Voltage: Note

that in this example, the reset voltage isreferenced to the high side of the inputvoltage (Vin). Therefore, the maximum drainvoltage of the MOSFET switch is Vin plusVreset. The worst case condition could occurat high line, and the table on the next pageis a summary of the circuit voltages as afunction of operating conditions for oneexample of an off-line converter with a 75%maximum duty cycle at low line.

-400

800 " "" "":

.-HiGH.~LiNE.:.

.~..:.~.700

600

:lOW liNE" :

:C~"

5000=::'

VDS

IV)400

300.l200

:u:100

-i ;--.j0

DUTY= 20%30% 75%

Fig 4. -Ideal RCD Forward Converter Waveforms


.D

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requirements and winding configurations.Off -line converter transformers incorporate a high

primary inductance to minimize the magnetizingcurrent and keep power losses low. If not, the peakmagnetizing current could conceivably be higherthan the reflected load current, reducing efficiency.Typically, the magnetizing current is designed to bebetween 10% -25% of the reflected load current.Each design is unique, but this is typical of trlany

design practices. Furthermore, primary magnetizinginductances are in the range of I -5mH for mostoff-line, high frequency designs. This being thecase, a 2.5mH primary is used for the purpose ofanalysis. Also, a leakage to magnetizing inductanceratio of 1% is used, colTesponding to 25pH.

Lpri = 2.5mH; Llkg = 25pH

85

132

180

265

This table uses rather optimistic reset conditions.In reality, it is difficult to design an optimal RCDnetwork to accommodate all leakage inductanceload effects while maintaining a low maximumclamp voltage. Low line and light load conditionsgenerally dictates the clamp capacitor and resistorvalue needed to facilitate the proper transformerreset. At higher line and load conditions, generallythe clamp's resistive load is less than ideal, causingthe clamp voltage to increase. In an off -line supply,this could push device ratings and safety isolationrequirements above 800 VDC, potentially creatingnew problems, especially when safety agencyregulations are considered.

Let's look at the design of an RCD clampnetwork for the following design specifications.

Pout = 2OOW

Fswitching = lOOkHz

T(period) = lOps

Duty cycle will adjust to the varying line input.but the volt-second product will be constant. Tocover the universal AC input range of 85 to 265V AC. the duty cycle will change from its maximumof 75% at 100 VDC (rectified and filtered 80 V AC)to 19% at 400 VDC.

Vin = 100 VDC, D = 0.75 (75%)

Vin = 250 VDC, D = 0.30 (30%)

Vin = 400 VDC, D = 0.19 (19%)

The peak magnetizing current is detennined by

Imag = (Vin.T(period).D) / Lmag

Under any of these conditions. the peak magne-

tizing current is 0.30 A because the transformer's

volt-second products must balance. The b"ansfonner

primary current can be approximated from the

following relationships, ignoring output inductor

charging current and any inefficiency in the entire

power conversion. At full load:

Leakage Inductance Effects:The previous examples of reset techniques do not

take into account the effect of the transformerleakage inductance -which is significant. It may bethe dominant factor in most off-line applications,especially where high leakage inductance is theresult of facilitating safety agency spacing andisolation requirements. In these applications, themagnetizing inductance effects on the clamp capaci-tor voltage are minimal, and reflected load currenteffects will primarily govern the clamp voltage. Theopposite of this may be more of the case in DC toDC converters and planar magnetic designs wheremuch lower leakage inductance is more common incomparison to off-line designs.

In either case, certain generalizations can be usedto arrive at quantitative results. For example, anoff-line transformer's leakage inductance is typicallysomewhere between 0.1% -1% of the magnetizinginductance, depending on a number of factors.These include core geometry or style, isolation


VCc = 330V

dVCc = lOV at light load

Load Effects: The energy into the clamp capaci-tor is equal to the energy stored in the leakageinductance provided that little energy is lost in theconversion. This is generally NOT the case in many200 Watt converters for a few reasons. First, aportion of this energy goes into charging theMOSFET switch output capacitance from essentiallyzero to the input voltage, plus the clamp voltage(Vin + V Clamp). Another portion goes into charg-ing the transformer primary capacitance from theinput to the clamp voltage, Vc. Both of thesecapacitances could easily be in the same order ofmagnitude as the clamp capacitance, and an exten-sive evaluation is necessary to determine the ef-fects. Detailed analysis of this requires the use ofmodelling and simulation tools, but a generalcomparison can be made py looking at the changein stored inductive energy in the leakage, WLlkg.

Leakage Inductance Effects Summary: Manycombinations of clamp capacitance and resistancevalues are possible for a given application, depend-ing on the ratio of light to full load current, theratio of leakage to magnetizing inductances, maxi-mum clamp voltage, transformer primary capaci-tance and MOSFET switch capacitance, Coss. Allof these parameters need to be weighed in additionto proper reset of the transformer core under all

Iin(DC) = PinNin(min) = 200W/100V = 2A

Ipri' = Iin(DC)/Duty(max) = 2A/0.75 = 2.66A

A good estimate of light load is ten percent ofthe full load current for most Buck derived convert-ers. For this 20W condition, the primary current is:

Iin(DC) = 20W / 100V = 0.2A

Ipri' = O.2A /0.75 = 0.266A

The actual primary current flowing in the leakageinductance is the sum of the reflected load currentand the magnetizing current, ignoring the outputinductor charging current for this analysis.

Imag(pk) = O.3A

Ipri'(max) = 2.66A

Ipri'(min) = O.27A

Ipri(max) = I(mag) + Ipri'(max) = 2.96A

(use 3A)Ipri(min) = I(mag) + Ipri'(min) = O.57A

(use O.6A)

Clamp Voltage: The clamp voltage and capaci-tor value needs to be determined. Since the primaryvolt-seconds must balance each cycle, a 300 Voltclamp is the minimum value for the listed(lOOVDC, 75% Dmax) design conditions. Notethat this condition must be met at light load, corre-sponding to the lower amount of leakage energydumped into the clamp network. As the loadincreases, so too will the clamp voltage asmore energy is transferred. Proper reset of aoo

the transformer must be guaranteed underthe worst case situation, corresponding tolow line. light load conditions. A ten percent! 400safeguard (approximately) will be added for

rincreased margin, resulting in a 330V clamp

voltage.IThe exact capacitance required is deter-

mined by the acceptable clamp capacitorripple voltage which causes heating due tothe ripple current flowing in the capacitor'sEquivalent Series Resistance (ESR). A goodinitial estimate for this analysis is lOV ofripple at light load since this ripple will onlyincrease with load.

500

~

200

100

Load Effects on Stored EnergyFigS.

Active Clamp/Reset Enhances Converter Performance 3-5

operation conditions to detennine the optimalcombination for a given design. Beyond the scopeof this presentation, an authoritative design proce-dure for this RCD clamp network could be generat-ed.

Active Clamp/Reset Technique:The newest adaptation of the common RCD type

reset technique is to replace the diode with anactive MOSFET switch. Its first purpose is to clampthe primary to the reset capacitor, just as diodewould. A second function, which a standard rectifi-er is unable to provide, is to allow a controlled(switched) transfer of energy back from the resetcapacitor to the primary side power stage of theconverter. Current in the MOSFET switch "chan-nel" is bidirectional during part of its active inter-val, but is zero during the remainder of the switch-ing cycle. Note that the active clamp and resettechniques are inactive during the normal powertransfer portion of the switching cycle, and onlyoperate during the main switch's off-time. For themost part, conventional square wave power conver-sion waveforms apply to system voltages andcurrents during the on-time of the main switch.However, significant improvements and differencestake place during the low loss clamp, reset and softalignment of the power switch. Two pivotal benefitsare obtained with this new approach: higher effi-ciency and zero voltage "soft" switching transitions.One adaptation of this circuit is shown in Figure 6.

SIGNIFICANT BENEFITS:

"recycles" b"ansformer magnetizing energyinstead of dissipating it in a resistor

facilitates Zero Voltage Transition of the mainswitch for higher efficiency

.uses lower voltage MOSFET and diodescompared to the RCD

reduced EMI/RFI via soft switching

eliminates lossy snubber network on primary

operates at fIXed frequency

allows much higher frequency operation

similar power b"ansfer to conventional squarewave switching

duty cycles beyond 50% max are obtainable

actively resets main transformer to third quad-rant of BH curve

DIFFERENCES AND SIMILARITIES:

This new approach requires a few more partsthan the other forward choices to achieve thebenefits listed previously. Differences include:

.an additional high voltage MOSFETclamp/reset switch

an isolated, variable duty cycle gate drive forthe clamp/reset switch

a modified PWM control technique to properlyprogram the associated delays between gatedrives to achieve the zero voltage transitions

a new gate drive technique to extract theproper clamp/reset drive pulse

Nearly all other aspects of the converter primaryand secondary power stage, including magneticcomponents are very similar to the RCD approach,although stressed less. Many existing forwardconverter designs can be modified for a "quick"comparison, but some changes are required in thecontrol circuitry and in the primary power stage.Nevertheless, modifying an existing unit is probablythe shortest, easiest and most direct route to an"apples-to-apples" evaluation of this improved

technique.

Fig 6. -Forward Converter with Active Clamp


FORWARD CONVERTER COMPARISONpower converter is referred to as switch " A " com-

posed of "QA", "CA" and "DA", whereas theclamp/reset switch is referred to as Q"C" {etc), forclamp. "Creset" is the clamp/reset energy storagecapacitor. The word "reset" was chosen instead of"clamp" so there would be no conflict with "Cc",the clamp switch output capacitor. Next, the circuitwill be redrawn slightly differently as shown inFigure 7. Note the similarity between ~is represen-tation of the active clamp and reset technique to theconventional half-bridge topology. The two excep-tions are the non center tapped secondary of themain transformer, and "missing" connection be-tween the input supply and the high side of thereset capacitor. Make these changes to a standardhalf-bridge, modify the gate drives and you've gotthe makings of an active clamp/reset forward. It'snot quite this simple because of issues with thetransformer secondaries, but there are similarities.

Conventional RCD Type ActiveParameter

Efficiencymax. DutyVoltage StressCurrent StressTurns Ratiol(mag),I(lkg)Higher Freq.Complexity

high<50%lowesthigherlowerrecycledGoodlowest

highest> 50%

highlower

high~best

highest

high> 50%highestlowerhighdissipatedfairmoderate

Qo Co DoD1

rl>I--

11~

Lo

Co:-

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QA CA DA"

VIN ..."'

po "' L~

Fig 7. Active Clamp Forward Converter

Theory of operation: One complete switchingperiod will be broken down into eight individualsections (to -t8) for the purpose of this presenta-tion. Depending on the level of interest, this tech-nique can be described in either more, or lessdetail, however eight relevant ones have beenselected. The gate drives, voltages and currents atall fundamental components and nodes will beanalyzed during each timing interval, and therespective waveforms will be highlighted.

Mastering the Active Clamp Technique: Thereare several fundamental timing intervals with thisnovel approach to explore in detail, only some ofwhich are entirely new. Overall, this technique is ablend of the attributes of conventional fixed fre-quency, square wave power conversion with thezero voltage transitions of the phase shifted, fullbridge technique. There is one interesting newdifference to note, necessary to facilitate ZVT .This active clamp technique forces a "reverse"magnetizing current to flow through the trans-former for a small portion of the timing period,storing energy in the primary inductance. Whenreleased, this energy is used to position themain switch voltage to zero by discharging theMOSFET(s) output capacitance just prior to itturning on. This alignment to zero drain voltagewill automatically occur each switching cycleprovided that enough inductive energy is storedto overcome the opposing capacitive energyrequirements of the circuit and powerMOSFET(s). Zero voltage transitions can beforced over a wide variety of input voltages and awide range of output load currents because of this"reverse" storage of energy.

First, the general circuit schematic of Figure 6will be expanded to include the MOSFET parasiticoutput capacitance (Coss) and the internal bodydiode for clarity. The three integral components ofeach switch will be separately labelled and identi-fied to demonstrate the exact current paths duringeach interval. The MOSFET channel (switch) isdesignated by "Q", the output capacitance by "C"and body diode by "D". The main switch of the


can be simplified for the sake of this presentationby assuming that nearly all of the secondary (out-put) current is flowing through output diode 02,and that only a small amount is conducted by 01.Another assumption is that there was ample energyavailable on the primary side to overcome thecoupling effects from the secondary to the primarywinding, and facilitate the zero voltage transition ofQA. Let's spare the details for now as they will beclarified in the analysis of the final timing interval,t7 to t8.

In summary , both switches are OFF and nopower is being transferred from input to output. Themain switch, MOSFET QA is aligned at zero voltsand a reverse current flowing in the primary due tostored inductive energy is clamping the switch there

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INITIAL CONDITIONS: time t < tO

The analysis of this technique will begin bystating the initial conditions where steady statecondition have previously been established and theconverter is up and running at normal outputvoltage and some static load condition. As for theswitches, MOSFET QA, the main power switch isOFF, but has already been aligned with zero volt-age across it The clamp/reset switch QC is alsoOFF with a voltage across it equal to the clamp(Vcr) voltage plus the input (Vin). Previously,energy had been stored in the transformers magne-tizing and leakage inductance which is now beingreleased as a "reverse" primary current. The pathfollowed is through the transformer from bottom totop, and into the positive terminal of the inputcapacitor, Cin, charged to Vin. This path continuesout through the low side of Creset, and over to themain switch where it is conducted through its bodydiode, DA. Enough energy has been stored tocontinue this condition even beyond time tO whenswitch QA is turned ON.

On the secondary side things are not quite soclear because of the unknown transformer leakageinductance and coupling between the windings. This

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10 1112 13 14 1518 1718

Fig 9. -Active Reset WaveformsFig 8. Initial Conditions --t < tO


via its body diode. DA. A table below Figure 8displays the various component conditions forfurther clarity .A preview of waveforms for theentire switching cycle is presented in Figure 9.

POWER TRANSFER: Figure 10, tO < t < tl

This inteIVal is nearly identical to conventionalsquare wave power conversion. It starts out at timetO when the forward's main switch QA is turnedON, initiating the transfer of power from theprimary to the secondary via the main transformer.From the onset of this inteIVal, switch QA wasaligned with zero volts across it, and "reverse"primary current was flowing through the body diodeDA, clamping the drain voltage to the lower rail.When QA is turned ON the current is diverted fromthe body diode to the device's channel since it'sgenerally a lower impedance and can conduct ineither direction. The transformer primary currentwill build to the reflected load current (Iout/N) atthe rate of Vin divided by the effective seriesinductance. The transformers leakage inductance(Llkg) will be used for this analysis, although anyother series inductance should be taken into ac-count. As this occurs, the driven current in the

transfonner secondary also climbs, forward biasingdiode Dl. Cunent previously flowing in diode D2is decreasing by the same amount rising in D I suchthat the two equal the full load cunent. This brieftransient portion of this interval could be examinedin closer detail, if desired, although somewhatincidental in the overall picture. Primary current isthe sum of three individual cunents, the reflectedoutput load current, the reflected output inductorcharging current and also the primary magnetizingcurrent.

Very quickly into this interval, the nonnal flowof power has been established and switch QAremains ON for the exact amount of time to regu-late the output voltage. This is all handled by thePulse Width Modulator (PWM) section of thecontrol circuitry which can be achieved by a num-ber of popular techniques and Ics. Once the correcttime has been reached at the end of this interval(tl), switch QA will be turned off. But for the mostpart, this interval is identical to conventionalswitching technology .

LINEAR TRANSITION: Figure II, tl < t < t2

At time ti, the COITect pulse width has beenreached and switch QA is turned OFF. "Instantly",the CUITent in the MOSFET device is diverted fromits channel (QA) to its output capacitance, CA. Thebody diode (DA) is reversed biased and not perti-nent. With the reflected "full" load cUITent flowingin the primary , fueled by the large output inductor(Lo), CA charges very quickly. The voltage acrossthe MOSFET device rises "linearly" while thevoltage across the clamp MOSFET (QC) simulta-neously decreases "linearly". This activity contin-ues until time t2 when CA is fully charged to theinput voltage (Vin). Similarly, the voltage acrossCC has decayed from its initial value of Vcr to(Vcr -Vin). This interval concludes at time t2 whenthe transformer's primary voltage reaches zero. Forclarity, this scenario can be viewed as two capaci-tors in parallel (CA & CC) being driven from a"constant" CUITent source equal to lout/N, endingwhen V(CA) reaches Vin.

In minuscule detail, this linear approximation isnot exact -but a useful simplification because the

Power Transfer --tO < t < tfFig 10.


ing relationship for time, dt, which corresponds to

dt(2 -I).

I = C..1.v/.1.t

The change in voltage, .1. V, is equal to Vin since

the transformer goes from Vin to zero during this

interval.

.1. V = Vin

11

OFF

E--OFF~

IPPK-. +IM

The effective capacitance in this equation is theparallel combination of the two switches' outputcapacitances, CA and CC. To compensate for theeffective capacitance of a MOSFET with highvoltage applied, International Rectifier, a majorMOSFET manufacturer suggest multiplying thespecified Coss term by a 4/3 factor. Also, thetransformer primary capacitance must be taken intoaccount as a parallel capacitance. The net capaci-lance is :

C = (CA + CC).4/3 + Cpri(Tl)Dependent on Leekage & Coupling

The primary current flowing at time tl can beapproximated by the output load (or inductor)current divided by the transformer turns ratio N.While this is a simplification, it's a fairly accuraterepresentation provided that the output ripplecurrent and transformer magnetizing currents are"low".

Ipri(tl) = Iout/N

Duration of this timing interval can be approxi-

mated as:

dt(2-1) = {(CA+CC).4/3+CpriTl].Vin.N} / lout

Note that while the primary current hasn'tchanged in amplitude very much, the route beingtaken does change, The full primary current nowdivides into charging the output capacitance of themain switch QA, and discharging the output capaci-tance of the clamp switch, QC. For the sake ofsimplicity, an approximation that the current dividesequally can be used for analysis, although the exactratio is a function of each device's output capaci-tance. Therefore, at time TI, the current in QAdrops from the full load current to one-half of that,and instantly goes from zero to half of the full loadcurrent in QC. This is an approximation assuming

Fig II. -Linear Transition --tl < t < t2

interval is so brief. Here's why. First, the primarycurrent is not constant, it's actually increasing.Although the net voltage across the transformerprimary is rapidly decreasing from Vin to zero, itstarts out positive and stores energy in the leakageand magnetizing inductances for the durntion.Superimpose this component on top of a "constant"reflected output current (due to the large outputinductor) and the sum is the net primary current -still increasing. Note that the charging and discharg-ing the two MOSFET output capacitances (CA andCC) is due to current flowing from the input supplyand clamp capacitor. It is NOT cause by transfer-ring previously stored inductive energy, as willoccur later in another timing interval to align theswitches back to zero voltage.

On the secondary side, an assumption is madethat all of the load current continues to flow onlythrough diode D 1 during this interval. As thetransformer voltage collapses to zero at t2, thissituation could change depending on the design,magnetic coupling and placement of the leakageinductances in the physical transformer.

Design equations: The brief time spent in thisinterval can be approximated by solving the follow-


at time t3 the current in QC can equal zero, butwill generally be slightly negative to guarantee thatthe enough energy is stored in the system to reachthe clamp voltage. A similar situation is present atthe main switch QA where its output capacitance ischarged to the clamp voltage Vcr. Any additionalcurrent flowing in the primary before turn on of theclamp/reset switch (at t3) goes towards increasingthe clamp capacitor voltage.

that the MOSFET switch output capacitances areidentical. In a practical application they will not bethe same since a smaller device is typically used forthe clamp/reset function. Therefore, it's likely thatslightly more than half will flow in the main switchand slightly less than that flows in the ZVT switch.

PASSIVE RESET & RESONANT TRANSITIONFigure 12, t2 < t < t3

At time t2 the transfonner primary voltage hasreached zero which is also reflected to its second-ary .This causes the full load current to transferfrom diode D 1 to D2 at a rate detennined primarilyby the secondary leakage inductance, but is allflowing in D2 at time t2. The transfonner voltagecontinues its reversal from zero on towards theclamp voltage, Vcr. This transition is a resonant onebecause the previous catalyst of reflected loadcurrent is now gone with D2 conducting. Thisreverse biasing of D 1 also allows the reversal ofTI's voltage which continues from t2 through t3when the clamp reset voltage is reached. Current inthe clamp switch QC is negative during this intervalas the output capacitance is discharging. Note that

PASSIVE RESET / Imag > 0:Figure 13, t3 < t < t4

At time t3 the transfonner primary voltage hasthe clamp voltage applied which facilitates the resetof the magnetizing inductance. Also at time t3 theclamp/reset switch QC is turned ON which allowsthe reset current to transfer from the device's bodydiode to its channel, generally providing a lowerimpedance path. The main goal of turning the resetswitch on, however, is to provide a path for currentto later flow from the clamp capacitor reservoir tothe transfonner primary to facilitate the ZeroVoltage Transition. But from time t3 until t4, theenergy stored in the transfonner's magnetizinginductance results in current is flowing back from

QA OFF --Qc OFF --

Increesing DecreeslngCA V" VCR .V" CC VCR --0

Qc

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Dc

!3 !4

OFF-- ONV.Q --

OFF -.

I ~~RI' ~~-;:CR1 OFF ---Decreasing

VPRI' O VCR

02 ON ---

IPRI

~~Dc OFF-- ON att3

D2 ONI =10

DecreaaingI .1. (12 13) .ImI IPR'

Fig 12. -Passive Reset andResonant Transition --t2 < t < t3 Passive Reset / Imag<O --t3 < t < t4Fig 13.


the transfonner to the clamp capacitor.Primary current decreases during this entire

interval until reaching zero at time t4. It may not benecessary to explore the wavefonns at time t4 ingreat detail. This interval was selected to demon-strate that there is a point in the overall conversioncycle when the transfonner has been correctly resetand the next switching cycle could begin at t4, if

necessary.

is used in addition to a large magnetizing induc-tance. This will only lead to major problems duringtransient response, and should be avoided.

As energy is transferred from the clamp storagecapacitor to the magnetizing inductance the capaci-tor voltage will decrease. Note that a resonant L/Ctank has been formed by these two components andmust be further analyzed. The characteristic tankimpedance (Zr) and frequency (ror) need to becalculated, and the following equations apply.

Zr = (Lmag/Creset)1/2

ror = 1 / (Lmag-Cresetr (ror in radians)

to convert this to frequency;

fres = ror / (2-3.14159), or ror / 6.28

the period of a complete resonant cycle is

Tres (period) = 11 fres

ACTIVE RESET I Imag < 0:Figure 14, t4 < t <t5

Beginning at time t4, the transfonner is activelyreset by switch QC to the clamp/reset voltage, Vcr.The magnetizing current starts out at zero duringthis intervill and is driven negative by the clampcircuit, storing energy in the magnetizing induc-tance. This will be used later to facilitate the ZeroVoltage Transition.

Primary current initiillly rises at the rate deter-mined by the clamp voltage divided by the magne-tizing inductance (Vcr/Lm). However, note that alinear approximation is not valid for more that thefirst instant of time. This rate will never turn out tobe truly linear unless a huge clamp capacitor villue

The active reset duration is the result of operat-ing at a specific duty cycle and frequency, with thedelay times accommodated. It is not programmed orcontrolled otherwise by the control circuit or PWM-just the result of performing output voltageregulation. Specific issues relating to this intervalare presented elsewhere in this text.

What's really interesting is that the clamp voltagewill adapt to the operating conditions and accom-modate changes favorably. For example, let'sarbitrarily let the main switch stay on too longwhich results in a higher magnetizing current (andenergy) than ideal. During the time between turnoff of the main switch and turn on of the resetswitch, the magnetizing inductance discharges intothe clamp capacitor, causing its voltage to increase.Now, when the reset switch turns on, it is at ahigher voltage than previously which results in ahigher reset current. This self correction will occureach cycle without the need of elaborate control

circuitry.

Fig 14. -Active Reset / Imag<O --t4 < t < tS


RESONANT TRANSITION:Figure 15, t5 < t < t6

The reset switch is turned OFF at time 15 causingthe primary current to divert from the device'schannel (QC) to its output capacitance (CC). Thevoltage across the switch begins to increase, forcingthe "source" node towards the lower supply railfrom its initial amplitude of Vcr. The transformerprimary voltage similarly begins to collapse, butnote that the magnetizing current is still increasingfrom its level at time t5. Even though the voltageacross the magnetizing inductance is decreasing,there is still voltage across it until time t6 causingthe current to increase, but at a reduced rate.

Note also that a change has occurred in the draincurrent of the main switch, QA. No current wasflowing in the device during the previous intervaltiming, but it does begin at time t5. The drain ofQA was held at the clamp voltage (Vcr) while theclamp/reset switch QC was ON until 15. Onceturned off, the primary current simultaneous chargesthe clamp switch output capacitor (CC) and dis-charges the main switch output capacitance CA.Since these are modelled in parallel, the totalprimary current is divided between the two circuits

as determined by the ratio of their output capaci-tances. The point here is that QA instantly seessome of the primary current to discharge its outputcapacitance which continues through this, and thenext timing interval.

Over on the secondary side, nothing has changedsince the last interval. The output inductor isdischarging its stored energy, released as a "con-stant" output current. Diode D2 is commutating thiscurrent to the load, and D 1 is off and reversedbiased.

This interval concludes at time t6 when thevoltage across the transformer is zero and theprimary current has reached its lowest negativevalue (Ir) for the switching cycle.

RESONANT TRANSITION:Figure 16, t6 < t < t7

The transition momentum established in theprevious timing interval continues through this oneas well, but with a few minor differences. First,notice that the primary current has reversed itsslope, and, although negative, is now headed backtowards zero. The transformer voltage reverses aswell, since the transitioning node starts out at Vinand goes to zero at time t7. This will position itwith the full input supply voltage across it, and novoltage across the main switch at the conclusion ofthe cycle.

This resonant interval is fueled by the energystored in the magnetizing inductance from theActive Reset interval. Enough inductive energymust have been stored to overcome the opposingcapacitive energy requirements of the two MOSFETswitches, QA and QC. To accommodate all operat-ing conditions, it is likely that the primary currentat time t7 will always be small, but non-zero tofacilitate ZVT. Any excess current will be funneledto the body diode of QA at time t7 for the mainswitch, and will go towards recharging the clampcapacitor voltage (Vcr) at the clamp/reset switchposition. What is beneficial is that the peak to peakmagnetizing current is constant over line and loadconditions in normal operation, so little overdesignis necessary .

Depending on the secondary circuit inductanceand coupling to the primary winding, the loadFig 15. -Resonant Transition --t5 < t < t6


Oc Cc DcT1 01 ~

~ o

.) .011 .0 02 GO?

i 17 0 16 & 17

will occur at some point during this or the nextinterval, it's obvious that this condition will not lastfor long as it might in other topologies and adapta-tions. Since numerous possibilities exist dependingon the exact transformer coupling, circuit parasiticsand potential use of external series inductances, itis best to leave this section for a more detailedanalysis by the user.

When time t7 is reached, the main switch QA ispositioned with zero volts across it due to the activereset technique and resonant circuit elements. Theactive clamp/reset switch is positioned to its highestamplitude with the full input and clamp voltageacross its drain to source terminals. Current flowingis very low and is used to maintain the switchesclamped in this position.

VIN;

81 17

Depending on leakage

CIRCULA nON INTERV AL:Figure 17, t7 < t < t8

This brief interval lasts between the time themain switch is completely positioned with zerovolts across it and when it is turned ON at time t8.Basically, this interval is used to accommodate allresonant circuit tolerances, ranges of input voltageand magnetizing current. Very liltle activity takes

Fig 16. -Resonant Transition --t6 < t < tl

cUlTent could transfer from D2 to D I during thisinterval. After all, the transformer primary voltagehas reached the same amplitude that it does fornormal operation, however notice that the current isreversed. Its clear that no power is being transferredfrom the primary to the secondary , however thesecondary voltage could be identical to that whileQA is on. Two situations are most prominent forthe load side. One is that the load current complete-ly transfers from diode D2 to Dl, but this wouldcouple back to the primary in opposition to theresonant tank cUlTent, and dominate. The effect ofthis would be to re-position the main switch withthe full input voltage across it, and the benefits ofZVT will go unrealized. The other situation is thatdiode D2 conducts the complete current and diodeDl is fully off. This would infer some rather lousy(bad) coupling between the transformers primaryand secondary windings, which is possible. Severalapproaches to this Active reset technique introduceseries inductance on the secondary side to properlyexecute and attain this transition and are listed inthis topic's Appendix for further information. Athird, but remote possibility is that both Dl and D2conduct half of the load current each. While this

t7 t8

OFF ---

VCA=O ---

ON ---

~UA

t7 18

OFF

Vcc .VCR .VIN

OFF

QN--- 1.101?

I IPRI

Fig 17. Circulation Interval --t7 < t < tB


place on the primary side since the last interval, butthe previously stated issue of secondary side CUf-rents applies to this interval as well. For the mostpart, the circuit simply "coasts" along until themain switch is re-asserted at time t8, or tO of thesuccessive switching cycle.

Details of the individual current paths withineach of the switches is displayed in Figure 18 and19.

gate drive outputs. The circuitry used to decipherthe two gate drives and timing delays for this, andother ZVT applications are built into these driverICs which also feature high current, MOSFETcompatible gate drive outputs. Although all of theachievable benefits from higher frequency operationmay not be realizable with this approach, it offersa quick evaluation of the technique with a minorengineering effort.

ZVT Limitations: As with other Zero VoltageSwitching (ZVS), Zero Current Switching (ZCS),Zero Voltage Transitions (ZVT) and Multi-ResonantConverter (MRC) designs, this active reset tech-nique also has limitations because of the resonanttank circuit requirements. As previously stated, themain limitation is the ability to store enough induc-tive energy in the leakage and magnetizing induc-tances to overcome the opposing capacitive energydemands of the MOSFET output capacitances. Whatis favorable, however, is that the peak magnetizingcurrent is constant with the converter in regulation,and so too is the stored inductive energy. The

Practical Design ConsiderationsThere's plenty to gain in efficiency, power

density and reduced EMI/RFI by switching aconventional forward converter design to this activeclamp/reset technique. For comparison, one place tostart is with an existing power supply. Each of theprevious items should be measured and character-ized for a conclusive, apples-to-apples comparison.What will be required is an additional switch,capacitor, gate drive solution and some control ordrive circuitry .One approach is to add these com-ponents on a circuit board which can be wired intothe existing unit. Advanced driver ICs, for example,the UC3714 and UC3715 are available to andconvert a generic PWM input into the two required

...ClOCK: 1 :

...VQ8QC : ~ ~ ~

VO:::~ :; : ~ : tf,-CL-

.

~~

mIPPK ..; ,IPN lu

O

-I. .:...:: : .

::.:.:f:.:::.!::.:.:

Icoa8 O T""C .; .

; : : ~ : :-r: .

~ lDIOOE O : : 1 i p

0. .' , j...:..~..j...[..t ~

.~

IR :.r ~..f : : + r..: ICHA~~:...I ji~:i i;..: lac O : i. ...:

1...~ : " : 1..s 1171

Main Switch Waveforms (Qa)

,..

t -0

Fig 19.

j-.i...f.i..j [.~.r.f '2 3 4 5 8 78

Clamp Switch Waveforms (Oc)

-,- .

.

...:~ I. .

Fig 18. -

Active ClamD/Reset Enhances Converter Performance 3-15

obstructing capacitive load of the switches, andtransfonner primary is constant as well. Therefore,once designed properly, the circuit will resonate tofacilitate the zero voltage transitions over all lineand load conditions. This relationship is identified

by:

LmagoImag2/2+LlkgoIpri2/2 > Cro(Vin+ Vcr)2/2

where Cr is the total resonant capacitance, theparallel combination of the two MOSFET outputcapacitors in parallel with the transformer primary

capacitanceThe magnetizing current is totally dependant on

the exact transformer design, a function of theferrite material permeability and number of turns.Leakage inductance is effected by the windingdesign and technique, and the energy is effected bythe output load current (squared) reflected to theprimary .This term will go towards zero when theload current decreases, so don't rely on it to makethe transitions possible at light load. Magnetizinginductance is the more significant energy term asfar as limiting factors are concerned.

the main switch turns off, the transformer resetsdown the B-H curve back towards the ferritematerial's residual flux density, Br. The "negative"voltage across the primary facilitates this reset, andthe magnetizing current reduces until it reacheszero. At this point, reset is complete, and this iswhen the main switch drain voltage will drop to theinput voltage, Vin, in a standard design. Operationis primarily limited to the first quadrant of the B- Hcurve, although any parasitic oscillations could pushit into the second quadrant for a brief time. Asevere resonance could extent this into the thirdquadrant, but this is unlikely to occur in mostdesigns because of EM! considerations.

The active reset/clamp technique is significantlydifferent from this description following the drivensection of the fIrSt quadrant operation. When themain switch turns off, the voltage across the prima-ry reverses, just like the conventional approach. Themagnetizing current decreases when the transformerprimary voltage reverses, which continues until it'sclamped by the clamp/reset capacitor, Cr. Up to thispoint, the two techniques are the same until themagnetizing current reaches zero.

By design, just prior to the magnetizing currentreaching zero the clamp/reset switch is turned onand the device channel is on, and in parallel withthe body diode. The stage has now been set for abidirectional flow of current as opposed to thefunction of the diode in the conventional type

B-H CharacteristicsOne area which is significantly different between

the Active clamp/reset technique and its predeces-sors is found in the transformer's B-H curve opera-tion. In most conventional designs, the transformeris driven in the first quadrant where both H (am-pere-tums) and B (flux density) are positive. When

..

I

-T

//

B8AT

Fig 20. -B-H Curve Differences B-H Curve Operational DifferencesFig 21


converters. Now, current reverses and is drivennegatively by the clamp voltage applied across thetransfonner primary , thus driving the core into thesecond, then third quadrant. Current continues tobuild while the switch is on, and energy is trans-ferred from the clamp/reset capacitor to the magne-tizing inductance. The significant difference withthis approach is the ability to drive into the thirdquadrant, necessary to facilitate the zero voltagetransition when later released. A comparison of theB-H characteristics is shown in Figures 20 and 21.

on the copper used in each winding and still fit intothe existing bobbin window, reducing copper losses.

Semiconductor StressVoltage stresses on the primary side power semi-

conductors are either the same, or lower than in aconventional square wave design. As indicated bythe waveforms, the peak voltage is actually reducedin comparison to the standard design and there's nopenalty of higher currents as seem in a zero currentswitched converter, nor higher voltages of thevariable frequency, zero voltage switched designs.Conduction losses in the transformer and switchbody diode will be slightly higher due to transfer-ring of energy during times where the previouscurrent was zero. However, these losses should befairly low since the reset magnetizing current is asmall percentage of the typical load current. Noth-ing should be different on the secondary side of theisolation boundary as far as the rectifiers currentratings are concerned, although lower reversevoltage rating is possible.

Core Losses and ConsiderationsThis third quadrant operation will NOT lead to

higher core losses than the conventional designs,despite false, but perceived higher voyage in fluxdensity. Here's why. When the main switch is on,B-H operation is in the upper right handed direc-tion, but usually occurring in the first quadrantonly. Whatever amount of change in B, or H tookplace still does, only it doesn't begin from where itdid before at the residual flux density, Br. With theactive clamp/reset technique, operation begins fromthe third quadrant when the main switch is turnedon. Normal operation is now centered about the B-H axis origins instead of somewhere in the firstquadrant. The net changes in B, and H, are thesame, assuming that same volt-second product isapplied to the b"ansformer, which is the case tomaintain regulation of the output. So delta B, hencecore losses are the same, and there is no penalty incore losses for the different mode of operation.

At lower frequencies, or with better core materi-als where core loss is not the dominant factor, theactive reset technique offers the benefit of higherflux density swings. By the operating characteristicjust described, the core can now be used at doubleits first quadrant ability as the total flux densityswing encompasses both first and third quadrantoperation. Theoretically, it allows complete opera-tion from the negative to positive saturation fluxdensities, -Bsat to +Bsat, although that's stretchingthings a bit. Nevertheless, this mode of operationallow reducing the number of turns in each windingby half. Assuming the magnetizing current isnegligible in comparison to the load current, thiswider operation provides the means to "double-up"

Increases in EfficiencyThe fIrst obvious improvement will be the

absence of MOSFET tum-on loss, specifically theone caused by discharging its own output capaci-tance, CA, The savings realized is:

Pcoss(QA) = Coss. Vin2/2 .Fconv

This corresponds to about 3.2 watts saved at highline in an off-line application switching at 250 kHz.For supplies under 100 watts, this amounts to a

significant savings.Power savings can amount to a bit more if an

external capacitor was placed in parallel with theMOSFET to reduce turn-off losses. This commondesign practice slows the voltage rise across thedevice's terminals which does reduce power lossassuming that the current is the same. One problemwith this, however, is what transpires at tum-on ofthe same switch. Any capacitance across the drainto source is dissipatively discharged by the switchthe next time it turns on. This would be eliminatedcompletely with the active reset control technique.


Finally, the elimination of the switching powerlost at turn on due to the simultaneous overlap offalling drain voltage and rising drain current willamount to a few watts saved in most designs. Sincethis loss is dependant on each applications specificpower requirements, gate drive and parasitic ele-ments, it becomes difficult to globally quantify. Butsmall as it might be, it does exist and will beeliminated as the resonant tank positions the mainswitch to zero voltage.

References:

1. CARSTEN, Bruce, "Design Techniques forTransfonner Active Reset Circuits at High Frequen-cies and Power Levels," High Frequency PowerConversion Proceedings. 1990 pages 235-246

2. JITARU, I. (Dan), "Zero Voltage PWM, DoubleEnded Converter," High Frequency Power Conver-sion Proceedings, 1992 pages 394-404

3. LEE, HUA, LEU, "Comparison of ForwardTopologies with Various Reset Schemes,"1991 VPEC Seminar Proceedings. pages 101-109,Virginia Power Electronics Center, Virginia Tech,Blacksburg, Virginia (USA) phone 1-703-231-4536

Other ApplicationsThe most likely extension of this technology is

for use in the Flyback converter. There will besignificant differences in the power waveformsbecause the flyback is an energy storage techniqueas opposed to the forward's energy transfer ap-proach. However, the basic power stage schematicand gate drive timing relationships are still applica-ble.

SummarySignificant advantages in performance and

efficiency can be realized with the activeclamp/reset technique in comparison to the conven-tional approach. It does require an additionalisolated MOSFET switch and modifications to thecontroVdrive circuitry to accommodate the addition-al switch and delay times. However, it does openthe door to much higher frequency operation withhigher efficiency and lower EMI/RFI, ultimatelyresulting in higher power density .As existing powersupply designs are stretched even further for higherpower and reduced size and cost, numerous techni-cal obstacles are bound to derail the progression be-yond some point. And as this day draws closer,advanced switching technologies like this activeclamp/reset technique, and other ZVT adaptations,are destined to command designers' attention.


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