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a Ultralow Input Bias CurrentOperational Amplifier
AD549*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
PRODUCT DESCRIPTIONThe AD549 is a monolithic electrometer operational amplifierwith very low input bias current. Input offset voltage and inputoffset voltage drift are laser trimmed for precision performance.The AD549’s ultralow input current is achieved with “Topgate”JFET technology, a process development exclusive to AnalogDevices. This technology allows the fabrication of extremely lowinput current JFETs compatible with a standard junction-isolated bipolar process. The 1015 Ω common-mode impedance,a result of the bootstrapped input stage, ensures that the inputcurrent is essentially independent of common-mode voltage.
The AD549 is suited for applications requiring very low inputcurrent and low input offset voltage. It excels as a preamp for awide variety of current output transducers, such as photodiodes,photomultiplier tubes, or oxygen sensors. The AD549 can alsobe used as a precision integrator or low droop sample and hold.The AD549 is pin-compatible with standard FET and electrom-eter op amps, allowing designers to upgrade the performanceof present systems at little additional cost.
The AD549 is available in a TO-99 hermetic package. The caseis connected to Pin 8 so that the metal case can be independentlyconnected to a point at the same potential as the input termi-nals, minimizing stray leakage to the case.
*Protected by Patent No. 4,639,683.
The AD549 is available in four performance grades. The J, K,and L versions are rated over the commercial temperaturerange 0°C to +70°C. The S grade is specified over the militarytemperature range of –55°C to +125°C and is available processedto MIL-STD-883B, Rev C. Extended reliability plus screening isalso available. Plus screening includes 168-hour burn-in, as wellas other environmental and physical tests derived fromMIL-STD-883B, Rev C.
PRODUCT HIGHLIGHTS1. The AD549’s input currents are specified, 100% tested, and
guaranteed after the device is warmed up. Input current isguaranteed over the entire common-mode input voltage range.
2. The AD549’s input offset voltage and drift are lasertrimmed to 0.25 mV and 5 µV/°C (AD549K), and 1 mVand 20 µV/°C (AD549J).
3. A maximum quiescent supply current of 700 µA minimizesheating effects on input current and offset voltage.
4. AC specifications include 1 MHz unity gain bandwidth and3 V/µs slew rate. Settling time for a 10 V input step is5 µs to 0.01%.
5. The AD549 is an improved replacement for the AD515, the OPA104, and the 3528.
NOTESAll min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used tocalculate outgoing quality levels.1Bias current specifications are guaranteed after five minutes of operation at T A = +25°C. Bias current increases by a factor of 2.3 for every 10°C rise in temperature.2Input offset voltage specifications are guaranteed after five minutes of operation at T A = +25°C.3Defined as max continuous voltage between the inputs such that neither input exceeds ± 10 V from ground.
Specifications subject to change without notice.
METALLIZATION PHOTOGRAPHDimensions shown in inches and (mm)Contact factory for latest dimensions.
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
NOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only and functional operation ofthe device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.
2For supply voltages less than ± 18 V, the absolute maximum input voltage is equalto the supply voltage.
AD549
REV. B –3–
WARNING!
ESD SENSITIVE DEVICE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD549 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.
AD549–Typical Performance Characteristics
SUPPLY VOLTAGE – V
INP
UT
VO
LTA
GE
– V
20
15
10
5
00 5 10 15 20
+VIN
–VIN
TPC 1. Input Voltage Range vs. Supply Voltage
SUPPLY VOLTAGE V
800
700
600
500
400
AM
PL
IFIE
R Q
UIE
SC
EN
T C
UR
RE
NT
–
A
0 5 10 15 20
TPC 4. Quiescent Currentvs. Supply Voltage
TEMPERATURE – C
3000
OP
EN
-LO
OP
GA
IN –
V/m
V
–55 –25 5 35 65 95 125
1000
300
100
TPC 7. Open-Loop Gain vs.Temperature
REV. B–4–
SUPPLY VOLTAGE – V
20
15
10
5
0
OU
TP
UT
VO
LTA
GE
SW
ING
– V
0 5 10 15 20
+VOUT
–VOUT
+25 CRL = 10k
TPC 2. Output Voltage Swing vs. Supply Voltage
INPUT COMMON-MODE VOLTAGE – V
120
100
90
80
70
CO
MM
ON
-MO
DE
RE
JEC
TIO
N R
AT
IO –
dB
–15 –10 0 +10 +15
110
TPC 5. CMRR vs. Input Common-Mode Voltage
WARMUP TIME – Minutes
30
|V
OS| –
µV
0 1 2 3 4 5 6 7
25
20
15
10
5
0
TPC 8. Change in OffsetVoltage vs. Warmup Time
LOAD RESISTANCE –
30
25
20
10
010 100 1k 10k 100k
5
15
OU
TP
UT
VO
LTA
GE
SW
ING
– V
p-p VS = 15 V
TPC 3. Output VoltageSwing vs. Load Resistance
SUPPLY VOLTAGE – V
3000
OP
EN
-LO
OP
GA
IN –
V/m
V
0 5 10 15 20
1000
300
100
TPC 6. Open-Loop Gain vs.Supply Voltage
COMMON-MODE VOLTAGE – V
50
INP
UT
CU
RR
EN
T –
fA
–10 –5 0 5 10
40
35
20
30
25
45
TPC 9. Input Bias Current vs. Common-Mode Voltage
AD549
REV. B –5–
POWER SUPPLY VOLTAGE – V
50
INP
UT
CU
RR
EN
T –
fA
0 5 10 15 20
40
35
20
30
25
45
TPC 10. Input Bias Current vs. Supply Voltage
FREQUENCY – Hz
100
80
60
40
–40
OP
EN
-LO
OP
GA
IN –
dB
10 100 1k 10k 100k 1M 10M
20
0
–20
100
80
60
40
–40
20
0
–20
PH
AS
E M
AR
GIN
– D
egre
es
TPC 13. Open-Loop FrequencyResponse
FREQUENCY – Hz
120
100
80
60
–20
PS
RR
– d
B
10 100 1k 10k 100k 1M 10M
40
20
0
+ SUPPLY
– SUPPLY
TPC 16. PSRR vs. Frequency Frequency Response
FREQUENCY – Hz
160
140
120
80
40
10 100 1k 10k
60
100
NO
ISE
SP
EC
TR
AL
DE
NS
ITY
– n
V/
Hz
20
TPC 11. Input Voltage Noise Spectral Density
OU
TP
UT
VO
LT
AG
E S
WIN
G –
V
FREQUENCY – Hz
40
35
30
20
10
10 100 1k 10k 100k 1M
15
25
5
0
TPC 14. Large SignalFrequency Response
SETTLING TIME – s
10
5
0
–5
–10
OU
TP
UT
VO
LT
AG
E S
WIN
G –
V
0 1 2 3 4 5
5mV
10mV
1mV
1mV
5mV
10mV
TPC 17. Output Voltage Swing and Error vs.
Settling Time
SOURCE RESISTANCE –
100k
INP
UT
NO
ISE
VO
LT
AG
E –
V
p-p
100k 1M 10M 100M 1G 10G 100G
1k
100
0.1
10
1
10k
RESISTORJOHNSON NOISE
WHENEVER JOHNSON NOISE IS GREATER THANAMPLIFIER NOISE, AMPLIFIER NOISE CAN BECONSIDERED NEGLIGIBLE FOR THE APPLICATION
1kHz BANDWIDTH
10HzBANDWIDTH
AMPLIFIER GENERATED NOISE
TPC 12. Noise vs. SourceResistance
FREQUENCY – Hz
100
80
60
40
CM
RR
– d
B10 100 1k 10k 100k 1M 10M
20
0
–20
TPC 15. CMRR vs. Frequency
AD549
REV. B–6–
TPC 18. Unity Gain Follower
TPC 21. Unity Gain Inverter
TPC 19. Unity Gain Follower Large Signal Pulse Response
TPC 22. Unity Gain Inverter Large Signal Pulse Response
TPC 20. Unity Gain Follower Small Signal Pulse Response
TPC 23. Unity Gain Inverter Small Signal Pulse Response
MINIMIZING INPUT CURRENTThe AD549 has been optimized for low input current and offsetvoltage. Careful attention to how the amplifier is used will reduceinput currents in actual applications.
The amplifier operating temperature should be kept as low aspossible to minimize input current. Like other JFET input am-plifiers, the AD549’s input current is sensitive to chip tempera-ture, rising by a factor of 2.3 for every 10°C rise. Figure 1 is a plotof AD549’s input current versus its ambient temperature.
TEMPERATURE – C
1nA
100pA
10pA
1fA–55 –25 5 35 65 95 125
1pA
100fA
10fA
Figure 1. Input Bias Current vs.Ambient Temperature
On-chip power dissipation will raise the chip operating temperature,causing an increase in the input bias current. Due to the AD549’slow quiescent supply current, the chip temperature when the(unloaded) amplifier is operating with 15 V supplies is less than3°C higher than its ambient temperature. The difference in theinput current is negligible.
However, heavy output loads can cause a significant increasein chip temperature and a corresponding increase in the inputcurrent. Maintaining a minimum load resistance of 10 Ω isrecommended. Input current versus additional power dissipa-tion due to output drive current is plotted in Figure 2.
ADDITIONAL INTERNAL POWER DISSIPATION – mW
6.0
5.0
4.0
1.0 0 25 50 75 100 125 150 175 200
3.0
2.0
NO
RM
AL
IZE
D IN
PU
T B
IAS
CU
RR
EN
T
BASED ON TYPICAL IB = 40fA
Figure 2. Input Bias Current vs.Additional Power Dissipation
CIRCUIT BOARD NOTESThere are a number of physical phenomena that generatespurious currents that degrade the accuracy of low currentmeasurements. Figure 3 is a schematic of an I-to-V converterwith these parasitic currents modeled.Finite resistance from input lines to voltages on the board,modeled by resistor RP, results in parasitic leakage. Insulationresistance of over 1015 Ω must be maintained between theamplifier’s signal and supply lines in order to capitalize on theAD549’s low input currents. Standard PC board material
AD549
REV. B –7–
width and the stability of the I-to-V converter. The case of the AD549is connected to Pin 8 so that it can be bootstrapped near the inputpotential. This minimizes pin leakage and input common-modecapacitance due to the case. Guard schemes for inverting andnoninverting amplifier topologies are illustrated in Figures 4 and 5.
Figure 4. Inverting Amplifier with Guard
Figure 5. Noninverting Amplifier with Guard
Other guidelines include keeping the circuit layout as compactas possible and keeping the input lines short. Keeping the as-sembly rigid and minimizing sources of vibration will reduce tri-boelectric and piezoelectric effects. All precision, highimpedance circuitry requires shielding against interferencenoise. Low noise coaxial or triaxial cables should be used for re-mote connections to the input signal lines.
OFFSET NULLINGThe AD549’s input offset voltage can be nulled by using balancePins 1 and 5, as shown in Figure 6. Nulling the input offset volt-age in this fashion will introduce an added input offset voltagedrift component of 2.4 µV/°C per millivolt of nulled offset(a maximum additional drift of 0.6 µV/°C for the AD549K,1.2 µV/°C for the AD549L, and 2.4 µV/°C for the AD549J).
Figure 6. Standard Offset Null Circuit
The approach in Figure 7 can be used when the amplifier isused as an inverter. This method introduces a small voltagereferenced to the power supplies in series with the amplifier’spositive input terminal. The amplifier’s input offset voltage driftwith temperature is not affected. However, variation of thepower supply voltages will cause offset shifts.
does not have high enough insulation resistance. Therefore,the AD549’s input leads should be connected to standoffsmade of insulating material with adequate volume resistivity(e.g., Teflon). The surface of the insulator’s surface must bekept clean in order to preserve surface resistivity. For Teflon, aneffective cleaning procedure consists of swabbing the surfacewith high grade isopropyl alcohol, rinsing with deionized water,and baking the board at 80°C for 10 minutes.
Figure 3. Sources of Parasitic Leakage Currents
In addition to high volume and surface resistivity, other propertiesare desirable in the insulating material chosen. Resistance to waterabsorption is important since surface water films drastically reducesurface resistivity. The insulator chosen should also exhibit minimalpiezoelectric effects (charge emission due to mechanical stress) andtriboelectric effects (charge generated by friction). Charge imbal-ances generated by these mechanisms can appear as parasitic leak-age currents. These effects are modeled by variable capacitor CP inFigure 3. Table I lists various insulators and their properties.*
Table I. Insulating Materials and Characteristics
Volume Minimal Minimal ResistanceResistivity Triboelectric Piezoelectric to Water
Material (V–CM) Effects Effects Absorption
Teflon® 1017–1018 W W GKel-F® 1017–1018 W M GSapphire 1016–1018 M G GPolyethylene 1014–1018 M G MPolystyrene 1012–1018 W M MCeramic 1012–1014 W M WGlass Epoxy 1010–1017 W M WPVC 1010–1015 G M GPhenolic 105–1012 W G W
G–Good with Regard to Property
M–Moderate with Regard to Property
W–Weak with Regard to Property
Guarding the input lines by completely surrounding them with ametal conductor biased near the input lines’ potential has twomajor benefits. First, parasitic leakage from the signal line isreduced since the voltage between the input line and the guardis very low. Second, stray capacitance at the input node is mini-mized. Input capacitance can substantially degrade signal band
*Electronic Measurements, pp. 15–17, Keithley Instruments, Inc., Cleveland,Ohio, 1977.
Teflon is a registered trademark of E.I. du Pont de Nemours and Company.Kel-F is a registered trademark of 3M Company.
AD549
REV. B–8–
Figure 7. Alternate Offset Null Circuit for Inverter
AC RESPONSE WITH HIGH VALUE SOURCE ANDFEEDBACK RESISTANCESource and feedback resistances greater than 100 kΩ will magnifythe effect of the input capacitances (stray and inherent to the AD549)on the ac behavior of the circuit. The effects of common-mode anddifferential input capacitances should be taken into account sincethe circuit’s bandwidth and stability can be adversely affected.
Figure 8. Follower Pulse Response from 1 MΩ Source Resistance, Case Not Bootstrapped
Figure 9. Follower Pulse Response from 1 MΩ Source Resistance, Case Bootstrapped
In a follower, the source resistance and input common-modecapacitance form a pole that limits the bandwidth to 1/2 π RS CS.Bootstrapping the metal case by connecting Pin 8 to the output mini-mizes capacitance due to the package. Figures 8 and 9 show thefollower pulse response from a 1 MΩ source resistance with andwithout the package connected to the output. Typical common-modeinput capacitance for the AD549 is 0.8 pF.
In an inverting configuration, the differential input capacitanceforms a pole in the circuit’s loop transmission. This can createpeaking in the ac response and possible instability. A feedbackcapacitance can be used to stabilize the circuit. The inverterpulse response with RF and RS equal to 1 MΩ appears in Figure 10.Figure 11 shows the response of the same circuit with a 1 pFfeedback capacitance. Typical differential input capacitance forthe AD549 is 1 pF.
COMMON-MODE INPUT VOLTAGE OVERLOADThe rated common-mode input voltage range of the AD549 isfrom 3 V less than the positive supply voltage to 5 V greaterthan the negative supply voltage. Exceeding this range willdegrade the amplifier’s CMRR. Driving the common-modevoltage above the positive supply will cause the amplifier’soutput to saturate at the upper limit of the output voltage.Recovery time is typically 2 µs after the input has been returnedto within the normal operating range. Driving the inputcommon-mode voltage within 1 V of the negative supplycauses phase reversal of the output signal. In this case, normaloperation is typically resumed within 0.5 µs of the input voltagereturning within range.
Figure 10. Inverter Pulse Response with 1 MΩ Source and Feedback Resistance
Figure 11. Inverter Pulse Response with 1 MΩ Source and Feedback Resistance, 1 pF Feedback Capacitance
DIFFERENTIAL INPUT VOLTAGE OVERLOADA plot of the AD549’s input currents versus differential input voltage(defined as VIN+ – VIN–) appears in Figure 12. The input current ateither terminal stays below a few hundred femtoamps until one in-put terminal is forced higher than 1 V to 1.5 V above the other termi-nal. Under these conditions, the input current limits at 30 µA.
DIFFERENTIAL INPUT VOLTAGE – V (VIN+ – VIN
–)
100
10
1
–5 –4 –3 –2 –1 0 1 2 3 4 5
INP
UT
CU
RR
EN
T –
Am
ps
100n
10n
1n
100p
10p
1p
100f
10f
IIN– IIN+
Figure 12. Input Current vs. Differential Input Voltage
AD549
REV. B –9–
INPUT PROTECTIONThe AD549 safely handles any input voltage within the supplyvoltage range. Subjecting the input terminals to voltages beyondthe power supply can destroy the device or cause shifts in inputcurrent or offset voltage if the amplifier is not protected.
A protection scheme for the amplifier as an inverter is shown inFigure 13. RP is chosen to limit the current through the invert-ing input to 1 mA for expected transient (less than 1 second)overvoltage conditions, or to 100 µA for a continuous overload.Since RP is inside the feedback loop, and is much lower in valuethan the amplifier’s input resistance, it does not affect theinverter’s dc gain. However, the Johnson noise of the resistorwill add root sum of squares to the amplifier’s input noise.
Figure 13. Inverter with Input Current Limit
In the corresponding version of this scheme for a follower,shown in Figure 14, RP and the capacitance at the positive inputterminal will produce a pole in the signal frequency response ata f = 1/2 π RC. Again, the Johnson noise RP will add to theamplifier’s input voltage noise.
Figure 14. Follower with Input Current Limit
Figure 15 is a schematic of the AD549 as an inverter with aninput voltage clamp. Bootstrapping the clamp diodes at theinverting input minimizes the voltage across the clamps andkeeps the leakage due to the diodes low. Low leakage diodes,such as the FD333s, should be used and should be shieldedfrom light to keep photocurrents from being generated. Evenwith these precautions, the diodes will measurably increase theinput current and capacitance.
Figure 15. Input Voltage Clamp with Diodes
SAMPLE AND DIFFERENCE CIRCUIT TO MEASUREELECTROMETER LEAKAGE CURRENTSThere are a number of methods used to test electrometer leak-age currents, including current integration and direct current tovoltage conversion. Regardless of the method used, board andinterconnect cleanliness, proper choice of insulating materials(such as Teflon or Kel-F), correct guarding and shieldingtechniques, and care in physical layout are essential to makingaccurate leakage measurements.
Figure 16 is a schematic of the sample and difference circuit. Ituses two AD549 electrometer amplifiers (A and B) as current-tovoltage converters with high value (1010 Ω) sense resistors (RSaand RSb). R1 and R2 provide for an overall circuit sensitivity of10 fA/mV (10 pA full scale). CC and CF provide noise suppressionand loop compensation. CC should be a low leakage poly-styrene capacitor. An ultralow leakage Kel-F test socket is usedfor contacting the device under test. Rigid Teflon coaxial cableis used to make connections to all high impedance nodes. Theuse of rigid coaxial cable affords immunity to error induced bymechanical vibration and provides an outer conductor forshielding. The entire circuit is enclosed in a grounded metalbox.
Figure 16. Sample and Difference Circuit for MeasuringElectrometer Leakage Currents
The test apparatus is calibrated without a device under testpresent. A five-minute stabilization period after the power isturned on is required. First, VERR1 and VERR2 are measured.These voltages are the errors caused by the offset voltages andleakage currents of the current to voltage converters.
VERR1 = 10 (VOSA – IBA × RSa)
VERR2 = 10 (VOSB – IBB × RSb)
Once measured, these errors are subtracted from the readingstaken with a device under test present. Amplifier B closes thefeedback loop to the device under testing, in addition to providingthe current to voltage conversion. The offset error of the device
AD549
REV. B–10–
under testing appears as a common-mode signal and does not af-fect the test measurement. As a result, only the leakage currentof the device under testing is measured.
VA – VERR1 = 10[RSa × IB(+)]
VX – VERR2 = 10[RSb × IB(–)]
Although a series of devices can be tested after only one calibra-tion measurement, calibration should be updated periodically tocompensate for any thermal drift of the current to voltageconverters or changes in the ambient environment. Laboratoryresults have shown that repeatable measurements within 10 fAcan be realized when this apparatus is properly implemented.These results are achieved in part by the design of the circuit,which eliminates relays and other parasitic leakage paths in thehigh impedance signal lines, and in part by the inherent cancel-lation of errors through the calibration and measurementprocedure.
PHOTODIODE INTERFACEThe AD549’s low input current and low input offset voltagemake it an excellent choice for very sensitive photodiodepreamps (Figure 17). The photodiode develops a signal current,IS, equal to:
IS = R × P
where P is light power incident on the diode’s surface in wattsand R is the photodiode responsivity in amps/watt. RF convertsthe signal current to an output voltage:
VOUT = RF × IS
Figure 17. Photodiode Preamp
DC error sources and an equivalent circuit for a small area(0.2 mm square) photodiode are indicated in Figure 18.
Figure 18. Photodiode PreampDC Error Sources
Input current, IB, will contribute an output voltage error, VE1,proportional to the feedback resistance:
VE1 = IB × RF
The op amp’s input voltage offset will cause an error currentthrough the photodiode’s shunt resistance, RS:
I = VOS / RS
The error current will result in an error voltage (VE2) at theamplifier’s output equal to:
VE2 = ( I + RF / RS) VOS
Given typical values of photodiode shunt resistance (on theorder of 109 Ω), RF / RS can easily be greater than one, especiallyif a large feedback resistance is used. Also, RF / RS will increasewith temperature, since photodiode shunt resistance typicallydrops by a factor of 2 for every 10°C rise in temperature. An opamp with low offset voltage and low drift must be used in order tomaintain accuracy. The AD549K offers guaranteed maximum0.25 mV offset voltage and 5 mV/°C drift for very sensitiveapplications.
Photodiode Preamp NoiseNoise limits the signal resolution obtainable with the preamp.The output voltage noise divided by the feedback resistance isthe minimum current signal that can be detected. This minimumdetectable current divided by the responsivity of the photodioderepresents the lowest light power that can be detected by thepreamp.
Noise sources associated with the photodiode, amplifier, andfeedback resistance are shown in Figure 19; Figure 20 is thespectral density versus frequency plot of each of the noisesource’s contribution to the output voltage noise (circuit param-eters in Figure 18 are assumed). Each noise source’s rms contri-bution to the total output voltage noise is obtained by integratingthe square of its spectral density function over frequency. The rmsvalue of the output voltage noise is the square root of the sum of allcontributions. Minimizing the total area under these curveswill optimize the preamplifier’s resolution for a given bandwidth.
The photodiode preamp in Figure 17 can detect a signal currentof 26 fA rms at a bandwidth of 16 Hz, which, assuming a photo-diode responsivity of 0.5 A/W, translates to a 52 fW rms mini-mum detectable power. The photodiode used has a high sourceresistance and low junction capacitance. CF sets the signal band-width with RF and also limits the “peak” in the noise gain thatmultiplies the op amp’s input voltage noise contribution. Asingle pole filter at the amplifier’s output limits the op amp’soutput voltage noise bandwidth to 26 Hz, a frequency comparableto the signal bandwidth. This greatly improves the preamplifier’ssignal-to-noise ratio (in this case, by a factor of 3).
Figure 19. Photodiode Preamp Noise Sources
AD549
REV. B –11–
FREQUENCY – Hz
10
1
10n1 1M10
VO
LT
AG
E N
OIS
E C
ON
TR
IBU
TIO
NS
NO
ISE
SP
EC
TR
AL
DE
NS
ITY
– n
V/
Hz
100 1k 10k 100k
100n
IF AND CS, NO FILTERS
IF AND CS, WITH FILTERS
AD549OPEN-LOOP GAIN
EN CONTRIBUTION,NO FILTER
ENCONTRIBUTION,
WITH FILTER
Figure 20. Photodiode Preamp Noise Sources’ SpectralDensity vs. Frequency
Log Ratio AmplifierLogarithmic ratio circuits are useful for processing signals withwide dynamic range. The AD549L’s 60 fA maximum inputcurrent makes it possible to build a log ratio amplifier with 1%log conformance for input current ranging from 10 pA to 1 mA,a dynamic range of 160 dB.
The log ratio amplifier in Figure 21 provides an output voltageproportional to the log base 10 of the ratio of the input currentsI1 and I2. Resistors R1 and R2 are provided for voltage inputs.Since NPN devices are used in the feedback loop of the front-end amplifiers that provide the log transfer function, the outputis valid only for positive input voltages and input currents. Theinput currents set the collector currents IC1 and IC2 of amatched pair of log transistors Q1 and Q2 to develop voltagesVA and VB:
VA, B = – (kT / q) ln IC / IES
where IES is the transistors’ saturation current.
The difference of VA and VB is taken by the subtractor sectionto obtain:
VC = (kT / q) ln (IC2 / IC1)
VC is scaled up by the ratio of (R9 + R10)/R8, which is equal toapproximately 16 at room temperature, resulting in the outputvoltage:
VOUT = 1 × log (IC2 / IC1) V
R8 is a resistor with a positive 3500 ppm/°C temperature coeffi-cient to provide the necessary temperature compensation. Theparallel combination of R15 and R7 is provided to keep thesubtractor section’s gain for positive and negative inputs matchedover temperature.
Frequency compensation is provided by R11, R12, C1, and C2.The bandwidth of the circuit is 300 kHz at input signals greater than50 µA and decreases smoothly with decreasing signal levels.
To trim the circuit, set the input currents to 10 µA and trim A3’soffset using the amplifier’s trim potentiometer so the output equals0. Then set I1 to 1 µA and adjust the output to equal 1 V by trim-ming R10. Additional offset trims on the amplifiers A1 and A2 canbe used to increase the voltage input accuracy and dynamic range.
The very low input current of the AD549 makes this circuituseful over a very wide range of signal currents. The total inputcurrent (which determines the low level accuracy of the circuit)is the sum of the amplifier input current, the leakage across thecompensating capacitor (negligible if polystyrene or Tefloncapacitor is used), and the collector-to-collector and collector-to-base leakages of one side of the dual log transistors. Themagnitude of these last two leakages depend on the amplifier’sinput offset voltage and are typically less than 10 fA with 1 mVoffsets. The low level accuracy is limited primarily by theamplifier’s input current, only 60 fA maximum when theAD549L is used.
Figure 21. Log Ratio Amplifier
The effects of the emitter resistance of Q1 and Q2 can degradethe circuit’s accuracy at input currents above 100 µA. Thenetworks composed of R13, D1, R16, R14, D2, and R17compensate for these errors, so that this circuit has less than 1%log conformance error at 1 mA input currents. The correctvalue for R13 and R14 depends on the type of log transistorsused. 49.9 kΩ resistors were chosen for use with LM394 transis-tors. Smaller resistance values will be needed for smaller log tran-sistors.
TEMPERATURE COMPENSATEDpH PROBE AMPLIFIERA pH probe can be modeled as a mV-level voltage source with aseries source resistance dependent upon the electrode’s compo-sition and configuration. The glass bulb resistance of a typicalpH electrode pair falls between 106 Ω and 109 Ω. It is thereforeimportant to select an amplifier with low enough input currentssuch that the voltage drop produced by the amplifier’s inputbias current and the electrode resistance does not become anappreciable percentage of a pH unit.
AD549
REV. B–12–
The pH probe output is ideally 0 V at a pH of 7 independent oftemperature. The slope of the probe’s transfer function, thoughpredictable, is temperature dependent (–54.2 mV/pH at 0 and –74.04 mV/pH at 100°C). By using an AD590 temperature sen-sor and an AD535 analog divider, an accurate temperaturecompensation network can be added to the basic pH probe am-plifier. Table II shows voltages at various points and illustratesthe compensation. The AD549 is set for a noninverting gain of13.51. The output of the AD590 circuitry (Point C) will beequal to 10 V at 100°C and decrease by 26.8 mV/°C. Theoutput of the AD535 analog divider (Point D) will be a tempera-ture compensated output voltage centered at 0 V for a pH of 7and has a transfer function of –1.00 V/pH unit. The outputrange spans from –7.00 V (pH = 14) to +7.00 V (pH = 0).
Table II. Illustration of Temperature Compensation
PROBE A B C DTEMP (PROBE OUTPUT) (A 3 13.51) (590 OUTPUT) (10 B/C)
0 54.20 mV 0.732 V 7.32 V 1.00 V25°C 59.16 mV 0.799 V 7.99 V 1.00 V37°C 61.54 mV 0.831 V 8.31 V 1.00 V60°C 66.10 mV 0.893 V 8.93 V 1.00 V100°C 74.04 mV 1.000 V 10.00 V 1.00 V
The circuit in Figure 22 illustrates the use of the AD549 as apH probe amplifier. As with other electrometer applications, theuse of guarding, shielding, Teflon standoffs, and so on is a mustin order to capitalize on the AD549’s low input current. If anAD549L (60 fA max input current) is used, the error contributedby the input current will be held below 60 µV for pH electrodesource impedances up to 109 Ω. Input offset voltage (which canbe trimmed) will be below 0.5 mV.
Figure 22. Temperature Compensated pH Probe Amplifier
C00
511–
0–7/
02(B
)P
RIN
TE
D IN
U.S
.A.
OUTLINE DIMENSIONS
8-Lead Metal Can [TO-99]Dimensions shown in millimeters and (inches)
6.35 (0.2500) MIN
12.70 (0.5000)MIN4.70 (0.1850)
4.19 (0.1650)
REFERENCE PLANE
1.27 (0.0500) MAX
0.48 (0.0190)0.41 (0.0160)
0.53 (0.0210)0.41 (0.0160)1.02 (0.0400)
0.25 (0.0100)
1.02 (0.0400) MAX
BASE & SEATING PLANE
0.86 (0.0340)0.71 (0.0280)
1.14 (0.0450)0.69 (0.0270)
4.06 (0.1600)3.56 (0.1400)
2.54 (0.1000) BSC
6
2 8
7
5
4
3
1
5.08(0.2000)
BSC
2.54(0.1000)
BSC
45 BSC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
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