ADC12DxxxxRF Family:Features and Performance

February 2013

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Speaker bio: Marjorie Plisch

• Marjorie Plisch is an applications engineer in the High Speed Signal Path Group since 2007.

• She received her BSEE from the University of Illinois, Champaign-Urbana in 2001, a MAPS degree from Multnomah University in 2005, and an Multnomah University in 2005, and an MSEE degree from Oregon State University in 2007.

• Her interests include engineering education, testing and analysis of high-speed ADCs and high-speed ADC applications.

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Outline

• GSPS ADC Portfolio Overview and Architecture

• Applications

• Operating Modes and Features

• RF vs Non-RF 12-bit GSPS ADCs• RF vs Non-RF 12-bit GSPS ADCs

• Key Performance Metrics

• Tools Overview

• Common Questions

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Portfolio and Architecture OverviewPortfolio and Architecture Overview

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TI GSPS ADC Portfolio

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Configurable: 4.0/3.6/3.2/2.0/1.6/1.0 GSPS interleaved 2.0/1.8/1.6/1/0.8/0.5 GSPS dual ADC

Excellent performance beyond 2.7 GHz Excellent performance beyond 11th Nyquist zone Noise floor:

-154/-155/-154.6/-154/-152.2/-150.5dBm/Hz IMD3@2.7GHz:

-65/-64/-70/-69/-71/-69 dBcPower: 4.6/4.4/4.0/3.5/2.5/2.0W

RF-Sampling capability replaces entire IF- and ZIF-sampling subsystems of mixers, LO synthesizers, filters, amplifiers, and ADCs

Industry’s widest Nyquist zone of 2 GHz enables wideband software-defined radio (SDR) and allows combining multiple channels into one

Reduction in board area, cost, and complexity Pin-compatible family allows range of resolution

and speed-grade end-products

ADC12D2000/1800/1600/1000/800/500RFRF Sampling ADCs w/ Industry’s Largest Nyquist Zone

EVM: ADC12D2000RFRB, ADC12D1800RFRB, ADC12D1600RFRB, ADC12D800RFRB

Power: 4.6/4.4/4.0/3.5/2.5/2.0W AutoSync feature for multi-ADC applications* Pin-compatible w/ ADC12D1x00 & ADC10D1x00

3G/4G basestation receive & DPD Microwave backhaul RF-Sampling, wideband SDR T&M (scopes, data acquisition, analyzers)

Block Diagram GSPS ADC

• Key features:

– Dual channels or single, interleaved channel

– Internally terminated, buffered input impedance

– Option for output 1:2

Block diagram for ADC12DxxxxRF

– Option for output 1:2 demultiplexing

– 2x interleave per channel

– Exception is ADC12D800/500RF: 1x interleave per channel

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What architecture is used for the GSPS ADC family?

Pipelined architecture

• Often used for high-speed, medium-accuracy ADCs

• Theory of operation:– Determine MSB

– Subtract from Vin– Subtract from Vin

– Amplify and determine LSB

• Example shown is for a 2-stage, 8-bit ADC

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Diagram is from “Analog Integrated Circuit Design” by Johns and Martin, 1997; “Circuit Techniques for Low-voltage and High-speed A/D Converters” by Waltari and Halonen, 2002.

Flash-based architectures

• Basic Flash Architecture– Can achieve high sampling rates

with low conversion latency

– Basic design requires 2N

comparators and latches

– Drawbacks are high power consumption, die area

Flash ADC Implementation

• What techniques can make a 12-bit 3.6 GSPS ADC practically realizable?– Folding and interpolating to

improve power consumption, reduce area

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Diagrams are from “Analog Integrated Circuit Design” by Johns and Martin, 1997; “Circuit Techniques for Low-voltage and High-speed A/D Converters” by Waltari and Halonen, 2002.

Flash ADC Implementation

Folding-Interpolating Architecture

GSPS ADC Detailed Architecture

• Architecture employs integrated techniques:– Folding

– Interpolating

– Pipelining

• Additional techniques:– Calibration

– Interleaving

– Error Correction

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For more details on the GSPS ADC architecture, see “A 1.8V 1.0Gsps 10b Self-Calibrating Unified-Folding-Interpolating ADC with 9.1 ENOB at Nyquist Frequency” by R. Taft, et al. ISSCC 2009 / Session 4 / High-speed Data Converters.

Only one bank is shown, i.e. no interleaving in this diagram

ApplicationsApplications

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Applications

uWave BackhaulRadar

Comms & SIGINT

Media Servers /STB

Data Acq.Auto Radar

3G/4G Basestation

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Comms & SIGINT

FTTH

Game Systems

3G/4G Basestation

Test equipment

Wireless BasestationsReplaces IF-Sampling

DSP

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RF ADC

DSP

Old: IF-Sampling

New: RF-Sampling

Co

st

Are

a

Tim

e

Time Domain Applications

Example Time Domain Applications

Oscilloscopes

RADAR – Radio Detection And Ranging

LIDAR/LADAR – LIght/LAser Detection and RangingLIDAR/LADAR – LIght/LAser Detection and Ranging

Time of Flight Mass Spectrometry

High Speed Digitizers – Biotech, Semiconductors, Aerospace, Physics…

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Features for Time Domain Applications

Key Features for Time Domain Applications

DC coupled inputs

Capacity to Synchronize Multiple Converters

Adjustable Offset

Adjustable Full Scale Range

Adjustable Aperture Delay

Support for Trigger Functionality

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Operating Modes and FeaturesOperating Modes and Features

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Operating Modes – Inputs/Outputs

Input Mode Effective sample rate, each stream

Sampled input(I or Q)

Effective Differential Input Impedance

Non-DES Fclk Both, separately 100 Ohms

DES-I Fclk x 2 I 100 Ohms

DES-Q Fclk x 2 Q 100 Ohms

DES-IQ Fclk x 2 Both, in parallel 50 Ohms

DESCLK-IQ Fclk x 2 Both, in parallel 50 Ohms

Output Mode Data Update Rate Each Port DCLK Frequency

Non-Demux Fclk Fclk/2

1:2 Demux Fclk/2 Fclk/4

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Control Modes

Feature Control Mode

ExtendedControl Mode

Non-ECM(pin controlled)

DDR Clock Phase Yes DDRPh

Power Down Yes PDI, PDQ

AC/DC Coupled Input No Via Vcmo

Dual Channel / Interleaved Yes NoDual Channel / Interleaved Yes No

Initiate Calibration Yes CAL

Full Scale Range 15 bits FSR (High/Low)

Offset 12 bits + sign No

LVDS Output Amplitude 1 bit No

LVDS Output Common Mode No Via Vbg

1:2 Demux/Non-Demux No NDM

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DES Timing Adjust

• Interleaving the I- and Q-channels creates a spur at fs/2 – fin in part from timing mismatch.

• The timing mismatch refers to the skew, not jitter. It has static the skew, not jitter. It has static and dynamic components.

• The Duty Cycle Correct feature addresses the dynamic component and is continuously running.

• DES Timing Adjust addresses the static component.

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Time Stamp

What does this feature do? Time Stamp captures another input signal than the analog input and converts it with the same total latency as the analog input signal.

How does it work? When Time Stamp is enabled, the DCLK_RST+/- inputs are commandeered as the Time Stamp input and the converted signal appears input and the converted signal appears at the LSB of the ADC.

For which applications is this feature useful?

Time Stamp is useful for applications which need to capture a trigger signal relative to the analog input signal.

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Read/Write Calibration Vectors

• What happens during calibration?

– Trim internal bias currents, analog input and clock Rin.

• Why use this feature?

– Saves startup time after system deployment, e.g. ADC12D1000RF:

• tCAL = 5.2 * 107 Sampling Clock Cycles = 52ms• tCAL = 5.2 * 10 Sampling Clock Cycles = 52ms

• tREAD/WRITE = 240 SPI Write Cycles = 0.35ms

– Return to precisely same calibration vector, e.g. Rin.

• When may this feature be used?

– If the expected operating conditions, i.e. FSR, Temperature, DES/Non-DES Mode, Sampling Clock, are constant and result in a static calibration vector.

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AutoSync

What does this feature do? Synchronize multiple ADCs in a system.

How does AutoSync function?

1. Align Sampling Clock to each ADC to align DCLK edge.

2. Configure ADCs into Master or Slave.3. Reference Clock (RCLK) to each ADC

aligns DCLK phase.

Why is AutoSync better than DCLK Reset?

• RCLK generated by ADCs and configured in closed loop.DCLK Reset? closed loop.• AutoSync runs continuously and any errors can propagate out.

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RF versus non-RF 12-bit GSPS ADCsRF versus non-RF 12-bit GSPS ADCs

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Available Products

Non-RF 12-bit ADCs RF 12-bit ADCs

ADC12D500RF

ADC12D800RF

ADC12D1000 ADC12D1000RF

ADC12D1600 ADC12D1600RF

ADC12D1800 ADC12D1800RF

ADC12D2000RF

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Decoder Ring:ADC 12 D 1800 RFADC Number of Bits Dual channel MSPS rate Special tag

Major EnhancementsADC12Dxx00RF versus ADC12D1x00

Fewer interleaving spurs (ADC12D500/800RF only)

1

New DES mode2

Noise improvement3

Linearity improvement4

Fewer Interleaving SpursSingle-Bank Mode (ADC12D500/800RF only)

I1

I2

Q1

Q2In

terl

ea

ve

Inte

rle

ave

InI

InQ

OutI

OutQ

Non-DESSpurs & Images

DES Spurs & Images

•Fixed spurs at fS/2

• Images around fs/2

•Fixed spurs at fS/2, fS/4

• Images around fs/2, fS/4

ADC12D1x00ADC12D1x00

I

Q

InI

InQ

OutI

OutQ

•No fixed spurs

•No images

•Fixed spurs at fS/2

• Images around fs/2

ADC12D500RF/800RF

New, Higher-fIN DES ModeDESCLKIQ for Supporting Higher Input Frequencies

IQ

Clk

IQ

Clk

Non-DES

DESI / DESQ ADC1xD1x00 modes

IQ

Clk

IQ

Clk

DESIQ

NEWDESCLKIQ

Improves interleaved fIN

range > 100%

Noise Floor PerformanceN

ois

e d

en

sit

y

ADC16DV160 = -157 dBFS/Hz

ADC12D1800RF = -154 dBFS/HzADC12D1800 = -152.5 dBFS/Hz

No

ise d

en

sit

y

ADC16DV160 = -157 dBFS/Hz

RF parts improve noise floor 1-2 dB versus previous 12-bit GSPS ADCs

Linearity Improvement of New RF ProductsIMD3 @ 2.7 GHz input

6 – 9 dB improvement

at 2.7 GHz

Linearity Improvement of New RF ProductsIMD3 @ -7 dBFS Input Power

5-10 dB 5-10 dB improvement

over all frequencies

Key Performance MetricsKey Performance Metrics

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Full-Power Bandwidth (FPBW)

• As the frequency to the analog input of the ADC increases, so does the loss in signal level due to parasitic elements in the input network.

• The FPBW is traditionally the point at which this loss reaches 3dB.

• The ADC can be used beyond the • The ADC can be used beyond the 3dB point because the dynamic performance is still good, although the part must be driven harder.

• The FPBW is the same regardless of the Sampling Frequency because it is a function of the analog input.

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ADC12DxxxxRF excels at IMD3 performance

Noise Power Ratio Concept

• Noise Power Ratio (NPR) is how “quiet” one unused channel in a wideband system remains when the other channels cause noise in it due to inter-modulation.

• In a wideband system and in conjunction with the Noise Floor measurement, it is more appropriate than a simple IMD test as a measurement of system performance.

RMS Noise Level [dB]

Frequency fs/2

NPR

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Product NPR [dB]

ADC12D500RF 50.7

ADC12D800RF 50.4

Noise Spectral Density

• NSD is measured in [dBm/Hz] in the interleaved (DES Mode).

• This is a more useful wideband metric because the noise in any channel

Product NSD [dBm/Hz]

ADC12D500RF -150.5

ADC12D800RF -152.2

ADC12D1000RF -154.0

ADC12D1600RF -154.6

ADC12D1800RF -155.0

the noise in any channel bandwidth of interest may be calculated.

• NSD performance of RF ADCs is close to 16-bit ADCs

ADC12D2000RF -154.0

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Tools OverviewTools Overview

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ADC12DxxxxRF Reference Board (RB)

• Additional required equipment: only a PC and clean input signal source

• On-board sampling clock or external clock

• External trigger function• External trigger function

• Pin control or ECM

• Hooks to use AutoSync

• FMC expansion header for larger data captures

• FPGA, schematic and layout source available

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Reference Board Hardware Kit

• AC/DC adapter and power cord

• USB cable

• (4) 6” SMA cables

• (4) DC blocks

• (2) 50Ω terminators

• Low-Distortion Balun Board(400MHz – 3GHz)

• Wide-Band Balun Board (4.5MHz – 3GHz)

• Older reference boards may also include CD with software and reference documents

Kit is included with RB

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Reference Board WaveVision5 Software

• Time Domain, FFT, Histogram

• Read/Write Registers

• Dynamic • Dynamic Performance Metrics

• Save/Load Data

• Simultaneous I/Q data display

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Reference Board Common Pitfalls

Reported Issue Root Cause Solution

The software does not recognize the boards

The driver failed to install properly

Watch the “Getting Started” video

The ADC output shows very large harmonic tones

The Signal Generator outputs harmonic tones, which the ADC converts

Use a band-pass filter after the Signal Generator

Performance issues when switching between

Insufficient isolation in relay on RB to entirely

Turn Signal Generator OFF or remove cable switching between

INT/EXT Clockrelay on RB to entirely block EXT Clock

OFF or remove cable when using INT CLK

• See the 10-minute video “Getting Started with the GSPS ADC Reference Board” online in the product folder for help with installing WaveVision5 software, board drivers, test bench setup, and product evaluation.

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Other Reference Board FAQ (1/2)

• How can I drive the ADC in DESIQ Mode?

– DESIQ Balun Board (TC1-DESIQ-SBB)

– Available for sale at Product Folder Boards tab $99

– This board cannot be used to drive DESCLKIQ Mode

• How much does the RB cost?

– $999 for the ADC10D1500RB

– $999 for the ADC12D1800/1600RB– $999 for the ADC12D1800/1600RB

– $999 for the ADC12D800RFRB

– $999 for the ADC12D2000/1800/1600RFRB

• Can I get extra balun boards? Yes!

– ADC-WB-BB $49

– ADC-LD-BB $49

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Other Reference Board FAQ (2/2)

• How can I get more data than 32k samples off the Reference Board?

– High pin-count FMC-connector on Reference Board creates two options:

– ADCRF2LA board interfaces to Agilent logic analyzer

– Other data capture and processingboard with HPC FMC connector, board with HPC FMC connector, such as the Xilinx ML605

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Xilinx ML605 board

Common QuestionsCommon Questions

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What is Max Allowed Input Signal Level?

• Limits may be found in the Absolute Maximum and Operating Ratings sections of the datasheet.

• Required common-mode voltage must be maintained to ensure proper output codes.

• Operating Limits by Application:

– DC-coupled – DC-coupled

• Range limit to each Vin+ and Vin- pin

• Differential Vin range limit by lifetime duty-cycle of part

– AC-coupled

• Max current limit

• Power limit (dBm)

• Absolute Maximum Limits are absolute current and voltage limits.

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Why is the FPBW different by Mode?

• The FPBW is a function of the analog input, not the sampling frequency.

• FPBW is influenced by routing and internal loadinternal load

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Do I really need to calibrate?

• It depends…

– Calibration is performed once when the ADC12DxxxxRF powers up.

– It is recommended to calibrate again when the operating conditions change significantly.

Operating Condition Changed Is calibration necessary?

Full-scale Range For large changes in FSR, yes.Full-scale Range For large changes in FSR, yes.

Temperature For ∆Temperature < 20°C, no. For larger changes, it is application dependent.

DES / Non-DES Mode Yes

AC / DC Coupled Mode Yes

Power-cycle I- or Q-channel Yes

Power supply Yes

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Questions?

•Thank you for attending!attending!

•Any questions?

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