Adder and Subtrator

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Introduction To Tools Of VHDL

For simulating any VHDL program we have to first open FPA Advantage 8.1 PS from the desktop. This wilopen a window of the program called as Design Manager window. Design Manger is the main interface of theprogram. We can create new project, open existing project, set preferences for the program, change settings using

this interface, etc.

From the window that appears on our screen we select File --- New --- Project. With the help of this window we

can give the name of the project for our VHDL program.


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In the new opened window titled Create New Project, enter a name for your project in the Name of new project:

filed and click Next.

On the following window, click Next again. This window gives us the summary of the project information wehave just mentioned.

In the next window, select the radio button next to Create new design files and then click Finish.


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After we open new file for simulating VHDL program the computer asks us about what type of program we want to

design and its categories and also File Type. In our next window that is given below we select VHDL File from the given

categories and COMBINED file from the File Types. By selecting the Combined file type we are selecting or including bot

the ENTITY and ARCHITECTURE in our VHDL program.


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After we declare that we need both the Entity and Architecture field we need to also declare their corresponding names

Thus in our next window we declare the name of the Entity and Architecture.


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After we assign the name of Entity and the Architecture the window for writing the program is opened and we have to

write the VHDL Dataflow code for the given program as it is shown in the below screen.


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Code Window

After done with the coding, save the code by clicking File and then Save.


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In order to compile the program, click the icon in the task bar as shown below:

This also opens log on window which gives us information about the complete compilation of program. In the next

window titled as Start ModelSim, click OK to proceed with the simulation.


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This will open the ModelSim simulator window with the object page also as shown.


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Model Sim Simulator

The object screen tells us about the inputs and output terminal we have used in our VHDL code. Press and hold

the Ctrl key on the keyboard and click every literal inside the Objects pane.


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In the taskbar, click Add, then click Wave and then select Signals in Design.


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This will open a new window, Wave showing the timeline and all the input/output literals on the left.

Result Window

Right click at all input literals and select Force to force the value of the input only. In the next dialogue box, enterthe value 0 or 1 in the Value field and click OK.


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Repeat the last two steps for other input signals as well. Then click the icon as shown below to obtain the timing

diagram as output to your digital design.

After Forcing the required value for each input signal, click Run button as shown below to obtain thecorresponding timing diagram.


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Result Window


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ELECTRONICS AND COMMUNICATION ENGINEERING

ASET(NOIDA)

DCS-II LAB RECORD

Submitted to Submitted by

Dr.Pradeep Kumar(Faculty ASET) Rohit Panwar

5ECE-1

A2305109071


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S. No Name of the Experiment Date of Experiment Signature


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EXPERIMENT No. 2

Aim:

To implement VHDL code for Half Adder, Full Adder, Half Subtractor and Full Subtractor.

Apparatus Required:

Theory:

A) Half AdderThe half adder is an example of a simple, functional digital circuit built from two logic gates. It accepts

two binary digits on its inputs i.e. A and B and produce two binary digits outputs, a sum(S) and a carry

(C).

Mathematically, the equations are represented as:

Sum = A XOR B eqn.(2.1)

Carry = A AND B eqn.(2.2)

The half adder is an example of a simple, functional digital circuit built from two logicgates

Logic Diagram:

Figure.(2.1)


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Truth Table:

Table.(2a)

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

B) Full AdderThe full adder is usually a component in a cascade of adders , which adds 8,16,32 etc. binary numbers.

The full adder accepts two input bits (A and B) and an input carry( Cin ) and generates a sum(S) and an

output carry(Cout).


Sum= A XOR B XOR Cin

eqn.(2.3)

Carry = AB + BCin + ACin eqn.(2.4)

Logic Diagram:

Figure.(2.2)
http://upload.wikimedia.org/wikipedia/commons/a/aa/Full_Adder.svg


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Truth table:

Table.(2b)

A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

C) Half SubtractorThe half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs,

X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).


Difference= A XOR B eqn.(2.5)

Borrow = A'B eqn.(2.6)

Logic Diagram:

Figure.(2.3)
http://en.wikipedia.org/wiki/Logic_circuithttp://en.wikipedia.org/wiki/Minuendhttp://en.wikipedia.org/wiki/Subtrahendhttp://en.wikipedia.org/wiki/Subtrahendhttp://en.wikipedia.org/wiki/Minuendhttp://en.wikipedia.org/wiki/Logic_circuit


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Truth Table:

Table.(2c)

X Y D B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

D) Full SubtractorThe full-subtractor is a combinational circuit which is used to perform subtraction of three bits. The Full

Subtractor accepts two input bits (A and B) and an borrow( BORin ) and generates a Difference(D) and

an output borrow(BORout).


Difference = A XOR B XOR BORin

Borrow = A'BORin + A'B + B BORin

Logic Diagram:
http://en.wikipedia.org/wiki/Logic_circuithttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Logic_circuit


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Figure.(2.4)

Truth table:

Table.(2d)

A B BORin D BORout

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1


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A)VHDL code for Half Adder

1)Using Dataflow Modeling

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY halfadder IS

port(a,B: IN std_logic; Sum,Carry: OUT std_logic);

END ENTITY halfadder;

--

ARCHITECTURE half_adder_A OF halfadder IS

BEGIN

Sum


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2)Using Behavioral Modeling

LIBRARY ieee;



ENTITY fulladder ISport(A,B,C: IN std_logic; Sum,Carry: OUT std_logic);

END ENTITY fulladder;

--

ARCHITECTURE fulladder_beh OF fulladder IS

BEGIN

process(A,B,C)

Variable v1,v2,v3:std_logic;

BEGIN

Sum


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C) VHDL code for Half Subtractor


LIBRARY ieee;



ENTITY halfsub IS

port(A,B:IN std_logic; Borrow, Diff:OUT std_logic);

END ENTITY halfsub;

--

ARCHITECTURE halfsub_A OF halfsub IS

BEGIN

Diff


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Output:

Result window of Half Subtrator

C) VHDL code for Full Subtractor


LIBRARY ieee;



ENTITY fullsub IS

port(A,B,C: IN std_logic; Diff,Borrow: OUT std_logic);

END ENTITY fullsub;

--

ARCHITECTURE fullsub_A OF fullsub IS

BEGIN

Diff


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2)Using Behavioral Modeling

LIBRARY ieee;



ENTITY fullsub ISport(A,B,C: IN std_logic; Diff,Borrow: OUT std_logic);

END ENTITY fullsub;

--

ARCHITECTURE fullsub_beh OF fullsub IS

BEGIN

process(A,B,C)

Variable v1,v2,v2: std_logic;

BEGIN

Diff


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Structural coding

1) Half Adder

library ieee;

use ieee.std_logic_1164.all;

entity andGate is

port( A, B : in std_logic;

F : out std_logic);

end andGate;

architecture func of andGate is

begin

F


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Result:VHDL code for Half Adder, Full Adder, Half Subtrator and Full Subtrator were implemented and their

simulation were tested.

Date post:	05-Apr-2018
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Adder and Subtrator

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