ADSP-BF7xx Blackfin+ Processor
Programming Reference
Revision 1.0, October 2016
Part Number82-100123-01
Analog Devices, Inc.Three Technology WayNorwood MA , 02062
Notices
Copyright Information
2016 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any formwithout prior, express written consent from Analog Devices, Inc.
Printed in the USA.
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Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Ana-log Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for itsuse; nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted by implication or otherwise under the patent rights of Analog Devices, Inc.
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The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-Board, EZ-KIT Lite, EZ-Extender, SHARC, andVisualDSP++ are registered trademarks of Analog Devices, Inc.
Blackfin+, SHARC+, and EZ-KIT Mini are trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of their respective owners.
ADSP-BF7xx Blackfin+ Processor i
Contents
Introduction
Core Architecture........................................................................................................................................... 11
Memory Architecture..................................................................................................................................... 13
Internal Memory ........................................................................................................................................ 13
External Memory........................................................................................................................................ 14
I/O Memory Space ..................................................................................................................................... 14
Event Handling.............................................................................................................................................. 14
Syntax Conventions ....................................................................................................................................... 15
Case Sensitivity........................................................................................................................................... 15
Free Format ................................................................................................................................................ 15
Instruction Delimiting................................................................................................................................ 15
Comments.................................................................................................................................................. 15
Notation Conventions ................................................................................................................................... 16
Glossary......................................................................................................................................................... 17
Register Names........................................................................................................................................... 17
Functional Units......................................................................................................................................... 18
Arithmetic Status Bits................................................................................................................................. 18
Fractional Convention ................................................................................................................................ 19
Saturation................................................................................................................................................. 110
Rounding and Truncating......................................................................................................................... 111
Automatic Circular Addressing ................................................................................................................. 112
Computational Units
Using Data Formats ....................................................................................................................................... 22
Binary String .............................................................................................................................................. 22
Unsigned Numbers..................................................................................................................................... 22
ii ADSP-BF7xx Blackfin+ Processor
Signed Numbers: Two's-Complement ........................................................................................................ 23
Fractional Representation: 1.15 and 1.31 ................................................................................................... 23
Complex Numbers ..................................................................................................................................... 23
Register Files.................................................................................................................................................. 23
Data Register File ....................................................................................................................................... 24
Accumulator Registers ................................................................................................................................ 24
Register File Instruction Summary ............................................................................................................. 25
Data Types..................................................................................................................................................... 27
Endianness ................................................................................................................................................. 28
ALU Data Types ......................................................................................................................................... 28
MAC Data Types........................................................................................................................................ 29
Shifter Data Types .................................................................................................................................... 210
Arithmetic Formats Summary................................................................................................................... 211
Rounding MAC Results............................................................................................................................ 212
Unbiased Rounding............................................................................................................................... 212
Biased Rounding ................................................................................................................................... 214
Truncation............................................................................................................................................. 214
Special Rounding Instructions .................................................................................................................. 214
Using Computational Status ........................................................................................................................ 215
ASTAT Register ........................................................................................................................................... 215
Arithmetic Logic Unit (ALU)....................................................................................................................... 215
ALU Operations ....................................................................................................................................... 216
Single 16-Bit Operations....................................................................................................................... 216
Dual 16-Bit Operations......................................................................................................................... 216
Quad 16-Bit Operations........................................................................................................................ 217
Single 32-Bit Operations....................................................................................................................... 217
Dual 32-Bit Operations......................................................................................................................... 218
ALU Division Support Features............................................................................................................. 218
Special SIMD Video ALU Operations ................................................................................................... 218
ADSP-BF7xx Blackfin+ Processor iii
ALU Instruction Summary ....................................................................................................................... 219
Multiply Accumulators (MACs)................................................................................................................... 221
MAC Operation ....................................................................................................................................... 222
Placing MAC Results in Accumulator Registers .................................................................................... 222
Rounding or Saturating MAC Results ................................................................................................... 223
Saturating MAC Results on Overflow ................................................................................................... 223
32-bit MAC Data Flow Details ............................................................................................................ 224
32-bit Multiply Without Accumulate .................................................................................................... 224
16-bit MAC Data Flow Details ............................................................................................................. 226
16-bit Multiply Without Accumulate .................................................................................................... 227
Dual 16-bit MAC Operations ............................................................................................................... 228
MAC Instruction Summary...................................................................................................................... 230
MAC Instruction Options..................................................................................................................... 231
Barrel Shifter (Shifter).................................................................................................................................. 233
Shifter Operations .................................................................................................................................... 233
Two-Operand Shifts .............................................................................................................................. 234
Three-Operand Shifts............................................................................................................................ 234
Bit Test, Set, Clear, and Toggle.............................................................................................................. 235
Field Extract and Field Deposit ............................................................................................................. 236
Packing Operation................................................................................................................................. 237
Shifter Instruction Summary .................................................................................................................... 238
ADSP-BF70x Computational Unit Register Descriptions ........................................................................... 240
Data Registers ......................................................................................................................................... 242
Accumulator 0 Register ........................................................................................................................... 243
Accumulator 1 Register ........................................................................................................................... 244
Accumulator 0 Extension Register ........................................................................................................... 245
Accumulator 1 Extension Register ........................................................................................................... 246
Arithmetic Status Register ....................................................................................................................... 247
Operating Modes and States
iv ADSP-BF7xx Blackfin+ Processor
User Mode ..................................................................................................................................................... 33
Protected Resources and Instructions ......................................................................................................... 33
Protected Memory...................................................................................................................................... 34
Entering User Mode ................................................................................................................................... 34
Example Code to Enter User Mode Upon Reset ...................................................................................... 34
Return Instructions That Invoke User Mode........................................................................................... 35
Supervisor Mode............................................................................................................................................ 35
Non-OS Environments............................................................................................................................... 36
Example Code for Supervisor Mode Coming Out of Reset...................................................................... 36
Emulation Mode............................................................................................................................................ 37
Idle State........................................................................................................................................................ 37
Example Code for Transition to Idle State .................................................................................................. 38
Reset State ..................................................................................................................................................... 38
System Reset and Power Up........................................................................................................................... 39
ADSP-BF70x Mode-Related Register Descriptions ....................................................................................... 39
System Configuration Register ................................................................................................................ 310
Program Sequencer
Introduction .................................................................................................................................................. 41
Sequencer-Related Registers ....................................................................................................................... 43
Instruction Pipeline ....................................................................................................................................... 44
Branches ........................................................................................................................................................ 46
Direct Jumps (Short, Long and Extra-Long) ............................................................................................... 47
Direct Call (Long and Extra-Long) ............................................................................................................. 48
Indirect Jump and Call (Absolute) .............................................................................................................. 48
Indirect Jump and Call (PC-Relative) ......................................................................................................... 48
Subroutines ................................................................................................................................................ 48
Stack Variables and Parameter Passing................................................................................................... 410
Conditional Processing ............................................................................................................................. 412
ADSP-BF7xx Blackfin+ Processor v
Conditional Code Status Bit.................................................................................................................. 412
Conditional Branches ............................................................................................................................ 413
Branch Prediction.................................................................................................................................. 413
Dynamic Branch Prediction .................................................................................................................. 415
Speculative Instruction Fetches.............................................................................................................. 426
Conditional Register Move.................................................................................................................... 427
Hardware Loops........................................................................................................................................... 427
Two-Dimensional Loops........................................................................................................................... 429
Loop Unrolling......................................................................................................................................... 430
Saving and Resuming Loops ..................................................................................................................... 430
Example Code for Using Hardware Loops in an ISR............................................................................. 431
Events and Interrupts................................................................................................................................... 432
Core Event Controller Registers ............................................................................................................... 433
Interrupt Pending Register (IPEND) .................................................................................................... 433
Interrupt Latch Register (ILAT) ............................................................................................................ 433
Interrupt Mask Register (IMASK)......................................................................................................... 434
Event Vector Table (EVT)......................................................................................................................... 434
Return Registers and Instructions............................................................................................................. 435
Executing RTX, RTN, or RTE in a Lower-Priority Event...................................................................... 437
Emulation Interrupt ................................................................................................................................. 437
Reset Interrupt ......................................................................................................................................... 438
Non-Maskable Interrupt (NMI) ............................................................................................................... 438
Exceptions ................................................................................................................................................ 439
Hardware Error Interrupt ......................................................................................................................... 439
Core Timer Interrupt ............................................................................................................................... 439
General-Purpose Core Interrupts (IVG7-IVG15) ..................................................................................... 439
Interrupt Processing..................................................................................................................................... 439
Globally Enabling/Disabling Interrupts.................................................................................................... 439
Servicing Interrupts .................................................................................................................................. 440
Interrupt Nesting...................................................................................................................................... 440
vi ADSP-BF7xx Blackfin+ Processor
Non-Nested Interrupts .......................................................................................................................... 441
Nested Interrupts .................................................................................................................................. 441
Self-Nesting of Core Interrupts ............................................................................................................. 443
Servicing System Interrupts ...................................................................................................................... 443
Clearing Interrupt Requests...................................................................................................................... 445
Software Interrupts................................................................................................................................... 445
Latency in Servicing Events ...................................................................................................................... 446
Hardware Errors and Exception Handling ................................................................................................... 447
SEQSTAT Register ................................................................................................................................... 447
Hardware Error Interrupt ......................................................................................................................... 447
Exceptions (Events)................................................................................................................................... 448
Exceptions While Executing an Exception Handler ............................................................................... 451
Allocating the System Stack................................................................................................................... 452
Exceptions and the Pipeline................................................................................................................... 452
Deferring Exception Processing............................................................................................................. 453
Example Code for an Exception Handler............................................................................................... 453
Example Code for an Exception Routine ............................................................................................... 454
ADSP-BF70x Sequencer-Related Register Descriptions .............................................................................. 455
Sequencer Status Register ........................................................................................................................ 456
Return from Subroutine Register ............................................................................................................. 460
Return from Interrupt Register ................................................................................................................ 461
Return from Exception Register ............................................................................................................... 462
Return from NMI Register ...................................................................................................................... 463
Return from Emulator Register ............................................................................................................... 464
Loop Top Register ................................................................................................................................... 465
Loop Bottom Register ............................................................................................................................. 466
Loop Count Register ............................................................................................................................... 467
Blackfin+ ICU Register Descriptions .......................................................................................................... 467
System ID Register .................................................................................................................................. 468
Context ID Register ................................................................................................................................ 469
ADSP-BF7xx Blackfin+ Processor vii
Event Vector Table Registers .................................................................................................................... 470
Event Vector Table Override Register ...................................................................................................... 471
Interrupt Latch Register .......................................................................................................................... 473
Interrupt Mask Register ........................................................................................................................... 476
Interrupt Pending Register ...................................................................................................................... 478
Blackfin+ BP Register Descriptions ............................................................................................................ 480
BP Configuration Register ...................................................................................................................... 481
BP Status Register ................................................................................................................................... 483
Core Timer (TMR)
TMR Features................................................................................................................................................ 51
TMR Functional Description ........................................................................................................................ 51
Blackfin+ TMR Register List...................................................................................................................... 51
TMR Block Diagram.................................................................................................................................. 52
External Interfaces................................................................................................................................... 52
Internal Interfaces ................................................................................................................................... 52
TMR Operation ............................................................................................................................................ 52
Interrupt Processing ................................................................................................................................... 53
Blackfin+ TMR Register Descriptions .......................................................................................................... 53
Core Timer Control Register (TCNTL) .................................................................................................... 54
Core Timer Count Register (TCOUNT) ................................................................................................... 55
Core Timer Period Register (TPERIOD) .................................................................................................. 56
Core Timer Scale Register (TSCALE) ........................................................................................................ 57
Address Arithmetic Unit
Addressing with the AAU............................................................................................................................... 63
Pointer Register File ................................................................................................................................... 64
Frame and Stack Pointers ........................................................................................................................ 64
DAG Register Set ....................................................................................................................................... 65
Indexed Addressing with Index and Pointer Registers................................................................................. 65
viii ADSP-BF7xx Blackfin+ Processor
Loads with Zero- or Sign-Extension ........................................................................................................ 66
Indexed Addressing with Immediate Offset ............................................................................................. 66
Auto-increment and Auto-decrement Addressing........................................................................................ 66
Pre-modify Stack Pointer Addressing .......................................................................................................... 67
Post-modify Addressing .............................................................................................................................. 67
Direct Addressing ...................................................................................................................................... 67
Addressing Circular Buffers ........................................................................................................................ 68
Addressing with Bit-reversed Addresses ...................................................................................................... 69
Modifying Index and Pointer Registers..................................................................................................... 610
Addressing Mode Summary ..................................................................................................................... 610
AAU Instruction Summary ....................................................................................................................... 612
ADSP-BF70x Address Arithmetic Unit Register Descriptions ..................................................................... 616
Pointer Register ....................................................................................................................................... 618
Frame Pointer Register ............................................................................................................................ 619
Stack Pointer Register .............................................................................................................................. 620
User Stack Pointer Register ...................................................................................................................... 621
Index (Circular Buffer) Register ............................................................................................................... 622
Modify (Circular Buffer) Register ............................................................................................................ 623
Base (Circular Buffer) Register ................................................................................................................ 624
Length (Circular Buffer) Register ............................................................................................................ 625
Memory
Memory Architecture..................................................................................................................................... 71
Overview of On-Chip Level-1 (L1) Memory .............................................................................................. 72
Overview of Other On-Chip (L2) and Off-Chip (L3) Memories ................................................................ 73
L1 Instruction Memory ................................................................................................................................. 73
L1 Instruction SRAM................................................................................................................................. 73
L1 Instruction Cache.................................................................................................................................. 74
Enabling L1 Instruction Cache................................................................................................................ 74
Cache Lines ............................................................................................................................................. 75
ADSP-BF7xx Blackfin+ Processor ix
Cache Hits and Misses ............................................................................................................................ 76
Instruction Cache Management .............................................................................................................. 76
L1 Data Memory ........................................................................................................................................... 78
L1 Data SRAM........................................................................................................................................... 78
L1 Data Cache............................................................................................................................................ 78
Enabling L1 Data Cache ......................................................................................................................... 79
Data Cache Access................................................................................................................................... 79
Cache Write Method ............................................................................................................................. 710
Data Cache Block Select........................................................................................................................ 710
Data Cache Bypass Mode ...................................................................................................................... 711
Data Cache Control Instructions........................................................................................................... 712
Data Cache Invalidation........................................................................................................................ 712
Extended Data Access .................................................................................................................................. 712
Memory Protection and Properties .............................................................................................................. 713
Memory Management Unit (MMU) ........................................................................................................ 713
Instruction CPLB..................................................................................................................................... 714
Data CPLB............................................................................................................................................... 714
CPLB Page Descriptors ............................................................................................................................ 715
Memory Page Properties ....................................................................................................................... 715
Default Memory Properties................................................................................................................... 716
CPLB Status Registers........................................................................................................................... 717
DCPLB and ICPLB Fault Address Registers ......................................................................................... 717
CPLB Management.................................................................................................................................. 717
CPLB Exception Cause............................................................................................................................. 718
L1 Parity Protection..................................................................................................................................... 719
Parity Protection Coverage ....................................................................................................................... 719
Parity Error Detection and Notification ................................................................................................... 719
Parity Error Recovery ............................................................................................................................... 720
Parity Errors Simultaneous with Exceptions and Interrupts...................................................................... 721
Direct Access To Parity Bits for L1 SRAM................................................................................................ 721
x ADSP-BF7xx Blackfin+ Processor
L1 Initialization Requirements ................................................................................................................. 722
Additional Notes on Parity Errors............................................................................................................. 722
Example Parity Handler............................................................................................................................ 722
Memory Transaction Model......................................................................................................................... 725
Load/Store Operation .................................................................................................................................. 725
Interlocked Pipeline.................................................................................................................................. 726
Alignment................................................................................................................................................. 726
Ordering of Loads and Stores ................................................................................................................... 726
Speculative Load Execution ...................................................................................................................... 727
Interruptible Load Behavior ..................................................................................................................... 727
Hazards of the High-Performance Memory Architecture .......................................................................... 727
Synchronizing Instructions ....................................................................................................................... 729
Cache Coherency...................................................................................................................................... 729
I/O Device Space...................................................................................................................................... 730
Memory-Mapped Registers....................................................................................................................... 730
Non-Speculative, Non-Interruptible Loads ............................................................................................... 730
Exclusive Load, Store, and Sync (Spin Lock Example) .............................................................................. 731
Atomic TESTSET Instruction (Spin Lock Example) ................................................................................ 733
L1 Memory Microarchitecture ..................................................................................................................... 733
L1 Memory Access.................................................................................................................................... 733
Memory Logical Sub-Bank Arrangement............................................................................................... 734
Misaligned Data Access to L1................................................................................................................ 735
L1 Data Stores....................................................................................................................................... 735
System Slave Interface ........................................................................................................................... 736
Core MMR Access.................................................................................................................................... 736
System Memory Access............................................................................................................................. 736
System Memory Interface...................................................................................................................... 737
System MMR Interface ......................................................................................................................... 738
L1 Cache Details ...................................................................................................................................... 738
Extended Data Access to L1 Caches ...................................................................................................... 738
ADSP-BF7xx Blackfin+ Processor xi
Cache Fills and Victims ......................................................................................................................... 742
Terminology ................................................................................................................................................ 742
Blackfin+ L1IM Register Descriptions ........................................................................................................ 745
Instruction Memory CPLB Address Registers .......................................................................................... 746
Instruction Memory CPLB Data Registers .............................................................................................. 747
Instruction Memory CPLB Default Settings Register .............................................................................. 749
Instruction Memory CPLB Fault Address Register .................................................................................. 751
Instruction Memory Control Register ..................................................................................................... 752
Instruction Parity Error Status Register ................................................................................................... 754
Instruction Memory CPLB Status Register .............................................................................................. 756
Blackfin+ L1DM Register Descriptions ...................................................................................................... 756
Data Memory CPLB Address Registers ................................................................................................... 758
Data Memory CPLB Data Registers ........................................................................................................ 759
Data Memory CPLB Default Settings Register ........................................................................................ 762
Data Memory CPLB Fault Address Register ............................................................................................ 765
Data Memory Control Register ............................................................................................................... 766
Data Memory Parity Error Status Register ............................................................................................... 768
Data Memory CPLB Status Register ....................................................................................................... 770
SRAM Base Address Register ................................................................................................................... 772
Instruction Reference Pages
Arithmetic Instructions.................................................................................................................................. 82
Add and Subtract Operations ..................................................................................................................... 83
16-Bit Add or Subtract (AddSub16) ........................................................................................................ 84
Vectored 16-Bit Add or Subtract (AddSubVec16) .................................................................................... 85
32-bit Add Constant (AddImm).............................................................................................................. 87
32-bit Add or Subtract (AddSub32)......................................................................................................... 88
32-bit Add and Subtract (AddSub32Dual) .............................................................................................. 89
32-Bit Add or Subtract with Carry (AddSubAC0) ................................................................................. 810
Accumulator Add and Extract (AddAccExt)........................................................................................... 811
xii ADSP-BF7xx Blackfin+ Processor
Accumulator Add or Subtract (AddSubAcc)........................................................................................... 812
Dual Accumulator Add and Subtract to Registers (AddSubAccExt) ....................................................... 813
32-bit Add then Shift (AddSubShift) ..................................................................................................... 814
Bit Operations.......................................................................................................................................... 815
Ones Count (Shift_Ones)...................................................................................................................... 816
Redundant Sign Bits (Shift_SignBits32)................................................................................................ 816
Redundant Sign Bits (Shift_SignBitsAcc) .............................................................................................. 817
Bit Mux (BitMux) ................................................................................................................................. 818
Bit Modify (Shift_BitMod) ................................................................................................................... 821
Bit Test (Shift_BitTst) ........................................................................................................................... 822
Deposit Bits (Shift_Deposit) ................................................................................................................. 823
Extract Bits (Shift_Extract).................................................................................................................... 826
Comparison Operations ........................................................................................................................... 829
Vectored 16-Bit Maximum (Max16Vec) ................................................................................................ 830
Vectored 16-Bit Minimum (Min16Vec)................................................................................................. 831
32-bit Maximum (Max32) .................................................................................................................... 832
32-Bit Minimum (Min32)..................................................................................................................... 833
Vectored 16-Bit Search (Search)............................................................................................................. 834
Conversion Operations............................................................................................................................. 836
Vectored 16-Bit Absolute Value (Abs2x16) ............................................................................................ 836
32-bit Absolute Value (Abs32)............................................................................................................... 838
Accumulator0 Absolute Value (AbsAcc0)............................................................................................... 839
Accumulator Absolute Value (AbsAcc1)................................................................................................. 840
Accumulator Absolute Value (AbsAccDual) ........................................................................................... 841
Vectored 16-bit Negate (Neg16Vec)....................................................................................................... 842
32-Bit Negate (Neg32) .......................................................................................................................... 842
Accumulator0 Negate (NegAcc0)........................................................................................................... 844
Accumulator1 Negate (NegAcc1)........................................................................................................... 844
Dual Accumulator Negate (NegAccDual) .............................................................................................. 845
Fractional 32-bit to 16-Bit Conversion (Pass32Rnd16) ......................................................................... 846
Accumulator0 32-Bit Saturate (ALU_SatAcc0)...................................................................................... 847
Accumulator1 32-Bit Saturate (ALU_SatAcc1)...................................................................................... 848
ADSP-BF7xx Blackfin+ Processor xiii
Dual Accumulator 32-Bit Saturate (ALU_SatAccDual) ......................................................................... 849
Logic Operations ...................................................................................................................................... 850
32-Bit Logic Operations (Logic32)........................................................................................................ 850
32-Bit One's Complement (Not32)....................................................................................................... 851
Move Operations ...................................................................................................................................... 852
Move 32-Bit Accumulator Section to Even Register (MvA0ToDregE) ................................................... 852
Move 16-Bit Accumulator Section to Low Half Register (MvA0ToDregL)............................................ 853
Move 16-Bit Accumulator Section to High Half Register (MvA1ToDregH).......................................... 854
Move 32-Bit Accumulator Section to Odd Register (MvA1ToDregO)................................................... 856
Move Register to Accumulator0 (MvAxToAx) ....................................................................................... 857
Move Accumulator to Register (MvAxToDreg) ..................................................................................... 857
Move 8-Bit Accumulator Section to Register Half (MvAxXToDregL) ................................................... 858
Pass 8-Bit to 32-Bit Register Expansion (MvDregBToDreg).................................................................. 859
Move Register Half to 16-Bit Accumulator Section (MvDregHLToAxHL)............................................ 860
Move Register Half (LSBs) to 8-Bit Accumulator Section (MvDregLToAxX) ........................................ 861
Pass 16-Bit to 32-Bit Register Expansion (MvDregLToDreg) ................................................................ 862
Move Register to Accumulator1 (MvDregToAx) ................................................................................... 863
Move Register to Accumulator0 & Accumulator1 (MvDregToAxDual) ................................................ 864
Move Register to Register (MvRegToReg)............................................................................................. 864
Conditional Move Register to Register (MvRegToRegCond) ................................................................ 865
Dual Move Accumulators to Half Registers (ParaMvA1ToDregHwithMvA0ToDregL) ......................... 866
Dual Move Accumulators to Register (ParaMvA1ToDregOwithMvA0ToDregE) .................................. 867
Multiplication Operations ........................................................................................................................ 868
16 x 16-Bit MAC (Mac16) .................................................................................................................... 869
16 x 16-Bit MAC with Move to Register (Mac16WithMv) ................................................................... 870
32 x 32-Bit MAC (Mac32) .................................................................................................................... 872
32 x 32-Bit MAC with Move to Register (Mac32WithMv) ................................................................... 874
Complex Multiply to Accumulator (Mac32Cmplx) ............................................................................... 876
Complex Multiply to Register (Mac32CmplxWithMv)......................................................................... 878
Complex Multiply to Register with Narrowing (Mac32CmplxWithMvN) ............................................ 880
16 x 16-Bit Multiply (Mult16) .............................................................................................................. 883
32 x 32-bit Multiply (Mult32)............................................................................................................... 885
xiv ADSP-BF7xx Blackfin+ Processor
32 x 32-Bit Multiply, Integer (MultInt)................................................................................................. 886
Dual 16 x 16-Bit MAC (ParaMac16AndMac16) ................................................................................... 887
Dual 16 x 16-Bit MAC with Move to Register (ParaMac16AndMac16WithMv) .................................. 888
Dual 16 x 16-Bit MAC with Move to Register (ParaMac16WithMvAndMac16) .................................. 889
Dual 16 x 16-Bit MAC with Moves to Registers (ParaMac16WithMvAndMac16WithMv) .................. 890
Dual 16 x 16-Bit MAC with Move to Register (ParaMac16AndMv) ..................................................... 891
Dual 16 x 16-Bit MAC with Moves to Registers (ParaMac16WithMvAndMv) ..................................... 892
Dual 16 x 16-Bit Multiply (ParaMult16AndMult16) ............................................................................ 893
Dual Move to Register and 16 x 16-Bit MAC (ParaMvAndMac16) ...................................................... 894
Dual Move to Register and 16 x 16-Bit MAC with Move to Register (ParaMvAndMac16WithMv)...... 895
Pointer Math Operations.......................................................................................................................... 896
32-bit Add or Subtract (DagAdd32) ...................................................................................................... 897
32-bit Add or Subtract Constant (DagAddImm) ................................................................................... 898
32-bit Add then Shift (DagAddSubShift) .............................................................................................. 899
32-bit Add Shifted Pointer (PtrOp)..................................................................................................... 8100
Pointer Logical Shift (LShiftPtr).......................................................................................................... 8101
Rotate Operations .................................................................................................................................. 8101
32-Bit Rotate (Shift_Rot32) ................................................................................................................ 8102
Accumulator Rotate (Shift_RotAcc) .................................................................................................... 8103
Shift Operations ..................................................................................................................................... 8104
16-Bit Arithmetic Shift (AShift16) ...................................................................................................... 8105
Vectored 16-Bit Arithmetic (AShift16Vec)........................................................................................... 8108
32-Bit Arithmetic Shift (AShift32) ...................................................................................................... 8110
Accumulator Arithmetic Shift (AShiftAcc)........................................................................................... 8113
16-Bit Logical Shift (LShift16) ............................................................................................................ 8115
Vectored 16-Bit Logical Shift (LShift16Vec) ........................................................................................ 8117
32-Bit Logical Shift (LShift) ................................................................................................................ 8119
Accumulator Logical Shift (LShiftA) ................................................................................................... 8121
Sequencer Instructions............................................................................................................................... 8123
Branch Operations ................................................................................................................................. 8124
Conditional Jump Immediate (BrCC) ................................................................................................. 8125
ADSP-BF7xx Blackfin+ Processor xv
Jump (Jump) ....................................................................................................................................... 8126
Jump Immediate (JumpAbs)................................................................................................................ 8127
Call (Call)............................................................................................................................................ 8128
Return from Branch (Return).............................................................................................................. 8129
Hardware Loop Set Up (LoopSetup) ................................................................................................... 8130
Control Code Bit Management Operations............................................................................................ 8134
Compute Move CC to a D Register (CCToDreg)................................................................................ 8134
Move CC To/From ASTAT (CCToStat16) .......................................................................................... 8135
Move Status to CC (MvToCC)............................................................................................................ 8136
Move Status to CC (MvToCC_STAT)................................................................................................. 8137
32-Bit Pointer Register Compare and Set CC (CCFlagP).................................................................... 8138
Accumulator Compare and Set CC (CompAccumulators)................................................................... 8139
32-Bit Register Compare and Set CC (CompRegisters)....................................................................... 8140
Event Management Operations .............................................................................................................. 8142
Interrupt Control (IMaskMv) ............................................................................................................. 8142
Sequencer Mode (Mode) ..................................................................................................................... 8143
Raise Interrupt (Raise) ........................................................................................................................ 8144
Stack Operations .................................................................................................................................... 8145
Linkage (Linkage)................................................................................................................................ 8146
Stack Pop (Pop) ................................................................................................................................... 8148
Stack Push (Push)................................................................................................................................ 8150
Stack Push/Pop Multiple Registers (PushPopMul16) .......................................................................... 8151
Synchronization Operations ................................................................................................................... 8155
Cache Control (CacheCtrl).................................................................................................................. 8155
Sync (Sync).......................................................................................................................................... 8157
SyncExcl (SyncExcl)............................................................................................................................. 8160
NOP (NOP) ....................................................................................................................................... 8160
32-Bit No Operation (NOP32)........................................................................................................... 8161
TestSet (TestSet).................................................................................................................................. 8162
Memory or Pointer Instructions ................................................................................................................ 8163
Load from Immediate (Value) Operations .............................................................................................. 8163
xvi ADSP-BF7xx Blackfin+ Processor
Accumulator Register Initialization (LdImmToAx).............................................................................. 8164
32-Bit Accumulator Register (.w) Initialization (LdImmToAxW)........................................................ 8164
32-Bit Accumulator Register (.x) Initialization (LdImmToAxX).......................................................... 8165
16-Bit Register Initialization (LdImmToDregHL)............................................................................... 8166
32-Bit Register Initialization (LdImmToReg)...................................................................................... 8167
Dual Accumulator 0 and 1 Registers Initialization (LdImmToAxDual) ............................................... 8168
Memory Load Operations ...................................................................................................................... 8169
8-Bit Load from Memory to 32-bit Register (LdM08bitToDreg) ........................................................ 8169
16-Bit Load from Memory to 32-Bit Register (LdM16bitToDreg)...................................................... 8170
16-Bit Load from Memory (LdM16bitToDregH) ............................................................................... 8173
16-Bit Load from Memory (LdM16bitToDregL) ................................................................................ 8175
32-Bit Load from Memory (LdM32bitToDreg)................................................................................... 8177
32-Bit Pointer Load from Memory (LdM32bitToPreg) ....................................................................... 8180
Memory Load (Exclusive) Operations..................................................................................................... 8181
8-Bit Load from Memory to 32-bit Register (LdX08bitToDreg) ......................................................... 8182
16-Bit Load from Memory to 32-Bit Register (LdX16bitToDreg)....................................................... 8183
16-Bit Load from Memory (LdX16bitToDregH) ................................................................................ 8183
16-Bit Load from Memory (LdX16bitToDregL) ................................................................................. 8184
32-Bit Load from Memory (LdX32bitToDreg).................................................................................... 8184
Pack Operations ..................................................................................................................................... 8185
Pack 8-Bit to 32-Bit (BytePack)........................................................................................................... 8185
Spread 8-Bit to 16-Bit (ByteUnPack)................................................................................................... 8186
Pack 16-Bit to 32-Bit (Pack16Vec) ...................................................................................................... 8189
Memory Store Operations ...................................................................................................................... 8190
16-Bit Store to Memory (StDregHToM16bit)..................................................................................... 8190
16-Bit Store to Memory (StDregLToM16bit) ...................................................................................... 8192
8-Bit Store to Memory (StDregToM08bit).......................................................................................... 8194
32-Bit Store to Memory (StDregToM32bit)........................................................................................ 8195
Store Pointer (StPregToM32bit).......................................................................................................... 8198
Memory Store (Exclusive) Operations..................................................................................................... 8199
16-Bit Store to Memory (StDregHToX16bit)...................................................................................... 8201
16-Bit Store to Memory (StDregLToX16bit) ....................................................................................... 8202
ADSP-BF7xx Blackfin+ Processor xvii
8-Bit Store to Memory (StDregToX08bit) ........................................................................................... 8203
32-Bit Store to Memory (StDregToX32bit) ......................................................................................... 8203
Specialized Compute Instructions.............................................................................................................. 8204
Block Floating Point Operations............................................................................................................. 8205
Exponent Detection (Shift_ExpAdj32) ................................................................................................ 8205
DCT Operations .................................................................................................................................... 8207
32-Bit Prescale Up Add/Sub to 16-bit (AddSubRnd12)....................................................................... 8207
32-Bit Prescale Down Add/Sub to 16-Bit (AddSubRnd20) ................................................................. 8208
Divide Operations .................................................................................................................................. 8209
DIVS and DIVQ Divide Primitives (Divide) ....................................................................................... 8210
Linear Feedback Shift Register LFSR Operations ................................................................................... 8213
40-Bit BXOR LSFR with Feedback to a Register (BXOR)................................................................... 8213
40-Bit BXORShift LSFR with Feedback to the Accumulator (BXORShift_NF).................................. 8219
32-Bit BXOR or BXORShift LSFR without Feedback (BXOR_NF) ................................................... 8220
Video Operations ................................................................................................................................... 8220
Vectored 8-Bit to 16-Bit Add then Clip to 8-Bit (Byteop3P) (AddClip) .............................................. 8221
Vectored 8-Bit Add or Subtract to 16-Bit (Byteop16P/M) (AddSub4x8) ............................................. 8223
Disable Alignment Exception (DisAlignExcept) .................................................................................. 8225
Byte Align (Shift_Align) ...................................................................................................................... 8226
Quad Byte Average (Byteop2P) (Avg4x8Vec)....................................................................................... 8227
Vector Byte Average (Byteop1P) (Avg8Vec) ......................................................................................... 8230
Dual Accumulator Extraction with Addition (AddAccHalf) ................................................................ 8233
Vectored 8-Bit Sum of Absolute Differences (SAD8Vec)...................................................................... 8234
Viterbi Operations.................................................................................................................................. 8236
16-Bit Add on Sign (AddOnSign) ....................................................................................................... 8236
Dual 16-Bit Modulo Maximum with History (Shift_DualVitMax) ..................................................... 8238
16-Bit Modulo Maximum with History (Shift_VitMax) ..................................................................... 8239
Instruction Page Tables.............................................................................................................................. 8243
ALU Binary Operations (ALU2op)......................................................................................................... 8243
Conditional Branch PC relative on CC (BrCC)...................................................................................... 8244
Move CC conditional bit, to and from dreg (CC2Dreg) ......................................................................... 8245
xviii ADSP-BF7xx Blackfin+ Processor
Copy CC conditional bit, from status (CC2Stat).................................................................................... 8246
CBIT................................................................................................................................................... 8246
Set CC conditional bit (CCFlag) ............................................................................................................ 8247
Conditional Move (CCMV) ................................................................................................................... 8249
GDST ................................................................................................................................................. 8249
GSRC.................................................................................................................................................. 8250
Cache Control (CacheCtrl)..................................................................................................................... 8250
PREGA ............................................................................................................................................... 8250
Call function with pcrel address (CallA) ................................................................................................. 8251
Compute with 3 operands (Comp3op) ................................................................................................... 8251
Destructive Binary Operations, dreg with 7bit immediate (CompI2opD) .............................................. 8252
Destructive Binary Operations, preg with 7bit immediate (CompI2opP)............................................... 8253
DAG Arithmetic (DAGModIk) .............................................................................................................. 8253
DAG Arithmetic (DAGModIm) ............................................................................................................. 8254
ALU Operations (Dsp32Alu).................................................................................................................. 8255
A0_HL................................................................................................................................................ 8259
A1_HL................................................................................................................................................ 8260
AOPL.................................................................................................................................................. 8260
DDST0_HL........................................................................................................................................ 8260
DSRC0_HL ........................................................................................................................................ 8260
NSAT.................................................................................................................................................. 8261
PAIR0 ................................................................................................................................................. 8261
PAIR1 ................................................................................................................................................. 8261
RS ....................................................................................................................................................... 8261
RSC..................................................................................................................................................... 8262
SAT..................................................................................................................................................... 8262
SAT2 ................................................................................................................................................... 8262
SMODE.............................................................................................................................................. 8262
SX ....................................................................................................................................................... 8263
SXA..................................................................................................................................................... 8263
XMODE ............................................................................................................................................. 8264
ADSP-BF7xx Blackfin+ Processor xix
Multiply Accumulate (Dsp32Mac) ......................................................................................................... 8264
CMODE............................................................................................................................................. 8265
CMPLXMAC...................................................................................................................................... 8266
CMPLXOP ......................................................................................................................................... 8266
MAC0 ................................................................................................................................................. 8266
MAC0S ............................................................................................................................................... 8267
MAC1 ................................................................................................................................................. 8267
MAC1S ............................................................................................................................................... 8267
MML .................................................................................................................................................. 8268
MMLMMOD0................................................................................................................................... 8268
MMLMMOD1................................................................................................................................... 8270
MMLMMODE................................................................................................................................... 8273
MMOD0 ............................................................................................................................................ 8275
MMOD1 ............................................................................................................................................ 8276
MMODE ............................................................................................................................................ 8278
NARROWING_CMODE .................................................................................................................. 8280
TRADMAC ........................................................................................................................................ 8280
Multiply with 3 operands (Dsp32Mult).................................................................................................. 8285
M32MMOD....................................................................................................................................... 8287
M32MMOD1..................................................................................................................................... 8288
M32MMOD2..................................................................................................................................... 8289
MML .................................................................................................................................................. 8291
MMLMMOD1................................................................................................................................... 8292
MMLMMODE................................................................................................................................... 8295
MMOD1 ............................................................................................................................................ 8297
MMODE ............................................................................................................................................ 8299
MUL0 ................................................................................................................................................. 8300
MUL1 ................................................................................................................................................. 8301
Shift (Dsp32Shf) .................................................................................................................................... 8301
Shift Immediate (Dsp32ShfImm) ........................................................................................................... 8305
AHSH4............................................................................................................................................... 8306
AHSH4S ............................................................................................................................................. 8307
xx ADSP-BF7xx Blackfin+ Processor
AHSH4VS .......................................................................................................................................... 8307
ASH5 .................................................................................................................................................. 8307
ASH5S ................................................................................................................................................ 8307
LHSH4 ............................................................................................................................................... 8308
LSH5 .................................................................................................................................................. 8308
Load/Store (DspLdSt)............................................................................................................................. 8308
Jump/Call to 32-bit Immediate (Jump32) .............................................................................................. 8310
Load Immediate Word (LdImm)............................................................................................................. 8311
Load Immediate Half Word (LdImmHalf) ............................................................................................. 8312
DST .................................................................................................................................................... 8313
DST_H............................................................................................................................................... 8313
DST_L................................................................................................................................................ 8313
Load/Store (LdSt) ................................................................................................................................... 8314
Load/Store 32-bit Absolute Address (LdStAbs) ....................................................................................... 8316
Long Load/Store with indexed addressing (LdStExcl) ............................................................................. 8317
Load/Store indexed with small immediate offset (LdStII) ....................................................................... 8318
Load/Store indexed with small immediate offset FP (LdStIIFP) ............................................................. 8319
Long Load/Store with indexed addressing (LdStIdxI) ............................................................................. 8320
Load/Store postmodify addressing, pregister based (LdStPmod)............................................................. 8321
Load/Store (Ldp) .................................................................................................................................... 8322
Load/Store indexed with small immediate offset (LdpII) .......