Advanced manufacturing concepts for crystalline silicon solar cells

1948 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 10, OCTOBER 1999

Advanced Manufacturing Conceptsfor Crystalline Silicon Solar Cells

Johan F. Nijs,Senior Member, IEEE,Jozef Szlufcik,Member, IEEE,Jozef Poortmans,Member, IEEE,S. Sivoththaman,Senior Member, IEEE,and Robert P. Mertens,Fellow, IEEE

Abstract—An overview is given concerning current industrialtechnologies, near future improvements and medium term de-velopments in the field of industrially implementable crystallinesilicon solar cell fabrication. The paper proves that considerableimprovements are still possible, both in efficiency and in pro-duction cost. The paper also proves that a lot of effort is beingput worldwide on thinner substrates and on thin-film crystallinesilicon cells deposited on cheap carriers, in order to save insubstrate cost and in order to gain more independence fromavailability problems of silicon feedback.

Index Terms—Photovoltaic cells, power semicondcutor devices,semiconductor device fabrication, silicon, solar energy.

I. INTRODUCTION

T HE world terrestrial PV-market is steadily growing tomaturity. A considerable market increase has been no-

ticed from 1996 to 1997, with a growth of 40% to morethan 125 MWp and from 1997 to 1998, with a growth ofmore than 20% to about 152 MWp [1]. Hence, the marketis characterized by a very healthy growth with increasingcommercial market segments and growing incentives and sub-sidies for demonstration projects, sponsored by governmentsand electricity supplier companies. Many capacity increases ofexisting companies and new initiatives have been announced.Crystalline silicon solar cells and modules keep on constitutingabout 85% of the world PV-market, the other 15% takenby thin-film approaches, today mainly amorphous silicon.Major concerns for bulk crystalline silicon (mono-, multi-,and ribbons) are the availability of good quality feedstockmaterials and, consequently, cheap substrates. This problemwas very explicit about one to two years ago and seemsto be easing a little bit. However, concerns for the futureremain and the PV-community is shouting louder for its own(cheap) feedstock supply, independent from micro-electronics.In crystalline silicon, the emphasis seems to be shifting frommonocrystalline to multicrystalline silicon and ribbons. Forthe longer term, a lot of R&D activities are performed onthin-film silicon layers on cheap silicon-like and nonsilicon-

Manuscript received December 18, 1998; revised April 16, 1999. This workwas supported in part by the European Commission (Joule-programme) andby the Flemish government. The review of this paper was arranged by GuestEditor A. Barnett.

J. F. Nijs and R. P. Mertens are with Interuniversity MicroelectronicsCenter (IMEC), Leuven-3001, Belgium, and the Electrotechnical Department,Katholieke Universiteit Leuven, Belgium (e-mail: [email protected]).

J. Szlufcik, J. Poortmans, and S. Sivoththaman are with InteruniversityMicroelectronics Center (IMEC), Leuven-3001, Belgium.

Publisher Item Identifier S 0018-9383(99)07618-2.

(a)

(b)

(c)

(d)

(e)

Fig. 1. PV-value chain.

like substrates. But on the latter, a considerable effort still hasto be made before commercial solutions will break through.

Efficiency of the solar cells, and hence, rated peak powerof the modules, remain very important parameters as theefficiency influences the costs/Wp on all levels of the fab-rication cycle. To a large extent, the efficiency is determinedby the solar cell fabrication process itself. A lot of interestingdevelopments have occurred lately, and are still progressing,in solar cell fabrication technologies on crystalline siliconsubstrates. The PV “value chain” is outlined in Fig. 1.

In Fig. 1(a), the feedstock material is obtained by reducingsand (SiO) to metallurgical grade silicon and then purifyingit further to electronic grade silicon. Traditionally, photo-voltaics use cheap reject material from the micro-electronicsindustry. In Fig. 1(b), this material is recrystallized throughCzochralski crystallization, resulting in monocrystalline sili-con, or through directional solidification or casting, resultingin poly/multicrystalline silicon, or through ribbon formationdirectly from the molten silicon. In the first two cases, thisis followed by wafer sawing, resulting in silicon substrates orwafers. This is followed by solar cell fabrication [Fig. 1(c)].The solar cells are interconnected into modules [Fig. 1(d)].The balance-of-system (BOS) components, such as storage

0018–9383/99$10.00 1999 IEEE

NIJS et al.: ADVANCED MANUFACTURING CONCEPTS FOR CRYSTALLINE SILICON SOLAR CELLS 1949

batteries, regulators, maximum power point tracking, dc–acinvertors, etc., are added [Fig. 1(e)]. The relative cost of thedifferent steps until module fabrication [Fig. 1(d)] are roughly(reference a 14% efficient advanced screenprinting process onmulticrystalline silicon): (a) (b) (finished wafer) 50–55%,(c) (cell fabrication) 18–20%, and (d) (module fabrication)27–30%. The false impression can be given now that solarcell fabrication might be relatively unimportant in the overallcost picture. However, the solar cell fabrication process, whichmust be fine-tuned to the type of substrate that is used, to alarge extent determines the efficiency as well as the yield, andthose two factors influence the cost/Wp on all levels (a)–(d).Therefore, the continuous search for improved, reliable, robust,and cheap solar cell technologies is of utmost importance forthe PV industry.

In this paper, bulk crystalline materials and cell technologieswill be discussed as a function of their implementabilitytime frame. Then, a separate section will be entirely devotedto thin-film crystalline silicon materials and solar cells, andconclusions will be formulated. Important to note is that thecontents of this review paper will be limited to low-cost,flat plate terrestrial photovoltaic markets, based on crystallinesilicon. Therefore, nearly no references will be made tomaterials or cells for space applications, neither cells forconcentrator applications, nor very high efficiency cells forefficiency records, PV-racing cars, or the like. Also, othermaterials, such as amorphous silicon, CdTe, CuInSe2, etc.,will be left out of the picture in this paper.

II. BULK CRYSTALLINE SILICON SUBSTRATES (INCLUDING

RIBBONS AND SOLAR CELL TECHNOLOGIES

A. Bulk Crystalline Silicon Substrates

Crystalline silicon solar cells continue to dominate world PVproduction, constituting in 1997 about 85% of the PV-marketshare. The crystalline market is further subdivided into singleor mono-crystalline (mono-Si) and multicrystalline silicon(mc-Si) cells (and a small market share for ribbons) withtheir PV-market shares of around 50% and 35%, respectively.The major problem of relatively thick bulk crystalline siliconsolar cells is availability of good quality silicon feedstockmaterial. To obtain inexpensive feedstock, the PV industryis using secondary grade polysilicon as a byproduct fromhyperpure polysilicon production or as tops and tails fromCzochralski growth for the IC industry. Although the problemcurrently has been eased temporarily, a rapid growth of the PVindustry in the recent past has led to a shortage of secondarypolysilicon feedstock and has driven up the feedstock priceabove /kg. Initiatives for starting a dedicated low-cost solargrade polysilicon production are still in pilot line phase [2].

1) Regular Bulk Materials (Cz, Casting/Directional Solid-ification, EMC): A very crucial step in the fabrication ofcrystalline silicon solar cells is ignot formation. There aretwo major competing technologies: 1) Czochralski pullingof monocrystalline ingots and 2) a casting process of mul-ticrystalline silicon ingots. Monocrystalline silicon has severalimportant advantages for solar cell processing. Typical dif-

fusion lengths from 200 to 400m are equal to or biggerthan standard wafer thickness. Cells with effective aluminumor boron back surface field yield high voltages. The wafersurface can be easily and with high-throughput textured inweak caustic solutions resulting in a low reflectance loss.Consequently, high short-circuit current can be obtained with-out an anti-reflection coating. Reasonable efficiencies areobtained using a very simple cell process. Typically, Czcells result in 1.5–2% (absolute) higher cell efficiencies thanmulticrystalline cells in current industrial cell processes. Dis-advantages are loss of the expensive silicon material in squareshaping of ingots, instability of finished cells due to thehigh oxygen content [3], and typically 25–30% higher waferprice in comparison with multicrystalline Si. Multicrystallinesilicon ignot fabrication can be subdivided into casting, truedirectional solidification (DS), and electromagnetic casting.The directional solidification techniques produce multicrys-talline silicon with diffusion lengths values as found in Cz-Si.Casting is evidently a lower cost opinion due to higherthroughput and the possibility for upscaling. However, slightlylower cell efficiencies are obtained from cast silicon wafers.A very important development in multicrystalline silicon iselectromagnetic casting (EMC) [4]. This technique relies oninduction melting and on the interactive forces between themagnetic field and the induced electric current, because ofwhich silicon can be melted and solidified without contactwith the crucible wall. Advantages of this technique are theabsence of crucible wear-out and of melt contamination fromthe crucible. Electromagnetic casting can be done, in principle,continuously and yields multicrystalline silicon material withthroughput an order of magnitude higher than the DS process.Cell efficiencies are typically 0.5–1% absolute lower thanthose from DS wafers, because of the much lower grain sizesin EMC material. Advantages of multicrystalline silicon, ingeneral, over monocrystalline are a lower wafer cost and aperfect long-term cell stability. Cell efficiencies approachingthe efficiencies of monocrystalline cells are obtained in a morecomplicated process, comprising deposition of anti-reflectioncoating and hydrogen bulk passivation.

For a long time, the standard substrate size has been 1010cm ; however, there is recently a clear tendency toward largersizes. Most of the solar cell manufacturers now base theirproduction lines on 12.5 12.5 cm wafers. Efficient cellsprocessed on 15 15 cm and even 20 20 cm substrateshave been reported [5]. The driving force toward these largercell sizes results from the fact that cell manufacturing andmodule assembly costs show relatively small area dependence,and therefore, the cost/Wp decreases with increasing cell size.On the other hand, the cell size is limited by series resistanceand by limitations of module sizes due to handling, windloads, module transportation, and system assembly. Therefore,cell sizes larger than 20 20 cm are rather excluded.Due to the success of developments in multi-wire sawing, awafer thickness of 150 m or smaller is becoming feasible,corresponding to final cell thickness of 120m or lower [6].This allows an important saving of silicon material. At thesame time, thinner cells correspond better to the optimumthickness if efficient light trapping and surface passivation


are possible [7]. In spite of significant progress in slicingtechniques, there is still around 200m of high-quality siliconper wafer lost in kerf waste. Limitations to further decreasethe final wafer thickness are set by decrease in yield due tohandling problems and breakage during solar cell and modulefabrication.

2) Ribbons: The ribbon technology basically means pro-ducing silicon directly in sheet form. The costs involvingwafering after ignot formation and the kerf losses are thereforeavoided. A number of ribbon techniques have been developedand used in solar cell applications, with each technique havingits own advantages and disadvantages. Despite their apparentsimplicity and cost-effectiveness, most of the Si ribbons pro-duced today, however, have inferior material quality comparedto conventional Cz-Si or cast mc-Si wafers. In this section, wewill review some of the ribbon techniques that were developedand used for PV applications.

a) Dendritic Web (D-WEB):The D-WEB technology isone of the very few techniques that yield ribbons in single crys-talline form. When an Si seed is raised from an equilibratedSi melt, secondary dendrites propagate into the melt and anSi film is formed by surface tension between the dendrites[8]. The crystallographic orientation of the film will be thatof the dendrite seeds. The film yields a readily processablesurface since the surface is shaped by crystallographic andsurface tension forces and not by any polishing, as used inconventional wafering [9]. However, the presence of twinplanes is possible parallel to the surface. Typical film thicknessis in the range 100–150m A throughput of 50 000 cm

per furnace per operating cycle has been reported. Solarcell modules with D-Web Si cells were reported to havean efficiency about 13.5%, and a number of installationswere reported. On a laboratory level, efficiencies as high as17.3% were achieved on 4-cmn-type D-Web Si of 11 -cmresistivity [10].

b) Edge-defined film-fed growth (EFG) ribbon process:This technology was initially developed in the 1970’s and hadbeen steadily progressing into multiple silicon ribbon growth[11], growth of large area sheets in form of tubes [12], etc.It involves positioning of a mating seed to form a meniscuswith a forming die filled with molten silicon. The tubes aregrown in nonagons. Formation rates of 146 cm/min have beenachieved. The grains along the tube surfaces are typically inthe order of 10 cm long and 1–2 cm wide. DLTS studiesperformed on EFG material have shown that FeB and CrBpairing limit the diffusion length [13]. EFG-Si quality wasalso found to improve after Al gettering and forming gasanneal [14]. Laboratory conversion efficiency of 14.1% hasbeen achieved with this material.

c) String ribbon process:This was initially developedas “edge supported ribbon” [15], and is presently improvedand commercialized. When two strings of a high-temperaturematerial are brought up through the silicon melt, a continuousSi film is drawn from the melt after seeding Si. The resultingfilm after solidification is polycrystalline. Growth of 5–6 cmwide films with 250 m thickness has recently been reported[16]. Typical pull speeds are in the range of 18–25 mm/min.Ribbons are cut by a scriber into size, typically 5.6 cm

15 cm. Some promising results have been obtained on 1-cm research cells on string ribbon material with an efficiencyof 15.1%. Like the EFG material, the string ribbon materialalso showed considerable improvements after Al-alloying andforming gas anneal [17].

d) Silicon sheets from powder (SSP):Si in powder formis used as starting material. It is poured through a funnel intoquartz carrier sheets [18] which first travel into a “first meltingzone” where surface melting of the powder layer is achievedby a focussed lamp-bank. The liquid silicon does not reachdown to the quartz carrier. The ribbons, called “pre-ribbons,”which are self-supporting, travel further into a zone-melting(ZMR) station where they are “scanned” by a molten strip ofSi melted by focused lamps. This results in large-grain mc-Siand the minority carrier diffusion length of the ZMR sampleswere about 250 m. Laboratory scale conversion efficienciesof 13.2% were reported for 4-cmcells. However, the scopeand method of the SSP was later modified to eliminate thecostly ZMR process. The relatively fast-produced pre-ribbonsare used as substrates for epitaxial growth of thin-film Si.The 15–40 m thick epitaxial Si films were deposited in anRTCVD system on the SSP pre-ribbons. Laboratory efficiencyof 8% on 4-cm cells has been achieved [19].

e) Ribbon growth on substrates (RGS):The RGS processis a horizontal ribbon growth technology where a substrate isused for the cooling over the bottom surface of the ribbon.The heat is removed by conduction, perpendicularly to thepulling direction, over the ribbon surface. The crystallizationand pulling velocities are therefore decoupled, leading tohigh production rates [20]. A heterogeneous nucleation takesplace with columnar grain structure in the range of 200

m Dislocation densities in the ribbons were found to bein the range 10–10 cm The oxygen content on thematerial was above 10 cm [21]. The material propertiesshowed significant improvements after Al-gettering and H-plasma treatments. A laboratory cell efficiency of over 11%was recently reported [22].

B. Current Industrial Technologies

Most of the commercially-fabricated crystalline silicon solarcells are still based on screenprinting. The industrial produc-tion of more advanced solar cell technologies such as lasergrooved buried contact (LGBC) and EFG ribbon solar cellscontribute less than 10% to the total commercial production.

1) Screenprinting:Screenprinting is a simple, robust, con-tinuous, and easily adaptable manufacturing process. A solarcell processing sequence based on screenprinting is wellestablished in the PV industry. Fully automated screenprintingsolar cell production lines are commercially available from afew companies. However, the commercial production processof screenprinting has not changed significantly for many years.The typical processing sequence is shown in Table I.

Characteristic features of the process presented in Table Iare its simplicity and small number of processing steps.Nevertheless, most of the current industrially-produced screen-printed solar cells do not include high-efficiency featuresbesides random texturization and aluminum BSF. Random


TABLE IPROCESSSEQUENCE OF A TYPICAL PRODUCTION PROCESS

FOR SCREEN PRINTING CRYSTALLINE SILICON SOLAR CELLS

TABLE IIPROCESSSEQUENCE OF A SCREENPRINTEDSOLAR

CELL BASED ON FIRING-THROUGH PECVD SiNx

texturization is effective in the case of monocrystalline cells,but still a large portion (28%) of the incident light is reflectedfrom randomly textured multicrystalline substrates. Often, atoo deeply diffused and not passivated emitter is responsiblefor a moderate blue response. The line widths of commerciallyscreenprinted contacts are, in most cases, larger than 100

m Therefore, the shadowing losses of screenprinted frontcontacts are relatively large and range between 8% and 10%.Absence of bulk passivation strongly limits the performanceof multicrystalline solar cells. This explains why the efficiencyof most industrial crystalline solar cells still ranges from12 to 13% for multicrystalline and from 13 to 15% formonocrystalline silicon solar cells.

An important effort has been made during the last few yearsby several research groups and companies, mainly in Japan andEurope, to improve the commercial solar cell process based onscreenprinted metallization [7], [23]–[27]. The main progresshas been made in paste formulation [27], fabrication of newtypes of fine line screens [28], and development of modernscreenprinters. New types of silver paste contain additives,which permit, during the firing process, a selective dissolvingof silicon dioxide and ARC layers such as TiOor SiN , whilepreventing deep penetration into bulk silicon [27]. This makesit possible to use a very simplified process firing through thepassivating oxide and/or anti-reflection coatings. Particularly,the screenprinting process based on firing through PECVDSiN anti-reflection layer seems to be extremely beneficial forefficiency improvement of industrial solar cells [25], [29]–[32].The processing sequence is presented in Table II. Fig. 2 showsa schematic cross section of the resulting solar cell.

Fig. 2. Schematic cross section of a solar cell fabricated with the fir-ing-through PECVD SiNx process.

Fig. 3. Absorption spectra of the same SiNx layer as deposited (solid line)and annealed (shadowed line).

The process presented in Table II takes advantage of theexperimental observation that a direct PECVD SiNlayercontains a large amount of hydrogen in the form of nitrogen tohydrogen (N-H) and silicon to hydrogen (Si-H) bonds. Anneal-ing of a hydrogen-rich silicon nitride layer at temperatures of600–800 C breaks the N-H and Si-H bonds. The cross-linkingof the broken bonds into Si-N or Si-Si bonds facilitates thebond breaking process. Fig. 3 presents the absorption spectraof the deposited and annealed SiNlayer at a temperature of800 C Released hydrogen diffuses into an underlying siliconsubstrate giving a perfect surface and bulk passivation. Anannealing time of less than 30 s is sufficient, since the diffusioncoefficient of atomic hydrogen in silicon at a temperatureabove 800 C is a few orders of magnitude larger than ata deposition temperature of 300–400C Because the siliconnitride layer acts not only as an anti-reflection coating, butalso serves as a source of atomic hydrogen, it is importantto optimize the plasma nitride deposition process not onlyfor obtaining a suitable refractive index, but also for a highhydrogen content.

The beneficial effects of the thermal treatment of PECVDSiN layer is combined with the firing step of screenprintedcontacts in a so-called firing-through process. The firing-


TABLE IIICHARACTERISTICS OFSOLAR CELLS FABRICATED ON STANDARD QUALITY AND DEFECTED MULTI-Si SUBSTRATES (CELL AREA 100 cm2)

through PECVD SiN process has a number of advantages[27], [30], [31]:

• Front contacts are not covered by ARC and can be directlysoldered during module assembly.

• As discussed earlier, hydrogen released from the SiNlayer at an elevated temperature gives excellent surfaceand bulk passivation; therefore, the dry oxidation stepcan be omitted.

• Elevated firing temperature makes simultaneous forma-tion of an Al-alloyed BSF possible.

• The PECVD SiN layer slows down the aggressiveetching of silicon by molten glass frit and acts as adiffusion barrier for unwanted impurities.

As a result, the processing step of contact firing-throughPECVD SiN combines the functions of a few separateprocessing steps: 1) front and back contact firing, 2) surfaceand bulk passivation, and 3) Al-BSF formation. Additionally,screenprinted contacts with high fill factors can be fabri-cated on shallow and well passivated emitters. Good qualityscreenprinted contacts can be made on emitters diffused upto 100 /sq. The bulk passivation properties of this processare particularly attractive since there are no other industrialalternatives. Thanks to all these benefits, high-efficiency so-lar cells can be fabricated using a low-cost screenprintingprocess. This process gives a large efficiency improvementin all multicrystalline materials and is particularly suitable forlower quality and defected multicrystalline silicon wafers likeribbons and EMC material. Table III and Fig. 4 [30] showimprovement in all cell parameters. Very good efficiencies areobtained on substrates sliced from the defected bottom part ofthe ingot, allowing significant savings of expensive silicon.

This process in a modified form and not always contain-ing all advantageous features, has already found its way tosolar cell production lines [2], [32], giving obvious efficiencygains. An average efficiency of 14.5% is achieved in a massproduction of large-area multicrystalline solar cells [29]. Usingthe process sequence from Table II, very encouraging resultshave been obtained in a pilot line. Top efficiencies of 16.3%for large area multicrystalline and 17.4% for Cz-Si cellshave been obtained and independently confirmed [31], [33].The screenprinting process is also well suited for larger cellsizes: 15 15 cm multicrystalline cells with efficiencies of15.3% have also been demonstrated on laboratory scale [34].Further efficiency improvements require the implementationof additional high-efficiency features into an industrial solarcell production process, as described in the sections below.

(a)

(b)

Fig. 4. Internal quantum efficiency for solar cells from Table III. (a) Cellson standard quality substrates. (b) Cells processed on wafers from the bottompart of the ingot.

2) Buried Contact Technology:The buried contact solarcell (BCSC) process has been developed at the Universityof New South Wales, Sydney, Australia [35], [36]. Manyaspects of the BCSC structure and its processing have beenextensively described in the technical literature [37]–[43].A laboratory efficiency as high as 21.3% on small-area FZmaterial has been reported [44]. A conventional commercialBCSC processing sequence, licensed to many solar cellmanufacturers, is presented in Table IV.

Although the buried contact solar cell is manufacturedindustrially, it embodies almost all characteristic features ofhigh-efficiency laboratory cells: shallow emitter diffusion witha very good surface passivation by a thick thermal oxide,very fine metallization line width, front contact passivationby heavy diffusion in the contact area, and Back SurfaceField (BSF). One of the important processing steps is the


TABLE IVCONVENTIONAL COMMERCIAL PROCESSSEQUENCE

OF BURIED CONTACT SOLAR CELL [41]

TABLE VSIMPLIFIED BURIED CONTACT SOLAR CELL PROCESSSEQUENCE [48]

growth of a very thick thermal oxide on the top surface,which simultaneously acts as a diffusion mask, a platingmask, and a surface passivation layer. This process has somedisadvantages when commercial applications are considered: alarge number of lengthy processing steps at high temperature(total time above 950 C of all processing up to 16 h),expensive equipment, and many pre-cleaning steps making theprocess complex and labor intensive [45]. In some processingsequences, the thick oxide is replaced by a silicon nitridethat also reduces the front surface reflection. Although theburied contact solar cell process has been licensed to manyleading solar cell manufacturers, only one so far has succeededin introducing it into a large volume production, thanks tosimplification of many processing steps [46]. Efficiencies closeto 17% are routinely obtained from the production process ofCz-Si cells [47].

A simplified buried contact solar cell process has beenproposed [42], [43], [48]. The processing sequence is presentedin Table V, and key features of the cell structure in Fig. 5.

The aim of this process simplification is to suit infrastructureand equipment already existing in many solar cell production

Fig. 5. Key features of a simplified buried contact solar cell design [48].

plants, based on screenprinted contacts. The number of high-temperature processing steps has been reduced to one, frontsurface passivation is achieved by retention of the diffusionoxide and a sprayed-on TiOlayer acts as an anti-reflectioncoating and plating mask. Pilot line efficiencies of close to17% on FZ substrates have been reported [43]. For a longtime, the BCSC process has been exclusively applied tomonocrystalline solar cells. Trials on transforming this processto multicrystalline solar cells have been published, but noefficiency results have been reported so far [43], [48].

3) Industrial Solar Cells on Silicon Ribbons:Many ribbontechnologies have been tried on laboratory or pilot scale[49]–[54], but only the Edge-defined-Film-fed Growth (EFG)polysilicon sheets [32] and string ribbon [16] have beenintroduced into high-volume production. Silicon ribbons offera significant cost advantage over traditional crystalline silicontechnology like Cz pulling or casting multicrystalline blocks.The cost saving arises from elimination of the slicing process,which is a significant cost contributor to Cz and multicrys-talline wafers. The development of the EFG process with thespecific purpose of achieving low-cost targets in terrestrialsolar cells started in 1974. An individual crystal is grown inthe form of a hollow octagonal tube, with eight 10-cm widefaces and average tube wall thickness of 300m The totaltube length is usually 4.6 m. The faces are then separatedand cut to lengths appropriate for cell processing. The processenvisioned for future EFG technology is based on high-speedgrowth of very thin (less than 100 m) cylinders with alarge diameter up to 1 m [55]. The electronic and mechanicalproperties of EFG ribbons differ from the properties of castor directionally solidified multicrystalline wafers. The EFGmaterial has high crystal defect density, grain boundaries, twingrains, and dislocations [32]. High mechanical stress and theuneven surface of EFG sheets make application of standardscreenprinting processes difficult because of high breakage.Therefore, a specific solar cell process had to be developed.Several patented processing steps have been developed inorder to passivate the highly defected EFG bulk material and totackle the problem of contacting the uneven surface. A detaileddescription of the EFG solar cell process is not published.Some information can be found in [56]. The process comprises


several patented processing steps: spray-on of liquid P-sourceand diffusion in an IR-belt furnace, plasma enhanced chemicalvapor deposition (PECVD) of silicon nitride anti-reflectioncoating preceded by ammonia plasma treatment in order toproduce hydrogen implantation, “pad printing” of solderablesilver contacts on the back and drying, “pad printing” ofaluminum paste and the back and drying, direct writing ofsilver paste on the front, and drying and co-firing of all contactsin an IR-furnace. During the first process, the front contactpaste penetrates through the PECVD silicon nitride layer andforms good ohmic contact, the aluminum paste creates deepp alloyed BSF region on the back, and at the same time,the heating process tends to promote the release of hydrogenfrom the silicon nitride and drives it deeper into the substrate,providing good bulk passivation. An efficiency of 14.3% onlarge-area EFG substrates has been reported [57].

In the case of the string ribbon process, high-temperaturenonconductive strings are drawn through a crucible of moltensilicon [53]. Growth takes place with a meniscus of 7 mm. Thestrings stabilize the edges of the growth ribbon. Continuouspulling for 86 h has already been achieved. Ribbons withthickness from 5 to 150 m have been grown using thismethod. Laboratory cell efficiencies of about 15% have beenobtained [58]. Current cell production process is based onribbons with a thickness of 250m p-type doped, and 5.6cm wide. Wafers of 5.6 cm 15 cm are cut from the ribbon.Research on growing 100-m thin ribbons has been completed[59]. PV modules based on string ribbon solar cells of 30 and60 Wp are commercially available.

C. Advanced Pilot Line Crystalline Solar Cell Technologies

The efficiency of future industrial solar cells will depend onsuccessful implementation of the efficiency enhancing and/oroverall cost decreasing processing steps. Many processingtechniques such as isotropic texturing, gettering, passivation,and light trapping are currently intensively tested in individualpilot lines. Results of these tests will decide the future im-plementation into mass production lines. The implementationcriteria are processing cost of the cell versus power (/Wp),productivity, reproducibility, width of the processing window,and availability of high-throughput processing equipment. Twoprocessing technique (isotropic texturing of multicrystallinewafers and selective emitter processing) are currently beingimplemented into production lines based on screenprinting.

1) Isotropic Texturing of Multicrystalline Substrates:Thesilicon surface obtained after saw-damage etching is shiny andreflects more than 35% of the incident light. The reflectionloss of commercial solar cells are reduced mainly by randomchemical texturing [60], [61]. Surface texturing reduces theoptical reflection from the monocrystalline silicon surface toless than 10% by allowing the reflected ray to be recoupledinto the cell. The random texturization process is not effectiveon multicrystalline substrates due to its anisotropic nature.Isotropic texturing methods based on photolithography andwet etching are not cost-effective. Many techniques such asmechanical grooving, defect etching, and reactive ion etchingare being tested by many groups [62]–[66].

Fig. 6. Reflectance curves of differently textured silicon wafers measuredafter PECVD SiNx ARC deposition.

The mechanical V-grooving, i.e., forming V-grooves in Siwafers by mechanical abrasion, using a conventional dicingsaw and bevelled blades, has evolved from a single-bladelaboratory technique to a multiblade, high-throughput processthat is almost ready for industrial implementation [67]. Fig. 6shows the reflectance curves of different texturization pro-cesses showing a clear advantage of the V-grooving processover random alkaline texturing. In addition to the reduced re-flection, an improvement in internal quantum efficiency in therange of 750–1000 nm has been observed in multicrystallinecells indicating the effect of light trapping.

Although the highest short-circuit currents on multicrys-talline material have been achieved with V-grooved surfaces,there is still a manufacturability problem related to low-cost metallization on deeply grooved surfaces. New types ofprinting techniques particularly suitable for metallization ofgrooved surfaces, such as roller printing, are currently underdevelopment [67]. When mechanical grooving was appliedfrom two sides of the wafer deeply enough and perpendicularto each other, the so-called POWER-cell [169] was createdby the University of Konstanz, in which a compromise canbe worked out between efficiency and light transmittance ofthe solar cell, offering a nice alternative to amorphous siliconcells in window integrated PV.

Contacting problems can be avoided by using microscopicisotropic surface structuring processes based on acid etching orReactive Ion Etching (RIE) [62], [66]. A proprietary acid solu-tion gives isotropic surface structuring, which, in combinationwith an anti-reflection coating, decreases the surface reflectionto a value significantly below randomly textured mc-Si wafers.Consequently, a 4% increase in short-circuit current has beenmeasured on finished multicrystalline Si solar cells. Fig. 7shows an SEM picture of a multicrystalline silicon surfaceetched with such an acid solution. This process produces,however, a relatively large amount of chemical waste whichhas to be treated, giving rise to additional processing costs.Therefore, in each specific case, the trade-off has to becarefully considered.

Reactive ion etching unlike mechanical grooving is a con-tactless and stress-free dry etching process. Silicon wafersare immersed in a direct chlorine plasma. By controllingthe gas flow, RF power, and reaction pressure, homogeneousmicroscopic pyramid-like structures have been formed on amulticrystalline silicon surface [68]. An efficiency over 17%


Fig. 7. SEM picture of acid textured multi-Si surface.

on large-area, laboratory processed multicrystalline cells hasbeen reported [66].

2) Selective Emitter Structures:The optimum emitterdoping profile should be either relatively deep and moderatelydoped, or a shallow emitter with a high surface concentration.Both profiles combined with surface passivation using high-quality thermal oxides or other passivating layers showreduced surface recombination losses and increased emittercollection efficiency. However, both industrial techniques usedfor front contact fabrication, i.e., screenprinting of silver pastesand electroless plating of Ni, require a high dopant surfaceconcentration ( surface concentration above 10cmand, preferably, a relatively deep junction to obtain acceptablecontact resistance and to avoid metallic impurity penetrationtoward the junction region. Typical emitter sheet resistancesused in a screenprinting metallization process are between 30and 50 /sq. This can be achieved by diffusion from liquidPOCl or solid P O sources in open tube furnaces or fromscreenprinted, sprayed-, or spin-on P-sources followed by aconveyor-belt furnace diffusion. Deep emitter and poor surfacepassivation leads to voltage and collection losses in the shortwavelength region. Two directions are followed in a pilot lineprocess development: 1) improved screenprinted contacts to ashallow homogeneously diffused emitter and 2) developmentof a selective emitter processes compatible for the industrialenvironment. The former is achieved by modification ofthe front contact paste composition and application of fastfiring of screenprinted contacts in IR or RTP furnaces. Thereare successful reports of good fill factors obtained by ascreenprinting process on high-resistance emitters [31]. Theprocessing window still has to be improved somewhat inorder to implement it in an industrial environment. The perfectsolution uses a selective emitter structure, shown schematicallyin Fig. 8. The emitter saturation current can be reducedby using shallow emitters for well-passivated surfaces and adeeper emitter under unpassivated regions, such as the metal-Siinterface. A large number of techniques have been establishedat laboratory levels to form selective emitters. Most of thesetechniques remain too complicated or expensive to be appliedin a cost-effective industrial environment. One exception is theconventional laser-grooved buried contact process [69], which

(a)

(b)

Fig. 8. Schematic representation of a selective emitter. (a) Fabrication bytwo diffusions. (b) Fabrication by one diffusion step and selective etch-back.

TABLE VISELECTIVE EMITTER PROCESS WITHTWO DIFFUSION STEPS [77]

utilizes selective emitters and is already applied in industrialsolar cell manufacturing. Recent progress in screenprintingtechnology has also demonstrated high-performance deviceswith selective emitter design [26]. In this section, three morerecent selective emitter approaches that have been developedand that have a strong potential for industrial application inthe near future, are discussed.

a) Selective emitter structure with two diffusion steps[Fig. 8(a)]: Athough a large number of selective emittertechniques involving two diffusion steps have been reported inthe literature, in Table VI we describe only one technology thatuses industrially compatible screenprinting technique. Such aprocess on 100-cmmc-Si substrates has resulted in 15.9%efficiency using SiN /MgF as a double A.R.C. [77].

b) Screenprinted, self-aligned, selective emitter process[Fig. 8(b)]: The process involves the fabrication of a ho-mogeneous emitter cell with a relatively deep junction andscreenprinted front metallization. After the metallization, thenonmetallized part of the emitter is partially etched by plasmaetching, with the metal fingers (in some cases protected by


Fig. 9. Schematic of the principle of single-step selective emitter diffusionfrom a screenprinted dopant source [71].

a screenprinted polymer paste) acting as a mask. A selectiveemitter is thereby formed. The process is attractive from thepoint of view that it does not require any alignment. Theprocess was first reported by Spectrolab [73], where an RFplasma etcher was used to thin the emitter in order to removethe diffusion damage at the surface layer. More than a 10%increase in was reported. The scope of the process was laterextended to incorporate 1) plasma hydrogenation, 2) plasmaetching, and 3) plasma deposition of SiN A.R.C. for thefabrication of mc-Si solar cells [74]. A 38.5% boost inalong with an 18-mV increase in was reported in 4-cmcells. The process was later modified and extended to industrialsize (100 cm) mc-Si cells [75] as a self-aligned selectiveemitter (SASE) process. A thin nitride protective layer wasdeposited, followed by a plasma hydrogenation treatment, andthen a thicker nitride was deposited for A.R.C. An absoluteefficiency increase of 0.6% was reported on large-area mc-Sicells [76].

c) Single-step selective diffusion from screenprintedP-dopant paste:This technology [70] basically involvesscreenprinting of a dopant (phosphorous) paste onto thewafer in the form of a finger pattern (i.e., by using a screensimilar to that for metallization) with some tolerance foraligned metallization, and performing the diffusion in a beltfurnace. The areas where the dopant is directly deposited aredeeply diffused, whereas the areas in between the “fingers”are shallowly diffused due to the gas phase transporation ofthe dopant in the belt furnace. Fig. 9 shows a scheme of thisdiffusion principle. The advantage is that the process does notrequire any additional masking or etching steps. An excellentsurface passivation is obtained by applying a PECVD SiNARC layer in combination with a firing-through process, asdescribed earlier.

The spreading resistance depth profiles shown in Fig. 10demonstrate that the proposed simple method is able to pro-duce a selective emitter in only one diffusion step. Thistechnology is especially suited for screenprinted solar cellsand requires an alignment during the screenprinting of thefront metal contact. Industrially compatible, high-throughputscreenprinting systems equipped with digital cameras are nowcommercially available with precise alignment facilities. Asimple processing sequence comprising alkaline saw damage

Fig. 10. Spreading resistance profiles from two different regions on theSi-wafer diffused inone diffusion step.

removal and texturization, the selective diffusion step fromthe P paste, a very short thermal oxidation (800C 1 min), aPECVD SiN deposition (single ARC), and a screenprintedmetallization gives cell efficiencies comparable to that ob-tained in sophisticated laboratory processes. The best cellsmanufactured on large-area (100 cm) Cz-wafers reached anefficiency of 17.9% (independently confirmed by FhG-ISE,Germany), a significant result for a screenprinting process.The same process applied to large-area multicrystalline wafersproduced cells with efficiencies above 16%. Fig. 11 showsthat the efficiency improvement originates from a significantlyincreased “blue response” of the selective emitter cell [72]. Aproblem still remaining for the implementation of this selectiveemitter process into solar cell production lines is the lackof commercially available stable screens. However, the latestdevelopments in stencil screens give strong indications thatdurable screens without deformation during production willsoon be commercially available [28].

D. Medium-Term Implementable CrystallineSilicon Solar Cell Technologies

The technologies discussed in this section are those techno-logically proven to be promising, but not yet applied, or in theshort-term implementable, in large-scale industrial production.These technologies, in our opinion, will certainly be strongcandidates for industrial application within the foreseeablefuture. We will discuss them under three subtopics—SectionII-D1: rapid thermal processing; Section II-D2: back-contacttechnologies, and Section II-D3: porous Si technologies.

1) Rapid Thermal Processing:In the microelectronics(IC) industry, rapid thermal processing (RTP) technology hasbeen progressively replacing conventional furnace processingin various processing steps. In the case of RTP, the heattransfer between the heat source and the wafer is by radiation.The heat sources generally used are optical lamps whichproduce short wavelength radiation with distribution peaksin the range of 0.2–1.0 m The RTP process is typicallycharacterized by the Si wafers selectively absorbing theradiation from the lamps, i.e., the wafer getting heated,but with the surroundings remaining relatively cool. Thereis no real thermal equilibrium between the wafer and thesurroundings. The well-established applications of RTP in


Fig. 11. Improved spectral response of screenprinted selective emitter solar cells.

Fig. 12. Schematic of a typical RTP thermal cycle. (Inset: the system set-up).

IC processing include silicide formation and annealing,annealing of implanted junctions, defect annealing, TiN barrierformulation, epitaxy, RTCVD of thin films, SiN stackedgates, oxidation, densification of CVD and PVD films, andso on. Typical temperature ramps in RTP are in the range50–300 C/s. Earlier, compared to furnace processing, RTPhad such disadvantages as a lower temperature uniformityand repeatability. Improved design of present-day furnacesseems to tackle problems to a large extent with, for example,some reactors claiming 3 C variation on 200-mm waferswith a temperature repeatability of0.5 C [78]. With thetrend of today’s semiconductor manufacturing being towardshrinking device geometry and increased wafer size (300 mm),the requirements for ambient control and low thermal budgetare extremely stringent, and RTP meets these conditions betterthan the conventional furnaces. Fig. 12 shows a schematic ofa typical RTP thermal cycle.

A more recent application of RTP is the processing of solarcells where key process steps such as junction formation (bothemitter and BSF), growth of a passivating oxide, annealing

of Si/dielectric interface, and Si/metal contact firing, can allbe done in optically heated systems with low thermal mass.RTP is particularly attractive in solar cell applications due toreduce process time, reduced cross contamination, and lowthermal budget. Some of the most commonly used dopantsources for RTP junction formation are: APCVD PSG andBSG [79], [80], spin-on B- or P-sources [see [81]–[84],evaporated or screenprinted Al, etc. Typical RTP emitterdiffusion is performed in a very short time (1 min), andresults in junctions which are 0.15–0.25m deep. Suchshallow junctions generally give good blue response when thefront surface is efficiently passivated. The excellent surfacepassivation and structural properties of rapid thermal oxides(RTO) [85]–[87] and PECVD SiO/Si N [88] have beendemonstrated for RTP-diffused solar cell emitters. MIS solarcells have also been fabricated with thin RTO oxides [89] andoxynitrides. Furthermore, gettering effects during RTP havealso been reported [90], [91]. Even though very impressiveresults were obtained initially with laboratory cells with high-efficiency technology, application of low-cost techniques suchas screenprinted metallization remained a challenge for RTPshallow emitters, and required compromise. Progress has sincebeen made in applying SP metallization to RTP emitters withhigh enough and junction depth suitable for SP.

Though fairly comparable performance has been obtainedin RTP and conventionally processed cells, the throughput ofthe RTP process remains too low to meet the requirementof the PV industry [92]. The reason is that the present-dayRTP furnaces that are commercially available are built for themicroelectronics industry (single wafer process, 1 wafer/min)which imposes strict requirements on lateral temperature uni-formity and repeatability. For industrial solar cell processing,however, an acceptable throughput (at least 600 wafers/h)is the principal requirement, whereas some tolerance can beallowed in temperature, etc. Bearing this in mind, a continuousmode optical lamp processing scheme seems to be the best way


TABLE VIIPERFORMANCE EVOLUTION OF RTP-PROCESSEDSOLAR CELLS FABRICATED ENTIRELY BY RTP

to meet the throughput requirement of the PV industry. Re-cently, progress has been made in this direction as well, by theuse of tungsten halogen lamp heating systems with conveyor-belt arrangement [93]. In Table VII, some of the results ofsolar cells fabricated entirely by RTP without involving anyconventional furnace processes are summarized.

2) Back Contact Cell Technologies:In the total cost ofmodule manufacturing, close to one-third arises from themodule fabrication itself. Therefore, the reduction in moduleassembling costs can lead to significant overall cost reduction.One of the ways to achieve this is to have both P and Ncontacts at the back side of the wafer. This allows the moduleassembly to be done with a much higher degree of automation

with less stringent handling restrictions. In addition, the shad-owing losses are largely reduced on the front side. Variousstructures have previously been discussed in the literature forback contact cells. Some of these include the inter-digitatedback contact (IBC) solar cell [104], the front-surface-fieldsolar cell [105], [106], point contact solar cells [107], emitterwrap-through (EWT) cell [108], etc. However, most of thesestructures are designed for concentrator solar cells with ahigh-quality bulk material. The one-sun performance of backemitter structures using cost-effective processes on moderatequality material has recently been theoretically investigated[109]. The study revealed that a reasonable performance isachievable with a back emitter cell with cost-effective indus-


Fig. 13. Schematic cross section of an FMWT cell structure (sectioned alonga front finger).

trial processes, provided the material is thin (180 m) andof relatively good lifetime ( m) with an excellentfront surface passivation. A novel technology, called the FrontMetallization Wrap-Through (FMWT) cell, has been recentlydeveloped [110], where the busbars are moved to the backside of the cell with the fingers remaining on the front side andconnected to the busbars via holes. With this technology, mostof the difficulties encountered in applying the back contacttechnique to cost-effective processes are overcome for thefollowing reasons:

1) Since the p-n junction is close to the front surface,the demand for material quality and surface passivationbecomes less stringent.

2) Since the metal fingers are on the front side, only a smallnumber of vias need to be made to contact the rear busbar (a number of fingers can be grouped per via).

3) The shadowing losses are still reduced because thebusbars are moved to the rear surface.

4) Module connection becomes simple.

Fig. 13 shows a schematic of the FMWT cell structure. Ini-tial FWMT cells have been fabricated with full screenprint-ing technology on 100-cm multicrystalline Si substrates.A promising efficiency of 13.1% was obtained with SiNA.R.C. [110].

3) Porous Silicon Technologies:An alternative low ther-mal budget approach consists of the formation of a porous Silayer at the emitter surface. Thanks to the dependence of therefractive index on the porosity, the porous Si layer exhibitsgood anti-reflection properties [111]. Moreover, thanks to theinteraction between the incident light and the Si-pores, theporous layer shows a distinct diffuse transmittance [112],[113], allowing its use as an optical diffusor layer for Si solarcells, which can fully or partially replace a separate textur-ization step. When the porous Si layer is formed after frontcontact, one obtains essentially a selective emitter structure. Inorder to be of industrial relevance, the porous Si layer shouldprovide surface passivation of the emitter surface. Detailedanalysis revealed that the surface recombination velocity atthe porous Si-Si interface is high and should be improved totake profit of the full potential of this technique [112].

III. T HIN-FILM CRYSTALLINE SILICON SOLAR CELLS

In order to obtain a further cost reduction of crystalline Sisolar cells, it is necessary to address the substrate, the costs

of which represent about 50–55% on module level. This costis equally distributed over the cost of the Si base material,crystallization, and sawing. The first cost factor, associatedwith the Si base material, can be reduced by reducing cellthickness, whereas the costs of crystallization and sawing canbe fully avoided when depositing the Si layer directly on a(low-cost) substrate. This forms the economical argumentationfor thin-film crystalline Si solar cells, a research domainwithin photovoltaics which attracted great interest over thepast several years. The low-cost substrate can be metallurgicalgrade Si, a high-temperature ceramic, glass, or stainless steel.It must be noted here that the term “thin-film” covers a broadthickness range of 1–100m [114]–[116].

Neglecting surface recombination, the ultimate energy con-version efficiency of a thin-film Si cell with a suitable opticalconfinement scheme is higher than its bulk Si counterparts,since volume recombination is lower in the thin-film cell.In reality, however, surface passivation puts a more severeconstraint on the maximal cell efficiency than (Auger) bulkrecombination (see [117]). Practically speaking, this meansthat requirements on bulk diffusion length to obtain a highopen-circuit voltage can be relaxed at the expense of a strongeremphasis on well-passivated interfaces. Hence, a crystalline Sithin-film technology will only be economically viable whenthe combined cost of substrate and deposition techniques aresubstantially lower than the cost of a bulk Si substrate. Becauseof the lack of reliable cost data, there is not yet a well-established generally accepted opinion about the most suitedsubstrate and deposition technique. Therefore, the followingsections provide an overview of the large variety of techniquesby which the thin crystalline Si layer can be grown on a largenumber of substrate types. Associated with these, the mainenergy conversion efficiency results and tendencies will bereviewed together with the impact of specific requirementslike optical confinement and nature of substrate (conductiveversus insulating) on the cell design.

The most straightforward approach to get an overviewof this extended domain is using the maximal temperatureduring the manufacturing of the active thin Si layer as aguideline throughout the discussion. Using this approach, onecan discriminate between three temperature ranges. In the firsttemperature region, the Si layer will be in the liquid phase (

melting temperature of Si) for a certain period of time. Thesecond temperature range is situated between 800C and themelting temperature of Si. In this temperature range, thermallyassisted chemical vapor deposition (CVD) and solution growth(SG) are the prominent deposition techniques. A third class oftechniques is executed at temperatures below 650C All thedeposition techniques in the last temperature region requiresome additional source of energy (plasma, ion-assisted, hot-wire CVD) to speed up the Si deposition, as compared to thepurely thermally activated deposition process, or rely on solidphase crystallization (SPC) of an initially amorphous Si layer.This division in three temperature regions goes hand in handwith a discrimination on the level of substrates, compatiblewith a certain maximal temperature. Schematically speaking,the first temperature region requires high-temperature ceramicmaterials or a highly doped inactive Si substrate with a


TABLE VIIIOVERVIEW OF DIFFERENT TECHNIQUES AS A FUNCTION OF THE MAXIMAL TEMPERATURE USED THROUGHOUT THE MANUFACTURING

OF THE ACTIVE LAYER OF THE THIN-FILM CRYSTALLINE Si CELL. THE REFERENCESMENTIONED IN THE TABLE SHOULD NOT

BE CONSIDERED AS AN EXHAUSTIVE LIST, BUT RATHER AN INDICATION OF WHERE ADDITIONAL REFERENCES CAN BEFOUND

dielectric buffer layer in between the substrate and the activeSi layer. The second temperature region is compatible withceramic substrates, which have to satisfy less stringent require-ments, however, than in the former case. When the substrateconsists of crystalline Si (e.g., metallurgical grade Si (MG-Si)or a highly doped Si-ribbon), there is the advantage that theactive layer can be epitaxially grown on this Si substrate. Inthis way, the number of grain boundaries and crystal defects inthe active layer can be reduced. The third temperature region iscompatible with glass substrates and bears the strongest hopefor a substantial cost reduction to a cost below 1/Wpeak.These cell concepts also make the link with-Si:H celltechnologies (see, e.g., the “micrograph” cell [118]).

Table VIII shows schematically the relationship betweenthe technique, used for manufacturing the crystalline layer,the substrate compatible with the technique, and the degreeof industrial maturity at the current time. In the followingsections, the different techniques are reviewed in more detail,together with recent efficiency results for each technique.

A. Temperature Range 1:

When a Si-layer is deposited by thermal CVD on a non-Si substrate, the grain size of the material thus formed will

be in the order of a few microns (defined as fine-grainedmaterial throughout the remainder of this text). Although itwas proven by Beaucarneet al. [136] that, in such fine-grained polycrystalline Si layers, n-diodes with reasonablylow recombination currents can be realized, it goes withoutsaying that a large-grain material with grain size well above100 m is closer to today’s well-established multicrystallineSi solar processes. In order to convert the fine-grained materialto the desired large-grain material, the Si layer is molten andcooled down, a process called liquid phase recrystallization.

This process puts severe requirements on the thermal sta-bility and thermal expansion coefficients of the substrate andrequires the use of buffer layers in between active layerand substrate when the risk for undesirable indiffusion ofimpurities from the substrate into the active layer is too large.These layers have to be quite thick (1 m) in order to act asan efficient barrier (see [123] for ONO-layers or [119] for SiC-layers on graphite; ONO stands for a combination of oxideand nitride layers). Besides the necessity for buffer layersin between substrate and the Si-layer to be recrystallized,there is also a need for a thick capping layer (mostly aplasma-deposited oxide layer) on top of the Si-layer. Thecapping layer has to prevent breakdown of the molten layer in


TABLE IXOVERVIEW OF MAIN RECENT EFFICIENCY OBTAINED IN LAYERS WHICH HAVE BEEN SUBJECTED TO

A RECRYSTALLIZATION PROCESSDURING THE MANUFACTURING OF THE LAYER (� = NO ANTI-REFLECTIVE COATING)

Fig. 14. Schematic overview of process steps to be taken into account whenapplying a liquid phase recrystallization step in the manufacturing process ofthe crystalline layer.

separate droplets (dewetting of the film). For the liquid phaserecrystallization, a large variety of techniques are available:Zone Melting Recrystallization (ZMR) by Stripheater [119],[136], melting of the layer in a Large-Area Heater [121] orby -beam [120] or by a scanning laser beam [122]. After therecrystallization, the capping layer is to be removed again. Inmost cases, the recrystallized layer is highly doped and actsas a back-surface field to screen surface recombination at thebuffer layer/Si layer interface (see Fig. 14). The highly dopedrecrystallized layer has to be thickened by a second Si growthcycle, in which the active Si-layer with a lower doping level isepitaxially grown on the recrystallized layer. The techniquesused for this second step are, in most cases, CVD or LPE,the details of which are reviewed in more detail in the nextsection. It remains to be seen whether these additional stepswill remain compatible with the final objective of obtaining alow-cost material in which the solar cell can be processed. Inaddition, the recrystallization should be executed at a sufficientspeed. The final defect density in the recrystallized films is astrong function of the scanning speed. With such low scanningspeeds, the throughput of this approach is, however, very low.Thinning down the film to enhance the (100) texture in therecrystallized films allows higher speeds (up to 1 mm/s), but

this still might be unsufficient. Recent work [123], however,has revealed that liquid phase recrystallization at higher speeds( 10 mm/min) might be achievable.

Because the material thus recrystallized typically containselongate grains which can reach lengths up to several millime-ters, a typical solar cell process uses the same basic techniquesdeveloped for bulk multicrystalline Si solar cells like impuritygettering and defect passivation by hydrogenation. Table IXgives an overview of the efficiency results, which were re-ported by several groups.

B. Temperature Range 2: 800C

In these deposition processes, the layer is deposited onthe substrate (or substrate buffer layer). In the subsequentdiscussion, a distinction is made between Si and non-Sisubstrates.

1) Crystalline Si Substrates:When the substrate consistsof an inactive highly doped crystalline Si substrate, the layeris grown under such conditions that the crystalline structureof the substrate is perpetuated into the grown layer, a processcalled epitaxial growth. The advantage here is that the thusgrown layer has a large-grain crystal structure (or is evenmonocrystalline), depending on the characteristics of the Si-substrate. Since the grown Si layer and the substrate havecomparable optical properties, optical confinement is difficultto realize in such a system. The substrates of interest are low-cost Si-substrates which, because of their doping and impuritylevel, do not allow the realization of a solar cell with sufficientefficiency in the substrate. By growth of an epitaxial layerwith suitable doping level and reduced impurity level on topof this substrate, a solar cell can be realized on top of thissubstrate (see [125] for a detailed analysis of the impurityreduction in the grown layer). Highly doped monocrystalline Sisubstrates have been reported by several groups to demonstratethe efficiency potential of this approach. The epitaxial layersare realized by CVD or LPE (electrodeposition from moltensalts is a technique coming close to LPE—see, e.g., [129]).CVD has been extensively used in the past for the growth ofepitaxial layers on Si metallurgical-grade substrates (see, e.g.,[139] and [140]) and is still at the foreground in the thin-filmcrystalline Si photovoltaic activities of many groups (see, e.g.,


TABLE XOVERVIEW OF EFFICIENCY RESULTS OBTAINED ON SOLAR CELLS IN EPITAXIAL LAYERS GROWN ON HIGHLY DOPED INACTIVE CARRIER SUBSTRATES

[124], [125]). CVD takes advantage of the large expertise,available in the field of microelectronics, which is translatedin highly reproducible and uniform layers, both on the level ofthickness and dopant control. Nevertheless, one can observe astrong interest toward the application of LPE-growth for thin-film crystalline Si solar cells (see, e.g., [141] and [142]). LPEis a technique where growth proceeds from a molten solution.The supersaturation in the growth regime is low, which reducesthe defect density and defect activity. Numerous studies (see,e.g., [143], [144]) give strong support for this view. EBIC-pictures of partially masked structures gave unambiguousevidence of the reduced recombination in the LPE-layers.This reduction is caused by the tendancy to strive for thelowest energy configuration of the dislocation network in theLPE-layer. In addition, impurities will be contained in themolten metal solution because of the distribution coefficientbetween the liquid and solid phase. However, the close-to-equilibrium character of LPE also leads to topology problemson certain types of ribbons or defective substrates. Whengrowing epitaxial layers by the LPE-technique on RGS- [145]or SSP-ribbons [146], the epitaxial layers are much thinner inthe region of the grain boundaries, which leads to problemsduring the emitter diffusion. In the regions where the epitaxiallayer is much thinner, the nemitter diffusion and p substrateare in direct contact, resulting in leaky junctions.

Table X gives an overview of the efficiency results obtainedin epitaxial layers grown on highly doped inactive carriersubstrates, grown by various techniques and processed accord-ing to different solar cell process schemes. The experimentalresults obtained on monocrystalline highly doped substrates

confirm the large efficiency potential of thin-film crystallineSi solar cells, especially when combined with a suitablebackside reflector (the intermediate oxide layer in case of theSIMOX-substrate). When the epitaxial layers are grown onmulticrystalline highly doped substrates, solar cell processescontaining a step during which hydrogen is introduced in theepitaxial layer, either by remote plasma hydrogenation [147]or a firing-through nitride step [125], have proven to be crucial.This allowed efficiencies over 13% in layers of only 20mwith a fully industrial solar cell process.

The experimental results in Table X on different types ofsubstrates do not allow us to make a final assessment onthe most suited deposition technique for the developmentof an industrial thin-film crystalline Si-technology, allowinghigh-throughput and/or large-area. An evolutionary approach,based on the existing CVD-expertise in the industry and thewillingness of CVD-equipment manufacturers to adapt theirsystems to the needs of a crystalline Si thin-film solar celltechnology, leads to a technology roadmap in which CVDmight be the preferred deposition technology in the mediumterm, whereas LPE might overtake in the longer term.

2) Amorphous or Microcrystalline Substrates:When thesubstrate has an amorphous or microcrystalline structure, thedeposited Si layer will be polycrystalline. By optimized CVD-deposition sequences in which the Si nucleation on the foreignsubstrate is influenced by the addition of HCl (see [151] fordeposition on AlO -substrate), by fine-tuning the temperaturein a rapid-thermal CVD-system (see [126] for deposition onAl O - and mullite substrates), or by using a suitable seedinglayer (see [152] for polycrystalline layers on special high-


temperature glass), the grain size can be tuned in the range2–20 m In such fine-grained Si layers grown directly on anAl O -substrate, base diffusion lengths of more than 5mhave been reported for np solar cells [130]. The efficiencyof devices processed in the layers is still below 5%, mainlybecause of the large junction recombination, resulting fromthe interaction between the electrical field of the junctiondepletion layer and the grain boundary depletion layer. Theelectrical field of the grain boundary layer reduces the junctiondepletion layer field and thereby increases the width of the“sweet spot,” in which carrier recombination is large (see[153] for the numerical analysis of these effects and [136]concerning experimental verification).

When the Si layer is deposited by SG, the grain size is,in most cases, much larger (100 m [154]). The smallersupersaturation during SG, as compared to typical CVD-conditions, retards the grain nucleation. The retarded grainnucleation (in some instances, there is no nucleation at all) isone of the main technical difficulties associated with SG onforeign substrates. Pretreating the surface by plasma sprayingSi or depositing a microcrystalline Si layer by PECVD [127]on the foreign substrate, represents a possible solution for thisproblem (see [128]).

C. Temperature Range 3: 650 C

When deposited at this low temperature, the whole cellprocess can be compatible with glass or stainless steel as asubstrate. The use of such substrates influences the total cellstructure. Since a classical emitter diffusion is incompatiblewith these substrates, the emitter is deposited in most cases andconsists of amorphous or microcrystalline Si and Transparentconductive oxides are being used for contacting the device.

1) Low-Temperature Epitaxial Growth:Thermally-assis-ted epitaxial growth at temperatures beneath 800C is quitedifficult; the combination of a low growth rate and highoxygen incorporation degrade the crystallographic quality ofthe layer. By supplying additional energy, the growth rate canbe enhanced. This can be done in an ECR-CVD system [155]or by means of the ion-assisted deposition (IAD) process[156]. Reasonable epitaxial layers can be grown by thesemethods on a crystalline Si substrate or suited seeding layeron glass. By means of IAD of an epitaxial layer on a highlydoped monocrystalline Si substrate, an efficiency of 9.9% wasobtained for a 12.5-m thick Si film.

2) Solar Cells in Directly Deposited Microcrystalline SiLayers: A large variety of plasma-assisted deposition methodsfor the deposition of microcrystalline Si layers (grain size

1 m) can be found in literature. A common feature ofall these techniques is the use of a plasma environmentto speed up the decomposition of SiHBesides the moreclassical radio-frequency plasma-enhanced CVD (RF-PECVD;see, e.g., [157]), electron cyclotron resonance CVD (see, e.g.,[133]) and very-high frequency PECVD (see, e.g., [118])are being studied because the latter are expected to sufferless from ion bombardment. The VHF-PECVD-grown layers,especially, have resulted in efficiencies neighboring the 10%-threshold, though it is not fully clear to which extent these

cells rely on drift or diffusion as collection mechanism for thephotogenerated carriers. The main technological issue for thistechnique is the enhancement of the deposition rate for themicrocrystalline Si without degrading the layer quality andthe reduction of the oxygen level in the layer. By combininga microcrystalline Si bottom cell with an-Si:H top cell, theso-called “micromorph” cells, a stable efficiency of 12% wasreported, whereas an efficiency near 8% was obtained fora microcrystalline cell with a thickness of 3m Also, thecell structures reported by Yamamotoet al. [114] should bementioned here. By a combination of optimal light throughthe STAR-structure (naturally Surface Texture and enhancedAbsorption with back Reflector) and high-quality microcrys-talline Si layers, cells with a thickness of only 2m producedan efficiency of 10.7%. The details about the techniques usedfor the production of these layers, however, are not available.

A relatively new method for Si-deposition at low temper-ature is the so-called hot-wire method. The method is basedon the decomposition of SiHin the neighborhood of a heatedwire of tungsten. The deposition apparatus and conditions aredescribed by Middyaet al. [132]. Despite the high growth rates(5–20 m/h) and the low substrate temperature (lower than550 C), the films are polycrystalline with columnar grains.The grain size is in the order of 1m Doping is easilyachieved by adding PHor B H to the gas mixture. Solarcells yielded conversion efficiencies of 3.7% in a cell with athickness of 1.5 m [158]. Since the photoconductivity couldbe substantially improved by hydrogenation, it is expected thatthese efficiencies will increase in the near future. The maintechnological issue with this technique is the wear-out of thetungsten wire because of the silicidation of the surface, whichrequires frequent replacement of the wire in the chamber.

3) Solid Phase Recrystallization:An alternative ap-proach for the manufacturing of the crystalline layer involvesthe deposition of an amorphous layer, which is subjected to aSolid-Phase Crystallization (SPC) step. Most of the expertisein this field originates from the domain of polycrystallinethin-film transistors. An interesting example of this approach,which does not require a temperature higher than 600C,has been proposed by Babaet al. [134]. An amorphous layeris recrystallized starting from a highly P-doped layer at thebackside. The high P-doping (10 cm ) shortens theincubation time for nucleation from 60 min to 3 min. Therecrystallized layer acts then as a seed for columnar grains,which extend throughout the layer. By using an-Si:H/c-Siheterojunction on top of the structure, an efficiency of 9.2%was obtained on a 1-cmcell with a thickness of 5 m [134].

D. Genuine Solutions

The overview of the different techniques shows the effi-ciency potential of the different approaches without giving apossibility for a final assessment about the technique whichhas the highest industrialization potential. This is attributed toseveral causes. The first one is valid for the high-temperatureroads (regimes 1 and 2) and is related to the risk of impuritydiffusion from the “impure substrate” into the active layer.Buffer layers are a principal solution, but their effect on cost-


Fig. 15. Pyramidal-film texture for thin-film crystalline Si solar cells on glasssubstrates (after Bermann, 1996).

effectiveness is a matter of intense research and debate withinthe photovoltaic community. The second cause is related tothe low-temperature road, where a clear view on the relationbetween layer structure, layer contamination, and depositiontechnique is still lacking.

A first alternative approach to get around all these actualunknowns is the use of highly perfect and pure Si substrateswhich are reused several times for the deposition process. Thereusable substrate serves to grow a highly perfect crystallinelayer by means of well-established epitaxial techniques, afterwhich the layer is separated from the substrate. By transferringthe thus formed thin layer to a suitable substrate, opticalconfinement can be separately optimized [159].

A prominent example is the Perforated Silicon process,the so-called -process [160], where, by means of the ion-beam assisted technique, a thin Si epitaxial layer is grown ona textured (100) monocrystalline Si substrate, the surface ofwhich is covered with a porous Si layer. The porous Si layerallows epitaxial growth, and at the same time, an easy removalof the epitaxial layer from the substrate, which is reused ina subsequent growth cycle. The dimensions of the proposedstructure have been optimized for optimal light confinement(see Fig. 15) and should result in currents above 35 mA cmin layers as thin as a few microns [159].

A conceptually similar idea has been worked out byTayanakaet al. [161]. They used a porous Si interlayerbetween substrate and epitaxial layer exhibiting a porositygradient. The porous Si near the substrate has a high porosity,facilitating removal of the layer, whereas the top of the porousSi layer has a low porosity to withstand the high temperaturesused in a classical epitaxial growth cycle without collapsingthe porous structure. The authors processed solar cells inthese layers by means of a screenprinting process and reachedan efficiency of 12.5% in a layer of 11m An alternativeapproach uses the strongly selective character of LPE (Si-growth only occurs only in regions where the solution is incontact with Si) and the tendency of this growth techniquetoward formation of (111) facets during growth.

In the so-called Epilift-process, developed at AustralianNational University [162], an epitaxial Si-grid is grown ona Si-substrate covered with oxide in which narrow linesare opened (see Fig. 16). The openings in the grid allow awet etchant to reach and etch the connection points to the

Fig. 16. Illustration of the epi-lift process, based on selective growth by LPEin local openings in an oxide layer (after Weber, 1996).

Fig. 17. Illustration of the reduction of the area influenced by a grainboundary (shaded area) in the case of a single-junction (left) compared toa parallel multijunction structure [163]. Figure reprinted with permission ofthe American Institute of Physics.

substrate. No cell results are available yet for this technique.A basically different approach consists in maximizing thecollection efficiency for the photogenerated carriers, evenwhen the diffusion length in the Si layer is only a few microns.A structure which is principally very insensitive to grainboundaries is the parallel multijunction (see Fig. 17 and [163]).

The efficiency potential is illustrated by an efficiency of17.6% obtained on a four-layered cell with an active thicknessof only 17 m [164]. Although at first sight, the reader mightexpect that the thickness of the individual layers also playsa strong role in the reduction of series resistance losses, thedesigner has a larger freedom in optimizing their thickness,thanks to re-injection effects between different layers [164].The increase in the number of depletion regions in the mul-tijunction cell raises concerns about the recombination in thejunction region which might dominate the dark current [165].Careful design of the junctions by inclusion of an intrinsicregion in the depletion layer and optimization of the fieldstrength are predicted to overcome these difficulties [166].

E. Industrial Thin-Film Crystalline Si Cell Initiatives

The next section provides information, available in the openliterature, on commercial processes used for the production ofthin-film crystalline Si devices. The information given is, ingeneral, very generic and does not reveal any details aboutsubstrate or used deposition technique.


1) Silicon-FilmTM Process, Commercialized by Astropower:Although most of the development in this field is still in anearly stage, the formation of continuous sheets of polycrys-talline silicon on conductive ceramics, the so-called Silicon-Film process, has already been put in the test production.Since these sheets are fabricated at the desired thickness, ingotsawing is avoided, leading to a significant cost reduction.Silicon-FilmTM is a proprietary process and only a verygeneral process sequence is published. The generic processconsists of ceramic formation, metallurgical barrier formation,polycrystalline layer deposition, emitter diffusion, and contactfabrication by screenprinting. The conductive ceramic sub-strate is fabricated from low-cost selected materials. The met-allurgical barrier prevents substrate impurities from enteringand contaminating the active thin silicon layer. In addition, therandomly textured and highly reflective metallurgical barrierlayer improves the light trapping. A suitable p-type doped30–100 m active layer is deposited from a liquid solution.Extensive gettering by means of phosphorus and aluminumtogether with H-passivation are needed to improve the bulkdiffusion length from the initial value of 20–40m Thisresulted in a best efficiency of 16.6% for small-area cells of1 cm [167]. Large-area cells with areas of 240, 300, and700 cm are developed. A cell with an area of 675 cmhasdemonstrated a record efficiency of 11.6%, whereas 12.2% wasachieved on a cell with an area of 240 cm[168]. PV-moduleswith Silicon-FilmTM cells are now under test production.

2) Parallel Multijunction Concept, Commercialized by Pa-cific Power: Based on the concept of Fig. 17, a large industrialinitiative has been started up under the name Pacific Solar, butno details about the deposition technique nor the cell processhave been revealed in the open literature.

F. Outlook for Thin-Film Crystalline Si Technologies

The results obtained by the different thin-film crystallineSi technologies on a wide variety of substrates provide con-vincing evidence that this type of technology can bring abouta significant reduction of the cost/Wp as compared to bulkcrystalline Si solar cells. The uncertainty about the choiceof optimal substrate and deposition technique will probablyresult in an evolutionary approach where the investmentsinto an industrial crystalline Si thin-film technology are tobe backed by expertise existing within the microelectronicand photovoltaic industry as well as a close cooperation withequipment manufacturers.

IV. CONCLUSIONS

An overview has been given of current industrial and nearfuture implementable crystalline silicon solar cell technologies.Crystalline silicon solar cells are alive and kicking and there isstill plenty of efficiency increase and production cost decreasepotential to saveguard its relative market share in comparisonwith competing materials for quite some time, if not forever,provided a solution is found for the availability of the neces-sary feedstock materials. One possibility for this is the use ofrelatively thin crystalline silicon layers on cheap substrates.

ACKNOWLEDGMENT

Many and sincere thanks to all the members of the Pho-tovoltaics Department of IMEC and supporting groups fortheir continuous and enthusiastic R&D efforts. A lot of resultsmentioned in this paper are based on their excellent work, asevidenced by the many references.

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Johan F. Nijs (M’91–SM’97) received the M.S. de-gree in electrical (electronic) engineering, the Ph.D.degree in applied sciences, and the M.B.A. degreefrom the Katholieke Universiteit (K.U.) Leuven,Belgium, in 1977, 1982, and 1994, respectively.

After a training period of two months at Philips,he joined the Electronics, Systems, Automation, andTechnology (ESAT) Laboratory of K.U. Leuven in1977 on a research program for the fabrication ofsilicon solar cells. From 1982 to 1983, he was aPostdoctoral Visiting Scientist at the IBM T. J.

Watson Research Center, Yorktown Heights, NY, working on the subjectof amorphous silicon technology. In 1983, he became a Research Assistantat the ESAT Laboratory of K.U. Leuven, and in the 1984, he joined theInteruniversity Microelectronics Center (IMEC), Leuven, as Head of thesilicon thin-film transistors on glass. Currently at IMEC, he is Director ofthe Photovoltaics Department, including long-term research on photovoltaicmaterials, concepts, and technologies, development of industrial crystallinesilicon solar cell fabrication technologies, and activities on photovoltaicsystems and their integration. In 1990, he was also appointed part-timeAssistant Professor at the K.U. Leuven. He has authored or coauthored morethan 200 papers published in conference proceedings and technical journals,and he is inventor/coinventor on ten patents/patent applications.

Jozef Szlufcik (M’93) was born in 1956. He re-ceived the M.S. degree in electronic engineeringin 1981 and the Ph.D. degree in 1989, both fromTechnical University of Wroclaw, Poland.

From 1981 to 1990, he had been working atthe Institute of Electronics in Silesian TechnicalUniversity, Gliwice, Poland, focusing his researchon thick-film microcircuits and photovoltaics. Hejoined the Interuniversity Microelectronics Center(IMEC), Leuven, Belgium, in 1990, where he iscurrently responsible for research and development

on low-cost solar cell processing techniques (group industrial solar cellprocessing). He has authored or coauthored nearly 50 papers that have beenpublished in conference proceedings and technical journals and has beengranted four patents in the field on microcircuits and photovoltaics.

Dr. Szlufcik is a member of the International Society for Hybrid Micro-electronics (ISHM).

Jozef Poortmans (M’99) received the M.S. de-gree in electronic engineering from the KatholiekeUniversiteit (K.U.) Leuven, Belgium, in 1985, andreceived the Ph.D. degree in June 1993, also fromK.U. Leuven. The subject of his Ph.D. study wasstrained SiGe-layers, grown in an UHV-VLPCVDhome-build reator. Both the deposition and the useof these SiGe-alloys within the base of a hetero-junction bipolar transistor were investigated in theframe of this study.

He the joined the Interuniversity MicroelectronicsCenter (IMEC), Leuven, where he was active in laser recrystallization ofpolysilicon anda-Si for SOI-applications and thin-film transistors. He joinedthe photovoltaics group, later department in IMEC, where he is actuallyresponsible for the group New Materials and Technologies. Within this groupthere are two main activities: the development of low thermal budget processes(RTP, plasma deposition), and thin-film crystalline Si solar cells on Si- andforeign substrates. He has authored or coauthored more than 130 paperspublished in conference proceedings and technical journals. He also had twobook articles about the properties of SiGe-alloys and heterojunction bipolartransistors published in 1994.

S. Sivoththaman(S’84–M’93–SM’98) received thePh.D. degree from the University of Paris, France,in 1993.

Since 1993, he has been with the InteruniversityMicroelectronics Center (IMEC), Leuven, Belgium.He is with the Photovoltaics (PV) Department in theMaterials, Components, and Packaging (MCP) Divi-sion and is currently responsible for implementationof new technologies. He has authored or coauthoredmore than 45 papers in refereed scientific journalsand conference proceedings. His current research

interests include silicon device and process technologies, low thermal budgetdielectrics, device physics, and modeling.

Dr. Sivoththaman is a member of the Materials Research Society (MRS)and the IEEE Electron Devices Society.

Robert P. Mertens (M’72–SM’82–F’94) receivedthe Ph.D. degree from the Katholieke UniversiteitLeuven, Leuven, Belgium in 1972. He was aVisiting Scientist at the University of Florida,Gainesville, in 1973. After his return to Belgiumin 1974, he became a Senior Research Associateof the National Foundation for Scientific Researchof Belgium. In 1984, he joined the InteruniversityMicroelectronics Center (IMEC), Leuven, as Vice-President, and was later Senior Vice-Presidentresponsible for research on materials, components,

and packaging. These activities include research on microsystems, photo-voltaics, and solid-state sensors. Since 1984, he has also been a Professor atthe University of Leuven, where he is teaching courses on devices and ontechnology of electronic systems.

Dr. Mertens was elected a Fellow of the IEEE for contributions to heavilydoped semiconductors, bipolar transistors, and silicon solar cells.

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Advanced manufacturing concepts for crystalline silicon solar cells

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