• 8086/8088 – Segments are 216 = 64kbytes – Note that segment can be contiguous, adjacent, disjointed, and
overlapping.
12
SWA.23
Memory Management Segmentation – IA-32
Segment
Selector Offset (8 nibbles)
Logical Address Linear Address
Space
Linear Address
Segment
Segment Base Address
Segment Table
(Global or Local Descriptor Table)
(located in memory)
+
SWA.24
Memory Management Protected-Mode
• Protected-Mode operation allows memory above the first 1Mbytes to be accessed by the 80286 through the latest Pentium,
• Protected-mode introduces protection: – 8088/86 is unable to block general functions
from accessing the kernel of the operating system (a program can go from any code segment to any other code segment). In protected mode the OS is given a mechanism to prevent the user from accidentally taking over the core of the OS and thus crashing your computer.
13
SWA.25
Memory Management Paging
Directory Table Offset
Linear Address
Page
Directory
Entry
Page Tables
Entry
Physical Address
Space
Phys. Address
Page
Page Directory
Base Address
(from CR3)
+
SWA.26
Memory Management Segmentation & Paging – IA-32
Directory Table Offset
Linear Address
Page
Directory
Entry
Page Tables
Entry
Physical Address Space
Phys. Address
Page
Page Directory
Base Address
(from CR3)
+
Selector Offset
Logical Address
Segment Table
(Global or Local Descriptor Table)
(located in memory)
+
Paging Segmentation
14
SWA.27
Instruction Set Architecture
SWA.28
Programming Languages
High-level Language (C, C++, Pascal, BASIC,FORTRAN)
Compile & Link
Machine Code (Bytes stored in memory)
Assembly Language
Assemble
Machine Code (Bytes stored in memory)
Tool: Compiler & Linker Tool: Assembler
A mix of assembly and a high-level language can be used: inline-assembly
Source Code:
15
SWA.29
Assembly Language Assembly Statements
START: MOV AX,34EH ; Move 34EH into the AX register
MOV DX,[1234H] ; Move the contents of the DS memory location
; with offset 1234H into the DX register
ADD DX,AX ; Add AX to DX and store the result into DX
END
Label
Mnemonic
Argument Comments
MOV AX , 34EH
Destination
Source
SWA.30
Register Transfer Language (RTL) Intro
• RTL is machine independent !!!!
( • ) = “Contents of • ” = “Move operand on right-hand-side source to the left-hand-side destination” „&‟ = “AND ” „|‟ = “OR” „^‟ = “Exclusive-OR” „+‟ = “Addition” „-‟ = “Subtraction” „*‟ = “Multiplication” „/‟ = “Division”
VHDL and Verilog are also machine independent description languages but they differ from RTL
16
SWA.31
Assembly Language Assembly Statements - RTL
START: MOV AX, 34EH
MOV DX, [1234H]
ADD DX, AX
AX 34Eh
DX (1234h)
DX (DX) + (AX)
Effective Address 1234h
SWA.32
Machine Code Listing
00C00 B8 4E 03 START: MOV AX,34EH
00C03 8B 16 34 12 MOV DX,[1234H]
00C07 01 C2 ADD DX,AX
END
Address Program bytes in memory
Byte located at memory location (ML) 00C0516
Generated automatically by the Assembler or manually using the instruction information sheets as can be found in Volumes 2a and 2b.
17
SWA.33
Machine Code In Memory
Assembly will be converted to machine code for machine interpretation. As a result the program consists of a bunch of bytes in memory!
1216
8D16
1E16
0063316
0063416
0063516
5616
0416
4016
4B16
0116
0063616
0063716
0063816
0063916
0063A1
6 D816 0063B16
A116
3416
2516
OF16
0063216
0063116
0063C16
0063D1
6 OF16 0063E16
mov ax,[1234] ax (123416)
mov bx,[0456] bx (045616)
inc ax ax (ax) + 1
dec bx bx (bx) - 1 add ax,bx ax (ax) + (bx)
and ax,0F0F ax (ax) & 0F0F16
x86 Assembly RTL
SWA.34
Instruction Set Architecture IA-32
• General purpose – Arithmetic, Logic, Shift – Control and Branch, – Data movement.
Example 1: MOV AX, [BX]+123H -> (BX)+123H is the effective address or offset
within the data segment (DS).
Example 2: ADD CX, [BP][SI]+12H -> (BP+SI)+12H is the effective address or offset
within the stack segment (SS).
One can override the default segment by explicitly indicating the segment within
which the data can be found.
Example 3: MOV AX, ES:[BX]+123H -> (BX)+123H is the effective address or offset
within the extra segment (ES).
SWA.46
Addressing Effective Address/Offset
bits32
bits16
bits8
none
8
4
2
1
*
)(
)(
)(
)(
)(
)(
)(
)(
)(
)(
)(
)(
)(
)(
)(
:
DIE
SIE
BPE
BXE
DXE
CXE
AXE
DIE
SIE
BPE
SPE
BXE
DXE
CXE
AXE
GS
FS
ES
SS
DS
CS
Segment Base Displacement
(a) 32-bit x86 Architectures
bits-16
bits-8
none
:DI
SI
BX
BP
ES
SS
DS
CS
Segment Base Index Displacement
(a) 16-bit x86 Architectures
( Index * Scale) Note 1:
Right-hand side of
the colon is referred
to as the effective address
Note 2:
Each component can
be positive or negative
(2s complement).
24
SWA.47
Constructing Addresses Default combinations
Segment Offset Special Purpose
CS IP Instruction address
SS SP and BP Stack address
DS BX, DI, SI, 8-bit number, 16-bit number Data address
ES DI String destination address
16-bit segment and offsets (Table 2-3 in textbook)
Segment Offset Special Purpose
CS EIP Instruction address
SS ESP and EBP Stack address
DS EAX, EBX, ECX, EDX, ESI, EDI,
8-bit number, 32-bit number Data address
ES EDI String destination address
FS No default General address
GS No default General address
32-bit segment and offsets (Table 2-4 in textbook)
SWA.48
Instruction Format Machine Code
25
SWA.49
Operands – Volumes 2a & 2b
“IA-32 Intel® Architecture Software Developer‟s Manual”, Volume 2a, pp. 3.640
SWA.50
Operands
26
SWA.51
Operands
SWA.52
Operands
27
SWA.53
SWA.54
28
SWA.55
SWA.56
Example 1
Ex 1 (286): MOV AX, [BP] + 1988H
r16 m16 MOV r16, m16
Volume 2a pp. 3-582(631)
29
SWA.57
SWA.58
Example 1
Ex 1 MOV AX, [BP] + 1988H
8B 86 88 19 Displacement: low-byte first
30
SWA.59
Example 2
Ex 2 (286): ADD [BP][DI]+1234H , CX
01 8B 34 12 Machine Code:
SWA.60
31
SWA.61
Example 3
Ex 5 (Pentium/Core): MOV EAX,[EBX+4*ECX]
Result: 8B 04 8B H
SWA.62
32
SWA.63
SWA.64
Others
Ex 4 : SUB BX , 03EFH
Result: 81 EB EF 03 H
Ex 5 : MOV [1234H], DS
Result: 8C 1E 34 12 H
33
SWA.65
Operand Table Examples
MOV r/m32, r32 Destination Source MOV [12345678H], EAX Memory direct Register direct MOV EDX, EAX Register direct Register direct MOV [EBP],ECX Based Register direct
MOV r/m16, imm16 Destination Source MOV [12345678H], A432H Memory direct Immediate MOV DX, A432H Register direct Immediate MOV [EBP], A432H Based Immediate
SWA.66
Utilization of registers or displacements
Type Base Index Scale Displacement
Register Operand No memory address required
Immediate Operand No memory address required
Direct2 - - - X
Register indirect X or X - -
Based X - - X
Index X - X
Based-Index X X - X
Scaled-Index1 - X X X
Based Scaled-Index1 X X X X
Addressing Modes IA-16 & IA32
1Only available in the 80386 through Pentium 2Or displacement addressing
