Advanced Packaging – Future ChallengesSuresh Ramalingam

© Copyright 2016 Xilinx.

Technology Trends in Packaging

3D IC Technology Development

Summary

Outline

Stacked Silicon Interconnect Technology Refers to Xilinx 3D solutions

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Cavity Down BGAs

Multi Chip Module

Flip Chip BGAs – EU bump

QFPs

2000-2010 2011 - 2016 2017 - 2020

Industry Trends in Packaging

Flip Chip BGAs – High

Pb/EU bump

PBGAs

CSPs

Flip Chip CSP

Flip Chip BGAs – Pb-free/Cu pillar

bump

Homogeneous SSIT

2.5D: SOC + HBM

SLIT

Surface Mount Leadframe 1st Generation BGAs 2nd Generation BGAs: Flip Chip 3rd Generation: WL, 2.5D, 3D 3D & Photonics Integration

Active Stacking

Photonics IOs

1990-2000

Cu-wire

Flip Chip PoP

SiP

Wafer level fan-out

3D TSV

Cu-pillar BOT and ETS

Until 1990

Panel/Wafer level 3D

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Multi-Die Technology (Side-by-Side)

Total silicon die area (mm2)

BT/WiFiPA

PM

Peripheral

I/O Controller

Laminate SiP

High

I/O

densi

ty

102

103

>104

Application Processor

Baseband

AP/BB die partition

AP + WIO

CPU + DRAMStandard fan-out

W/S<10/10um, ML<2

Advanced fan-out

W/S<3/3um, ML<3

GPU,CPU + Memory

FPGA + ASIC

FPGA die partition2.5D Si interposer

W/S<1/1um, ML > 3

• EMIB

• Fan-out

• POSSUM

• Fine Line Substrate

• Glass interposer

Grey Zone: Scaling(multi-die integration & fine line & metal layer)

Underfill

Temporary Bond

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3D IC Technology Landscape

Oxide-to-oxide

bond

Cu-to-Cu bond

Chip level Device level W2W C2W level

Players

Samsung DRAM / Hynix NAND & DRAM / IBM /

Micron / Elpida / Qualcomm / Nokia

Samsung Vertical-Gate NAND/ Besang /

Monolithic 3D IC / Stanford

SONY (Stacked CIS) / Tezzaron / Ziptronix/

MIT Lincon Lab

TSV size 5~10um 0.5~2um contact through oxide 2~5um in diameter

TSV pitch 30~50um 1~4um (not limited) 5~10um

TSV count 1k~5k Not limited Not limited

Key features

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Supply Chain

TSMC CoWoS in production

UMC/SPIL technology is qualified

TSV Si

Interposer

TSV Si

Interposer

Chip-on-Wafer

Bonding (1)

FPGA (1)

Memory (2)

Logic IP (3)

Thinning/

C4/Sorting

Packaging on

substrate

Final Test &

Shipment

TSMC CoWoSTM

UMC

SPIL

Interposer Thinning/

C4/Sorting

KGI die

reconfiguration

*Re-usable cavity wafer

De-carrier &

Dicing

Packaging on

substrate

uBump/Sort

uBump/Sort

uBump/Sort

KGD (1~3)

chip stacking

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3D IC Technology Development

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3D IC Anatomy & Assembly Flow

Micro-BumpsPower / Ground / IOs / Routing

Through-Silicon Via (TSVs)Connects Power / Ground / IOs to C4 Bumps

Passive Silicon Interposer (65nm)4 Metal Layers Connecting Micro-Bumps & TSVs

C4 Bumps Connects Silicon to Package

> 150,000 Micro-bumps

> 10,000 TSVs

> 10,000 C4 Bumps

> 90 Processing Steps in 3D IC Flow (From Bump

to Completed Package)

Primary Chip on Wafer Assembly Steps

Achieved Good Yield & Quality

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CoWoS Technology

– Top dies are attached to full-thickness interposer wafers thus getting around the thin interposer warpage and poor micro-

bump joining problem

Reconfigurable CoW (rCoW) Technology

– Xilinx patent issued worldwide (US/TWN/CN/EU/IND/JPN/KR)

– Release layer approach that withstands reflow & maintains low warpage

Warpage controlKeep warpage below <10um over entire temp range

CoS

CoWoS rCoW

Critical Challenge: Warpage Control

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HTS Aging Reliability Issue

Voiding or crack in micro-joint during long term stress (HTS in particular)

– Due to limited Sn source and its dual consumption rate from top and bottom pad

Resolution : Heavy Cu doping into LF solder cap (with Ni barrier layer)

– Xilinx patent issued

– Take advantages of ductile IMC (Cu-Sn) and slower IMC reaction (Ni with Cu-Sn IMC)

– Passed 3X reflow + 150oC aging condition for > 1000 hrs

-Stable Cu-Sn IMC

-Super slow IMC reaction

Standard

Cu/Solder

Diffusion flux model of inter-diffusion HTS aging performance

-Fast Cu-Sn reaction

-kirkendal void form

-Ductile IMC

-Brittle NiSn IMC

-Slow IMC reaction

-Large Vol shrinkage

Hybridized

*Reference images

(from no-doping u-bump)

In production

(Monolithic)Target

In production

(SSIT)

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High Speed Signaling - Substrate Materials

32G2.0 dB insertion loss at Nyquist Frequency

Low loss substrate and design

56G

Ceramic

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Economic and technology forces

are aligned to enable 2.5D/3D stacking

The “end game” will see three distinct

technologies: Logic, Memory, Analog

TSV and 3D stacking already deployed in Smartphones,

High end FPGAs & Servers

Summary

Analog Logic Mem

Package

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END