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Applied Materials Confidential SILICON SYSTEMS GROUP Advanced Packaging Technology 5 th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM
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Page 1: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential SILICON SYSTEMS GROUP

Advanced Packaging

Technology

5th March 2013

Jeff Turner, SBU GPM

Isaac Ow, MDP GPM

Page 2: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

Outline

Bumping adoption and drivers

Supply chain

Scaling & new challenges

Keys to obtaining good contact resistance

Keys to obtaining good WID uniformity

Page 3: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

Drivers

- Form Factor requirements

- Power efficiency

- Performance

- Cost is not the main

consideration, however, rising

Au prices + lower cost of

bumping pushes for the

adoption

- Increased I/O requirements

- New schemes that needs

bumping - Interposers

- BSI CIS

- TSV 3D IC

WLP (Bumping) Adoption is Growing

Page 4: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

RDL/Micro-Bump Scaling

Technology Node (nm)

Po

lym

er

op

en

ing

/ P

itch

m)

≤32/28nm Node ≥45nm Node

<30µm

≤32/28nm Node ≥45nm Node

Via

Rc (

mO

hm

s)

Via Rc

Requirement

Typical Via Rc

Performance

<20µm

>60µm

Page 5: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

PVD UBM/RDL

Typical Packaging Flow

Degas PVD Ti PVD Cu Sputter

Etch

Preclean

Bondpad

Polymer (PI) coating and patterning

Resist coating and patterning

ECD Deposition

Resist strip and

UBM etch

Surface

Prewet

Resist

Strip Ti/Cu

UBM Etch ECD

Cu/Ni/Solder

Page 6: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

WLP Roadmap Challenges

Reliability • Electro-migration (IMC engineering)

• Stress management (CTE, Ductility, Low

MP alloys)

• Chip-package interaction (Low K damage)

• Voiding, Composition

Wafer Handling • Low temp. processes

• Thin wafer warpage control

• Bonded (Glass/Epoxy) substrates

Contact Resistance • Rc challenge with via pad reduction

• Next gen Polymer outgas (Low T)

• Thicker Polymer

Pillar/bump • Within-Die (WID) NU%

• Ultra-fine pitch interconnects

Glass/Epoxy

Page 7: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

Contact Resistance – Preclean Tech is Key

[1] JVSTA 8(3) May/June 1990 P2376-2381,

[2] Mater. Res. Soc. Symp. Proc. Vol908E – OO14-07.1 2006

Page 8: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

Contact Resistance – Preclean Tech is Key

Source: Adam R. Zbrzezny et al, Reliability of High I/O

Count Wafer Level Packages, 2008 Electronic Components

and Technology Conference

Smaller polymer opening (smaller A)

Thicker Polymer layer

(More outgassing)

Source: Glenn Rinne et al, Reaching Détente in the Design and

Material Selection for Hi Rel WLCSP's, 2004 Electronic

Components and Technology Conference

Rc = ρ(L/A)

Page 9: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

Within Die Non-Uniformity Factors

Current Distribution (sub-die scale)

– Local Current Distribution effects have shown to be minimal in modeling and empirical results

Reaction Profile

– Competing Reactions – hydrogen evolution (not a factor as long as mass transfer is high enough)

Mass Transfer

– Tests changing Bulk (wafer level) Concentration Gradients (changing agitation rates) have shown

minimal impact

– Tests impacting Local (feature level) Concentration Gradients indicate a potential path for

improvement to WID NU

9

AR = 2

Convection

Diffusion

Cu2+ depletion in the bottom of the via

can lead to variations in local plating rate

Via Level Model Generated by Semitool’s Computational Fluid

Dynamics Modeling Group

Applied internal

Data

Page 10: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

0%

1%

2%

3%

4%

5%

6%

Baseline Chemistry Mechanical

Conditions Modifications Modifications Future

WID

NU

%

WID NU% Reduction Progress

DC Process

Modified waveform

Within Die Non-Uniformity Improvement

10

26% Reduction

26% reduction in WID NU

Page 11: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

APDC Overview

Located in Singapore: Situated in proximity to customers,

engineering & manufacturing

Over 50 staff: Process, hardware, product management,

technical & customer support

14,000 sqft class 10 cleanroom: 11 AMAT tools & full integration

capability

Key focus: wafer level packaging, product development, process

integration, customer demos, collaboration and training

Page 12: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

Applied Materials Confidential

R 140

G 140

B 140

R 220

G 220

B 220

R 69

G 153

B 195

R 254

G 203

B 0

R 255

G 121

B 1

R 234

G 40

B 57

R 155

G 238

B 255

R 146

G 212

B 0

R 75

G 75

B 75

R 6

G 30

B 60

SILICON SYSTEMS GROUP

Via Reveal Via Last/

CIS-TSV

Via Middle/

Interposer

Interposer

Wiring

RDL/ UBM

Microbump

Focus Areas by Application

New hardware & product

development

New applications

Materials selection &

Integration

Unit & integrated

processes demos

Page 13: Advanced Packaging Technology - Applied Materials...Advanced Packaging Technology 5th March 2013 Jeff Turner, SBU GPM Isaac Ow, MDP GPM

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