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AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4...

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applications. and all claims, damages, loss, cost, expense or liability arising out of or in connection with the use or performance of products in such part, for any claim or damage arising from such use, and agree to fully indemnify, defend and hold harmless Avnet from and against any party using or selling products for use in any such applications do so at their sole risk and agree that Avnet is not liable, in whole or in nuclear applications or applications in which the failure of the product could result in personal injury, death or property damage. Any AND/OR NON-INFRINGEMENT. This material is not designed, intended or authorized for use in medical, life support, life sustaining or WARRANTIES AND CONDITIONS OF MERCHANTABILITY, SUITABILITY OR FITNESS FOR A PARTICULAR PURPOSE, TITLE INCLUDING, WITHOUT LIMITATION, REPRESENTATIONS REGARDING ACCURACY AND COMPLETENESS, ALL IMPLIED "AS IS" basis. AVNET HEREBY DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, to this material or resulting from its use. Avnet makes no warranty or representation respecting this material, which is provided on an Avnet is not responsible for typographical or other errors or omissions or for direct, indirect, incidental or consequential damages related service marks and trade names other than its own. trade names are the properties of their respective owners and Avnet, Inc. disclaims any proprietary interest or right in trademarks, without the prior written permission of Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All trademarks and This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in any form or by any means Copyright 2018, Avnet, Inc. All Rights Reserved. 01 BOM: 12:24:07 pm Time: AES-ULTRA96-G B Doc Num: 27 Variant: 00 1 SCH-US1DEV 1 3/9/2018 of Sheet: Date: Sheet Title: PCB Rev: Size: Project Name: Avnet Design Services Revision:1 Avnet Design Services Sheet Name 1 2 3 4 5 6 D C B A 6 5 4 3 2 1 A B C D AES-ULTRA96-G 01 - Avnet Lead Sheet 02 - Block Diagram 03 - Zynq Bank 0 04 - Zynq Banks 26 - HD 05 - Zynq Banks 65 66 - HP 06 - Zynq BAnks 500 501 502 - MIO 07 - Zynq Banks 503 - Config 08 - Zynq Bank 504 - Memory 09 - Zynq Banks 505 - GTR 10 - Zynq Power 1 11 - Zynq Power 2 12 - GND 13 - Zynq Decoupling 14 - LEDs 15 - PS LPDDR4 DRAM 16 - Fixed Clocks 17 - Expansion Headers 18 - PS Display Port Connector 19 - PS Display Port IO 20 - PS Micro SD Card AES-ULTRA96-G Avnet Lead Sheet www.ultra96.org 21 - PS WiFi - Bluetooth 22 - PS USB 3_0 ULPI Upstream 23 - PS USB 3_0 ULPI Downstream 24 - PS USB 3_0 Hub 25 - I2C MUX 26 - PMIC 27 - Power Connector - Mounting Holes
Transcript
Page 1: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

applications.

and all claims, damages, loss, cost, expense or liability arising out of or in connection with the use or performance of products in such

part, for any claim or damage arising from such use, and agree to fully indemnify, defend and hold harmless Avnet from and against any

party using or selling products for use in any such applications do so at their sole risk and agree that Avnet is not liable, in whole or in

nuclear applications or applications in which the failure of the product could result in personal injury, death or property damage. Any

AND/OR NON-INFRINGEMENT. This material is not designed, intended or authorized for use in medical, life support, life sustaining or

WARRANTIES AND CONDITIONS OF MERCHANTABILITY, SUITABILITY OR FITNESS FOR A PARTICULAR PURPOSE, TITLE

INCLUDING, WITHOUT LIMITATION, REPRESENTATIONS REGARDING ACCURACY AND COMPLETENESS, ALL IMPLIED

"AS IS" basis. AVNET HEREBY DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO,

to this material or resulting from its use. Avnet makes no warranty or representation respecting this material, which is provided on an

Avnet is not responsible for typographical or other errors or omissions or for direct, indirect, incidental or consequential damages related

service marks and trade names other than its own.

trade names are the properties of their respective owners and Avnet, Inc. disclaims any proprietary interest or right in trademarks,

without the prior written permission of Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All trademarks and

This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in any form or by any means

Copyright 2018, Avnet, Inc. All Rights Reserved.

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV

1

3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

Revision:1

Avnet Design Services

Sheet Name

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

AES-ULTRA96-G

01 - Avnet Lead Sheet

02 - Block Diagram

03 - Zynq Bank 0

04 - Zynq Banks 26 - HD

05 - Zynq Banks 65 66 - HP

06 - Zynq BAnks 500 501 502 - MIO

07 - Zynq Banks 503 - Config

08 - Zynq Bank 504 - Memory

09 - Zynq Banks 505 - GTR

10 - Zynq Power 1

11 - Zynq Power 2

12 - GND

13 - Zynq Decoupling

14 - LEDs

15 - PS LPDDR4 DRAM

16 - Fixed Clocks

17 - Expansion Headers

18 - PS Display Port Connector

19 - PS Display Port IO

20 - PS Micro SD Card

AES-ULTRA96-G

Avnet Lead Sheet

www.ultra96.org21 - PS WiFi - Bluetooth

22 - PS USB 3_0 ULPI Upstream

23 - PS USB 3_0 ULPI Downstream

24 - PS USB 3_0 Hub

25 - I2C MUX

26 - PMIC

27 - Power Connector - Mounting Holes

Page 2: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Block Diagram 2

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

Page 3: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

SYSMON_VP_R_I2C

GND

SYSMON I2C Address selection

GND

SYSMON_VN_R_I2C

Zynq Bank 0

SYSMON_VP_R_I2CSYSMON_VN_R_I2C

GND

L1

21

FERRITE-600

SYSMON_AGND

FPGA_SYSMON_AVCC

FERRITE-600

1 2

L2GND

VCCAUX

SYSMON_AGND

NCNC

C151

2

10.47UF6.3V

R46DNP

1

2

VCCAUX

R4220.5K

1

2

R4320.5K

1

2

U1

T8T7N10N9K10K9M10L9L10M9VN_M9

VP_L10VREFN_L9VREFP_M10GNDADC_K9

VCCADC_K10DXN_N9

DXP_N10POR_OVERRIDE_T7

PUDC_B_0_T8

XCZU3SBVA484BANK 0

FBGA_484_0P8MM

XCZU3-SBVA484B

2

1DNPR147

2

11.00KR148

GND

VCCAUX

C560.1UF25V2

1

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Bank 0 3

Page 4: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Zynq Banks 26 - HD

VCCAUX

U1

A6B7B5B6A7A8A9B9C7C8C5D5D8E8D6D7F7F8E5E6F6G7G5G6

B8E7 VCCO_26_E7

VCCO_26_B8IO_L1P_AD11P_26_G6IO_L1N_AD11N_26_G5IO_L2P_AD10P_26_G7IO_L2N_AD10N_26_F6IO_L3P_AD9P_26_E6IO_L3N_AD9N_26_E5IO_L4P_AD8P_26_F8IO_L4N_AD8N_26_F7

IO_L5P_HDGC_AD7P_26_D7IO_L5N_HDGC_AD7N_26_D6IO_L6P_HDGC_AD6P_26_E8IO_L6N_HDGC_AD6N_26_D8IO_L7P_HDGC_AD5P_26_D5IO_L7N_HDGC_AD5N_26_C5IO_L8P_HDGC_AD4P_26_C8IO_L8N_HDGC_AD4N_26_C7

IO_L9P_AD3P_26_B9IO_L9N_AD3N_26_A9

IO_L10P_AD2P_26_A8IO_L10N_AD2N_26_A7IO_L11P_AD1P_26_B6IO_L11N_AD1N_26_B5IO_L12P_AD0P_26_B7IO_L12N_AD0N_26_A6

XCZU3SBVA484BANK 26

FBGA_484_0P8MM

XCZU3-SBVA484B

HD_GPIO_0

HD_GPIO_1HD_GPIO_2

HD_GPIO_3HD_GPIO_4

HD_GPIO_5

HD_GPIO_6

HD_GPIO_7

HD_GPIO_8

HD_GPIO_9HD_GPIO_10

HD_GPIO_11

HD_GPIO_12

HD_GPIO_13

BT_AUD_FSYNC

BT_AUD_OUTBT_AUD_IN

BT_AUD_CLK

CSI0_MCLKCSI1_MCLK

BT_HCI_CTSBT_HCI_RTS

HD_GPIO_14

HD_GPIO_15

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Banks 26 - HD 4

Page 5: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Zynq Banks 65 66 - HP

VCCO_HP

U1

C2D2F2F3C3D3D1E1E3E4F1G1

F4

H3G4H4G2H2H5J5J1K1K3K4J2J3

L3L4L1L2M4M5M1M2N4N5P1N2

N3

P2R5P5T1R1T4R4U1U2R3P3T2T3K5

B3G3K2P4 VCCO_65_P4

VCCO_65_K2VCCO_65_G3VCCO_65_B3

VREF_65_K5IO_L1P_T0L_N0_DBC_65_T3IO_L1N_T0L_N1_DBC_65_T2

IO_L2P_T0L_N2_65_P3IO_L2N_T0L_N3_65_R3

IO_L3P_T0L_N4_AD15P_65_U2IO_L3N_T0L_N5_AD15N_65_U1

IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65_R4IO_L4N_T0U_N7_DBC_AD7N_65_T4

IO_L5P_T0U_N8_AD14P_65_R1IO_L5N_T0U_N9_AD14N_65_T1IO_L6P_T0U_N10_AD6P_65_P5IO_L6N_T0U_N11_AD6N_65_R5

IO_T0U_N12_VRP_65_P2

IO_T1U_N12_65_N3

IO_L7P_T1L_N0_QBC_AD13P_65_N2IO_L7N_T1L_N1_QBC_AD13N_65_P1

IO_L8P_T1L_N2_AD5P_65_N5IO_L8N_T1L_N3_AD5N_65_N4IO_L9P_T1L_N4_AD12P_65_M2IO_L9N_T1L_N5_AD12N_65_M1

IO_L10P_T1U_N6_QBC_AD4P_65_M5IO_L10N_T1U_N7_QBC_AD4N_65_M4

IO_L11P_T1U_N8_GC_65_L2IO_L11N_T1U_N9_GC_65_L1IO_L12P_T1U_N10_GC_65_L4IO_L12N_T1U_N11_GC_65_L3

IO_L13P_T2L_N0_GC_QBC_65_J3IO_L13N_T2L_N1_GC_QBC_65_J2

IO_L14P_T2L_N2_GC_65_K4IO_L14N_T2L_N3_GC_65_K3

IO_L15P_T2L_N4_AD11P_65_K1IO_L15N_T2L_N5_AD11N_65_J1

IO_L16P_T2U_N6_QBC_AD3P_65_J5IO_L16N_T2U_N7_QBC_AD3N_65_H5

IO_L17P_T2U_N8_AD10P_65_H2IO_L17N_T2U_N9_AD10N_65_G2IO_L18P_T2U_N10_AD2P_65_H4IO_L18N_T2U_N11_AD2N_65_G4

IO_T2U_N12_65_H3

IO_T3U_N12_65_F4

IO_L19P_T3L_N0_DBC_AD9P_65_G1IO_L19N_T3L_N1_DBC_AD9N_65_F1

IO_L20P_T3L_N2_AD1P_65_E4IO_L20N_T3L_N3_AD1N_65_E3IO_L21P_T3L_N4_AD8P_65_E1IO_L21N_T3L_N5_AD8N_65_D1

IO_L22P_T3U_N6_DBC_AD0P_65_D3IO_L22N_T3U_N7_DBC_AD0N_65_C3IO_L23P_T3U_N8_I2C_SCLK_65_F3

IO_L23N_T3U_N9_65_F2IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65_D2

IO_L24N_T3U_N11_PERSTN0_65_C2

XCZU3SBVA484BANK 65

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

A2A3A4B1B2B4C4VREF_66_C4

IO_T0U_N12_VRP_66_B4IO_L11P_T1U_N8_GC_66_B2IO_L11N_T1U_N9_GC_66_B1

IO_L12P_T1U_N10_GC_66_A4IO_L12N_T1U_N11_GC_66_A3

IO_T3U_N12_66_A2

XCZU3SBVA484BANK 66

FBGA_484_0P8MM

XCZU3-SBVA484B

DSI_CLK_PDSI_CLK_N

NCNC

DSI_D3_PDSI_D3_N

CSI1_D0_PCSI1_D0_N

HSIC_STR

NCNC

NCNC

CSI1_D1_PCSI1_D1_N

CSI1_C_PCSI1_C_N

HSIC_DATA

DSI_D1_PDSI_D1_NDSI_D2_PDSI_D2_N

CSI0_D0_PCSI0_D0_NCSI0_D1_PCSI0_D1_N

NCNCNCNCNCNCNC

NCNCNCNCNCNC

NCNCNCNC

DSI_D0_PDSI_D0_N

NC

NCNC

NC

NC

CSI0_D3_PCSI0_D3_N

CSI0_C_PCSI0_C_N

CSI0_D2_PCSI0_D2_N

R1451

2

2401/20W1%

GND

NC

NC

FAN_PWM

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Banks 65 66 - HP 5

Page 6: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Zynq Banks 500 501 502 - MIO

MIO56_USB0_DATA0

MIO60_USB0_DATA4

MIO62_USB0_DATA6

MIO52_USB0_CLK

MIO55_USB0_NXTMIO54_USB0_DATA2MIO53_USB0_DIR

MIO61_USB0_DATA5

MIO63_USB0_DATA7

MIO57_USB0_DATA1

MIO59_USB0_DATA3MIO58_USB0_STP

VCC_PSAUX

VCC_PSAUX

MIO68_USB1_DATA0

MIO72_USB1_DATA4

MIO74_USB1_DATA6

MIO64_USB1_CLK

MIO67_USB1_NXTMIO66_USB1_DATA2MIO65_USB1_DIR

MIO73_USB1_DATA5

MIO75_USB1_DATA7

MIO69_USB1_DATA1

MIO71_USB1_DATA3MIO70_USB1_STP

MIO76_WLAN_IRQ

U1

AA5V6

Y6AB6AB5AA6W6AB4AA4Y5AA3Y3Y4W5W3AB2W2AA2V5V3V4Y1AA1U6U5V2W1U4PS_MIO0_U4

PS_MIO1_W1PS_MIO2_V2PS_MIO3_U5PS_MIO4_U6PS_MIO5_AA1PS_MIO6_Y1PS_MIO7_V4PS_MIO8_V3PS_MIO9_V5

PS_MIO10_AA2PS_MIO11_W2

PS_MIO12_AB2PS_MIO13_W3PS_MIO14_W5PS_MIO15_Y4PS_MIO16_Y3

PS_MIO17_AA3PS_MIO18_Y5

PS_MIO19_AA4PS_MIO20_AB4PS_MIO21_W6

PS_MIO22_AA6PS_MIO23_AB5PS_MIO24_AB6PS_MIO25_Y6

VCCO_PSIO0_500_V6VCCO_PSIO0_500_AA5

XCZU3SBVA484BANK 500

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

C11F10

C13A13D13A12B12C12A11B11E13D12B10D11C10C9E11D10E10F13E9F12F11G10F9G12G11G9PS_MIO26_G9

PS_MIO27_G11PS_MIO28_G12PS_MIO29_F9

PS_MIO30_G10PS_MIO31_F11PS_MIO32_F12PS_MIO33_E9

PS_MIO34_F13PS_MIO35_E10PS_MIO36_D10PS_MIO37_E11PS_MIO38_C9

PS_MIO39_C10PS_MIO40_D11PS_MIO41_B10PS_MIO42_D12PS_MIO43_E13PS_MIO44_B11PS_MIO45_A11PS_MIO46_C12PS_MIO47_B12PS_MIO48_A12PS_MIO49_D13PS_MIO50_A13PS_MIO51_C13

VCCO_PSIO1_501_F10VCCO_PSIO1_501_C11

XCZU3SBVA484BANK 501

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

C16D14

B18F18B17D18D17C17F17A17A16B16G17D16B15E16F16C15G16D15E15A14B14E14C14G15F14G14PS_MIO52_G14

PS_MIO53_F14PS_MIO54_G15PS_MIO55_C14PS_MIO56_E14PS_MIO57_B14PS_MIO58_A14PS_MIO59_E15PS_MIO60_D15PS_MIO61_G16PS_MIO62_C15PS_MIO63_F16PS_MIO64_E16PS_MIO65_B15PS_MIO66_D16PS_MIO67_G17PS_MIO68_B16PS_MIO69_A16PS_MIO70_A17PS_MIO71_F17PS_MIO72_C17PS_MIO73_D17PS_MIO74_D18PS_MIO75_B17PS_MIO76_F18PS_MIO77_B18

VCCO_PSIO2_502_D14VCCO_PSIO2_502_C16

XCZU3SBVA484BANK 502

FBGA_484_0P8MM

XCZU3-SBVA484B

GND

MIO23_GPIO_PB 21

B3U-1000P

SW4

MIO26_POWER_INT_B

MIO32_PS_FP_PWR_ENMIO33_PL_PWR_EN

MIO27_DP_AUX_OUTMIO28_DP_HPDMIO29_DP_OEMIO30_DP_AUX_INVCC_PSAUX

GND

1

2

3

HDR_SMT_LC_1X3

J6

MIO0_UART1_TX_LS

MIO1_UART1_RX_LS

U4

2

5

4

3

9

67

1

10

8 A1

DIR1

DIR2

VCCA VCCB

A2

GND

B2

B1

OE

QFN_RSW_10

SN74AVC2T245

GND

GND

VCC_3V3

1

2

C170.1UF25V

GND

1

225V0.1UFC41

VCC_PSAUX

MIO0_UART1_TX

MIO1_UART1_RX

GND

MIO7_WLAN_ENMIO8_BT_EN

MIO2_UART0_RX_BT_HCI_TXMIO3_UART0_TX_BT_HCI_RX

MIO42_SPI0_MISO

MIO38_SPI0_SCLK

MIO43_SPI0_MOSI

MIO41_SPI0_CS

MIO17_PS_LED3

MIO22_SD0_CLK_R

MIO13_SD0_DAT0_RMIO14_SD0_DAT1_RMIO15_SD0_DAT2_RMIO16_SD0_DAT3_R

MIO21_SD0_CMD_R

MIO24_SD0_DETECTMIO25_VBUS_DET

MIO0_UART1_TXMIO1_UART1_RX

MIO4_I2C1_SCLMIO5_I2C1_SDA

MIO18_PS_LED2MIO19_PS_LED1MIO20_PS_LED0

MIO23_GPIO_PB

MIO12_I2C_MUX_RESET_B

MIO31_INA226_PMBUS_ALERT

VCC_PSAUX

MIO10_SPI1_MISO

MIO6_SPI1_SCLK

MIO11_SPI1_MOSI

MIO9_SPI1_CSMIO34_POWER_KILL_B

MIO36_PS_GPIO1_0MIO37_PS_GPIO1_1

MIO39_PS_GPIO1_2MIO40_PS_GPIO1_3

MIO44_PS_GPIO1_4MIO45_PS_GPIO1_5

2

14.70KR23

PMIC_IRQ

R152

1 2

3030

21

R153

30

21

R154R155

1 2

30R156

1 2

3030

21

R157

MIO49_SD1_D3MIO48_SD1_D2MIO47_SD1_D1MIO46_SD1_D0

MIO51_SD1_CLKMIO50_SD1_CMD

MIO22_SD0_CLK

MIO13_SD0_DAT0MIO14_SD0_DAT1MIO15_SD0_DAT2MIO16_SD0_DAT3

MIO21_SD0_CMD

2

1 R1584.70K

VCC_PSAUX

4.70KR1601

2

1 J20

TP_PAD

VCC_3V3

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Banks 500 501 502 - MIO 6

Page 7: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Zynq Banks 503 - Config

GND

GND

GND

GND

JTAG_TCKJTAG_TMS

JTAG_TDI

PS_DONE

PS_INIT_BPS_PROG_B

1.8V

INIT_B = 0, RED LED ON

DONE_0 = 0, DONE LED OFF

DONE_0 = 1, DONE LED ON

PS_INIT_B

PS_POR_B

PS_REF_CLK

PS_PADIPS_PADO

PS_MODE0_1PS_MODE2PS_MODE3PS_PADOPS_PADI

VCC_PSAUX

GND

VCC_3V3

VCC_3V3

C1482

1

22PF50V

50V22PF

1

2

C149

R451

2

4.7M

U29

3

2

1

4

6

5 DIR

VCCB

B

VCCA

GND

A

SC70_6

SN74AVC1T45

JTAG_TDO

GND

PS_SRST_B

LED-RED-SMT

21

DS7

INIT_B = 1, RED LED OFF

VCC_PSAUX

VCC_PSAUX

VCC_PSAUX

25V0.1UFC66

2

1C690.1UF25V 2

1

X5

2

1 X1

X2

32.768KHZ

20PPM

R2520

1

2

R103

261

1 2

GND

VCC_3V3

21

261R104

150MW

Q3

RUM001L02T2CL2

3

1PS_DONE

21

LED-GRN-SMT

DS6

VCC_PSAUX

R50499

1

2

499R511

2

R324.70K

1

2

R334.70K

1

2

R344.70K

1

2

4.70KR351

2

4.70KR371

2

4.70KR31 1

2

U1

G13H16

K12K18K16K13H14H13J12J13H12K15K14L12H17J17H18J15H15J16PS_MODE0_J16

PS_MODE1_H15PS_MODE2_J15PS_MODE3_H18PS_PADO_J17PS_PADI_H17PS_DONE_L12

PS_PROG_B_K14PS_INIT_B_K15

PS_JTAG_TDI_H12PS_JTAG_TDO_J13PS_JTAG_TMS_J12PS_JTAG_TCK_H13PS_REF_CLK_H14PS_SRST_B_K13

PS_ERROR_OUT_K16PS_ERROR_STATUS_K18

PS_POR_B_K12

VCCO_PSIO3_503_H16VCCO_PSIO3_503_G13

XCZU3SBVA484BANK 503

FBGA_484_0P8MM

XCZU3-SBVA484B

PS_MODE0_1 is used to reset USB devices

C15033PF50V2

1

1 TP_PADJ16

J17TP_PAD1

PS_ERROR_STATUSPS_ERROR_OUT

SW2

43

12

218-2LPSTRF BOOT MODE: JTAG 11 SD 01 USB 00

GND

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Banks 503 - Config 7

Page 8: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

GND

VCCO_PSDDR

PS_DDR_CKE0

PS_DDR_CS0_N

NC

NC

PS_DDR_CAA0

PS_DDR_DQSA0_TPS_DDR_DQSA0_CPS_DDR_DQSA1_TPS_DDR_DQSA1_C

PS_DDR_CAA1PS_DDR_CAA2PS_DDR_CAA3PS_DDR_CAA4PS_DDR_CAA5

PS_DDR_CKA_TPS_DDR_CKA_C

PS_DDR_DMA0PS_DDR_DMA1

PS_DDR_DMB0PS_DDR_DMB1

PS_DDR_DQSB0_TPS_DDR_DQSB0_CPS_DDR_DQSB1_TPS_DDR_DQSB1_C

PS_DDR_CAB0PS_DDR_CAB1PS_DDR_CAB2PS_DDR_CAB3PS_DDR_CAB4PS_DDR_CAB5

NCNCNCNC

NCNCNCNCNC

PS_DDR_RST_B

NC

LPDDR4_PS_ZQ

PS_DDR_DQ0PS_DDR_DQ1PS_DDR_DQ2PS_DDR_DQ3PS_DDR_DQ4PS_DDR_DQ5PS_DDR_DQ6PS_DDR_DQ7PS_DDR_DQ8PS_DDR_DQ9PS_DDR_DQ10PS_DDR_DQ11PS_DDR_DQ12PS_DDR_DQ13PS_DDR_DQ14PS_DDR_DQ15PS_DDR_DQ16PS_DDR_DQ17PS_DDR_DQ18PS_DDR_DQ19PS_DDR_DQ20PS_DDR_DQ21PS_DDR_DQ22PS_DDR_DQ23PS_DDR_DQ24PS_DDR_DQ25PS_DDR_DQ26PS_DDR_DQ27PS_DDR_DQ28PS_DDR_DQ29PS_DDR_DQ30PS_DDR_DQ31

NCNC

NCNC

NCNCNCNC

PS_DDR_CS1_N

PS_DDR_CKE1

PS_DDR_CKB_TPS_DDR_CKB_C

NCNC

NCNC

NC

Zynq Bank 504 - Memory

240R931

2U1

AA22AB20AB17AB19AB21AB16Y20Y19W17Y18Y21AA21AA18AA19AA17AA16Y16W16U17V17U15T21U19T18U16W18V22U20V20W20V18V19U22U21W22W21Y9

AA9Y13AA13V9V8

V12V13P20R20

AB9AB14U9W13R19

AB11Y10AB10W10AA8Y8AB7AA7AA11Y11AA12AB12Y14AA14Y15AB15W8W7V7V10U7T9U10T10U11U12W12W11V14U14W15V15

T22P22R21P21R18P18N18N19

T19

Y22Y17V21V16T20P19AB18 VCCO_PSDDR_504_AB18

VCCO_PSDDR_504_P19VCCO_PSDDR_504_T20VCCO_PSDDR_504_V16VCCO_PSDDR_504_V21VCCO_PSDDR_504_Y17VCCO_PSDDR_504_Y22

PS_DDR_ZQ_T19

PS_DDR_DQ71_N19PS_DDR_DQ70_N18PS_DDR_DQ69_P18PS_DDR_DQ68_R18PS_DDR_DQ67_P21PS_DDR_DQ66_R21PS_DDR_DQ65_P22PS_DDR_DQ64_T22

PS_DDR_DQ31_V15PS_DDR_DQ30_W15PS_DDR_DQ29_U14PS_DDR_DQ28_V14PS_DDR_DQ27_W11PS_DDR_DQ26_W12PS_DDR_DQ25_U12PS_DDR_DQ24_U11PS_DDR_DQ23_T10PS_DDR_DQ22_U10PS_DDR_DQ21_T9PS_DDR_DQ20_U7

PS_DDR_DQ19_V10PS_DDR_DQ18_V7PS_DDR_DQ17_W7PS_DDR_DQ16_W8

PS_DDR_DQ15_AB15PS_DDR_DQ14_Y15

PS_DDR_DQ13_AA14PS_DDR_DQ12_Y14

PS_DDR_DQ11_AB12PS_DDR_DQ10_AA12

PS_DDR_DQ9_Y11PS_DDR_DQ8_AA11PS_DDR_DQ7_AA7PS_DDR_DQ6_AB7PS_DDR_DQ5_Y8

PS_DDR_DQ4_AA8PS_DDR_DQ3_W10

PS_DDR_DQ2_AB10PS_DDR_DQ1_Y10

PS_DDR_DQ0_AB11

PS_DDR_DM8_R19PS_DDR_DM3_W13PS_DDR_DM2_U9

PS_DDR_DM1_AB14PS_DDR_DM0_AB9

PS_DDR_DQS_N8_R20PS_DDR_DQS_P8_P20PS_DDR_DQS_N3_V13PS_DDR_DQS_P3_V12PS_DDR_DQS_N2_V8PS_DDR_DQS_P2_V9PS_DDR_DQS_N1_AA13PS_DDR_DQS_P1_Y13PS_DDR_DQS_N0_AA9PS_DDR_DQS_P0_Y9PS_DDR_ODT1_W21PS_DDR_ODT0_W22PS_DDR_CKE1_U21PS_DDR_CKE0_U22PS_DDR_CK_N1_V19PS_DDR_CK1_V18PS_DDR_CK_N0_W20PS_DDR_CK0_V20PS_DDR_CS_N1_U20PS_DDR_CS_N0_V22PS_DDR_BG1_W18PS_DDR_BG0_U16PS_DDR_RAM_RST_N_T18PS_DDR_PARITY_U19PS_DDR_ALERT_N_T21PS_DDR_ACT_N_U15PS_DDR_BA1_V17PS_DDR_BA0_U17PS_DDR_A17_W16PS_DDR_A16_Y16PS_DDR_A15_AA16PS_DDR_A14_AA17PS_DDR_A13_AA19PS_DDR_A12_AA18PS_DDR_A11_AA21PS_DDR_A10_Y21PS_DDR_A9_Y18PS_DDR_A8_W17PS_DDR_A7_Y19PS_DDR_A6_Y20PS_DDR_A5_AB16PS_DDR_A4_AB21PS_DDR_A3_AB19PS_DDR_A2_AB17PS_DDR_A1_AB20PS_DDR_A0_AA22

XCZU3SBVA484BANK 504

FBGA_484_0P8MM

XCZU3-SBVA484B

NC

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Bank 504 - Memory 8

Page 9: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Zynq Banks 505 - GTR

GND

R651

2

500

GTR_LANE3_RX_PGTR_LANE3_RX_N

GTR_LANE3_TX_PGTR_LANE3_TX_N

GTR_LANE2_TX_PGTR_LANE2_TX_NGTR_LANE2_RX_PGTR_LANE2_RX_N

GTR_LANE1_TX_PGTR_LANE1_TX_N

GTR_LANE0_TX_PGTR_LANE0_TX_N

NCNC

NCNC

GTR_CLK1_DP_27M_N

GTR_CLK1_DP_27M_P

GTR_CLK0_USB_26M_P

GTR_CLK0_USB_26M_N

GTR_CLK0_USB_26M_C_P

GTR_CLK0_USB_26M_C_N

GTR_CLK0_USB_26M_C_PGTR_CLK0_USB_26M_C_N

GTR_CLK1_DP_27M_C_P

GTR_CLK1_DP_27M_C_N

GTR_CLK1_DP_27M_C_PGTR_CLK1_DP_27M_C_N

NCNC

NCNC

C70

0.1UF

25V

21

C71

0.1UF

25V

21

25V

0.1UF

C72

21

25V

0.1UF

C73

21

U1

K21K22M21M22F21F22H21H22C19C20D21D22A19A20B21B22L19L20J19J20G19G20E19E20M20PS_MGTRREF_505_M20

PS_MGTREFCLK3N_505_E20PS_MGTREFCLK3P_505_E19PS_MGTREFCLK2N_505_G20PS_MGTREFCLK2P_505_G19PS_MGTREFCLK1N_505_J20PS_MGTREFCLK1P_505_J19PS_MGTREFCLK0N_505_L20PS_MGTREFCLK0P_505_L19

PS_MGTRRXN3_505_B22PS_MGTRRXP3_505_B21PS_MGTRTXN3_505_A20PS_MGTRTXP3_505_A19PS_MGTRRXN2_505_D22PS_MGTRRXP2_505_D21PS_MGTRTXN2_505_C20PS_MGTRTXP2_505_C19PS_MGTRRXN1_505_H22PS_MGTRRXP1_505_H21PS_MGTRTXN1_505_F22PS_MGTRTXP1_505_F21PS_MGTRRXN0_505_M22PS_MGTRRXP0_505_M21PS_MGTRTXN0_505_K22PS_MGTRTXP0_505_K21

XCZU3SBVA484BANK 505

FBGA_484_0P8MM

XCZU3-SBVA484B

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Banks 505 - GTR 9

Page 10: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

VCCINT

Zynq Power 1

VCCAUXVCCAUX

VCCINT

VCCINT

U1

R9R11P8P10N11M8L11K8J9J11H8H10VCCINT_H10

VCCINT_H8VCCINT_J11VCCINT_J9VCCINT_K8

VCCINT_L11VCCINT_M8

VCCINT_N11VCCINT_P10VCCINT_P8

VCCINT_R11VCCINT_R9

XCZU3SBVA484BANK VCCINT

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

T6R7R6N7VCCBRAM_N7

VCCBRAM_R6VCCBRAM_R7VCCBRAM_T6

XCZU3SBVA484BANK VCCBRAM

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

M7L7J7H7VCCINT_IO_H7

VCCINT_IO_J7VCCINT_IO_L7VCCINT_IO_M7

XCZU3SBVA484BANK VCCINT_IO

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

P6M6VCCAUX_M6

VCCAUX_P6

XCZU3SBVA484BANK VCCAUX

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

L6K6J6VCCAUX_IO_J6

VCCAUX_IO_K6VCCAUX_IO_L6

XCZU3SBVA484BANK VCCAUX_IO

FBGA_484_0P8MM

XCZU3-SBVA484B

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Power 1 10

Page 11: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Zynq Power 2

MGTRAVTT

MGTRAVCC

GND

1 2

FERRITE-600

L3

PS_SYSMON_AGND

PS_SYSMON_AVCC

1 2

L4

FERRITE-600

VCC_PSAUX

VCC_PSPLL

VCC_PSINTLP

VCC_PSINTFP

VCC_PSAUX

PS_SYSMON_AGND

6.3V0.47UFC152

2

1

U1

K19H19F19PS_MGTRAVCC_F19

PS_MGTRAVCC_H19PS_MGTRAVCC_K19

XCZU3SBVA484BANK PS_MGTRAVCC

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

D19B19A21PS_MGTRAVTT_A21

PS_MGTRAVTT_B19PS_MGTRAVTT_D19

XCZU3SBVA484BANK PS_MGTRAVTT

FBGA_484_0P8MM

XCZU3-SBVA484B

U1

M12L14L13R14R13P13P12N13N12T17P17N17T16T14T13T12R16R15N14M15M14N15M17M16L17L16P15P16GND_PSADC_P16

VCC_PSADC_P15VCC_PSAUX_L16VCC_PSAUX_L17VCC_PSAUX_M16VCC_PSAUX_M17VCC_PSBATT_N15

VCC_PSDDR_PLL_M14VCC_PSDDR_PLL_M15

VCC_PSINTFP_N14VCC_PSINTFP_R15VCC_PSINTFP_R16VCC_PSINTFP_T12VCC_PSINTFP_T13VCC_PSINTFP_T14VCC_PSINTFP_T16

VCC_PSINTFP_DDR_N17VCC_PSINTFP_DDR_P17VCC_PSINTFP_DDR_T17

VCC_PSINTLP_N12VCC_PSINTLP_N13VCC_PSINTLP_P12VCC_PSINTLP_P13VCC_PSINTLP_R13VCC_PSINTLP_R14VCC_PSPLL_L13VCC_PSPLL_L14VCC_PSPLL_M12

XCZU3SBVA484BANK PS_POWER

FBGA_484_0P8MM

XCZU3-SBVA484B

25V0.1UFC65

2

1

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Power 2 11

AES?

Page 12: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Zynq GND

GND

U1

Y7

Y2

Y12

W9

W4

W19

W14

V11

V1

U8

U3

U18

U13

T5

T15

T11

R8

R22

R2

R17

R12

R10

P9

P7

P14

P11

N8

N6

N22

N21

N20

N16

N1

M3

M19

M18

M13

M11

L8

L5

L22

L21

L18

L15

K7

K20

K17

K11

J8

J4

J22

J21

J18

J14

J10

H9

H6

H20

H11

H1

G8

G22

G21

G18

F5

F20

F15

E22

E21

E2

E18

E17

E12

D9

D4

D20

C6

C22

C21

C18

C1

B20

B13

AB8

AB3

AB22

AB13

AB1

AA20

AA15

AA10

A5

A22

A18

A15

A10

A1

GND_A1

GND_A10

GND_A15

GND_A18

GND_A22

GND_A5

GND_AA10

GND_AA15

GND_AA20

GND_AB1

GND_AB13

GND_AB22

GND_AB3

GND_AB8

GND_B13

GND_B20

GND_C1

GND_C18

GND_C21

GND_C22

GND_C6

GND_D20

GND_D4

GND_D9

GND_E12

GND_E17

GND_E18

GND_E2

GND_E21

GND_E22

GND_F15

GND_F20

GND_F5

GND_G18

GND_G21

GND_G22

GND_G8

GND_H1

GND_H11

GND_H20

GND_H6

GND_H9

GND_J10

GND_J14

GND_J18

GND_J21

GND_J22

GND_J4

GND_J8

GND_K11

GND_K17

GND_K20

GND_K7

GND_L15

GND_L18

GND_L21

GND_L22

GND_L5

GND_L8

GND_M11

GND_M13

GND_M18

GND_M19

GND_M3

GND_N1

GND_N16

GND_N20

GND_N21

GND_N22

GND_N6

GND_N8

GND_P11

GND_P14

GND_P7

GND_P9

GND_R10

GND_R12

GND_R17

GND_R2

GND_R22

GND_R8

GND_T11

GND_T15

GND_T5

GND_U13

GND_U18

GND_U3

GND_U8

GND_V1

GND_V11

GND_W14

GND_W19

GND_W4

GND_W9

GND_Y12

GND_Y2

GND_Y7

XCZU3SBVA484

BANK GND

FBGA_484_0P8MM

XCZU3-SBVA484B

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

12Zynq GND

Page 13: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Zynq Decoupling

BANK 505

GNDGND

1

2

C204.7UF6.3V

1

26.3V4.7UFC21

MGTRAVTTMGTRAVCC

VCCO_PSDDR

GND

VCCO_PSDDR

GND

Place this cap directly under U1

GND

C1600.47UF

6.3V 2

1

VCC_PSINTFP

GND GND

C234.7UF6.3V 2

1

VCC_PSINTLPVCC_PSINTLP

VCCPSINTFP

VCCPSINTLP

GND

VCC_PSAUX

VCCPSAUX/PSADC/PSDDRPLLPSIO1-3

VCCPSDDR16V0.01UFC4

2

1 C50.01UF16V2

1

16V0.01UFC6

2

1

C380.22UF

25V 2

1

25V0.22UFC39

2

1 MGTRAVCC/AVTT

PL VCCAUX / VCCAUX_IO

PL VCCINT/VCCBRAM

GND

GND

GND

1

2

C184.7UF6.3V

VCCINT

VCCAUX VCCAUX

C1530.47UF

6.3V 2

1 C1570.47UF

6.3V 2

1

6.3V0.47UFC158

2

1

C1790.47UF

6.3V 2

1

C1800.47UF6.3V 2

1

C1810.47UF6.3V 2

1

6.3V0.47UFC182

2

1

6.3V0.47UFC183

2

1

C1840.47UF6.3V 2

1C1850.47UF6.3V 2

1

6.3V0.47UFC186

2

1C1870.47UF6.3V 2

1

6.3V0.47UFC159

2

1

6.3V0.47UFC161

2

1

C30.01UF16V2

1

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Zynq Decoupling 13

Page 14: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

GND

JTAG Headers - LEDs

JTAG_TDI

JTAG_TMS

JTAG_TCK

PS_SRST_B

JTAG_TDO

VCC_PSAUX

JTAG on Bottomside

MIO17_PS_LED3

MIO18_PS_LED2

MIO19_PS_LED1

MIO20_PS_LED0

LED-GRN-SMT

DS2

12

DS3

LED-GRN-SMT

12

LED-GRN-SMT

DS4

12

LED-GRN-SMT

DS5

12

261R99 1

2

R100261

12

261R101 1

2

R102261

12

4.70KR261

2

4.70KR271

2

4.70KR281

2

4.70KR291

2

4.70KR301

2

J2

7

6

5

4

3

2

1

HDR_1x7

HDR_SMT_LC_1X7

GND

1

3

2RUM001L02T2CL

Q5

150MW

GND

150MW

Q6

RUM001L02T2CL2

3

1

GND

1

3

2RUM001L02T2CL

Q7

150MW

GND

150MW

Q8

RUM001L02T2CL2

3

1

VCC_3V3

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

JTAG Headers - LEDs 14

Page 15: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

40 OHM INTERFACE

MEM_IF C1

GND

GND

DQA0DQA1DQA2DQA3DQA4DQA5DQA6DQA7DQA8DQA9DQA10DQA11DQA12DQA13DQA14DQA15

DQSA0_TDQSA0_CDQSA1_TDQSA1_C

DMIA0DMIA1

CAA0CAA1CAA2CAA3CAA4CAA5

CKA_TCKA_C

CKEA0CKEA1CKEA2

ODTA

CSA0CSA1CSA2

DNUA1DNUA2DNUA3DNUA4

VDD1A1VDD1A2VDD1A3VDD1A4

VDD2A1VDD2A2VDD2A3VDD2A4VDD2A5VDD2A6VDD2A7VDD2A8VDD2A9VDD2A10VDD2A11VDD2A12

VDDQA1VDDQA2VDDQA3VDDQA4VDDQA5VDDQA6VDDQA7VDDQA8VDDQA9VDDQA10

DNUA5DNUA6

DQB0DQB1DQB2DQB3DQB4DQB5DQB6DQB7DQB8DQB9

DQB10DQB11DQB12DQB13DQB14DQB15

DQSB0_TDQSB0_CDQSB1_TDQSB1_C

DMIB0DMIB1

CAB0CAB1CAB2CAB3CAB4CAB5

CKB_TCKB_C

CKEB0CKEB1CKEB2

ODTB

CSB0CSB1CSB2

DNUB1DNUB2DNUB3DNUB4DNUB5DNUB6

VDD1B1VDD1B2

VDD2B1VDD2B2

VDD2B5VDD2B6VDD2B7VDD2B8VDD2B9

VDD2B10

VDD1B3VDD1B4

VDD2B3VDD2B4

VDD2B11VDD2B12

VSSA1

VSSA2

VSSA3

VSSA4

VSSA5

VSSA6

VDDQB9

VDDQB1VDDQB2VDDQB3VDDQB4VDDQB5VDDQB6VDDQB7VDDQB8

VDDQB10

ZQ0ZQ1ZQ2

RESET

VSSA7

VSSA8

VSSA9

VSSA10

VSSA11

VSSA12

VSSA13

VSSA14

VSSA15

VSSA16

VSSA17

VSSA18

VSSA19

VSSA20

VSSA21

VSSA22

VSSA23

VSSA24

VSSA25

VSSA26

VSSA27

VSSA28

VSSB1

VSSB3

VSSB2

VSSB4

VSSB5

VSSB6

VSSB7

VSSB8

VSSB9

VSSB10

VSSB11

VSSB12

VSSB13

VSSB14

VSSB15

VSSB16

VSSB17

VSSB18

VSSB19

VSSB20

VSSB21

VSSB22

VSSB23

VSSB24

VSSB25

VSSB26

VSSB27

VSSB28

VSSB29

VSSB30

LPDDR4 PS MEMORY DATA[15:0]

PS_DDR_CAA0

PS_DDR_DQSA0_TPS_DDR_DQSA0_C

PS_DDR_DQ0

PS_DDR_ODT

PS_DDR_DQ1PS_DDR_DQ2PS_DDR_DQ3PS_DDR_DQ4PS_DDR_DQ5PS_DDR_DQ6PS_DDR_DQ7

PS_DDR_DQSA1_TPS_DDR_DQSA1_C

PS_DDR_CAA1PS_DDR_CAA2PS_DDR_CAA3PS_DDR_CAA4PS_DDR_CAA5

PS_DDR_DMB0PS_DDR_DMB1

NCNCNCNCNCNC

NCNCNCNCNCNC

PS_DDR_CKA_TPS_DDR_CKA_C

PS_DDR_DQSB0_TPS_DDR_DQSB0_CPS_DDR_DQSB1_TPS_DDR_DQSB1_C

PS_DDR_DMA0PS_DDR_DMA1

PS_DDR_CAB0PS_DDR_CAB1PS_DDR_CAB2PS_DDR_CAB3PS_DDR_CAB4PS_DDR_CAB5

PS_DDR_ODT

PS_DDR_CKB_TPS_DDR_CKB_C

PS_DDR_RST_B LPDDR4_PS_ZQ1LPDDR4_PS_ZQ2LPDDR4_PS_ZQ3

PS_DDR_CS0_N PS_DDR_CS0_N

PS_DDR_CKE0 PS_DDR_CKE0

GND

GND

VDD1 = 1.80V

VDD2 = 1.10V

1.1V

1.1V

VCC_PSAUX

1.1V

1.1V

VCCO_PSDDR

PS_DDR_CKE1

PS_DDR_CS1_NNC

NCPS_DDR_CKE1

PS_DDR_CS1_NNC

NC

GND

PS_DDR_RST_B

PS_DDR_ODT

C1620.47UF6.3V2

1

PS LPDDR4 DRAM

VCC_PSAUX

VCCO_PSDDR

VCCO_PSDDR

VCCO_PSDDR

VCCO_PSDDR

VCCO_PSDDR

VCC_PSAUX

25V0.1UFC97

2

1

C350.068UF16V2

1

C360.068UF16V2

1

GND

C1630.47UF6.3V2

1

VDDQ = 1.10VVCCO_PSDDR

C421000PF25V2

1 C431000PF25V2

1

C441000PF25V

1

2

C451000PF25V

1

2

C461000PF25V2

1

240R901

2

R91240

1

2

R92240

1

2

VCCO_PSDDR

4.70KR19 1

2

4.70KR20 1

2

1

2 10V10UFC192

GND

VCCO_PSDDR

PS_DDR_DQ8PS_DDR_DQ9PS_DDR_DQ10PS_DDR_DQ11PS_DDR_DQ12PS_DDR_DQ13PS_DDR_DQ14PS_DDR_DQ15

PS_DDR_DQ17PS_DDR_DQ18

PS_DDR_DQ22

PS_DDR_DQ16

PS_DDR_DQ19PS_DDR_DQ20PS_DDR_DQ21

PS_DDR_DQ23PS_DDR_DQ24PS_DDR_DQ25PS_DDR_DQ26PS_DDR_DQ27PS_DDR_DQ28PS_DDR_DQ29PS_DDR_DQ30PS_DDR_DQ31

LPDDR4 16GBIT SRAM MICRON

U2

MT53B512M32D2NP-062 WT:C

AB10

AB8

AB5

AB3

Y12

Y8

Y5

Y1

W11

W9

W4

W2

V12

V8

V5

V1

T12

T10

T8

T5

T3

T1

P12

P10

P3

P1

N11

N4

N9

N2

K11

K9

K4

K2

J12

J10

J3

J1

G12

G10

G8

G5

G3

G1

E12

E8

E5

E1

D11

D9

D4

D2

T11

G11A8A5

AA10

AA5AA3W12W8W5W1U10U3

AA8

C12

C8

C5

C1

A10

A3

AB9AB4

N12N10

U12U1

U8U5R12R8R5R1

N3N1

T9T4

AB12AB11AB2AB1AA12AA1

N5R3R4

T2

N8P5P4

P9P8

P11R11R10R9P2R2

Y10Y3

V10W10V3W3

AA9Y9V9U9U11V11Y11AA11AA4Y4V4U4U2V2Y2AA2

B12B1

F10F3D12D8D5D1B10B8B5B3

K12K10K3K1H12H8H5H1F8F5A9A4

G9F12G4F1

A12A11A2A1

K5H3H4

G2

K8J5J4

J9J8

J11H11H10H9J2H2

C10C3

E10D10E3D3

B9C9E9F9F11E11C11B11B4C4E4F4F2E2C2B2

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PS LPDDR4 DRAM 15

Page 16: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Fixed Clocks

CLK0ACLK0B

CLK2B

CLK3BCLK3A

XAXB

CLK2A

FS0FS1

LOS

OEB_ALL

RESET

CLK1BCLK1A

GNDPAD

GND2

VDD1

VDD2

VDDO0

VDDO1

VDDO2

VDDO3

GND1

GND3

GND

GND

GND

GND

X1

X2GND2

GND1

VCC_PSAUX

NC

NC

SYSCLK_OEB_ALL

SYSCLK_RESET

33.33333333MHz LVCMOS(100/3)NC

X1

25MHZ1

34

2

VCC_PSAUX

26MHz LVDS

27MHz LVDS

PS_REF_CLKPS_REF_CLK_R

GTR_CLK1_DP_27M_NGTR_CLK1_DP_27M_P

GTR_CLK0_USB_26M_PGTR_CLK0_USB_26M_N

C590.1UF25V 2

1

25V0.1UFC60

2

1

25V0.1UFC61

2

1C620.1UF

25V 2

1C630.1UF25V 2

1

25V0.1UFC64

2

1

50PPM

R960

1

2

1%

24.9

R52

1 2

4.70KR17 1

2

R184.70K

1

2

DNPR821

2

R810

1

2

DNP

DNPR951

2

NC

U23 QFN24_4X4MM

SI5335A-B07834-GM

23

4

11

15

16

20

24

7

6 25

1817

3

5

8

1912

14

21

109

13

2122

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Fixed Clocks 16

Page 17: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

Expansion Headers

GND GND

VCC_5V0

10

17

2

3 4

5 6

7 8

9

12

14

16

18

20

22

24

26

28

3029

27

25

23

21

15

11

13

32

1

19

31

33

35

37

36

38

34

4039

HDR_2X20_SMT

J7

HD_GPIO_0

HD_GPIO_1

HD_GPIO_2

HD_GPIO_3

HD_GPIO_4

HD_GPIO_5

LSEXP_I2C0_SDA

LSEXP_I2C0_SCL

LSEXP_I2C1_SDA

LSEXP_I2C1_SCL

VCC_PSAUX

1 2

3

5

7

9

11

13

15

17

19

4

6

8

10

12

14

16

18

20

22

23 24

26

27 28

29 30

21

25

3231

39

37

35

33 34

36

38

40

41 42

44

45 46

48

49 50

51 52

43

47

5453

59

57

55 56

58

60

HDR_2X30_SMT

J3

GNDGND

CSI0_MCLK

CSI1_MCLK

DSI_CLK_P

DSI_CLK_N

DSI_D0_P

DSI_D0_N

DSI_D1_P

DSI_D1_N

DSI_D2_P

DSI_D2_N

DSI_D3_P

DSI_D3_N

HSIC_STR

HSIC_DATA

CSI0_C_P

CSI0_C_N

CSI0_D0_P

CSI0_D0_N

CSI0_D1_P

CSI0_D1_N

CSI0_D2_P

CSI0_D2_N

CSI0_D3_P

CSI0_D3_N

HSEXP_I2C3_SDA

HSEXP_I2C3_SCL

HSEXP_I2C2_SDA

HSEXP_I2C2_SCL

CSI1_C_P

CSI1_C_N

CSI1_D0_P

CSI1_D0_N

CSI1_D1_P

CSI1_D1_N

USB2D3_N

USB2D3_P

NC

NC

SPI shared with HS headerDifferent CS signals

PS_POR_PB_B

POWER_PB_B

VCC_PSAUX

R1241

2

100K1/20W1%

VSYS_IN

MIO10_SPI1_MISO

MIO6_SPI1_SCLK

MIO11_SPI1_MOSI

MIO9_SPI1_CS

HD_GPIO_9

HD_GPIO_10

HD_GPIO_11

HD_GPIO_12

HD_GPIO_13

HD_GPIO_8

HD_GPIO_6

HD_GPIO_7

MIO42_SPI0_MISO

MIO38_SPI0_SCLK

MIO43_SPI0_MOSI

MIO41_SPI0_CS

MIO36_PS_GPIO1_0 MIO37_PS_GPIO1_1

MIO39_PS_GPIO1_2 MIO40_PS_GPIO1_3

MIO44_PS_GPIO1_4 MIO45_PS_GPIO1_5

HD_GPIO_14

HD_GPIO_15

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Expansion Headers 17

Page 18: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

GND

GND

GND

GND

GND

GND

GND

GND

VCC

GND

IO2

IO1

IO3

IO4

D2_N

D0_PGND1D0_ND1_PGND2D1_ND2_PGND3

GND4D3_N

VCC2

VCC1

D3_P

NC

DRL_R_PDSO_N6

TPD4E001DRLR

U25

5

4

1

2

3

6

SON_15P

TPD8S009DSMR

U15

14

10

15

13

1211

87654321

9

VCC_3V3

VCC_3V3

VCC_3V3

DP_HPD_LS

GTR_LANE1_TX_N

GTR_LANE0_TX_NDP_HPD_R

GTR_LANE1_TX_P

GTR_LANE0_TX_P

GT1_DP_TX_C_PGT1_DP_TX_C_N

GT0_DP_TX_C_NGT0_DP_TX_C_P

DPAUX_C_PDPAUX_C_N

DP_SHLD_GND_R

PS Display Port Connector

NCNC

NCNC

NC

NC

NCNC

NC

1

20.01UFC11

25V

U20

49

8

7

6

2

1

5

3 EN

POK_B

IN

GND

FB

BYP

OUT

EPGS

TDFN_8_EP

MAX8902B

GND

VCC_5V0

GND

DP_VCC3V3

DP_VCC3V3

DP_VCC3V3

GND

DP_VCC3V3_OUT

P1

14

6

1210

1517

1387

4

1

16

24

18

911

23

19

2

2122

53 20DP_PWRML_LANE0_P

ML_LANE0_N

SHLD2SHLD1

HOTPLUG_DET

GND6

SHLD3

ML_LANE1_NML_LANE1_P

AUX_CH_N

SHLD4

AUX_CH_P

GND1

CONFIG1

GND2GND3GND4

ML_LANE2_NML_LANE2_P

ML_LANE3_PML_LANE3_N

CONFIG2

GND5

2129320-3

NC

0.1UF

25V

C8121

25V

0.1UF

C82

21

25V

0.1UF

C83

21

0.1UF25V

C84

2

1

0.1UF25V

C85

2

1

25V0.1UFC86

2

1

25V0.1UFC87

2

1

0.1UF

25V

C88

21

10V10UF

C169

2

1C17010UF10V2

1

10V10UF

C171

2

1

R44

1 2

10

R54

1 2

00

21R55

R1071.0M

1

2

1.0MR1081

2

100KR871

2

100KR891

2

100KR881

2

1

2

R2118.2K

R154.02K

1

2

D112

MSS2P330V2A

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PS Display Port Connector 18

Page 19: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

DIN

RIN_P

RIN_NROUT

DE

RE_B

VCC

GND

DOUT_P

DOUT_N

NC1NC2NC3NC4

FIN1019

TSSOP_14U12

13653

11

12

7

14

8

1

49

10

2

GND

GND

GND

VCC_3V3

VCC_3V3

DPAUX_P

DP_VBIAS_TX

DPAUX_N

DPAUX_C_P

DPAUX_C_N

PS Display Port IO

NCNCNCNC

DP_HPD_LS

GND

VCC_3V3

GND

VCC_PSAUX

GND

DP_AUX_OUT_LS

DP_OE_LS

GND

DP_AUX_IN_LS

DP_HPD_LS

25V0.1UFC78

2

1

25V0.1UFC79

1 2

25V0.1UFC80

1 2

1

2

C760.1UF25V

25V0.1UFC77

2

1

U24

156

12

138

16

1

23

1110

5

9

4

147 1A2 1B2

1DIR

2A2

2DIR

VCCA VCCB

1OE_B

2OE_B

2A1 2B1

2B2

1A1 1B1

GND GND

QFN_RSV_16

SN74AVC4T245

49.9R601

2

49.9R611

2

1.50KR161

2

2.49KR641

2

MIO27_DP_AUX_OUT

MIO28_DP_HPD

MIO29_DP_OE

MIO30_DP_AUX_IN

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PS Display Port IO 19

Page 20: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

PS Micro SD Card

GND

GND

VCC_3V3

MIO24_SD0_DETECT

MIO22_SD0_CLK_LS

MIO13_SD0_DAT0_LSMIO14_SD0_DAT1_LSMIO15_SD0_DAT2_LS

MIO16_SD0_DAT3_LSMIO21_SD0_CMD_LS

C74

25V

0.1UF

21

R384.70K

1

2

J4

18

1617

1415

11

12

10

78

65

134

1

32 CD_DAT3

CMD

DAT2

VDDSH1

CLKVSS

DAT1DAT0

CARD_DETECT

SH0

COMMON_DETECT

SH3SH2

SH5SH4

SH6

SCHA4B0419

VCCIO_VCC1IO_VCC2IO_VCC3IO_VCC4IO_VCC5CLK_VCC

IO_VL3IO_VL4IO_VL5

IO_VL1IO_VL2

CLK_VLCLK_RET EP

GND

VL

U13 TQFN_16

MAX13035E

2

131711

12

31

1094

1487651516

NC

2

1 R22DNP

DNP

GND

C55

21

25V

0.1UF

C58

21

25V

0.1UF

VCC_PSAUX

MIO22_SD0_CLK

MIO13_SD0_DAT0MIO14_SD0_DAT1MIO15_SD0_DAT2MIO16_SD0_DAT3MIO21_SD0_CMD

MIO22_SD0_CLK_LS_R

MIO13_SD0_DAT0_LSMIO14_SD0_DAT1_LSMIO15_SD0_DAT2_LSMIO16_SD0_DAT3_LSMIO21_SD0_CMD_LS

GND

VCC_PSAUX VCC_3V3

SD_VCC_3V3

SD_VCC_PSAUX

1 2L17

FERRITE-220

GND

SD_SHLD_GND

MIO22_SD0_CLK_LS

SD_GND

SD_GNDSD_GND

0

21

R159

R162

1 2

0 1/10W

5% 5%

1/10W

0

21R163

R164

1 2

0 1/10W

5%

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PS Micro SD Card 20

Page 21: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

GND_1

GPIO11

GPIO9

GPIO10

GPIO12

WL_SDIO_CMD_1V8

GND_7

WL_SDIO_CLK

GND_9

WL_SDIO_D0_1V8

WL_SDIO_D1_1V8

WL_SDIO_D2_1V8

WL_SDIO_D3_1V8

WL_IRQ_1V8

GND_15

GND_16

GND_17

RF_ANT2

GND_19

GND_20

RESERVED1

RESERVED2

GND_23

GND_24

GPIO4

GPIO2

GPIO1

GND_28

GND_29

GND_30

GND_31

RF_ANT1

GND_G1GND_G2GND_G3GND_G4GND_G5GND_G6GND_G7GND_G8GND_G9GND_G10GND_G11GND_G12GND_G13GND_G14GND_G15GND_G16GND_G17GND_G18

GND_49

BT_HCI_RTS_1V8

BT_HCI_CTS_1V8

BT_HCI_TX_1V8

BT_HCI_RX_1V8

GND_54

GND_55

BT_AUD_IN

BT_AUD_OUT

BT_AUD_FSYNC

GND_59

BT_AUD_CLK

GND_61

RESERVED3

GND_63

GND_64

GND_G19GND_G20GND_G21GND_G22GND_G23GND_G24GND_G25GND_G26GND_G27GND_G28GND_G29GND_G30GND_G31GND_G32GND_G33GND_G34GND_G35GND_G36

GND_33

GND_34

GND_35

EXT_32K

GND_37

VIO_IN

GND_39

WLAN_EN

BT_EN

WL_UART_DBG

BT_UART_DBG

GND_44

GND_45

VBAT_IN_47

GND_48

VBAT_IN_46

PS WiFi - Bluetooth

GND GND

GND

GNDMIO76_WLAN_IRQ

MIO49_SD1_D3

MIO48_SD1_D2

MIO47_SD1_D1

MIO46_SD1_D0

MIO51_SD1_CLK

MIO50_SD1_CMD

VCC_PSAUX

BT_AUD_FSYNC

BT_AUD_OUT

BT_AUD_IN

BT_AUD_CLK

BT_HCI_CTS

BT_HCI_RTS

GND

VCC_3V3

VCC_PSAUX

NC

U1632 4

1GND1GND2CLKOUT

VDD

32.768KHZ

EXT_32K

VCC_PSAUX

GND

NC

NC

NC

NC

NC

NC

NC

GND

U21

13 2GND1

GND2

SIG

DNP

GND DS8

12

LED-YELLOW-SMT

VCC_3V3

DS1

LED-BLUE-SMT

12

VCC_3V3

GND GND

Q1

2

3

1

RUM001L02T2CL

RUM001L02T2CL

1

3

2

Q2

MIO7_WLAN_EN MIO8_BT_EN

0.1UF25V

C98

2

1

C99

25V

0.1UF

21

4V1UFC51

2

1

150MW

10PPM

150MW

C17210UF10V 2

1

R105261

12

U10

A2

B2

B1

A1FEED

2_4G 5GNC

ANT016008LCD2442MA1RF_ANT1_CRF_ANT1 RF_ANT1_FEED

DNPDNP

1

2

C16

GND

C19

2

12.2PF50V

GND

J101 TP_PAD

TP_PAD

1 J11

TP_PAD

1J12

J13

1TP_PAD

NC

NC

1 2 3 4 5 6 7 8 9 10

11

12

13

56

34

9596979899100

33

94

57

58

59

60

61

62

63

64

838485

35

36

37

QFN_MOC_100

7273747576777879808182

38

U3

39

49

50

86878889909192

14

15

16

17

18

19

20

21

22

93

51

52

53

54

55

666768697071

23

24

25

26

27

28

29

30

31

32

65

40

41

42

43

44

45

47

48

46

WL1831MODGBMOCR

GNDGND

C15DNPDNP2

1

C14

8PF

25V

21

C22

10PF

50V

21

R69

DNP1

2

R138

DNP1

2 2

1DNP

R139

R140

DNP1

2 2

1DNP

R141

R142DNP

1

2

21

R1064.70K

MIO2_UART0_RX_BT_HCI_TX

MIO3_UART0_TX_BT_HCI_RX

MIO7_WLAN_EN

MIO8_BT_EN

L131.5NH

2

1

R1294.70K1/16W1%

1

2 1%1/16W4.70K

R130

1

2

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PS WiFi - Bluetooth 21

Page 22: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

REFSEL2_14

DATA0_3

RBIAS_23

ID_23

VBUS_22

VBAT_21

VDD33_P

DM_19

DP_18

CPEN33_17NC_12

REFSEL0_8

DATA4_7DATA6_10

CLKOUT_1

NXT_2

DATA2_5

REFSEL1_11

VDDIO_32

DIR_31

DATA5_9

DATA7_13

DATA1_4

SPK_L_15

REFCLK_26

SPK_R_16

XO_25

VDD18_30

DATA3_6

STP_29

VDD18_28

RESETB_27

CTR_GND_33

GND1

D1_ND1_P

GND2

D2_PD2_N NC1

NC2

NC3NC4

100 ohm for USB 3.0 USB_SSTX_P/N, USB_SSRX_P/N

Thick trace for ULPI_VBUS and related nets

GND

ULPI0_VBUS

FERRITE-220

L11 21

FERRITE-220

L12 21

GND

GND

GND

6.3V2.2UFC1

2

1

GND

GND

GND

GND

GND

USB3320_QFN32

USB3320_QFN32U8

3327

28

29

6

30

25

16

26

15

4

139

31

32

11

5

2

1

10

7

812

17

18

19

20

21

22

23

24

3

14

GND

DNPDNPC40

2

1

ULPI0_D_P

ULPI0_D_N

ULPI0_VBUS_L

ULPI0_SHLD_GND

ULPI0_CON_GND_L

90 ohm impedance for USB 2.0 ULPI_D_P/N,

USB 3.0 AC coupling for TX

GTR_LANE2_TX_C_P

GTR_LANE2_TX_C_N

MIO56_USB0_DATA0

ULPI0_VDD33

MIO60_USB0_DATA4

MIO62_USB0_DATA6

MIO52_USB0_CLK

MIO55_USB0_NXT

MIO54_USB0_DATA2

MIO53_USB0_DIR

MIO61_USB0_DATA5

MIO63_USB0_DATA7

MIO57_USB0_DATA1

MIO59_USB0_DATA3

MIO58_USB0_STP

ULPI0_D_P

ULPI0_D_N

USB_RST_B

GNDGND GND

USB_RST_B

C16518PF50V2

1C16618PF50V 2

1

GND

U22DQA_R_PSON_N10

TPD4E05U06DQAR109

765

4

8

12

3

PS USB 3_0 ULPI Upstream

PS_POR_B

NC

NC

NC

ULPI0_VBUS_R

NC

U14

4

5

3

2

1 A

BYAND

GND

VCC

SC70_5

SN74LVC1G08

NC

PS_MODE0_1

VCC_PSAUX

VCC_PSAUX

VCC_5V0

VCC_PSAUX

ULPI0_VBUS

C890.1UF25V2

1C900.1UF25V2

1 C910.1UF25V2

1

C920.1UF25V2

1

C930.1UF25V2

1

C94

0.1UF

25V

21C95

0.1UF

25V

21

C960.1UF25V2

1

1UF35V

C32

2

1

GTR_LANE2_TX_P

GTR_LANE2_TX_N

GTR_LANE2_RX_P

GTR_LANE2_RX_N

1.0MR109 1

2

1%

R6810.0K

1

28.06KR58

1 2

GTR_LANE2_RX_PGTR_LANE2_RX_N

GTR_LANE2_TX_C_PGTR_LANE2_TX_C_N

GTR_LANE2_RX_PGTR_LANE2_RX_N

GTR_LANE2_TX_C_PGTR_LANE2_TX_C_N

J1

10

6

7

8

9

16

15

5

14

13

12

11

1

4

3

2D_N

D_P

ID

VBUS

SHLD1

SHLD2

SHLD3

SHLD4

GND

SHLD5

SHLD6

SSRXN

GND_DRAIN

SSTXP

SSTXN

SSRXP

692622030100

100PPM

24.000MHZ

X21 2

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PS USB 3_0 ULPI Upstream 22

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PS USB 3_0 ULPI Downstream

REFSEL2_14

DATA0_3

RBIAS_23

ID_23

VBUS_22

VBAT_21

VDD33_P

DM_19

DP_18

CPEN33_17

NC_12

REFSEL0_8

DATA4_7

DATA6_10

CLKOUT_1

NXT_2

DATA2_5

REFSEL1_11

VDDIO_32

DIR_31

DATA5_9

DATA7_13

DATA1_4

SPK_L_15

REFCLK_26

SPK_R_16

XO_25

VDD18_30

DATA3_6

STP_29

VDD18_28

RESETB_27

CTR_GND_33

GND

GND

6.3V2.2UFC2

2

1

GND

GND

GND

GND

GND

USB3320_QFN32

USB3320_QFN32U9

33

27

28

29

630

25

16

26

15

4

139

31

32

11

5

2

1

10

7

8

12

17

18

19

20

21

22

23

24

3

14

ULPI1_VDD33

ULPI1_D_P

ULPI1_D_N

VCC_5V0

VCC_PSAUX

VCC_PSAUX

NC

NC

NC

USB_RST_B

GND

90 ohm impedance for USB 2.0 ULPI_D_P/N

MIO68_USB1_DATA0

MIO72_USB1_DATA4

MIO74_USB1_DATA6

MIO64_USB1_CLK

MIO67_USB1_NXT

MIO66_USB1_DATA2

MIO65_USB1_DIR

MIO73_USB1_DATA5

MIO75_USB1_DATA7

MIO69_USB1_DATA1

MIO71_USB1_DATA3

MIO70_USB1_STP

C1010.1UF25V2

1C1020.1UF25V2

1 C1030.1UF25V2

1

C1040.1UF25V2

1

1.0MR110 1

2

R71 10.0K

1 2

8.06KR59

1 2

MIO25_VBUS_DET

R123

1 2

DNP

DNP

DNP

ULPI1_CPEN

100PPM

24.000MHZ

X31 2

C1678PF50V2

1C1688PF50V 2

1

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PS USB 3_0 ULPI Downstream 23

Page 24: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

PS USB 3_0 Hub

GND

ULPI1_D_N

USB 3.0: Connect TX to RX, add AC coupling

GND

USB_RST_B

MIO25_VBUS_DET_LS

GND

U5

36353432

3029

2726

2524

2322

2019

1817

1413

1110

98

76

34

21

5354

55443116

12

4943

5

33282115

37

47

50

48

51

4546

3940

38

41

42

56

52

57GND_PAD

TESTEN_ATEST

RBIAS

RESET_N

SPI_CE_N_CFG_NOM_REM

SPI_CLK_SMCLK

SPI_DI_CFG_BC_ENSPI_DO_SMDAT

USB2DM_UPUSB2DP_UP

USB3DM_RXUP

USB3DM_TXUP

USB3DP_RXUP

USB3DP_TXUP

VBUS_DET_GPIO16

VDD12_15VDD12_21VDD12_28VDD12_33

VDD12_5

VDD12_43VDD12_49

VDD12_12

VDD33_16VDD33_31VDD33_44VDD33_55

XTALIN_CLK_INXTALOUT

USB2DP_DN1USB2DN_DN1

USB3DM_TXDN1USB3DP_TXDN1

USB3DP_RXDN1USB3DM_RXDN1

USB2DP_DN2USB2DM_DN2

USB3DP_TXDN2USB3DM_TXDN2

USB3DP_RXDN2USB3DM_RXDN2

USB2DP_DN3USB2DM_DN3

USB3DP_TXDN3USB3DM_TXDN3

USB3DP_RXDN3USB3DM_RXDN3

USB2DP_DN4USB2DM_DN4

USB3DP_TXDN4USB3DM_TXDN4

USB3DP_RXDN4USB3DM_RXDN4

GANG_PWR_PRT_CTL4PRT_CTL3PRT_CTL2PRT_CTL1

SQFN_56_EPUSB5744_56VQFN

VCC_1V2

VCC_3V3

VCC_1V2

VCC_3V3

GND

GND

USB5744_SDA_RUSB5744_SCL_R

D_N

D_P

VBUS

SHLD1

SHLD2

GND

SSRXN

GND_DRAIN

SSTXP

SSTXN

SSRXP

GND

GND

USB_PORTA_SHLD

USB_PORTA_VBUS

USB2D1_NUSB2D1_P

USB_SSRX1_NUSB_SSRX1_P

USB_SSTX1_NUSB_SSTX1_P

USB_SSTX1_C_N

USB_SSTX1_C_P

USB2D2_NUSB2D2_P

D_N

D_P

VBUS

SHLD1

SHLD2

GND

SSRXN

GND_DRAIN

SSTXP

SSTXN

SSRXP

USB_SSRX2_NUSB_SSRX2_P

USB_SSTX2_C_N

USB_SSTX2_C_P

USB_SSTX2_NUSB_SSTX2_P

GND

GND

USB_PORTB_SHLD

USB_PORTB_VBUS

USB2D3_NUSB2D3_P

NCNC

NCNC

NCNC

NCNC

NCNC

U18

74

2

35

6 1VOUTVIN

GNDFAULT_B

ILIMITENABLE

EP

MLF6_2X2MM_EP

MIC2009_MLF6

VCC_5V0

GND

R971

2

100

USB_PORTA_VBUS

VOUTVIN

GNDFAULT_B

ILIMITENABLE

EP

U19

74

2

35

6 1

MLF6_2X2MM_EP

MIC2009_MLF6

VCC_5V0

GND

100

2

1 R98

USB_PORTB_VBUS

100 ohm for USB 3.0 GTR_LANE3*

90 ohm impedance for USB 2.0 ULPI_D_P/N,

C105

0.1UF

25V

21

25V

0.1UF

C106

21

C1070.1UF

25V

2

1

C110

0.1UF

25V

21C111

0.1UF

25V

21

25V0.1UFC112 2

1

25V

0.1UF

C113

21

C1140.1UF25V

2

1

C115

0.1UF

25V

21

25V0.1UFC1162

1

C1170.1UF25V 2

1

25V0.1UFC118

2

1

25V0.1UFC119

2

1C1200.1UF25V 2

1

25V0.1UFC121

2

1C1220.1UF25V 2

1C1230.1UF

25V 2

1

25V0.1UFC124

2

1

25V0.1UFC125

2

1C1260.1UF

25V 2

1C1270.1UF

25V 2

1

25V0.1UFC128

2

1

C471000PF

25V 2

1

25V1000PFC48

2

1

C491000PF

25V 2

1 C501000PF

25V 2

1

2

1330R111

R112330

1

2

R471.00K

1

2

R8612.0K

1

2

C136

21150UF

6.3V

X5R

X5R

6.3V

150UF

1 2

C137

J8

692121030100

6

8

9

7

5

4

10

11

1

3

2

692121030100

J9

6

8

9

7

5

4

10

11

1

3

2

VCC_3V3

10.0KR1211

2 2

1 R12210.0K

R1251

2

200K1/20W1%

GND

1%1/20W200K

2

1 R126

C12

12PF

50V

21

50V

12PF

C13

21

85 ohm for USB 3.0 USB_SSRX*, USBSSTX*

90 ohm impedance for USB 2.0 USB2D*

GND1

GND2X2

X1

40PPMX4

25.00MHZ

3 4

1 2

R143

1 2DNP

DNP

21R144

USB5744_SDAUSB5744_SCL

GND

GND

GND

DIR

VCCB

B

VCCA

GND

A

1.8VVCC_3V3

1

2

C750.1UF25V

5

6

4

1

2

3

SN74AVC1T45

SC70_6U6

1

225V0.1UFC100

VCC_PSAUX

MIO25_VBUS_DET_LSMIO25_VBUS_DET

ULPI1_D_P

GTR_LANE3_RX_C_N

1 225V

0.1UF

C193

1 2

C194

0.1UF

25V

GTR_LANE3_RX_C_P

GTR_LANE3_RX_PGTR_LANE3_RX_N

C195

0.1UF

25V

21

25V

0.1UF

C196

21

GTR_LANE3_TX_C_NGTR_LANE3_TX_C_PGTR_LANE3_TX_P

GTR_LANE3_TX_N

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PS USB 3_0 Hub 24

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I2C MUX

PMIC_SDAPMIC_SCL

LSEXP_I2C0_SDALSEXP_I2C0_SCLLSEXP_I2C1_SDALSEXP_I2C1_SCL

MIO12_I2C_MUX_RESET_B

GND

RESET_B

A1A0

VCC

SDASCL

A2

GND

SD3SC3SD4SC4SD5SC5SD6SC6SD7SC7

SD2SC2

SD1SC1

SD0SC0

TCA9548APWR_TSSOP_24

TSSOP_24U11

54

76

98

20191817161514131110

12

21

2223

24

12

3HSEXP_I2C3_SDAHSEXP_I2C3_SCL

HSEXP_I2C2_SDAHSEXP_I2C2_SCL

VCC_PSAUX

VCC_PSAUX

VCC_3V3

C570.1UF25V2

1

R3

2.21K

1

2

2.21K

R4

1

2

R5

2.21K

1

2

2.21K

R6

1

2

R7

2.21K

1

2

R8

2.21K

1

2

R9

2.21K

1

2

R102.21K

1

2

2.21K

R11

1

2

2.21K

R12

1

2

2.21K

R13

1

2

2.21K

R14

1

2

R1134.99K

1

2

R1144.99K

1

2

R1154.99K

1

2

4.99KR1161

2

R1174.99K

1

2

R1184.99K

1

2

DNPR781

2

R79DNP

1

2

DNPR801

2

2

1

DNP

R22

1DNP

R1

USB5744_SCLUSB5744_SDA

VCC_3V3

INA226_PMBUS_SDAINA226_PMBUS_SCL

NCNC

MIO4_I2C1_SCLMIO5_I2C1_SDA

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

I2C MUX 25

Page 26: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

U33

65

64

52

45

44

43

42

41

40

39

37

36

35

34

33

30

29

25

23

22

20

12

10

7

6

5

4

3

2

1

6362

61

60

5958

57

56

55

54

53

51

50

49

48

47

46

38

32

31

28

27

26

2421

19

18

17

16

15

14

13

11

9

8DRV5V_2_A1

LDOA1

PVIN3

CTL1

CTL6_SLPENB2

IRQB

GPO1

SWB1

PVINSWB1_B2

SWB2

PVIN5PVIN4

GPO2

GPO3

GPO4

SWA1

PVINSWA1

DRV5V_1_6

PVINVTT

VTT

VTTFB

LDOA3

PVINLDOA2_A3

LDOA2

VREF

LDO3P3

VSYS

LDO5P0

V5ANA

CLKDATA

CTL2

CTL3_SLPENB1

CTL4CTL5

FBGND2

FBVOUT2

DRVH2

SW2

BOOT2

PGNDSNS2

DRVL2

LX3

FB3

LX5

FB5

FB4

LX4

FBVOUT1

ILIM1

DRVH1

SW1

BOOT1

PGNDSNS1

DRVL1

DRVL6

PGNDSNS6

BOOT6

SW6

DRVH6

FBVOUT6

ILIM6

AGND

ILIM2

GNDPAD

QFN_64_8X8MM_EPTPS6508641

PMIC

VSYS

GND

GND

LDO5V0

PMIC_SDAPMIC_SCL

PMIC_IRQ

MGTRAVCCVCC_PSPLL

VCCO_HP

VCCAUX

GND

LDO5V0

GND

1

26.3V4.7UFC30

GND

C1642

1

4.7UF10V

GND

C146

2

12.2UF10V

GND

10V2.2UF

1

2

C147

GND

VCC_5V0

C314.7UF6.3V2

1

GND

SW11 2

B3U-1000P

GND

MGTRAVCC

C244.7UF6.3V2

1

VCC_PSPLL VCCO_HP

1

2 6.3V4.7UFC25

GND

GND

VCC_PSAUX

PMIC_VREF

U26

5

32

4

1 TG

BG

VIN

PGND

VSW

CSD87381P

GND

VSYS

GND

BUCK1_SW

VCC_5V0

GND

TG

BG

VIN

PGND

VSW

CSD87381P

1

4

23

5

U27

BUCK2_SW

GND

470NH

1 2

L10

VSYS

VCC_PSINTLP

GNDZ221

GND

TG

BG

VIN

PGND

VSW

U28

5

32

4

1

CSD87381P

BUCK6_SW

GND

VSYS

VCC_PSAUX

GND

12Z3

0201_SHORT

GND

FBOUT6

FBOUT1

FBOUT2_P

DRVH1

DRVL1

DRVH2

DRVL2

DRVH6

DRVL6

1 2

Z4

VCCO_PSDDR

GND

GND

FBOUT2_N

VCC_3V3

GND

VCC_1V2

GND

BUCK3_SW

BUCK4_SW

BUCK5_SW

C264.7UF6.3V2

1

VCC_5V0

GND

R56

1 2

0

1

2 6.3V4.7UFC27

Z5 21

1 2Z6

Z7 21470NH

L6

1 2

L7

470NH

21

470NH

L8

1 2

ILIM6

BOOT6

BUCK_FB5

BUCK_FB4

BUCK_FB3

ILIM2

BOOT1

BOOT2

ILIM1

U31

D1D2

C2B2A2

C1B1A1

VOUT_A1VOUT_B1VOUT_C1

VIN_A2VIN_B2VIN_C2

ON GND

BGA8_TI_YZP

TPS22920YZPRB

GNDGND

VCC_PSINTLP

PSINTFP_EN

VCC_PSINTFP

6.3V4.7UFC28

2

1VOUT_A1VOUT_B1VOUT_C1

VIN_A2VIN_B2VIN_C2

ON GND

TPS22920YZPRB

BGA8_TI_YZP

A1B1C1

A2B2C2

D2 D1

U32

GNDGND

VCC_PSINTLP

VCCINT_EN

VCCINT

1

2

C294.7UF6.3V

25V0.1UFC130

2

1 C1310.1UF25V2

1

25V

0.1UF

C132

21

C133

0.1UF

25V

21

25V

0.1UF

C134

21

C1350.1UF25V 2

1 C331UF35V2

1C341UF35V 2

1

4V1UFC54

2

1

C521UF4V 2

1 C531UF4V 2

1

35V22UFC139

2

1

C14122UF35V

2

1

35V22UFC143

2

1

C14422UF35V

2

1

C1022UF6.3V

2

1

6.3V22UFC7

2

1

6.3V22UFC8

2

1

C922UF6.3V

2

1

20%

C17410UF10V 2

1

10V10UF

C175

2

1

10V10UFC177

2

1

21

0201_SHORT

Z8

C1782

1

47UF35V

R62

2.37K

1 2

R7210.0K

1

2

10.0KR731

2

R7410.0K

1

2

10.0KR751

2

R7610.0K

1

2

1%11.0K

R85

1 2

R24

9.31K

1 2

LDO3V3

MGTRAVTT

MGTRAVTT

NC

MIO32_PS_FP_PWR_EN_LS

GND

1

32

Q4

VCC_PSAUX

MIO33_PL_PWR_EN

MIO32_PS_FP_PWR_EN

LDO3V3

R11910.0K

1

2

POWER_EN_RPS_POR_PB_B

R7710.0K

1

2

PS_POR_PB_B

SW3

B3U-1000P

1 2

GND

POWER_PB_BPOWER_EN

GND

PSINTFP_ENPS_POR_B

NCVCCINT_EN

LDO3V3

C670.1UF25V 2

1

GND

C68

2

1DNPDNP

GND

LDO3V3

2

110.0KR83 R84

10.0K1

2

MIO26_POWER_INT_B

R120

1 2

0

MIO34_POWER_KILL_B

Z921SNS1

Z1021SNS2

Z1121SNS6

20%

L9

2.2UH

21

GND

R133

1 2

357K

1/20W

1%

R13231.6K1/20W1%

1

2

C189

2

1DNPDNPDNP R

134

1 2

6.49K

1/20W

1%

21

LED-GRN-SMT

DS9

21 R146

261

GND

VCC_3V3

C37

2

147UF6.3VX5R

U7

8

7

5

4

3

9 621GND

ONT

PDT

GNDPAD

PB_B

VIN

KILL_B

EN

INT_B

DFN_3X2MM_8P_EP

LTC2954CDDB-1TRMPBF

L5

1.0UH

21

10.0KR361

2

LDO3V3

2

1 R3910.0K

LDO3V3

6.3V1.5UFC129

2

1

R1610

1 2

POWER_EN

C197DNPDNP 2

1

GND

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

PMIC 26

Page 27: AES-ULTRA96-G · zynq banks 65 66 - hp vcco_hp u1 c2 d2 f2 f3 c3 d3 d1 e1 e3 e4 f1 g1 f4 h3 g4 h4 g2 h2 h5 j5 j1 k1 k3 k4 j2 j3 l3 l4 l1 l2 m4 m5 m1 m2 n4 n5 p1 n2 n3 p2 r5 p5 t1

VCC_PSAUX 1.80V

GND

GND

GND

GND

Power Connector - Mounting Holes

MH1

MH_111_2001

MH_111_200

MH2

1

MH3

MH_111_2001

MH_111_200

MH4

1

CENTER_PWR

GND

PLUG_DET

IN OUT

GND 21

0.01

R63

1

23

PJ-041H

J5

12

3

ELK-EA221FAU34

VSYS_R

GND

1TP_PAD

J14

1J15TP_PAD

VSYS

F9 21

3.0AVSYS_F

VSYS_IN

12v Power Brick

J181

DNP

DNP

1J19

GND

VCC_5V0

Fan wires, place near board edge

A0A1

GND

SCLSDAALERT

VS_PVBUS

VIN_N

VIN_P

U35

INA226

8

10

9

6

345

712

GND

VCC_3V3

VSYS_VIN_N

VSYS_VIN_P

I2C ADDR0x40

MIO31_INA226_PMBUS_ALERTINA226_PMBUS_SDAINA226_PMBUS_SCL

GNDGND

R13510

2

1R13610

2

1

1

2 25V

C1900.1UF

0.1UFC191

25V2

1

VCC_3V3 3.30V

VCC_1V2 1.20V

LDO5V0 5.00V

LDO3V3 3.30V

VCCINT 0.85V

VCCAUX 1.80V

VCCO_HP 1.20V

VCC_5V0 5.00V

VCC_PSDDR 1.10V

MGTRAVCC 0.90V

MGTRAVTT 1.80V

RAIL VOLTAGE

VCC_PSINTFP 0.85V

VCC_PSINTLP 0.85V

VCC_PSPLL 1.20V

USB_PORTA_VBUS 5.00V

USB_PORTB_VBUS 5.00V

DP_VCC3V3 3.30V

D2

12

DL4148

100V

500MW

VCC_3V3

R1501

2

01/10W5%

R1511

2

DNPDNPDNP

FAN_PWM

VCCO_HP

PWR_BRICK_12V

PB1

BRKT1

THERMAL_BRACKET

MS1

NYLON_SCREW NYLON_SCREW

MS2

MS3

MACHINE_SCREW_M2_5MACHINE_SCREW_M2_5

MS4 MS5

MACHINE_SCREW_M2_5MACHINE_SCREW_M2_5

MS6

MSO1

STANDOFF_4_5MM STANDOFF_4_5MM

MSO2 MSO3

STANDOFF_4_5MM STANDOFF_4_5MM

MSO4

CBL1

DP

Display Port Cable

Mini DP

DP_CABLE

FAN?

5V Fan

FAN_5V

Q9

23

1

NDS331N460MW

2

1 R1491.00K1/16W1%

31

01BOM:

12:24:07 pmTime:

AES-ULTRA96-G

B

Doc Num:

27

Variant:

001SCH-US1DEV 3/9/2018

ofSheet:

Date:

Sheet Title:

PCB Rev:

Size:

Project Name:

Avnet Design Services

1 2 3 4 5 6

D

C

B

A

654321

A

B

C

D

Power Connector - Mounting Holes 27


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