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Page 1 Agilent Digital Measurement Forum DisplayPort Compliance test challenges and solutions
Page 1
Agilent DigitalMeasurement Forum
DisplayPort Compliance test challenges and solutions
Page 2
Agenda
Introduction to DisplayPort
Testing Considerations in DisplayPort
Compliance Program
Validation Tools and Leverage
in the Design and DeBug Process
Page 3
Introduction to DisplayPort
1. High Level View of the world: PC vs Consumer Electronics
2. Physical interface
3. Benefits
DisplayPort
HDMI
Page 4
Introduction: Display Technologies Overview
HDMI
UDI
DisplayPort
1.1 1.2
1.3 1.4?DVI 1.0
2.0?
Wireless HDMIConsumerElectronics
PersonalComputer
DisplayPort
Today
Wireless HD
2.0?
Page 5
DisplayPort Technology Overview
DPCD / EDID
1 to 4 high speed lanes (1.62, 2.7Gb/s) – Source to Sink only– Fixed data rate independent of display refresh– Support maximum of 10.8Gbit/s data rate WQXGA (2560x1600) resolution over
3m cableAuxiliary channel for bidirectional link communication (1Mb/s)Auto detect of cable plug/unplugScalable to DDR/QDR rates for higher capacity displays
Hot Plug Detect(Interrupt Request)
Page 6
DisplayPort Technology (Main Link Lanes)
Data Rate• 1.62 Gbs• 2.7 Gbs (units supporting 2.7 must support 1.62 as well)
Lanes• Each lane is Differential, 100Ω. • 1, 2, 4 lane models for video data transport. 4 lane model capable must support 1
& 2 lane models. 2 lane model must support 1 lane model. Lanes are uni-directional
• ANSII standard 8b/10b• Each lane has separate clock recovery• Single ended lines of each lane are source and sink terminated and biased. No
external pull-up is needed for test equipment.
Receiver• PLL BW=10MHz effective
Page 7
DisplayPort Technology (Main Link Lanes)
DisplayPort Signal Parametrics• 400, 600, 800, 1200 mVolts pk-pk. 1200 is optional• 0, 3.5, 6, 9.5 dB pre-emphasis. 9.5dB is optional• No combination of voltage and pre-emphasis can exceed 1200mVolts pk-
pk• Spread Spectrum Clocking (30-33KHz spreading frequency, downspread)• Rise time not to be below 75ps• Total Jitter and Non-ISI jitter is specified
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DisplayPort Technology (AUX Channel)
• Designated Control Link lane called ‘the AUX Channel’ specified. Operates at 1Mbs and is used in Link Training and Link Management and is Bidirectional Half Duplex
• The Transmitter is the master• Receiver gains attention by pulling down on the Hot Plug Detect Line• Manchester II coding
Hot Plug Detect
AUX
AUX Control
Transmitter Receiver
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DisplayPort and HDMI TechnologiesHDMI DisplayPort
Market HDTV/Gaming PCsTechnology TMDS (8B/10B) PCI-E (ANSI 8B/10B)Configuration 4 lanes (3 Data, 1 Ck)
Differential, DC coupled1,2 or 4 lanes
(Embedded Clock) Differential, AC coupled
Bit Rate 250Mbs to 3.4Gbs per lane
1.62 or 2.7Gbs
Tx/Rx Negotiation EDID/DDC AUX ChannelCompliance Authorized Test Centers Qualified Test HousesOwnership HDMI.org VESAStd/Royalty Closed/Yes Open/NoDriving Need HDTV and HDCP MarginModels External External and Embedded
Page 10
What does DisplayPort mean?
Fewer ConnectorsFewer ICs
CheaperLess PowerMore Available PinsHas Headroom
Looks like a margin playScalable benefits vs resolution
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• Computer Graphics Controller• Computer Display• Multimedia monitor• Device concentrator• Device replicator• Repeater• Display controller• Multimedia / AV selector (e.g. Home theater receiver)• Legacy converter / Protocol Bridge (e.g. DP <-> HDMI/VGA/DVI)• Handheld Video• Chip-chip communications• Cables
DisplayPort Applications
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Testing Considerations for DisplayPortFamiliar Measurement and Development Problems
Content Display
Phy Layer Test Points
Link Layer/Protocol/HDCP Test and Control Points
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Physical Layer CTS Testing
Physical Layer Compliance Test Points
The DisplayPort C.T.S. focuses on Testpoints TP2 and TP3
In practice, cannot have the testpoint in the middle of aconnection, so the measurement setup always includesthe whole connection
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Physical Layer CTS Testing: Test Points, cont
Source Testing
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Physical Layer CTS Testing Test Points, cont
Cable Testing
Sink Testing
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LinkLayer Testpoints
Source Sink
TP
TP
TP
Some Phy Layer MeasurementsRequired
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Analyzer
Generator
Ref Source
Ref Sink
Source
Sink
Cable(different generator and analyzer needs)
Generator
Analyzer
Hybrid and Branch Devices
Generator
Ref Source
Ref SourceAnalyzer
Ref Sink
Phy CTS Instrumentation Elements (Generic)
Aux
Aux
AuxAux
Aux
DUT
DUT
DUT
DUT
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DisplayPort Compliance (Official Compliance Process)
VESA approved Test Center
DisplayPort Logo License Agreement
Adopter
Adopter’s Product
Logo Granted
Link Layer CTSTest 1Test 2Test 3:
Phy Layer CTSTest 1Test 2Test 3:
DisplayPort Compliance Checklists
Compliant Product List
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DisplayPort ComplianceA lot like USB…
Compliance maturity obviously is low at this point:VTM will administer the compliance testing at Plugtests.No official statement on interoperability test regimen like USBNo official mechanisms for cooperation between test vendors, test labs, plugfests and VESA to assure ‘conscious interoperability’.
Plugfests Focus to facilitate interoperability by exposure and by test
Logo Yes
CertificationVESA approved independent Test centers: Allion, ETC, NTS, Contech Research
Product Change
CriteriaRe-certification required at Test House if Critical or Significant changes are made
Self Certification Under Discussion
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Source (TX) Channel Test– High speed lanes
• Link training• Tx mask compliance (noise, jitter)• Pre-emphasis/Non-pre-emphasis• Skew
– Aux Channel• Link negotiation and training• Sink device (EDID) support• Error injection
– Hot Plug– SSC support– Tx <-> Source connector interconnect– Multimedia (audio, video, sink event)
Link Layer Test– Source reference– Sink reference– Branch test (coordinated
source/sink)
DisplayPort Validation Tasks (Phy/Link)Sink (Rx) Test
– High speed lanes• Link training• Jitter/noise tolerance
– Aux Channel control– Hot Plug– Link Training, Deskew– Multimedia(audio, video, source event)
Branch / Replicator / Concentrator / Bridge Device Test
– Tx/Rx test– Error handling– Conversion to proprietary protocol– BER (with and without interconnect)– Pre-emphasis repeating– DP/HDMI/DVI Adapter
HDCP– Challenge / response protocol
Cable / Connector test– Loss, NEXT, FEXT, Skew, Return loss
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Compliance Tests (Phy Layer)1. Source Tests
• Eye Diagram Test• Non-PreEmphasis Level • Pre-Emphasis Accuracy• Intra pair skew• Inter pair skew• Frequency Accuracy• Non-ISI Jitter• Total Jitter• AC Common Mode noise• Unit Interval• Maximum/Minimum BitRate• Spread Spectrum Modulation
Frequency• Spread Spectrum Modulation
Deviation accuracy
2. Sink Tests• Jitter Tolerance
3. Cable Tests• Intra Pair Skew• Far End Noise• Cable and Connector Impedance • Insertion Loss• Near End Noise• Return Loss
Page 22
Physical Parameter Verification in Link Layer Compliance Tests
Source Tests• AUX Read after Hot Plug
Connect• EDID Reads• DPCD Reads• Link Training• Link Maintenance• Main Stream Data Mapping• Maximum Pixel Rate• Main Video Stream Format
Change Handling
Sink Tests• AUX Channel Protocol• EDID Reads• DPCD Reads• Link Training• Link Maintenance• Main video Reconstruction• Maximum Pixel Rate• Main Video Stream Format
Change Handling
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Compliance Test Specification: A Phy CTS Test:
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Testing the Source
These are the conditions that need to be tested for compliance.Optional configurations are demoted w/red x’s.Red test labels are informative tests and are NOT required.
Example: Test 3.2: All data rates, lanes and levels that apply to your DUT must be tested. Pre-emphasis is OFF for this test
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Compliance Test Specification: Sink TestingStressed Eye oriented
Fixed Level
Jitter components: --Inter Symbol-
Interference
--Sinusoidal Jitterswept.
JTHBR Curve And Compliance Test Points(Taken From DP1.1 Spec)
2 MHz
10 MHz20 MHz 100 MHz
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Characterization/Validation Tasks
Measure
Test(Parameter to
Measure)
Set DUT condition
Instrument Configuration
Bit RateLaneLevelSSCPre-Emphasis
SignalMeas. Type
Pass/fail constraintsReporting
DisplayPortCTS
(# Parameters) x (# Modes) => Many Measurements Cutting corners is tempting – DON’T DO IT!
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Requirements for Test Instrumentation
• The instrument must understand the spec before beginning testing
• CTS and Specification knowledge must drive test selections
• Automated sequencing thru selected tests, prompting for setup changes as necessary
• Clear, test specific, easy DUT configuration
• Benefits:
• Speedy test execution enables 100% coverage – no need to “reduce” the test matrix if test time or resources are limited
• Automatic setup assures accurate measurement– Assures working products are correctly certified as compliant
Page 28
DisplayPort Source Testing
DSO90000A Infiniium Oscilloscopes
U7232A DisplayPort Compliance Test SW
W2641A DisplayPort Fixture
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New Version of Code (U7232A V1.5 and higher)
Enables Flexible TestingC.T.S Testplan
One Condition at a time
User Defined conditions
Compliance conditions only
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Leverage to the Design and Debug ProcessEqualization of cable end signal.
Degraded Eyedue to 5m cable
Equalized Eye
Useful for Receiver Equalization evaluation or Sanity check
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Leverage to Debug Process: Jitter Analysis
A
B
B
A
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Leverage to Debug: Eye Diagram Analysis
Alternating Pattern
w/PRBS7 Pattern
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Pre-Emphasis and Qualified Triggering
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DisplayPort Sink Test Solution
W2641A
N4903A or 81250A BERT Systems
ManualMOI Posted
12/04
Cable Emulator
5/15
N5990A opt155
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DisplayPort Sink Testing
Sink Device
DP RxGUI of N4903ATable of CTS
Back Channel
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Sink Testing w/N4903A
Pattern Setup
Jitter Setup
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Instrument-Based Specification Driven Testing
Tx Test
Media Test
Rx Test
DP CTS
Specification and CTS knowledge built into the instrument
Page 38
DisplayPort Support Overview
• Source Test
• Sink Test
• Cable/Connector/Interconnect Test
Compliance Test
86100C Digital Communications Analyzer
E5701A Vector Network Analyzer
N4903A J-BERT81250A Par-BERT
DSO80804BRealtime Oscilloscope
U7232AComplianceSoftware
Page 39
Agilent DisplayPort Standards Activities
• VESA member
• Editor of DisplayPort Compliance Test Specification
• Participant in initial private & public plugfests.
• Active collaboration with lead DisplayPort architects
Page 40
Summary
DisplayPort is definitely on its way!
DisplayPort enables better margins.
DisplayPort links are dynamic.
Compliance Testing is beginning to show a rigorous posture.
Agilent has broad product offering to support development and validation of DisplayPort designs.
Page 41
Additional Resources
DisplayPort information
www.agilent.com/find/displayport
www.displayport.org
Signal Integrity information:
www.agilent.com/find/si
