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1 1 Agilent Press Briefing ITC 2001
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Agilent Press BriefingITC 2001
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Agenda• Agilent - SmarTest Program Generator and
Synopsys - TetraMAX Demo
• Agilent - Concurrent Test Demo
• Agilent displays solution to meetmanufacturer's challenges
R
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Synopsys / Agilent Demo at ITC 2001Tester-aware EDA/DFT:IEEE P1450.6/CTL compliant description of the Agilent 93000 is provided as input to Synopsys’ Tetramax.
Benefit: Tester-rule checking can take place during EDA, minimizing debugging and virtual tester simulation.
EDA/DFT-aware ATE:IEEE 1450/1999 compliant input to SmarTest PG
Benefit: Program Generation knows the tester configuration for which the patterns were generated
Directly loadable 93KTest Program
CTL
STIL
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The Agilent / Synopsys Partnership
...in making design tools and testers work together
...through standards-based: - ATE-aware EDA/DFT tools- EDA/DFT-aware ATE tools
…by simultaneously:- lowering the cost-of-test - reducing time-to-market
Lead the Industry…
…others will follow
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Streamlined Agilent 93000 SOC Test Generation for:
- Fastest time-to-volume
- Lowest cost-of-test
Agilent SmarTest Program Generator
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Test Program Generation Stage: A Strategic Position to Tackle Key Issues
Effort applied
atTest Program Generation
Overall
Effort
Needed
Design Test
Timeto Market
Cost
of TestMuch less effortrequired to tackle COT & TTM if applied at DFT
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SmarTest PG Streamlines the Test Program Development Process
Without SmarTest PG
With SmarTest PG
AWKScript
EDA
Data Translation
Cyclization
VI Editor(Data View
& Editing)Pin MappingManual
Data EntryData
Extraction
AWKScript
EDA Data Extraction
Setups Cyclization View Resultsand Adjust
DirectlyLoadableOutput
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SmarTest PG makes the Agilent 93000 Family “Design Ready”
P600
P800
P1000
C400e
C300e
.wgl .vcd
STIL (Q3 ‘02)
Mentor
Synopsys
Internal
Cadence
EDASystems Agilent
93000
Family
SmarTest Program GeneratorDirectly Loadable
Output
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SOC Development Process
Design
Scan Vectors
BIST IP
STIL/
WGL SmarTest Program
Generator
Agilent93000SOC
Series
EDA
Simulation
Place/Route
RTL
SynthesisATPG
Functional Test VectorsSTIL /
VCD
Pin Configuration & other design data
Tester Simulation
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Agilent SmarTest Program GeneratorClosing the Loop Between Design and Test
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Concurrent Test
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Business Trends
• Shrinking product life cycles, product life and profit margins
• Increasing competition• Supply chain fragmented• Industry moving from TTM driven to • TTV driven
Device Trends
• Faster speed, more complexity• Increased cost-of-test as a % of mfg. cost• SOC design methodology begs for test
reuse and more DFT• Sub-micron technology increases
availability of real estate for DFT• System in a Package
Industry Needs•Reduced test development time to shorten life cycles and free upengineering resources
•Reduced test costs as a % of manufacturing cost to maintain and increase profit margins
Semiconductor Industry Drivers
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ConcurrentConcurrent Testing:Testing:An Effective Method for Reducing the CostAn Effective Method for Reducing the Cost--ofof--TestTest
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Concurrent Test Leverages Trends in the Industry
ConcurrentTest
Common IP Libraries
Custom Design, Proprietary Gate Libraries
Flexible ATE, Tester Per Pin
Dedicated ATE,Shared Resource ATE
DFT Methods and IP Integration Standards
Ad Hoc TestImplementation
Design to Test Links,EDA/ATE vender cooperation
Proprietary Design and Test Development Tools
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Agilent’s Tester Architecture for Concurrent TestingPer-Pin Architecture
– unrestricted port configuration with single pin granularity– matches the device-under-test’s pin-out (test mode and mission mode)
Test Processor-Per-Pin– independent period, timing, levels,
pattern and sequencing per-pinUniversal Pin Concept
– each tester pin can operate in differentmodes (SCAN, BIST-Control,functional, …) for every test
Port Synchronization– phase-synchronous operation for interdependent ports– uncompromised OTA spec between ports
Logic Core
CPUIP 2
IP 1
SCANPORT 1
S(D)RAM Flash
BISTPORT 2
PORT 3
Mixed Signal
DAC
ADC
CODEC
PORT 4
ANALOG
SOC Port 4
Clock
AnalogPort 3
Port 2
Port 193000
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Eliminates Tester-Related Design Constraints
Embedded IP cores may havecompletely different natures :
–Operation frequency–Supply voltage–Pattern generation algorithms
ATE equipment must be able to deal with this variety of performance features contained in a single chip.
The 93000’s Per-Pin ATE Architecture is Mandatory
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Accelerated Time-to-MarketIP core test re-useStraightforward cyclization of “fractional busses”Scan chain balancing for multiple clock domains
Improved Test CoverageMission mode/structural test pattern mixingInterface testing at mission mode frequency ratios
Agilent’s Concurrent Test Can Also Deliver...
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Concurrent Test
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Semiconductor Manufacturers’ Challenges
Improved Utilization
Improved Communication Across the Supply Chain
Lower Test Costs
Time to Volume & Test Development
2020
Booth
93000 with RF - Display the RF Measurement suite for the Agilent 93000 SOC Series
93000 Mixed Signal Test - Display the mixed signal test examplesespecially for digital consumer devices such as DVD/CD,STBand ADSL on the Agilent 93000 SOC Series
93000 NP2500 - Display the latest high-speed models, which run up to 2.5 Gbps on the Agilent 93000 SOC Series
93000 Jitter Verification - Display how jitter and jitter verification arekey parameters in determining the performance of high-speedcommunications devices, such as SerDes, SONET, Gigbit and Ethernet on the 93000 SOC Series
93000 YieldPro Contactor - Display the capability to accessleaded/leadless (BGA, CSP, BBC, LCC etc… ) contactsin a reliable and accurate fashion at high speed
93000 Load/interface boards - Display how board solutionscan benefit greatly from breakthrough in Load boarddesign and fabrication technologies to achieve the highest level of accuracy
Versatest V4400 - Display the scalable performance of the V4400 that will allow the customer to choose threedifferent performance grades (40/70/100)
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Agilent 93000 SOC Series
FOR ALLMODELS!
PRIC
E
PERFORMANCE
C200eC200eC400eC400e
Ce-ModelsCe-Models P600P600P800P800
P1000P1000NP1700NP1700
NP2500NP2500P-ModelsP-Models
NP-ModelsNP-Models
Buy today, upgrade tomorrow!Buy today, upgrade tomorrow!
PCT3600PCT3600
RF Measurement
Suite
RF Measurement
Suite
Wide Rangeof Analogmodules
Wide Rangeof Analogmodules
The last test platform you’ll ever need to buy
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• Up to 2.5 Gbps, True Differential• For up to 256 ports• Native Source Synchronous support• Jitter measurement throughput of 10 ms/port• Superior retiming architecture for jitter of < 5 ps
NP-ModelsNEWNEWNEW
Agilent 93000 SOC SeriesComputation & Wired Communications
2323
NP2500for
Engineering Measurements at Production Throughput!
NP2500for
Engineering Measurements at Production Throughput!
Rapid IORapid IORapid IO
Manyothers...
ManyManyothers...others...
EmbeddedSerDes
EmbeddedEmbeddedSerDesSerDes
InfiniBandInfiniBandInfiniBand
HyperTransportHyperTransportHyperTransport3GIO3GIO3GIO
Agilent 93000 SOC Series - NP2500Overcoming the Challenges of Ultra High Speed I/O Test
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•Up to 12 RF ports•3 GHz modulated source(s)•8 GHz measure•Multi-tone stimulus•Frequency hopping•Quad-site•Real-time RF data processing•Real-time BER measurements•Fast switching sources
Less than 7 second test time for quad-site test of SiW1502™ Bluetooth Radio Modem IC — demonstrated July 2001.
Available TODAY !
The SiW prefix is a trademark of Silicon Wave, Inc.
RF Measurement Suite for Bluetooth Test
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Riaz ChaudhryVice President Semiconductor Operations
”We recognize Agilent as a leader in wireless test.As a result, we feel very confident that the 93000 will help us achieve our goals of providing high-performance Bluetooth solutions that consistently
deliver a superior user experience.”
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Enhancing the RF Measurement Suite to address challenging requirements of leading edge WLAN standards.
Enhancements Include:– 6 GHz modulated source(s)– New, wider bandwidth RF receiver - 40 MHz IF bandwidth– OFDM modulation– Error Vector Magnitude (EVM) Measurements
Upcoming EnhancementsRF Measurement Suite
Showing July 2002 !
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Agilent Versatest Series Memory Test SystemContinually Lowering the Cost of Test
•• Tester Per Site Architecture Tester Per Site Architecture •• Highest ThroughputHighest Throughput
•• Flash Test ExpertiseFlash Test Expertise•• Lowest Cost of TestLowest Cost of Test
V1300V1300V1100V1100
V1000V1000
V3300V3300V2100V2100
V1200V1200
V3300ADV3300AD
Value Value LineLine
PerfPerfLineLine
Time
Perf
Tester Per Site Roadmap Enabling Cost of Test Reduction
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Agilent Versatest Series Model V4400Provides lowest Cost of Test by increased
throughput, accuracy and parallelismCapable of testing discrete, burst mode and embedded flash devices with speeds up to
100MHz (200Mhz in MUX mode) Able to test up to 36 sites in parallel
Provides the flexibility to combine 8 sites into a single super-site in Master-Slave mode to
test up to 512 pin count devicesShortens program development time through
powerful APGIncreases reliability through elimination of
mechanical relays in signal path and Agilent 3rd generation water cooling techniques
Reduces floor space requirements: Typical Test Cell with TEL P8XL = 28 ft2 (2.6 m2)
Introduced last yearITC 2000!
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'99 '00 '01 '02 '03 '04
A Continuing Family of Testers
40 MHz
70 MHz
100 MHz
• SW Compatible• Upgradeable• Optimized Cost of Test
Agilent V4400Agilent V4400V4400/F70
V4400/F40
V4400/F100
Latest Family MembersLatest Family Members
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Scalable Performance- Speed- Accuracy- Buffer Memory/Error Catch Ram- Vector Memory- Number of Test Sites- Number of Pins per site
Scalable PerformanceV4400/F40, F70, F100
The V4400 can be configured along three dimensions to provide the
optimal configuration for our customer’s needs
Scalable Cost of Test
Scalable Cost of Test Flexible Applications
Flexible Applications
Scal
a ble
Per
form
ance
Scal
a ble
Per
form
ance
Scalable Cost of Test- Multiple price entry points- Upgradeability
Flexible Applications- NAND and NOR- Wafer sort, speed-at sort- Embedded Flash - Hi-mix- Sync Flash
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