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Alcatel-Lucent OmniPCX EnterpriseCommunication Server
DPT1
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Legal notice:
Alcatel, Lucent, Alcatel-Lucent and the Alcatel-Lucent logo are trademarks ofAlcatel-Lucent. All other trademarks are the property of their respectiveowners.
The information presented is subject to change without notice.
Alcatel-Lucent assumes no responsibility for inaccuracies contained herein.
Copyright © 2013 Alcatel-Lucent. All rights reserved.
The CE mark indicates that this product conforms to the following CouncilDirectives:- 2004/108/EC (concerning electro-magnetic compatibility)- 2006/95/EC (concerning electrical safety)- 1999/5/EC (R&TTE)
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Chapter 1Hardware description
Presentation ............................................................................................. 1.1
Environment ............................................................................................. 1.1
Functional blocks ................................................................................... 1.2
List ................................................................................................................. 1.2
Blocks description .......................................................................................... 1.3
Chapter 2Hardware configuration
Reference .................................................................................................. 2.1
Presentation ............................................................................................. 2.1
Strappings ................................................................................................ 2.1
Meaning of the LED ............................................................................... 2.2
Display ........................................................................................................... 2.2
Meaning ......................................................................................................... 2.3
Cadencing ..................................................................................................... 2.3
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Chapter 3External connections
Connection ............................................................................................... 3.1
Output pins ............................................................................................... 3.2
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1.1 Presentation
The DPT1 (Dual Port T1) board authorises the connection of 2 primary T1 access to the publicnetwork.
There are two modes of interface for connection to the network:
- short line (short haul DSX1): connection through a termination unit (200m max),
- long line (long haul DS1): direct connection (2Km max).
The configuration of the DPT1 board is described in DPT1 - Hardware configuration .
The connection of the DPT1 board is described in DPT1 - External connections .
1.2 Environment
Figure 1.1: DPT1 board inputs/outputs diagram
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1.3 Functional blocks
1.3.1 List
The DPT1 board is structured around the following functional blocks:
- processor part,
- backpanel interface part,
- T1 interface,
- signalling detector (Q23),
- gain adjustment,- supervision interface,
- power supply.
Chapter 1
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Figure 1.2: DPT1 board functional summary diagram
1.3.2 Blocks description
1.3.2.1 Processor part
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This part manages the different DPT1 board blocks. It contains:
- an MC68360 micro-controller operating at 25 MHz,
- 256kb external RAM,
- 512kb FLASH EPROM.
1.3.2.2 Backpanel interface part
This interfaces the DPT1 board with the other system boards. This part is composed of:
- a C1 circuit,
- a clock reception and generation block.
1.3.2.3 T1 interface module
The DPT1 board supports 2 T1 accesses. Each interface is composed of the following parts:
Figure 1.3: T1 interface
These interface have the following properties:- multi-frame accepted: SF (Super Frame:12 frames) and ESF (Extended Super Frame: 24
frames),
- short lines (short haul), long lines (long haul),
- B8ZS or AMI modulation with ZCS code,
- change of bit rate from 1544Khz to 2048khz and from 2048Khz to 1544Khz,
- DL channel controller (supervision channel),
- robbed bit extraction,
- alarm supervision and generators,
- data looping,- possibility of stopping the bit robbing,
- microprocessor interface (Motorola type),
- extraction of a synchronous clock with T1 data.
1.3.2.4 Signalling detector
The block processes the DTMF(Q23) and BTD signalling.
(DTMF: Dual Tones MultiFrequencies, BTD: Busy Tone Detector).
The signalling detector is composed of a DSP (Digital Signal Process) (TMS320LC54x)
Chapter 1
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This part is supplied with 3.3V.
1.3.2.5 Gain adjustment
The TRIMMER ASIC adjusts the audio level of each channel. =
1.3.2.6 Supervision interface
This carried out the following three functions:
- Led interface,
- Synchronisation or non-synchronisation of the system with the T1 data flow,
- Synchronisation of the board.
1.3.2.6.1 Led interface
The led interface controls 10 leds. 8 display the T1 link alarms (LOS, AIS, RAI and LFA foreach T1 interface. The other 2 give the operating status of the board (CPU, BSY) (see DPT1 -Hardware configuration ).
1.3.2.6.2 System synchronisation
Each of the two interfaces may or may not supply a clock (512 KHz). Transmitted via thebackpanel to the CPU, it is used to synchronise the system's PLL.
1.3.2.6.3 Board synchronisation
Like all the interface boards, this receives three system clocks:
- 16 MHz: 4 x the bit rhythm,- 8 kHz: frame synchro
- 256 kHz: clock for switching power supply.
1.3.2.7 Power supply
From the 48V, the CM40R convertor supplies the board with the necessary voltage (+5V,+3.3V and +12V).
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Chapter 1
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2.1 Reference
DPT1 board reference : 3BA 23164 AA
2.2 Presentation
The diagram below gives the position and number for each strap present on the DPT1 board.
Figure 2.1: View of the DPT1 Board
2.3 Strappings
The ex-factory strappings are shown on a grey background.
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2.4 Meaning of the LED
2.4.1 Display
The DPT1 board has 10 LED located on the front panel.
Chapter 2
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Figure 2.5: DPT1 Board Front Panel
2.4.2 Meaning
table 2.1: Summary
LED Meaning
CPU (green LED) CPU activity indicator
BSY (orange LED) Activity indicator of at least one trunk
AIS (INT1) (blue LED) Alarm Indication Signal INTerface 1 (The incomingsignal has become an unframed bit stream with con-stant “1”)
RAI (INT1) (yellow LED) Remote Alarm Indication INTerface 1(The distant lineend signalizes an alarm)
LOS (INT1) Loss Of Signal INTerface 1 (Input signal has an insuf-ficient density of ones)
LFA (INT1) Lost of Frame Alignment INTerface 1 (After detectingincorrect frame alignment, the line is out of synchron-ization)
AIS (INT2) (blue LED) Alarm Indication Signal INTerface 2 (The incomingsignal has become an unframed bit stream with con-stant “1”)
RAI (INT2) (yellow alarm) Remote Alarm Indication INTerface 2(The distant lineend signalizes an alarm)
LOS (INT2) Loss Of Signal INTerface 2 (Input signal has an insuf-ficient density of ones)
LFA (INT2) Lost of Frame Alignment INTerface 2 (After detectingincorrect frame alignment, the line is out of synchron-ization)
2.4.3 Cadencing
table 2.2: CPU LED
Cadencing Meaning
ON fixed Initialization in progress
100 ms (ON)/ 1s (OFF) Loading in progress
10 ms (ON)/ 10 ms (OFF) Re-flashing boot
300 ms (ON)/ 300 ms (OFF) CPU wait
8 x (900 ms (ON)/ 600 ms (OFF))/1s (OFF)
RAM Test error
8 x (300 ms (ON)/ 600 ms (OFF))/1s (OFF)
Checksum error
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Chapter 2
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3.1 Connection
The DPT1 board is plugged into an interface position on the ACT shelf.
Figure 3.1: Connection diagram
If the connection is :
- by cable : in this case, the connection to the distribution frame is carried out using a DPT1cable (seeDPT1 cable - Hardware description ) or a DPT1/RJ45 cable (see DPT1 RJ45cable - Hardware description ).
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- by patch panel (VH cabinet only) : in this case, the connection is carried out using the
patch panel : 16-port, 4-wire module (see Patch Panel - 16 ports module - 16 ports module).
3.2 Output pins
Backpanel rear side view
C B A REMARKS
1
2 L1RING L1TIP
3 L1RING1 L1TIP1
45
6
7 GND
8 GND
9 GND
10 L2RING L2TIP
11 L2RING1 L2TIP1
12
13
14 L2RING1 L2TIP1 Double output points given theconnection to a VH
15 L2RING GND L2TIP
16 GND
17
18
19
20
21
22
23 GND
24 GND
25 GND
26
27
28
Chapter 3
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Backpanel rear side view
C B A REMARKS
29
30 GND
31 GND
32 GND
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Chapter 3
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