Algorithm Development Using Model-Based Design

Eric Cigan

MathWorks

Model-Based Design

2

A single shared development environment

Model-Based Design

3

A single shared development environment

Verify operation before committing to hardware

Validate performance on chip

Deploy design on target system

IMPLEMENTATION

Model-Based Design Workflow for Altera SoCs

INTEGRATION

Ve

rifica

tion

ARM Cortex-A9 Programmable Logic

IP Core Generation

with HDL Coder

Build Executable

with Embedded Coder

C code

generation

HDL code

generation

DESIGN

RESEARCH REQUIREMENTS

System Modeling

Algorithms for

ARM core

Algorithms for

programmable fabric

Hardware/Software Partitioning

Software

design

iteration

Hardware

design

iteration

User defines

partitioning

Workflow automates

code and interface-

model generation

Workflow automates

the build and

download through

the Altera tools

SoC Design Challenge

ARM®

ProcessorC-Code

Software

InterfaceFPGAHDL Code

Hardware

SoC Design Challenge

ARM®

ProcessorC-Code

Software

• Typically programmed in C

• Often runs a Linux operating system

• Well-established workflows exist

CHALLENGES

• FPGA Designers not familiar with programming processors

• What should run on the processor vs. the FPGA?

SoC Design Challenge

FPGAHDL Code

Hardware

• Typically programmed in VHDL/Verilog

• Established workflows exist

CHALLENGES

• DSP/Processor programmers not familiar with FPGA Design

• What should run on the FPGA vs. the processor?

SoC Design Challenge

Interface

• Altera SoCs use “standard” AXI interface between

FPGA and ARM

CHALLENGES

• No established rules for hooking up the interface

• Many different “flavors” of AXI for different bandwidth

requirements

SoC Model-Based Design Workflow

SoC Model-Based Design Workflow

FPGAHardware

AXI AXI

ARMSoftware

IP Core Workflow

HDL IP Core

Generationusing

HDL Coder

MATLAB and Simulink

Algorithm and System Design

Simulink Model

Testbench

HW

AXI Lite

Accessible

Registers

Algorithm

From

MATLAB/

Simulink

External

Ports

IP Core

Generation

IP Project

AX

I 4

Memory/

Control

Programmable Logic IP Core

Algorithm

from

MATLAB/

Simulink

AXI Lite

Accessible

Registers

AI

External

Ports

IP Core Workflow

Embedded System

Integration

FPGA Hardware

FPGA Bitstream

MATLAB and Simulink

Algorithm and System Design

HDL IP Core

Generationusing

HDL Coder

Embedded System

Integration

AXI4

Accessible

Registers

Algorithm

From

MATLAB/

Simulink

External

Ports

SoC Model-Based Design Workflow

SW Interface

Model Generation

Simulink Model

SW

HW

SW Interface Model

SW

SW I/O

Driver

Blocks

SW Interface

Model Generation

MATLAB and Simulink

Algorithm and System Design

Embedded System

Integration

Altera SoC Platform

FPGA Bitstream

HDL IP Core

Generation

using

HDL Coder

SoC Model-Based Design Workflow

SW Interface

Model Generation

SW Build

using

Embedded Coder

MATLAB and Simulink

Algorithm and System Design

Embedded System

Integration

Altera SoC Platform

FPGA Bitstream

HDL IP Core

Generation

using

HDL Coder

External Mode

PIL

• Real-time Parameter

Tuning and Verification• External Mode

• Processor-in-the-loop

SW Build

using

Embedded Coder

SW Interface Model

SW

SW I/O

Driver

Blocks

SoC Hardware/Software Workflow Summary

Embedded System Project

Simulink Model

SW

HW

DesignIP Core

Generation

FPGA IP Core

Algorithm

from

MATLAB/

Simulink

AXI Lite

Accessible

Registers

External

Ports

AX

I4 B

us

Processor

Em

be

dd

ed

Syste

m

Inte

gra

tio

n

FPGA IP Core

Algorithm

from

MATLAB/

Simulink

AXI Lite

Accessible

Registers

External

PortsGenerate SW

Interface Model

SW Interface Model

SW

SW I/O

Driver

Blocks

FPGA

BitstreamSW

Build

Target Platforms Supported with Model-Based Design for Altera SoCs

16

Altera Cyclone V SoC Development Kit

Arrow SoCKit

Custom Cyclone V SoC boards

Adding Support for Custom Altera SoC Boards

and Reference Designs

MATLAB

Search

Path

Board plugin

Registration file

+AlteraCycloneV

Board definition file

+ArrowSoCKit

Board definition file

+user_custom_board

Board definition file

Reference Design plugin

Registration file

+qsys_base_131

Registration Design definition file

+qsys_base_140

Registration Design definition file

+user_custom_project1

Reference Design definition file

Extensible Board and Reference Design definition

Reference Design Example

ARM

CPU

AXI Bus

A/D

IP

D/A

IP

PCIe

IP

DDR

IP

ALGORITHMIC

IP

Summary and Next Steps

19

Altera SoC workflow support from MathWorks: Enables combined hardware/software code generation

Provides predefined support for on Altera SoC and Arrow SoCKitdevelopment boards, and can be extended to other SoC boards.

Learn more about Model-Based Design for Cyclone V SoCs

Visit http://www.mathworks.com/asdf

Visit mathworks.com/alterasoc

Contact us at altera@mathworks.com for instructions on how toget this workflow.

Watch Altera/MathWorks webinar

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MATLAB and Simulink Features targeting field-oriented control algorithm into Altera’s

Drive-on-a-Chip Reference Design