Ali Javey, SungWoo Nam, Robin S.Friedman, Hao Yan, and Charles M. Lieber

Ting-Ta Yen

Semiconductor NWs and CNT are potential materials for future electronic components.

They are usually chemically derived single-crystalline nanostructures.

Advantage over conventional semiconductors: 1. Enable integration of high-performance device elements onto any substrate. 2. Scaled on-currents and switching speeds are higher than planar Si structures. 3. Intrinsically miniaturized dimensions. 4. Facilitate the continuation of Moore’s law and quest for faster and smaller electronics. 5. Capability of assembling high-performance NW building blocks (3D integrated electronics).

In planar Si technology, it has been difficult to achieve 3D integrated structures, due in part to materials-related challenges associated with the need of high-temperature process to produce single-crystalline silicon.

So…. Monolithic integration of individual and parallel arrays of crystalline

NWs as multifunctional and multilayer circuits. 10 addressable vertical layers. Through both “bottom-up” and “top-down” hybrid methodology. Higher temperature materials growth is independent of the low

temperature assembly and fabrication steps.

How to assemble and control orientation and density at spatially defined locations on the device substrate?

Contact printing of NWs from growth substrate to prepatterned chip substrate.

Although NWs are grown with random orientation, they are well-aligned by sheer forces during the printing process.

3D NW circuits are fabricated by the iteration of the contact printing, device fabrication, and separation layer deposition steps N times.

Low processing temperature required.

NWs were printed by sliding a growth substrate consisting of a “lawn” of Ge/Si core/shell NWs (d~15nm, l~30μm), against a device substrate (Si/SiO2 or Kapton).

Prior to transfer, the device substrate was patterned with a photoresist layer (~500nm) for two purposes:

1. To prevent transfer of particles and low-quality NW material close to the surface of the growth chip 2. To enable selective assembly of the NWs at defined locations The sliding process results in the direct and dry transfer of

NWs from the growth substrate to the desired device substrate chip.

After transfer, PR is removed in acetone, leaving only patterned NWs, which are well-aligned along the sliding direction.

Using printed Ge/Si NW heterostructures (~10nm thick core with ~2μm shell) as channel material. (Ge/Si were congifured as top-gated devices.)

NWs are cleanly printed only at lithographically predesigned locations.

Contact printed NWs are aligned and uniform across large length scales (~mm scale).

NWs are assembled with high density (~4NW/ μm).

Consisting of 10 layers of Ge/Si multi-NW FETs on a Si substrate.

The 3D NW FET structure exhibits consistent layer-to-layer electrical properties with on-currents of ca. 3 mA and maximum transconductance, gm, of ca.1 mS.

Vertically stack these layers without performance degradation. On-current can be readily scaled simply by adjusting the

device width and NW density.

Low Ge/Si NW density growth substrates were used for the contact printing step in order to reduce the density of transferred NWs.

Much narrower 1μ width S/D electrodes were used to ensure a high yield of single-NW device.

ION ~10 μA and Vds ~1V. Scaled Ge/Si NW FETs afford diameter-normalized ION(2.1

mA/ μm) and gm(3.3 mS/ μm) are both better than state-of-the-art planar Si technology.

Fabricated on flexible plastic substrate (Kapton). Lower layer: PMOS inverters (load + switching FET) Upper layer: floating gate memory elements (FET + floating gate)

DC inverter characteristics (quasi-DC gain = 3.5) AC inverter characteristics (gain is greater than unity at 50 MHz) Hysteresis in current-voltage characteristics of a memory

element (large and reproducible hysteresis loop) Switching characteristics of memory (writing & erasing operation result in well-defined and nonvolatile

ON and OFF states transitions)

Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer.

FET characteristics are not affected by sequential stacking. 3D circuitry can be demonstrated on plastic substrates. The ability to assemble reproducibly sequential layers of

distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.

Thank you !