All Programmable Technologies in AcademiaCyber security challenge to critical infrastructure...

© Copyright 2013 Xilinx .

Patrick Lysaght

Senior Director

All Programmable Technologies in Academia


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Agenda

Xilinx: a Generation Ahead at 28nm

The “Industrial Internet” ~ aka The Internet of Things

Academia in Transition

The “Post-PC” Era

~ The rising importance of embedded SOCs

ZED: Zynq®-7000 All programmable SoCs in Education

Vivado® Design Suite: a CAD suite for All Programmable

Systems


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A Generation Ahead at 28nm

28nm

Portfolio: All Programmable FPGAs, SoCs and 3D ICs today

Product: Extra node of performance, power and integration

Productivity: Unmatched time to integration and implementation

Xilinx at 28nm


The First System Optimized FPGAs

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Scalable and System Optimized Architecture

In production now

Virtex-7 2x bandwidth & capacity, 35% power, SerDes

Kintex-7 35% power, 45% faster logic, 2x DSP

Artix-7 15% faster and $5-$10 lower system BOM

FPGAs


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The First All Programmable 3D IC

7V2000T in production now

2x capacity, 2x bandwidth

4x more 28Gbps SerDes channels

Only programmable homogeneous and heterogeneous 3D IC

Volume ramped significantly in Q2, 2012


Highest bandwidth FPGA with 2.78 Tb/s serial

connectivity

Electrically-isolated 28G transceivers for optimal

signal integrity

Heterogeneous Integration

Different silicon

processes

Passive interposer

Homogeneous

digital logic

Noise isolation

28G

Transceivers

28G

Transceivers

13G

Transceivers

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Page 7

The First All Programmable SoC

All devices in production now

>25% ARM performance, 45% logic performance

Highest productivity with Vivado HLS, ARM ecosystem

All Major OS’s supported and in use, 20 unique dev boards

350+ Customers actively designing,100+ partners

Shipped 20,000 devices, 4000 development boards


The First SoC Strength Design Suite

In production now

Built from the ground up for the next decade of devices

Now used for ~50% of 28nm designs, 100% of 3D ICs

Delivering 4x productivity, turning months to weeks

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Industry Mandates

Programmable

Imperative

Programmable

Systems

Integration

Insatiable Intelligent Bandwidth

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Insatiable Intelligent Bandwidth

We Will Soon Live in a 100 Gb World

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Overall IP Traffic

in exabytes per month:

CAGR 29%


IPV6 enables Dramatic M2M Growth

Source: The Zettabyte Era,

Cisco VNI: Forecast and Methodology, 2011-2016

120.5% CAGR in Machine-to-Machine traffic starting from 2012

IPv6-Capable Fixed Devices by Device type, in Millions, 2011-2016


The Internet of Things

http://www.cisco.com/web/about/ac79/docs/innov/IoT_IBSG_0411FINAL.pdf

The internet of

things was born

between 2008

and 2009

when for the first time

more “things or objects”

were connected to the

Internet than people

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The “Internet of Things”, is “the general idea of things, especially

everyday objects, that are readable, recognizable, locatable,

addressable, and controllable via the Internet …”

US National Intelligence Council

Today, more than 20 percent of Internet traffic originates from non-

computing devices

Predictions are that by 2020, as many as 50 billion machines will be

plugged into the Internet

Tremendous opportunities for multi-disciplinary teaching research in

networked, embedded systems

IOT ... an Internet dominated by networked

“things” (not PCs, cell phones and tablets)

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Re-target Internet technologies for the benefit

of big industry

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Source: Industrial Internet: Pushing the Boundaries of Minds and Machines

Peter C. Evans and Marco Annunziata, GE, November 26, 2012


Scale up the vision on a grand scale …

and we get the “Industrial Internet”



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Illustrative Classes of Large Rotating Machines

aka “Big Things that Spin”

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Motivation: “The power of 1%”

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These opportunities have their doppelgängers …

Cyber security challenge to critical infrastructure

Shortage of high-quality electricity for exploding data center

demand

Challenge of energy-efficient, high performance computing

– Especially high performance, embedded computing

Immediate skills shortage

– From “digital mechanical engineers” to the data analytics scientists

The Merger of Industrial Revolution and Internet

Revolution is a Complex Vision


Meanwhile, Academia is in Transition …

Prof John Hennessy, President of Stanford University,

says that this change is due to the “coming tsunami in

educational technology”.

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Agents of Change in Educational Technology

New delivery formats

– edX, Coursera, Udacity

– Khan Academy,

Codeacademy

Broadband Internet

Video everywhere

– YouTube

E-Books

Printing-on-Demand

Search engines, etc

– Google, Wikipedia

Social media

– Peer interaction &

learning

Open Source

– Software & textbooks

Rapid curriculum expansion

– Especially in electronics

& computing

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Universal mobility & connectivity

The Internet of people is expanding to the “Internet of things”

Computing has become an immersive, connected experience

The “Cloud” underpins the mobile experience

Embedded systems using systems-on-chip (SOC) are the key

technology enabler of the Post-PC era

– They are drivers for major changes in engineering education

Characteristics of The Post-PC ERA

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The PC is not dead – it remains a powerful tool for more

competent users

But non-PC, consumer, electronic devices proliferate

– These devices have more specialized functionalities and more intuitive

interfaces, for example smart phones, tablets, E-readers, HDTVs

– Embedded heterogeneous SOCs will drive of the Industrial Internet

The curriculum in Electronics and Computer Engineering must

change to meets the need to teach and research the challenges

of engineering of SOCs in embedded systems

Enabling Post-PC ERA Engineering Education

Education for SOC Engineering is Vital

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Coping with curriculum expansion driven by the rise of SOC

technology in embedded systems in the post PC era

Educating a generation of engineers in systems design and

integration

Educating students to understand and practice design re-use by

using third-party IP and designing for re-use by creating their

own re-usable IP

Introducing High-level Synthesis from traditional software

programming languages such as C, C++, SystemC

The Emerging Educational Challenges

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An Image Processing Example

The Back Projection algorithm is

used in variety of tomography

applications, including CAT

scanners

Takes raw data from a scan at

different angles and reconstructs

an image based on that data

From Datasets re-construct the

image 256

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Complete Design Consumes 2 Watts !!!

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Accelerator

AXI_DMA

m m

m

s

AXI_DMA

m m

m

s

m

s

m

s

AXI4 Lite interconnect

s s

AXI4 interconnect

s s

m ACP

Accelerator

ACP

HDMI

Output

m

Memory

256 KB On-Chip Memory

Snoop Control Unit (SCU)

DMA Configuration

512 KB L2 Cache

Timers / Counters

General Interrupt Controller

Cortex™-A9 MP Core™

32/32 KB I/D Caches

NEON™/FPU Engine


32/32 KB I/D Caches

NEON™/FPU Engine

ARM® CoreSight™ Multi-core & Trace Debug

AMBA® Switches


The Next Step: “Design for Re-use”

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Accelerator

AXI_DMA

m m

m

s

AXI_DMA

m m

m

s

m

s

m

s

AXI4 Lite interconnect

s s

AXI4 interconnect

s s

m ACP

Accelerator

ACP

HDMI

Output

m

Memory

256 KB On-Chip Memory

Snoop Control Unit (SCU)

DMA Configuration

512 KB L2 Cache

Timers / Counters

General Interrupt Controller


32/32 KB I/D Caches

NEON™/FPU Engine


32/32 KB I/D Caches

NEON™/FPU Engine

ARM® CoreSight™ Multi-core & Trace Debug

AMBA® Switches

These are the only new IP blocks

in the design


Complete ARM®-based Processing System

– Dual ARM Cortex™-A9 MPCore™, processor centric

– Integrated memory controllers & peripherals

– Fully autonomous to the Programmable Logic

Tightly Integrated Programmable Logic

– Used to extend Processing System

– High performance ARM AXI interfaces

– Scalable density and performance

Flexible Array of I/O

– Wide range of external multi-standard I/O

– High performance integrated serial transceivers

– Analog-to-Digital Converter inputs

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Zynq-7000: ALL PROGRAMMABLE Platform for

Post-PC Era Engineering Education

Best-in-class Embedded Processing and FPGA Technologies

7 Series

Programmable

Logic

Common

Peripherals

Custom

Peripherals

Common Accelerators

Custom Accelerators

Common

Peripherals

Processing

System

Memory

Interfaces

ARM®

Dual Cortex-A9

MPCore™ System


ARM is the world’s leading semiconductor IP company

800 processor licenses sold to more than 250 companies

Over 20 billion ARM based chips shipped to date

Two billion chips based on ARM RISC processor technology

shipped during the second quarter of 2012*

In contrast:

– Fewer than 100 million worldwide PC shipments in Q2 2012**

* Source www.arm.com ; ** Source Gartner

Embedded Processing Leader for Post-PC Era

SOC Designs

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http://www.arm.com/


Zed Board: Zynq in Education and Development

Low cost Zynq Evaluation and Development Kit (XC7Z020)

Open source SW and IP

– Linux

– Eclipse based IDE

– Vivado HLS: C to FPGA

– Reference designs

Configurable levels of abstraction for the first-time, novice user,

or the most advanced researcher

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See zedboard.org


ZRobot Robot Example

ZED board enabled Robot

… wirelessly controlled

by an Android tablet

… with full video relay

from ZRobot cameras

to tablet display

See the demo at the

Xilinx Booth

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Next Steps: ZRobot- Mark 2

© Copyright 2012 Xilinx

Processing

System

DDR Memory Controller

AMBA® Switches

APU

Dual ARM

Cortex-A9

AMBA® Switches

Programmable Logic

DDR 3

AXI4 Interconnect (Lite)

WIFI

Access Point

Linux

Boa Webserver

MJPEG Encoding

ZED Board

GE

GPIO

SDIO SD Card

OpenCV

Computer Vision

S_AXI_GP 32b bit

S_AXI_HP 64 bit

Motor Control

PWM

Voice

Processing

Video

Pre-processing

Surround

CCD Cameras

Sensor Farm

Car Wheels

Robotic ARMs

Sensor

Interfaces

Status LEDs

Face Detection

Lane Detection

Computer Vision

Sensor & Peripheral

Reference Designs

Robotics/Industrial

RTOS

Advanced Motor

Control

Remote Video

Remote Control

Android App IE Webpage


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Xilinx Tools: From Vision to Deployment

More Than Just Silicon – A Comprehensive Platform Offering


Design Reuse Flow enables

parallel implementation

for Team Design

– Place & Route modules out

of context from top level design

– Iterate on these modules without

overhead of the full design

– Assemble results in context of

top for exact preservation

Package IP and reuse in new designs

– Reuse module as a pre-verified

placed & routed result

Vivado Design Reuse:

Hierarchical Design Flows

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Share IP within your team, project or company

3rd party IP delivered with a common look and feel

Reuse IP at any point in the implementation process

– Source, placed, or placed and routed

Package Designs into System-Level IP for Reuse

IP Packager

Source (C, RTL, IP, etc)

Simulation Models

Documentation

Example Designs

Test Bench

Processor

SystemPCIe

Memory

Interface

User IP Xilinx IP 3rd

Party IP

Display

Processing Datapath

Embedded Interconnect

Memory Interfaces

Vivado IP Integrator

Standardized IP-XACT

representation

Xilinx IP

3rd Party IP

User IP

Reuse in different designs

Reuse multiple times

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Integrated IP catalog

– Powerful search capabilities

– Single-click access to IP functionality

and collateral

IP customization and generation

– Instant access to customization GUI

– Generate output products in

project or remote directory

– Customize graphically or via Tcl

Seamless IP Access and Customization

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IEEE 1685

IP-XACT is an industry standard way to represent

data about IP (meta-data)

– Port information

– Latency

– Configurable parameters

– Etc.

ASCII XML based

Enables IP to be used in multiple vendor tools flows

IP Packager: IP-XACT

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1. Unzip IP to a local directory

2. Right-click on IP Catalog

3. Add directory to IP Catalog

Extensible IP Catalog: Add Packaged IP

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A graphical design environment to enable rapid and accurate

connection of complex IP

– Connections made at the interface level, not the individual signal level

– Automatic setting and propagation of IP parameters

– Automated generated of RTL

– Full support for arbitrary levels of design hierarchy

– Capable of processor-based or non-processor based design creation

Tight integration with Vivado IP Packager flow for rapid IP and

subsystem reuse

Vivado IP Integrator

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IP Integrator User Interface

System Hierarchy

View

TCL Console

Interface Connections

with Real-time DRCs

Hierarchy Support

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Starts at C

– C

– C++

– SystemC

Produces RTL

– Verilog

– VHDL

– SystemC

Automates Flow

– RTL Verification

– IP Packaging

Vivado High-Level Synthesis Design Flow

Function

Architecture

IP Block

Vivado HLS

C Synthesis

RTL

Design

RTL Verification

Behavioral

Verification

C

Wrapper

IP Package Vivado IP Integrator

System Generator

Packaging

C Specification

C Verification

C

Design

C

Test Bench

Vivado IP Packager

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Function

Architecture

Function versus Architecture

void top ( int& dout1, int& dout2, int din1, int din2 ) { dout1 = din1+din2; dout2 = din1*din2; }

Sequential

always @(posedge clk) begin if (rst == 1’b1) state <= RESET; else state <= next_state; case (state) RST: next_state <= INPUT; INPUT: if (ivld == 1’b1) begin next_state <= CALC; rdin1 <= din1; rdin2 <= din2; end CALC: next_state <= OUTPUT; OUTPUT: next_state <= RESET; default: next_state <= RESET; endcase end

State machine

RESET

rst

INPUT OUTPUT

ivld !ivld CALC

always @(posedge clk) case (state) RST: begin dout1 <= 32’b0; dout2 <= 32’b0; ovld <= 0’b0; end CALC: begin dout1 <= din1+din2; tmp <= din1*din2; end OUTPUT: begin dout2 <= tmp; ovld <= 1’b1; end endcase

Datapath

+

*

dout1

dout2

din1

din2

module top (dout1,dout2, din1,din2, ovld,ivld, clk,rst); output [31:0] dout1,dout2; output ovld; input [31:0] din1,din2; input ivld; input clk; input rst; reg [31:0] tmp,rdin1,rdin2; reg [31:0] dout1,dout2; reg ovld; reg [1:0] state, next_state; parameter RESET=2’b00,INPUT=2’b01, CALC=2’b10,OUTPUT=2’b11; endmodule

Parallel

Process

Interface

Storage

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Zynq®-7000 All Programmable SoCs integrate state-of-the-art

FPGA technology with best-in-class embedded CPUs to define a

new class of ALL PROGRAMMABLE SOC devices which are ideal

for teaching and research

Vivado® Design Suite is a new tool suite based on hierarchical,

design re-use and high-level synthesis which has been designed

for the next decade of programmable systems integration

Teaching and researching the principles and practice of SOC

engineering is now possible at the undergraduate and graduate

levels

Zynq and Vivado in Education

Page 42


The collective opportunity is huge but the complexity is non-

trivial

– Especially for integrated multi-disciplinary teaching and research

The individual contribution is crucial

– But the challenge can be overwhelming in isolation

Effective collaboration and re-use are essential

– Not only to promote rapid dissemination

– But also rapid, widespread reuse of best practice

The Internet is both the challenge and the opportunity

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Promoting & Disseminating Best Practice


Xilinx is a learning company

– We provide enabling technologies not vertical products so we are

constantly learning from our customers and partners

XUP adopts the same approach with our academic partners

We strive to …

– Provide the best possible enabling technology

– Identify and support best teaching and research practices

– Partner to disseminate best practice as widely as possible

So please, give us your feedback

– We need your good ideas!

XUP’s Charter

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Page 45

Closing Thoughts …

“Don’t believe everything you read on the Internet.”

Abraham Lincoln,

U.S. President


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Enabling Technologies for Academia

28nm

Xilinx: All Programmable leadership at 28nm

The Internet is both the opportunity and the challenge

Zynq and Vivado will enable Professors and students to

reach new levels of creativity and collaboration in their

teaching and research


Page 47

Thank You

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All Programmable Technologies in AcademiaCyber security challenge to critical infrastructure...

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