Allen Bradley-PLC5 Programming Guide

December 1997

Supersedes Doc. ID 9399-L5PG-04.17.95

PLC-5®

A.I. SERIES™

PROGRAMMING GUIDE

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Table of Contents

11 Introduction........................................................................................................1-1How to Use This Manual ................................................................................................. 1-2

22 Planning Programs for Your Application..........................................................2-1Functional Specification ........................................................................................... 2-2Detailed Analysis ..................................................................................................... 2-2Program Entry.......................................................................................................... 2-2Testing ..................................................................................................................... 2-3Acceptance ............................................................................................................... 2-3

Using Main Control Programs......................................................................................... 2-4How the Processor Interprets the MCPs .................................................................... 2-4

Configuring Main Control Programs ............................................................................... 2-6Specifying The Order of Main Control Programs...................................................... 2-6Disabling Main Control Programs ............................................................................ 2-6

Monitoring Main Control Programs ................................................................................ 2-7Using Interrupt Programs ................................................................................................ 2-8

33 Designing Programs for Your Application........................................................3-1Machine Example ........................................................................................................... 3-2Creating the Functional Specification.............................................................................. 3-3Creating the Detailed Analysis ........................................................................................ 3-5Entering the Program ...................................................................................................... 3-9Using Other Processor Programming Features............................................................... 3-11

Examples of Special Programming Applications..................................................... 3-12Checking for Completeness ........................................................................................... 3-13

44 SFC Building Blocks..........................................................................................4-1SFC Building Blocks....................................................................................................... 4-1

Step.......................................................................................................................... 4-1Transition................................................................................................................. 4-2Simple Path.............................................................................................................. 4-2Selection Branch ...................................................................................................... 4-3Simultaneous Branch................................................................................................ 4-4GOTO and Label Statements .................................................................................... 4-5

Drawing an SFC.............................................................................................................. 4-6Example SFC ........................................................................................................... 4-8How Selection Branches Work.................................................................................. 4-9

PLC-5 A.I. Series Software Reference

ii

How Simultaneous Branches Work ......................................................................... 4-10Using GOTOs and Labels ....................................................................................... 4-11

Using the SFR Instruction.............................................................................................. 4-12

55 Writing Ladder Logic......................................................................................... 5-1Converting Machine Statements to Ladder Logic............................................................. 5-2

Rung Logic Example ................................................................................................ 5-3Example Discrete I/O Instructions ............................................................................ 5-3

Constructing Ladder Rungs ............................................................................................. 5-5Writing Rung Logic.................................................................................................. 5-5Writing Branch Logic ............................................................................................... 5-7

Arranging Input Instructions ......................................................................................... 5-10

66 Organizing Data Table Files.............................................................................. 6-1Understanding Data Storage ............................................................................................ 6-2Organizing Data into Files and Data Blocks .................................................................... 6-4Default Data Table Files .................................................................................................. 6-6

77 Addressing Data Table Files............................................................................. 7-1Specifying Logical Addresses .......................................................................................... 7-2

Using Address Mnemonics ....................................................................................... 7-4Specifying I/O Image Addresses ...................................................................................... 7-6Specifying Indirect Addresses .......................................................................................... 7-8Specifying Indexed Addresses........................................................................................ 7-10

Indexed Addressing Example.................................................................................. 7-11Specifying Symbolic Addresses...................................................................................... 7-12

SoftLogix 5 Symbols............................................................................................... 7-13Addressing Frequently Used Files.................................................................................. 7-14

Status File for PLC–5/10, PLC–5/12, and PLC–5/15 Processors.............................. 7-15Status File for PLC–5/25 Processors....................................................................... 7-15

88 Using a Selectable Timed Interrupt .................................................................. 8-1Writing STI Ladder Logic ............................................................................................... 8-2Setting Up an STI............................................................................................................ 8-3

Storing the Location of the STI File in the Processor Status File ............................... 8-3Block Transfers Used Within an STI......................................................................... 8-4

99 Using a Processor Input Interrupt .................................................................... 9-1Writing PII Ladder Logic................................................................................................. 9-2PII Application Examples ................................................................................................ 9-4

Using Counter Mode................................................................................................. 9-4Using Bit Transition Mode........................................................................................ 9-4

Setting Up a PII ............................................................................................................... 9-6

Table of Contents

iii

Configuring the PII .................................................................................................. 9-6Block Transfers Used Within a PII ........................................................................... 9-7

Monitoring a PII.............................................................................................................. 9-8PII Return Mask ....................................................................................................... 9-8PII Accumulator ....................................................................................................... 9-8PII Scan Times ......................................................................................................... 9-8

1010 Writing a Fault Routine ....................................................................................10-1Using Fault Routines ..................................................................................................... 10-2

Responses to a Major Fault ..................................................................................... 10-2Major Fault Codes .................................................................................................. 10-3

Programming a Fault Routine........................................................................................ 10-8Set an Alarm .......................................................................................................... 10-8Clearing the Fault................................................................................................... 10-8Using Shutdown Logic ..........................................................................................10-10Testing a Fault Routine .........................................................................................10-10

Setting Up a Fault Routine ...........................................................................................10-11Enabling a Fault Routine .......................................................................................10-11Changing the Fault Routine from Ladder Logic.....................................................10-11Clearing a Major Fault ..........................................................................................10-12

Setting Power–Up Protection........................................................................................10-13Allowing or Inhibiting Startup...............................................................................10-13

1111 Using Adapter Mode.........................................................................................11-1Using Adapter Mode ..................................................................................................... 11-2Operating in Adapter Mode........................................................................................... 11-3

Configuring an Original PLC-5 Processor for Adapter Mode.................................. 11-3Configuring a New Platform PLC-5 Processor for Adapter Mode............................ 11-4

Transferring Discrete I/O and Block Data ..................................................................... 11-5Programming Discrete Data Transfers........................................................................... 11-8

Using Rack 3.......................................................................................................... 11-8Creating an Adapter Image File - Original PLC-5 Processors ................................. 11-9Creating an Adapter Image File - New Platform PLC-5 Processors......................... 11-9Transferring Bits between Supervisory (PLC-2) and Adapter Processors................11-10Determining the Status of the Adapter Processor ...................................................11-11Determining the Status of the Supervisory Processor .............................................11-12

Programming Considerations for Using Adapter Mode.................................................11-13Programming Block Transfers - Original PLC-5 Processors .........................................11-14

Addressing Tips for Block Transfers......................................................................11-15Example Ladder Logic .................................................................................................11-18

Supervisory Processor (PLC–2/30, PLC–3, PLC–5, or PLC–5/250) .......................11-18Adapter Processor (PLC–5/15, –5/25)....................................................................11-23


iv

Adapter Processor (New Platform Processors) ....................................................... 11-24

1212 Using Scanner Mode ....................................................................................... 12-1Operating in Scanner Mode ........................................................................................... 12-1

Configuring an Original PLC–5 Processor for Scanner Mode.................................. 12-1Configuring a New Platform PLC–5 Processor for Scanner Mode ........................... 12-1

Transferring Discrete Data ............................................................................................ 12-2Transferring Block Data ................................................................................................ 12-3

Queued Block Transfer Requests............................................................................. 12-4Block Transfers to Local I/O ................................................................................... 12-4Block Transfers to Remote I/O................................................................................ 12-4Block Transfers in Fault Routines or Selectable Timed Interrupts (STIs)................. 12-5

Block Transfer Sequence Original PLC-5 Processors ..................................................... 12-6Block Transfer Sequence New Platform PLC-5 Processors............................................. 12-8

Block Transfer Sequence with Status Bits ............................................................... 12-9Block Transfer Timing: Original PLC-5 Processors .................................................... 12-11

Instruction Run Time............................................................................................ 12-11Waiting Time in the Queue................................................................................... 12-11Transfer Time....................................................................................................... 12-11

Block Transfer Timing: New Platform PLC-5 Processors............................................ 12-12Instruction Run Time............................................................................................ 12-12Waiting Time in the Holding Area........................................................................ 12-12Transfer Time....................................................................................................... 12-12

When the Processor Detects a Major Fault ................................................................... 12-13When a Resident Local I/O Rack Faults ....................................................................... 12-14When a Remote I/O Rack Faults .................................................................................. 12-15Recovering from a Resident Local I/O or Remote I/O Rack Fault ................................. 12-16

Using I/O Status File Bits to Monitor Rack Faults ................................................. 12-16Using Fault Routine and Ladder Logic to Recover................................................. 12-17

Index

Introduction

1-1

1 Introduction

This manual provides you with information about programming the Allen–BradleyPLC–5 family of programmable logic controllers. This information includes:

• Planning your projects

• Basics of SFC programming

• Basics of ladder logic programming

• Basics of the PLC–5 data table, including the various methods you can use toaddress data table files

• Using selectable timed interrupts, processor input interrupts, and fault routines

• Setting up the processor for adapter and scanner mode

• Programming through a serial port

Note For information on the PLC–5 instruction set, see the Instruction Set Reference or theinstruction set help in the software (from the Online or Offline Editor, select [F6]Utility, [F9] Util2, [F7] Keyconf, [F4] Inshelp or press [Shift-F10]).

PLC-5 processors can be grouped into three categories: Original (classic ), NewPlatform (NP5 or Enhanced), and Secure. As much as possible, this manual will referto a group of processors rather than listing individual models. The table below lists thedifferent processors in each category. (The processor type given includes all variants ofthat processor: L-Local, E-Ethernet, C-ControlNet, and V-VME.)

Original New Platform Secure

PLC-5/10 PLC-5/11 PLC-5/16

PLC-5/12 PLC-5/20 PLC-5/26

PLC-5/15 PLC-5/30 PLC-5/36

PLC-5/25 PLC-5/40 PLC-5/46

PLC-5/VME PLC-5/60 PLC-5/66

PLC-5/80 PLC-5/86

Command Portal keysfor this function:.UUKI

PLC-5 A.I. Series Programming Guide

1-2

How to Use This Manual

This manual is a guide to programming the PLC–5 family of programmable logiccontrollers. While this manual will not tell you everything about PLC–5 programming,it does discuss the major program structures that you can use in your projects.

Before you begin with your PLC–5 project, read through Chapter 2 – PlanningPrograms for Your Application. This chapter describes an Allen–Bradleyrecommended procedure for developing PLC–5 programs using multiple main controlprograms. While much of the material in that chapter is devoted to New Platform andSecure PLC-5 processors, a great deal of the information applies to Original PLC-5processors as well. For those using one main control program, or for those usingearlier PLC–5 processors, Chapter 3– Designing Programs for Your Applicationcontains the Allen–Bradley recommended procedure for developing programs.

Chapter 4– SFC Building Blocks describes the components of Sequential FunctionCharts. If your processor supports SFC programming, this chapter can help you getstarted with SFCs.

The rest of the manual is to be used as a guide—the first place to turn when you havequestions about:

• Using interrupt programs (selectable timed interrupts and program inputinterrupts)

• PLC-5 data table structures

• Adapter and scanner mode

• Serial port programming

Planning Programs for Your Application

2-1

2 Planning Programs for YourApplication

Allen–Bradley recommends that you develop a design specification for yourprogramming application. The design specification is a conceptual view of yourapplication and is used to determine your sequential function chart (SFC) and ladderlogic requirements.

This chapter gives you an overview on how to plan your design specification for yourprocessor; the next two chapters give you more specific detail to prepare your designspecification.

In planning and developing the programs for your application, we recommend that youuse the Program Development model shown below.

FunctionalSpecification(general conception)

DetailedAnaylsis

Program

Testing

Acceptance

Development

Sign-off

Each box represents an activity that you perform. Begin with the functionalspecification, and move on to the detailed analysis. Based on the detailed analysis, youcan enter your programs and test them. When testing is complete, you are ready toimplement the programs in your application.

This model also allows for interaction of the activities at the different levels. Thedetailed analysis can be used as the basis for developing your testing procedures andrequirements. And, because the functional specification is well thought out, it can beused as the program sign–off document.


2-2

Not all machine processes can be controlled with an SFC implementation; thefollowing description of the program development model is generalized to fit mostprocesses. The power of an SFC is that it is a descriptive programming language thatyou can use to describe your process in terms of machine states and transitionconditions. Because this description executes your process control, your SFC providesthe link between these two “legs” of the development model.

Functional SpecificationThe functional specification represents a very general view of your process or adescription of operation. Identify the events and the overall order in which they mustoccur. This functional specification can be in any form: written statements,flowcharts, or rough-draft sequential function charts (SFC). Use the form that is mostfamiliar to you. Allen–Bradley recommends that you generate a rough-draft SFC so thatyou have a better correspondence between your beginning diagrams and your finishedprogram.

Detailed AnalysisIn this phase, you take the functional specification and add the details of your process.Identify your inputs and outputs, specific actions and transitions between actions (thatis, the bit-level details needed to write your program.

If you are using a New Platform or Secure PLC-5 processor, you also determine thenumber of Main Control Programs (MCPs) and the programming method for eachduring this phase. Use MCPs when you are describing your process in terms offunction or in terms of geography. You then break down those functions into ladderprograms, sequential function charts (SFCs), or structured text.

For typical SFC applications, an SFC program controls the order of events in yourprocess by issuing commands. A command, such as fwd_conv_cmd to move aconveyor forward, is simply a data table storage bit (for example B3:0/7) which you setup in the SFC. You then program the ladder logic for fwd_conv_cmd in a separateladder program to control the actual outputs to move the conveyor.

The ability to have one SFC program defining the sequence and then separate ladderlogic programs controlling outputs is the basis of New Platform and Secure PLC-5processors’ main control program feature. For more information on this feature, seethe next section, titled “Using Main Control Programs.”

If you are using an Original PLC-5 processor, note that you can have only one mainprogram. For information on planning a design specification using only one mainprogram, see Chapter 3– Planning Programs for Your Application.


2-3

Program EntryIn this phase, you enter the programs into your computer using the SFC Editor, LadderEditor, or Structured Text Editor. For more information on entering SFCs, ladderlogic, or structured text, see the PLC–5 A.I. Series Software Reference manual.

TestingIn this phase, you test the programs you have entered. You may want to consider usingRSLogix Emulate 5™ processor emulation to simulate your system.

AcceptanceOnce testing is complete, your resulting programs should match your functionalspecification.


2-4

Using Main Control Programs

New Platform and Secure processors only

New Platform and Secure PLC-5 processors can have up to 16 control programs activein a single PLC-5 processor to control your process. Each of these programs is called amain control program (MCP).

This chapter describes the effects of using multiple main control programs and how aNew Platform or Secure PLC-5 processor interprets the main control programs.

By using several main control programs, you can define one main control program foreach particular machine or function of your process. This allows you to separatesequential logic (SFCs) from ladder logic and structured text to subdivide your processand make troubleshooting easier.

For example, you can specify an SFC program to define the order of events in theprocess and separate ladder logic and structured text programs to directly control theoutputs. Each of these is a main control program.

A main control program can be a sequential function chart, ladder program, orstructured text program in any program file numbered 1 through 1999. You can useany mix of SFC, ladder, and structured text programs to define up to 16 main controlprograms. One data table is used by all MCPs (that is, you do not have a separate datatable for each MCP).

How the Processor Interprets the MCPsThe main control programs are scheduled to execute in the order in which you specifiedon the Processor Configuration screen. An I/O image update and housekeeping takesplace after each MCP is completed. After the last MCP is completed, all MCPs arethen repeated in the same order. Note that the watchdog setpoint covers one scan of allMCPs. The drawing below shows how the processor interprets MCPs.


2-5

If the MCP is a ladder program, the program is executed normally (that is, rungs areexecuted from the first rung to the last, with all timers, counters, jumps and subroutinesactive). After the END instruction in the ladder program, the processor initiates an I/Oupdate (reading local inputs, writing local outputs, reading remote buffers and writingremote outputs to the buffer). The next MCP is then started.

If the MCP is a structured text program, the program is executed normally. After thelast line in the structured text program, the processor initiates an I/O update and thenext MCP is started.

If the MCP is a sequential function chart, only the active steps are scanned andtransitions from those active steps are examined; then (after one complete pass throughthe active steps) the processor initiates an I/O update and the next MCP is started.


2-6

Configuring Main Control Programs

New Platform and Secure PLC-5 processors only

You configure which programs are your main control programs on the ProcessorConfiguration screen.

Specifying The Order of Main Control ProgramsOn the Processor Configuration screen, specify the program file number and the orderin which the MCPs should be run. This configuration is read before the MCP isexecuted; if you make a change to the configuration screen regarding an MCP, thatchange takes effect on the next execution of the MCP. You can also change the MCPinformation through ladder logic by manipulating the status file. The change thentakes effect on the next execution of that MCP.

You can have the same program file number specified more than once as a maincontrol program. For example, you may want a program to execute frequently and havea higher priority over other programs.

If you do not want to use multiple main programs, program your main SFC (programfile 1) or ladder program (program file 2) and the processor will execute your mainprogram. You do not need to make any entries on the Processor Configuration screen(the processor automatically enters the main file in the first MCP entry).

For more information on how to specify your program file numbers on theconfiguration screen, see the PLC–5 A.I. Series Software Reference manual.

Disabling Main Control ProgramsEach MCP has an inhibit bit in the processor status file (S:79). You can set these bitsto tell the processor to skip over the MCP until the bit is reset. Disable an MCP if youwant to hold a machine state temporarily, regardless of transitions (for example, inmachine fault conditions). Disabling an MCP can also help improve scan time; if youknow you don’t need to run one of your MCPs every scan, you can disable it until youneed it.

If you disable an MCP, outputs remain in the state that they were in during the lastscan (that is, all actions remain active). Make sure you consider any outputs thatmight be controlled within that MCP before disabling it. Otherwise, injury topersonnel or damage to equipment may result.

Note If the disable bit is set for all MCPs, a minor fault occurs to warn you that no MCPsare executing.

!


2-7

Monitoring Main Control Programs


The program scan times for each MCP are stored in the processor status file (S),displaying the previous and maximum scan time. The status file also stores thecumulative scan time, S:8 (the scan time for one complete pass through all MCPs), andthe maximum cumulative scan time, S:9.


2-8

Using Interrupt Programs

If you are using interrupt programs (such as a Selectable Timed Interrupt or a ProcessorInput Interrupt), they have a higher priority than a main control program. Theprocessor uses the following priorities for programs:

1. Fault Routine

2. Processor Input Interrupt (PII)

3. Selectable Timed Interrupt (STI)

4. Main Control Programs

If an interrupt occurs during the execution of an MCP, the processor stops the MCP,executes the interrupt program, and returns control to the MCP at the point that it wasstopped.

You can protect important parts of your main control programs from interruption byusing the User Interrupt Disable (UID) and User Interrupt Enable (UIE) instructions.These instructions allow you to temporarily “disable” interrupts. If a condition arisesthat would normally call for the interrupt program, these instructions tell the processorto finish executing the rungs in the MCP first. For more information on theseinstructions, see the PLC–5 A.I. Series Instruction Set Reference manual.

Remember, however, that interrupt programs are re–enabled at each END instruction(regardless of the UID state). If you want to completely disable an interrupt program,enter a 0 in the appropriate address of the processor status file.

• For Original PLC-5 processors, disable the STI by entering 0 in S:31, using theProcessor Status screen

• For New Platform and Secure PLC-5 processors, disable the STI by entering 0 inS:31, and disable the PII by entering 0 in S:46, using the Processor Configurationscreen.

For more information on disabling interrupts in the status file, see the PLC–5 A.I.Series Software Reference manual.

Designing Programs for Your Application

3-1

3 Designing Programs for YourApplication

Based on the model discussed in the previous chapter and the information on usingMCPs, this chapter uses a drill–machine example to help show how to complete thefirst two activities in the Program Development Model: functional specification anddetailed analysis. Information on the program entry phase is in the remaining chaptersof this manual and in the PLC-5 A.I. Series Software Reference manual.

Note If you are using an Original PLC-5 processor, you can use only one main program.You can still apply some of the steps in this chapter, but you must incorporate theminto your one main SFC and supporting ladder programs.


3-2

Machine Example

The following example uses a description of a specific machine operation to show howto identify conditions and actions and how to group the actions into steps of machineoperation. The drawing below shows a hardware block diagram.

Off

Auto

Fwd

AdvanceAssembly

DrillMotor

N.C. LS2

Held Open

LS3 N.O. LS4N.O.

ConveyorMotor

UnloadStation

LoadStation

Clamp

CL1

LS1

LS5 N.O.

N.O.

Fwd

Fwd


3-3

Creating the Functional Specification

The functional specification represents a general description of the operation of yourprocess in Auto mode. Based on the drill machine example, this general descriptionmight be:

1. The operator starts the conveyor by selecting AUTO.

2. The operator puts a block of wood onto the conveyor.

3. The wood moves into position and actuates LS1.

4. When the wood is in position:

a. The conveyor stops.

b. CL1 clamps the wood.

c. The drill station moves forward.

5. The drill station moves forward and closes LS3. This action turns on the drillmotor.

6. The drill station moves to full depth and closes LS4. This action:

a. Stops forward motion of the drill station

b. Initiates a 2–second dwell

7. The drill station backs up after the 2–second dwell.

8. The drill motor stops when LS3 is released.

9. The drill station reaches home position and opens LS2. This action:

a. Stops the reverse motion

b. Opens the clamp

c. Starts the conveyor forward

10. The wood is ejected when LS5 toggles to indicate the cycle is complete.

We recommend that you create a rough–draft SFC to represent this general description.An SFC is drawn using a series of boxes and lines. A box represents a step, or oneindependent machine operation. A transition, shown as a in the drawingbelow, is a logic condition that lets the processor progress from one step to the next.


3-4

initialization

conveyor forward

010 AUTO operator starts cycle

011 LS1 wood in position

012 LS4 hole drilled

013 TMR1 dwell timer done

014 LS2 station home

015 LS5 wood ejected

drill

dwell

reverse drill

eject

For more information on the building blocks of SFC diagrams, see Chapter 4- SFCBuilding Blocks.


3-5

Creating the Detailed Analysis

Now that you have a functional specification, start filling it in with the details of yourprocess. Identify the hardware requirements. The table below identifies hardwarerequirements for the inputs and outputs of the drill machine.

Input Part Description

AUTO selector switch select automatic mode

LS1 N.O. limit switch part in place

LS2 N.C. limit switch drill station home

LS3 N.O. limit switch drill motor on

LS4 N.O. limit switch drill station at full depth

LS5 N.O. limit switch cycle complete

Output Part Description

DSF drive motor move drill station forward

DSB drive motor move drill station back

DM drill motor drill motor on

CL1 electric clamp clamp 1 on

CMF drive motor move conveyor forward

TMR1 timer dwell timer

Use the hardware requirements (with the functional specification) to match the inputsand outputs with the actions of the process. The table below shows the hardwarerequirements with the general description for the drill machine example.

When This Happens: Take This Action:

AUTO switch closes conveyor moves forward (CMF = on)

LS1 closes conveyor stopsclamp holds wooddrill station advances

(CMF = off)(CL1 = on)(DSF = on)

LS3 closes drill motor starts (DM = on)

LS4 closes drill station stopsdwell timer starts

(DSF = off)(TMR1 = on)

timer done drill station backs up (DSB = on)

LS3 opens drill motor stops (DM = off)


3-6

When This Happens: Take This Action:

LS2 opens drill station stopsclamp releases woodconveyor starts

(DSB = off)(CL1 = off)(CMF = on)

LS5 closes wood is ejected

Once you identify the individual actions, you can add these actions to your functionalspecification to complete the planning of your program. The following drawing showsthe detailed analysis of the drill machine example.


3-7

initialization

conveyor forward

010 AUTO operator starts cycle

011 LS1 wood in position


013 TMR1 dwell timer done

014 LS2 station home

015 LS5 wood ejected

ladder file action name

2 init


3 conv_frwd


4 clamp_on

5 drill_adv

6 drill_on

drill

dwell

reverse drill

eject


7 rev_drill


9 clamp_off

8 drill_move


3-8

Now that you have an SFC program that defines the individual machine actions foryour process (Process Sequence MCP), you can create a ladder logic program thatcontrols the outputs of those machine actions (Outputs MCP). The order in which youprogram these rungs does not matter. This program merely contains the ladder logicthat defines a command for each machine action in your process. Your ProcessSequence MCP determines in what order they are executed.

You can also create a Modes MCP that defines the operation of your hardware in thedifferent machine modes (Auto, Manual, Fault, Cycle Start/Stop, etc.).


3-9

Entering the Program

Once you have finished your detailed analysis, that is, you have the MCPs defined andprogrammed (for example, the drill machine has a Process Sequence MCP, OutputsMCP and a Modes MCP), enter the program into your computer. The example belowillustrates what would be entered in the Process Sequence MCP, Outputs MCP andModes MCP for one step from the drill machine.


3-10



4 clamp_on5 drill_adv6 drill_on

drill

FaultAutodrill

modemodestationforward

JogManualmode pushbutton

(ladder logic for action)

Process Sequence MCP

Ladder Logic for Outputs MCP

Ladder Logic for Modes MCP (rung that controls Auto mode)

FaultAutomodeAll_homepushbutton

Manualpushbutton

Automode

Automode

fwd_drill_cmd *

fwd_drill_cmd *

* Any symbol can be used forthis "command" to controlan output.


3-11

Using Other Processor Programming Features

Use your design specification to determine if you need one or more of the followingspecial processor programming features:

• Power-up routines

• Time–driven interrupt routines

• Event–driven interrupt routines

• Fault–driven interrupt routines

The table below explains when to use these special programming features.

If a Portion of LogicShould Execute:

Mark thatPortion with a: Description:

Immediately upondetecting conditionsthat require a startup

Power-up/FaultRoutine

Create a separate file for a controlled start–upprocedure, for the first time you start aprogram or when you start a program aftersystem down time. The processor executesthe power-up/fault routine to completion.

At a specified timeinterval

SelectableTimed Interrupt(STI)

Create a separate program file and specify theinterrupt time interval. The processorinterrupts the main logic program at thespecified interval, runs the STI to completion,then resumes the main logic program where itleft off.

Immediately when anevent occurs

Processor InputInterrupt (PII)

Create a separate program file and specify 16inputs of an input word in the I/O rack. Whenthe event(s) occurs, the processor interruptsthe main logic program, runs the PII tocompletion, then resumes the main logicprogram where it left off. This feature is onlyavailable with New Platform and Secure PLC-5processors.

Immediately upondetecting a majorfault

Fault Routine Create a separate file for a controlled responseto a major fault. The first fault detecteddetermines which fault routine is executed.The processor executes the fault routine tocompletion. If the routine clears the fault, theprocessor resumes the main logic programwhere it was interrupted. If not, the processorfaults and switches to program mode.


3-12

Examples of Special Programming ApplicationsThe table below describes programming situations that might require specialprogramming features.

If the Application is to: Choose a:

Eject a faulty bottle from a bottling line PII

Send critical status to a supervisory processor via DH+after detecting a major fault

Fault routine

Monitor machine position every 250ms and calculate theaverage rate–of–change

STI

Shut down plant floor devices upon detecting a major fault Fault routine

Restart the system after the system has been shut down Power–up routine

Take a measurement and compare it with a standard every1.0 seconds

STI


3-13

Checking for Completeness

When you complete the functional specification and the detailed analysis, review themand check for missing or incomplete information such as:

• Insufficient input conditions

• Safety conditions

• Startup or emergency shutdown routines

• Alarms and alarm handling

• Fault detection and fault handling

• Message display of fault conditions

• Abnormal operating conditions

SFC Building Blocks

4-1

4 SFC Building Blocks

This chapter describes the components used to create a Sequential Function Chart(SFC) and how to use those components in an SFC.

Note SFCs are somewhat different between Original and New Platform processors. Whenchanging the processor type from an Original to a New Platform processor, SFCs willbe converted automatically. The reverse (from New Platform to Original), however, isnot true.

SFC Building Blocks

An SFC uses the following types of building blocks:

• Step

• Transition

• Simple Path

• Selection Branch

• Simultaneous Branch

• GOTO statements and labels

StepA step typically represents an independent machine state. One step of ladder logic runsrepeatedly, top to bottom, until a logic condition (transition) lets the processor progressto the next step of the chart. You draw a step as a numbered and labeled box in theSFC. The number 007 in the example below represents the ladder file number thatcontains the ladder logic for that step.


4-2

007 Step

Corresponding ladder logic

Mixer 1 }

New Platform and Secure PLC-5 processors can have up to eight actions per step. Anaction is a subset of a step. Instead of assigning a single ladder file to a step, you canassign individual ladder files to actions of a step to better represent the individualpieces of your operation.

TransitionA transition represents the logic condition that lets the processor progress from one stepto the next. You draw a transition as a numbered cross below its step (see the followingdrawing).

017

EOT

Transition

Corresponding ladder logic

}Every transition must contain at least one EOT (End of Transition) instruction.

Simple PathA simple path contains a series of steps and transitions that execute one at a time insequence.

SFC Building Blocks

4-3

009

010

007

008

Mixer 1

Dump 1

Selection BranchA selection branch contains alternative paths from which the processor selects one.This is equivalent to an “OR” structure. Draw a selection branch as parallel pathsconnected with single horizontal lines (see the drawing below). Notice that transitionsare located within the structure’s boundaries and are at the top of each parallel path.

009

010

007Mixer 1

008Dump 1

011

015

012Mixer 7

014

017

013Rinse 1

016

003


4-4

Simultaneous BranchA simultaneous branch runs steps simultaneously that are in parallel paths (theprocessor shares processing time for each path). This is equivalent to an “AND”structure. Draw a simultaneous branch as parallel paths connected with doublehorizontal lines as shown in the following drawing. Notice that a common transitionfor the last step in all the paths is outside of the branch. The processor finishes runninga simultaneous branch when it has scanned each step in each path at least once and thecommon transition is true.

009

010Mixer 1

008Dump 1

012Mixer 7

013Rinse 1

026

When using simultaneous branches, you may want to include a “dummy” step at theend of each path to synchronize the simultaneous actions. This dummy step merelyholds each path (until all paths have been executed) before moving on to the transition.Using the example above, the structure would look like the following:

009

010Mixer 1

008Dump 1

012Mixer 7

013Rinse 1

026

015 015 015Dummy Dummy Dummy

SFC Building Blocks

4-5

You can combine SFC building blocks (step, transition, selection branch, andsimultaneous branch) to build structures that represent your programming application.

GOTO and Label StatementsA GOTO statement tells the processor to continue program execution at anotherlocation marked with a label. The example below shows a GOTO statement and itsassociated label.

016 017

019

018

015

003:

GO TO003


4-6

Drawing an SFC

After you identify the major areas of machine operation, convert the logical paths andsteps that you labeled in your design specification to SFC building blocks. The tablebelow helps explain when to use which SFC building blocks.

Note At this point, do not worry about the actual ladder logic for each step and transition.After you complete the SFC, you can develop the ladder logic.

If You Have: Then Draw: Using These Rules:

An independent machine state A step/transition pair A step must always be followed by atransition.

A clearly defined chain of eventsthat occur sequentially

For example, in one heat–treating area, the temperaturemust ramp up at a particularrate, maintain the temperaturefor a certain duration, then coolat a particular rate.

A simple path of stepsand transitions

For design purposes, number steps andtransitions consecutively from 2.

Start the path with a step; end the pathwith a transition.

Two or more alternative pathswhere only one is selected

For example, depending on abuild code, one station musteither drill or polish.

A selection branchThe transitions beginning each path arescanned from left to right. The first truetransition determines the path taken.For an Original PLC-5 processor, youcan define up to 7 paths in the structure.For a New Platform or Secure PLC-5processor, you can define up to 16paths.

See How Selection Branches Work onpage 4-9.

Two or more parallel paths thatmust be scanned at least once

For example, communicationsand block transfers must occurwhile control logic is executing.

A simultaneous branchAll paths are active in the structure.For an Original PLC-5 processor, youcan define up to 7 parallel paths. For aNew Platform or Secure PLC-5processor, you can define up to 16parallel paths.

See How Simultaneous Branches Workon page 4-10.

For special cases, use the rules listed in the following table.

SFC Building Blocks

4-7

If You Have: Then:

To jump within the SFC Use a GOTO statement and label.See Using GOTOs and Labels on page 4-11.

A step that needs to be runin multiple places within theSFC

Repeat the step where needed or use a global subroutinethat gets called from multiple steps by the sameprocessor.

A step that can be ignoredbased on logic conditions

Create two selection branches, one with and one withoutthe step; place the step in a subroutine; or combine thestep with another step that is segregated by an MCRzone.

An SFC branch structurewithin another branchstructure (nesting)

Nest the branch structures. The software supports asmany levels of nested branches as you can store basedon processor memory.

To reset the logic in an SFCprogram

Use the SFR instruction to reset the chart.See the Instruction Set Reference manual.

To disable a Main ControlProgram (New Platform andSecure PLC-5 processorsonly)

Set the disable bit for the MCP on the ProcessorConfiguration screen.See the PLC–5 A.I.Series Software Reference manual.


4-8

Example SFC

002InitialStep

003

010

013

008

012

006

011

009

007

004

005014

015

SFC Building Blocks

4-9

How Selection Branches WorkWhen a processor runs a selection branch, the processor finds the path that is true forthe program scan and runs the steps and transitions in that path. If more than one pathin a selection branch goes true at the same time, the processor chooses the left–mostpath.


4-10

How Simultaneous Branches WorkWhen a processor runs the simultaneous branch, the processor scans the branch fromleft–to–right, top–to–bottom. It appears that the processor runs each path in the branchsimultaneously. The following drawings show a typical scan sequence.

Typical SFC Scan of a Simultaneous Branch

Typical SFC Scan of a Simultaneous Branch when a Transition Goes True

transition transition transitiontransitiontruefalse false falsetrue

transitionfalsetransition

falsetransition

falsetransition

step added to list ofsteps to be scanned

first scan

last scan/post scan

First: Then:

SFC Building Blocks

4-11

The following table lists considerations for selecting SFC scan sequences.

Control Characteristic: Considerations:

When a transition is true, theprocessor scans that step one last timeso that the processor can resetnon-retentive outputs.

Your application may have to consider theextra time for the post scan.

If you are using a New Platform or SecurePLC-5 processor, you can configure your SFCprogram to do a manual reset instead of anautomatic reset.

The last step in each path of asimultaneous branch must be executedbefore the processor scans thecommon transition.

The processor cannot exit the simultaneousbranch until the last step in each path has beenexecuted.

Using GOTOs and LabelsGOTO and label statements tell the processor to stop scanning the current path, jump toanother step, and continue scanning.

General Rules for GOTOs and Labels

• Each label must have a unique 3 digit number (001 – 250), the same as itscorresponding GOTO.

• You can have up to 250 labels in one SFC.

• More than one GOTO can jump to the same label.

• You cannot jump into, out of, or between simultaneous branches.

• Use sparingly to avoid confusing the flow of the SFC.

Rules for Placing GOTOs and Labels

• You can only place GOTOs at the end of the SFC or after the last transition of aselection branch.

• You can only place labels immediately before a step or before a simultaneousbranch.

• You cannot place a label between a step and its transition.


4-12

Using the SFR Instruction


The SFR instruction resets the logic in an SFC. When an SFR instruction goes true,the processor performs a postscan/lastscan and then resets the logic in the SFC on thenext program scan. The chart remains in this reset state until the instruction goes false.The SFR instruction also resets all retentive actions that are currently active.

Use the SFR instruction with care. Unexpected machine motion could injurepersonnel.

Use the SFR instruction to handle situations that require resetting your machines. Forexample, if a machine goes out of alignment, use the SFR to reset the chart, align themachine, and then disable the SFR to start the SFC again.

For more information on the SFR instruction, refer to the Instruction Set Referencemanual.

!

Writing Ladder Logic

5-1

5 Writing Ladder Logic

After you have a design specification for your application, you are ready to create theladder logic. This chapter shows you how to:

• Convert statements of machine operation into rungs of ladder logic with digital I/Oinstructions

• Construct ladder rungs in the correct format

• Arrange instructions for fast program scan

• Assign bit addresses to digital I/O instructions


5-2

Converting Machine Statements to Ladder Logic

Ladder logic is a program written in a format resembling an electrical ladder diagram.A programmable controller uses the program to sense inputs and control outputs.

Ladder logic programs:

• Examine the on/off status of machine devices by reading bit data in the input andoutput image file

• Make decisions based on input and output conditions

• Control the on/off status bit data in the output image file which in turn controls theon/off status of output devices

To write ladder logic, you need to understand these definitions:

Rung –a logic statement that controls one or more bits based on the state of other bitsexamined. Ladder logic is composed of a listing of rungs. Each rung connects at onepoint to the left and right power rails. A rung must have at least one output instruction.

Input (condition) instructions – examine input and output conditions that thendetermine the true or false state of the instruction. These commands appear on the leftside of a rung—to the left of the output instructions. A rung may have multiple inputinstructions.

Output (control) instructions – control the state of a bit or bits based on input(condition) instructions. These commands are placed on the right side of a rung, to theright of the input instructions. Each rung must have at least one output instruction (ormore).


5-3

Rung Logic Example

Rung 1

Rung 2

Rung 3

Rung 4

Rung 5

input (condition) output instructionelementsinstruction elements

Note Each input instruction and output instruction you enter generates a rung element. Aseach input instruction is executed, the addressed bit is examined to see if it matches acertain condition (on or off). If the condition is found (rung 1 above), the rung elementis set true. Input instructions must contain a continuous path of true elements from thestart of the rung to the output instruction for the output instruction to be enabled. If arung element is unconditioned (that is, has no input instructions as in rung 4 above),the output instruction is always enabled.

The PLC–5 A.I. ladder editor highlights logically true instructions when the processoris in run, remote run, or test mode.

Example Discrete I/O InstructionsThe example rung format above uses the following discrete I/O instructions:

Name: Examine–OnFormat:Description: An input instruction that examines a bit for an ON condition as follows:

If the bit is: Then the instruction is:

ON (1) true

OFF(0) false


5-4

Name: Output Energize

Format:Description: An output instruction that controls the status of one bit (which in turncould control the on/off status of the output device).

If the instruction is: Then the bit is:

enabled (rung is true) set to 1

disabled (rung is false) reset to zero

For information about other available instructions, refer to Allen-Bradley's InstructionSet Reference manual or to the online help in PLC-5 A.I. Series (accessed with thecommand sequence .UUKI or [Shift-F10] then [F4]).


5-5

Constructing Ladder Rungs

When you construct ladder rungs, there are guidelines you should follow for writingrung and branch logic.

Writing Rung LogicWhen you write rung logic, follow these guidelines:

• Sort the actions “to be taken” from the conditions “to be examined” for eachstatement of machine operation.

• Select the appropriate input instruction for each condition and the appropriateoutput instruction for each action.

Some input devices and input modules use inverse (negative) logic where a logicallytrue condition turns the bit off, and a logically false condition turns the bit on. Ifused incorrectly, these instructions can cause unexpected operation with damage toequipment or injury to personnel.

• Arrange input instructions on the left–hand side of the rung as shown in the tablebelow.

If you have multiple inputconditions and:

Then arrange the instructions:

all conditions must be true totake action (logical AND) ] [ ] [ ] [

in series

any of several conditions mustbe true to take action (logicalOR)

in parallel

] [] [

] [

a combination of AND and ORconditions must be true to takeaction

in series and parallel

] [] [

] [

!


5-6

• Arrange output instructions on the right–hand side of the rung as shown in thetable below.

If you program: Then arrange the instruction(s):

a single output instruction

( )

at the far right

multiple output instructions

Note All parallel outputs areenabled when the logicpath becomes true.

in parallel( )

( )

( )

a conditioned outputinstruction

in a separate output branch( )

( )] [

• Label each instruction with the name of the device it examines or controls.

• You can program as many instructions per rung as you want.

Rung Example

A statement of machine operation reads:

When LS1 and LS2 are closed, or when SW6 is closed, turn on FAN1 andBULB1.

Translate the statement to a rung as follows:

• The “when” indicates an input condition.

• The “and” indicates serial input conditions

• The “or” indicates parallel input conditions.

• The “turn on” portion of the statement indicates two outputs (in parallel).

• When input conditions provide a logically “true” path across the rung, the rung istrue and the outputs are energized.


5-7

The drawing below shows what a rung would look like for the above statement ofmachine operation with the outputs in parallel.

SW6

FAN1LS1 LS2

BULB1

Writing Branch LogicWhenever you program instructions in parallel, you must create branches. Follow theserules for input and output branching.

• The number of parallel branches allowed is limited only by processor memory.

• Branches must not overlap. (A branch cannot start inside another and end outsideit.) Branches may, however, be nested. See the section below.

For example, this is not allowed:

• An output branch must end with an output instruction.

For example, input instruction (A) is not allowed in that position:

A

Nested Branching

Input and output branches can be “nested” to avoid redundant instructions and toprovide more efficient programming. A “nested” branch is a branch that starts or endswithin another branch. You can nest branches up to four levels deep.


5-8

] [ ] [ ] [ ( )

] [

] [

] [

] [] [

] [

( )

( )] [

] [

Nested Input and Output Branches

] [

Nested branching can be converted into non-nested branches by repeating instructionsto make parallel equivalents.

] [ ] [ ] [ ( )

] [

] [

] [

Non-Nested Equivalent Parallel Branch

] [ ] [ ] [

] [

] [

( )

Nested Branch

A B C F

D

E

A B C F

D C

E

Execution Time and Branch Structure Considerations

In general, non-nested branches are more efficient than nested branches. Both of theexamples shown below accomplish the same result with the same number of outputinstructions; however, the non-nested branching example is evaluated approximately1 microsecond faster than the nested branching example.


5-9

Nested Branching

( )

( )

Non-Nested Branching

( )

( )

( ) ( )

Branches can only be nested four deep, but are otherwise limited only by processormemory.


5-10

Arranging Input Instructions

You can improve or impede the rate of program scan by how you arrange instructionswithin a rung based on these two considerations:

• Place instructions most likely to be false, first in a rung. Place instructions mostlikely to be true, last in a rung.

For example:

Most likelyto be FALSE

Most likelyto be TRUE

• Place the input path that is most likely to be true as the top path in a branch. Placethe less likely to be true input branches further down in the branch.

For example:

Path most likely to be true

less likely

least likely

Organizing Data Table Files

6-1

6 Organizing Data Table Files

This chapter shows you how to organize data storage for your programs. All of the datayour processor examines or changes is stored in files in data storage areas of memory.Data storage areas store:

• Data received from input modules

• Data to be sent to output modules; this data represents decisions made by theladder logic

• Intermediate results made by the ladder logic

• Preloaded data such as presets and recipes

In addition, the processor uses other areas of data storage to:

• Control instructions

• Store system status

The drawing below shows the relationship between I/O modules, data storage, andladder programs.

DATA STORAGE

I/O Image Files

Block transfer files

Other Data Files

LADDER PROGRAM

ExamineData

ReturnResults

Discrete Inputs

Analog Inputs

Discrete Outputs

Analog OutputsINPUT

MODULESOUTPUT

MODULES


6-2

Understanding Data Storage

The processor divides data storage into: types, files, elements and bits.

• Data storage is divided into types. Types let you specify different formats andranges to accommodate different types of data.

• Types are divided into files. – Files let you group and organize logically relateddata. When you need to access data, you specify the file in which the data isstored.

file #

integer

file #

File 999

DataTypes

file 7

• Files are made up of elements. Typically, these are 16–bit data values. When youneed to access this data, you specify it with a formatted address. For informationon address formats refer to the Hardware Interface Configuration User's Guide oryour Allen-Bradley documentation.

integer elements

2

10201

64

7779

File #

IntegerFile

sample data


6-3

• Each element contains multiple bits. This is the smallest division of data. A bitcontains a value of zero or one. When you need to access this data, you specify itwith a formatted address.

0276 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0

sample data

IntegerElement

Binary bit pattern for 276

• Some sections of data storage are used to control instructions. Within thesesections, data is subdivided into sub–elements at the bit or word level. When youneed to access this data, you specify it with a formatted address.

2760

432

Timer File #

Timer #

(preset .PRE)

(accumulated .ACC)

timer sub-elements samle data

1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(control word contains enabled (.EN), timing(.TT), and done (.DN) bits)

control

In addition to the processor–defined structures, you can organize the data in files intodata blocks that help group and organize logically related data. When you need toaccess this data, you specify only the starting address within the file instead of eachindividual address.

File #

Starting addr

up to 999

recipe “A" data

recipe “B" data

production counts

elements

(Length)

Starting addr(Length)

Starting addr(Length)


6-4

Organizing Data into Files and Data Blocks

When you organize data files, you can use processor–defined data files, where each filestarts at word 0, or sub–divide these files into user–defined data blocks, where youspecify the starting address of the first word in the data block.

When you organize data, group data by similar kind, such as:

• The result of calculations

• Inputs from analog modules

• Outputs to analog modules

• Batch recipes

You might also want to leave room for future expansion when grouping data. Do thisby leaving gaps between

• Data blocks within a file

• Groups of sequentially numbered files

• Modules in an I/O chassis

Note Gaps in the numbering system use several words of overhead memory for each file ordata block you skip. However, if you plan on programming online, gaps are necessarysince you cannot create or delete data files while in RUN mode. Use care when leavinggaps.

Follow these rules when organizing your data files:

• Group large amounts of related data into files.

• Address the data files from 3–999 as needed. The table on page 6-6 lists thedefault data table file numbers.

• Address the elements needed in each data file consecutively from 0–999.

• Address the words of I/O image data according to how you configured your I/O:

♦ 0–37 (octal) for PLC-5/10, -5/12, -5/15, -5/11, -5/20

♦ 0–77 (octal) for PLC-5/25, -5/30

♦ 0-177 (octal) for PLC-5/40

♦ 0-277 (octal) for PLC-5/60, -5/80


6-5

• When organizing bit data, address the bits in each element 0–15 (decimal) forbinary or integer files.

• When addressing I/O image bits, address them 00–07 or 10–17 (octal).


6-6

Default Data Table Files

The table below lists the default data table files. These are the data table files thatappear after you clear memory.

File Type: Last Address: Size (elements): Size (words):

O output O:037* 32* 32*

I input I:037* 32* 32*

S status S:31 32 32 for Original128 for New Platform

B binary (bit) B3/15 1 1

T timer T4:0 1 3

C counter C5:0 1 3

R control R6:0 1 3

N integer N7:0 1 1

F floating point F8:0 1 2

*depends on processor type

Addressing Data Table Files

7-1

7 Addressing Data Table Files

This chapter explains how to use the following types of formats for addressing data fileswhen you write your ladder programs:

• Logical address - an alpha–numerically coded format with punctuation to specifythe data location. For example: N23:0. See page 7-2.

• I/O image address - logical address format, but relates physical locations in theI/O chassis to memory locations in the I/O image file. For example: I:017/17. Seepage 7-6.

• Indirect address - logical address format, but lets you change address values inthe base address with your ladder program. For example: N[N7:6]:0. See page 7-8.

• Indexed address - index prefix (#) followed by a logical address format, but offsetby an index value from the processor status file. For example: #N23:0. See page7-10.

• Symbolic address - ASCII character name that relates the address (of an element,sub-element, or bit) to what it represents in the application. For example:MIXER_1. See page 7-12.


7-2

Specifying Logical Addresses

Use a logical address to access a bit, element, sub–element, data block, file, or I/Oimage bit. The format of a logical address corresponds directly to the location in datastorage.

1. Specify the data type and file number.

File numbers 0 through 8 are the default files. If you need additional storage, youcan create files by specifying the appropriate identifier and a file number from 9 to999. Refer to the table below.

Default Files User-Defined Files

File Type IdentifierFile

Number IdentifierFile

Number

Output O 0

Input I 1

Status S 2

Bit B 3 B

Timer T 4 T

Counter C 5 C

Control R 6 R

Integer N 7 N 3-999

Floating Point F 8 F

String* ST*

ASCII A

BCD D

Block Transfer* BT*

Message* MG*

PID* PD*

SFC Status* SC*

ControlNet Message* CT*

*File type only available on New Platform PLC-5 processors.

Note Although files 3 through 8 are defaults, they may be used for otherpurposes if deleted and then recreated as a different file type.

2. Include a colon (:) followed by the element number. You can substitute a semi–colon (;) for the colon (:) delimiter.


7-3

3. If you want to specify a bit number, include a front slash (/), period (.), or a space,followed by the bit number. A space appears as an underscore (_) character.

4 If you want to address a member, such as a done bit or an accumulated value,include a front slash (/), period (.), or a space, followed by the mnemonic. A spaceappears as an underscore (_) character.

The table below summarizes how to address different data structures.

To Specify theAddress of a:

Use TheseParameters:

ElementN9:22

File Type

File Number

Element Delimiter

Element Number

FileF8

File Type

File Number

Bit Within a Binary FileB3/245

File Type

File Number

Bit Delimiter

Bit Number

Bit Within a Control FileR6:7.DN

Element Number

Sub-Element Delimiter

Bit Mnemonic

For more information on the structure and addressing of the different data types, referto the 1785 PLC-5 Programmable Controllers Addressing Reference document.

Note Use the / delimiter only for addressing bit numbers. Do not use it to address data bitsby mnemonic. Never use it for a division symbol. The division symbol is the verticalbar ( | ).


7-4

The following table explains the examples shown above.

Valid Address: Type ofAddress:

Explanation:

N9:22 Element integer file 9, element 22

F8 File floating–point file 8

B3/245 Bit binary file 3, bit 245 (word 15, bit 5)

R6:7.DN Bit control file 6, element 7, done bit

Using Address MnemonicsAddress mnemonics let you address members at the word or bit level according toname. The available address mnemonics depend on the type of data file (timer,counter, control, etc.) and the program instruction that you want to address.

Certain PLC–5 data file elements are made up of multiple words. For example, Timerand Counter elements use 3 words of processor memory per element, whereas PD fileelements use 82 words per element. In order to address individual sub–elements or bitswithin these multi–word data types you must use word or bit mnemonics. Thesemnemonics fall into two categories, reserved and non–reserved.

Reserved mnemonics may be delimited in the manner described above for sub–elementwords or bits, but cannot be used in conjunction with the ( _ ) character as a symbolname. For example, the symbol name SYM_1_ACC is not valid (unless SYM_1 is thesymbol for a timer or counter, in which case PLC-5 A.I. Series will convert it toSYM_1.ACC and treat the _ACC as the accumulated value sub-element rather thanpart of a symbol).


7-5

The following is a partial list of reserved word (w) and bit (b) mnemonics. Moremnemonics can be found in the 1785 PLC-5 Programmable Controllers AddressingReference.

Timer Counter Control

.ACC (w) .ACC (w) .POS (w)

.PRE (w) .PRE (w) .LEN (w)

.EN (b) .CU (b) .EN (b)

.TT (b) .CD (b) .EU (b)

.DN (b) .DN (b) .DN (b)

.OV (b) .EM (b)

.UN (b) .ER (b)

.UA (b) .UL (b)

.IN (b)

.FD (b)

Non–reserved mnemonics can be accessed only by using the ( . ) delimiter. Forexample, if the symbol PID_LOOP1 is assigned to address PD21:0, then the setpointsub–element would be addressed as PID_LOOP1.SP but not as PID_LOOP1_SP orPID_LOOP1/SP.


7-6

Specifying I/O Image Addresses

Use an I/O image address to access an input or output bit in the I/O image table. Theformat of an I/O image address corresponds the physical location of the data in the I/Ochassis to the storage location in the I/O image table.

When you specify an I/O image address, include the following:

• Specify I for input or O for output.

• Include a colon (:) as a file delimiter followed by the I/O rack number: (00-37octal)

♦ 00-03 octal for PLC–5/10, -5/11, -5/12, -5/15, -5/20

♦ 00-07 octal for PLC–5/25, -5/30

♦ 00-17 octal for PLC–5/40

♦ 00-27 octal for PLC–5/60, -5/80

• Include the I/O group number (0-7).

• Include a front slash (/) as a terminal delimiter followed by the terminal number(0-7, 10-17).


7-7

The table below shows valid I/O image addresses.

To Specify This Address: Use These Parameters: In ThisFormat:

Input Image BitI for input2-digit I/O rack number

use 00-03 (or 00-07 PLC-5/25, -5/30)use 00-03 (or 00-17 PLC-5/40)use 00-03 (or 00-27 PLC-5/60, -5/80)

I/O group number (0-7)Terminal number (00-07, 10-17)

I:017/01

Output Image BitO for output2-digit I/O rack number

use 00-03 (or 00-07 PLC-5/25, -5/30)use 00-03 (or 00-17 PLC-5/40)use 00-03 (or 00-27 PLC-5/60, -5/80)

I/O group number (0-7)Terminal number (00-07, 10-17)

O:017/00

The following table shows some I/O image address examples.

Valid Address: Explanation:

I:017/01 Input rack 1, I/O group 7, terminal 1

O:017/00 Output rack 1, I/O group 7, terminal 0


7-8

Specifying Indirect Addresses

With indirect addressing, one component of a logical address is represented by anotherlogical address. The processor uses the value from the substitute address to form theindirect address. The substitute address is enclosed within brackets [ ]. For example, ifthe value in N7:0 is 13, then the indirect address T[N7:0]:0.ACC refers to addressT13:0.ACC. Only word addresses can be used to specify an indirect value (not bit ormulti-word addresses). Note that you cannot indirectly address I, O or S file types.

Follow these guidelines when specifying indirect addresses:

• You can indirectly address a file number, word number, or bit number.

• The substitute address must be one of the following types: N, T, C, R, B, I, O, orS. Any T, C, or R address used must be a word-length sub-member address, suchas T4:0.ACC.

• Enter the substitute address in brackets [ ].

Note Instructions with indirect addresses execute slower than instructions with directaddresses because the processor has to look up each indirect address.

Allocate addresses in the data table to include any indirect addresses you specify.The data table will not automatically expand to include indirect addresses.

Examples

Indirect AddressIndirect ComponentRefers To

If O:017 = 10, then theindirect address refers to

N[O:017]:8/4 a file number N10:8/4

T4:[O:017] an element number T4:10

N20:[O:017]/4 an element number N20:10/4

N20:8/[O:017] a bit number N20:8/10

The data table will expand to include an address used to specify an indirect address.For example, specifying the indirect address N11:[N22:33]/[N44:55] would cause thedata table to expand to include the following addresses: N11:0, N22:33, and N44:55.

!


7-9

When using indirect addressing, the indirect address must point to a valid data fileand/or element. During RUN mode operation, if the ladder execution comes acrossan invalid or out of range indirect address a run time error will occur and thePLC-5 processor will halt.

If you are using a New Platform processor prior to series E, and if an invalidaddress destination is used in an FLL or COP instruction, the instruction will beterminated AFTER one word has been written at the invalid address. Theprocessor continues to operate in run mode.

Note To monitor or troubleshoot invalid address occurrences, condition the indirect addressladder rung with a limit test of the indirect address to insure that the address stayswithin the intended range. Conditioning of rungs may be especially advisable if thePLC-5 processor has no control over the indirect address that is being set (that is, theaddress is determined by values from an I/O module or a peer processor).

If you are using a File Copy (COP) or a File Fill (FLL) instruction with EnhancedPLC-5 processors (Series D and earlier), and you specify an indirect address in thedestination parameter, you may write data outside of the intended data table fileand cause unpredictable controller operation.

To ensure that your program correctly references the intended memory location,when using indirect addressing, we highly recommend that your program performbounds checking via the ladder logic.

Although no error messages are reported with New Platform PLC-5 processors(Series D and earlier), when data is written outside of the intended data table filewith New Platform PLC-5 processors (series E and later), an indirect address out ofrange condition is detected, displaying one of the following fault codes:

This Fault Code Indicates this Fault

20 Indirect address out of range high

21 Indirect address out of range low

!

!


7-10

Specifying Indexed Addresses

Indexed addresses add an offset value to the given logical address to determine theactual address. Indexed addresses consist of a prefix ( # ) followed by a logical addressreferred to as a base address. The offset value to be added to the base address is storedin the processor status file, word S:24. For example, if S:24 has a value of 12, then theindexed address #N7:10 would actually reference N7:22 in the data table.

The value in S:24 can be positive or negative. The data table is not automaticallyexpanded to accommodate indexed addresses. For example, if N7 contains 20 elementsand S:24 contains a value of 30, then #N7:10 refers to an integer at address N7:40,which does not exist. That is, N7:40 is outside the bounds of file N7. This is referredto as crossing a file boundary, and causes a major fault.

The processor does not check indexed addresses to make sure that the addresses donot cross data table file boundaries. If the indexed address exceeds the data tablearea of memory, the processor initiates a run-time error and sets a major fault.

Follow these guidelines when specifying indexed addresses:

• Make sure the offset value (positive or negative) does not cause the indexed addressto exceed the file type boundary.

• When an instruction uses more than two indexed addresses, the processor uses thesame index value for each indexed address.

• Set the offset word to the index value you want immediately before enabling aninstruction that uses an indexed address.

File instructions manipulate the offset value stored at S:24. Make sure that youmonitor or load the offset value you want prior to using an indexed address; failureto do so could result in unpredictable machine operation with possible damage toequipment and/or injury to personnel.

When a User Error Handler, STI routine, or I/O Interrupt routine, is invoked, theS:24 value is stored, and when the routine ends, the original value is restored.Therefore, you can’t use these routines to set the value in S:24.

!

!


7-11

The following instructions manipulate the offset value in S:24:

BSL/BSR Bit Shift Left/RightDDT Diagnostic DetectFFL/FFU FIFO Load/UnloadLFL/LFU LIFO Load/UnloadFAL File Arithmetic and Logic

COP File CopyFLL File FillFSC File Search and CompareSQI/SQL/SQO Sequencer Input/Load/OutputFBC File Bit Compare

Indexed Addressing ExampleThe MVM instruction in this example uses an indexed address in both the source anddestination addresses.

Masked MoveSource #N7:10

0Mask 0033h

Dest #N11:50

MVM If the offset value stored in S:24 is 10, then theaddresses referenced in the instruction will be asfollows.

Base Address Offset Address

Source N7:10 N7:20

Destination N11:5 N11:15


7-12

Specifying Symbolic Addresses

With symbolic addresses, you can substitute a name for an address so the address willrelate physically to the application. For example, you could substitute the name LS1 forinput image bit I:007/10 to indicate the input from Limit Switch #1.

When you specify symbolic address, follow these guidelines:

• The symbol can contain up to 15 of the following characters:

♦ A - Z (upper case)

♦ 0 - 9

♦ _ ! @ % ^ & ( ) | { } \ ; = + - , < > ' ` ~ "

Note If you are using Structured Text, the characters $ ( ) | : ; + = - < and > areNOT valid in symbol names.

• You can substitute a symbolic address for both the element and bit addresses.

• Record the symbols you define and their corresponding logical addresses.

Note Do not use the % character in a symbol name even though it is allowed. Anyoccurrence of the % character in a symbol name will produce errors when importing orexporting a file.

To use symbolic addresses, you assign symbols to logical addresses with theprogramming software. Symbols are a feature of the programming software, not theprocessor. If you use PLC–5 A.I. on a terminal other than the one in which you definedsymbols, you will not have access to the symbol database you created. The softwarestores the database on the hard disk of the programming terminal that you used to enterthe symbols.

After you define the symbol for an existing logical address, you can use the symbolicaddress anywhere else in ladder logic to reference that same address.


7-13

The following table shows some examples of valid symbolic addresses.

Type of Address: Logical Address: Symbolic Address:

Input image I:015/00I:015/03I:015/06

LS1AUTO1SW1

Output image O:013/00O:013/02O:013/04

M1CL1L1

Element F10:0F10:1

CALC_1CALC_2

Note You can use a symbol when addressing a subelement of a word address. Assign asymbol to the word address and then append the subelement mnemonic to the symbolfor the word. For instance, if the symbol for T4:0 is TIMER, then the symbol forT4:0.DN is TIMER.DN.

SoftLogix 5 SymbolsIf you are using the SoftLogix 5 controller, Structure Names must start and end with aletter. Structure Names may NOT contain any of the following characters:

` ~ ! @ # $ % ^ & * ( ) - + = { } [ ] | \ : ; " " < > ? , . / or a space


7-14

Addressing Frequently Used Files

For the best memory organization, address your most frequently used instructionsbetween the end of the status file and physical word 256 for bit instructions or betweenthe end of the status file and physical word 4096 for element instructions.

Note Instructions programmed using bit addresses below word 256 and word addressesbelow 4096 use half as many storage words as addresses above these limits. Theprocessor can also access the addresses below these limits more quickly than addressesabove these limits.

Data table files are contiguous in memory.

I/O files 0 and 1

• are fixed at 32 words in PLC–5/10, –5/12, –5/15, -5/11, and -5/20 processors

• vary from 32–64 words in PLC–5/25, and -5/30 processors. The default is 32 inPLC-5/25 processors and 64 in PLC-5/30 processors.

• vary from 32–128 words (128 is the default) in PLC–5/40 processors

• vary from 32–192 words (192 is the default) in PLC–5/60 and -5/80 processors

Status file 2 is fixed at 32 words for Original PLC-5 processors and 128 words for NewPlatform PLC-5 processors. Files 3–999 vary in size. These files contain only thenumber of words corresponding to the highest address that you assign (see the drawingbelow).


7-15

output image

input image

status

binary, timer, counter, control,integer, floating point

File TypePLC-5/25PLC-5/15

Word # Word #File #

00

032-6432

164-12864

296-16096

256

4096

3-999according to your

application

Status File for PLC–5/10, PLC–5/12, and PLC–5/15 ProcessorsThe status file ends at word 95 for PLC–5/10, PLC–5/12, and PLC–5/15 processors.Use addresses B3:0 - B3:159 in binary file 3 for your most frequently used binaryaddresses. Use addresses up to word 4096 in files 4 and greater for your mostfrequently used element addresses.

Status File for PLC–5/25 ProcessorsThe status file ends at word 159 for PLC–5/25 processors if you use the entire input andoutput image files. Use addresses B3:0 - B3:95 in binary file 3 for your most frequentlyused binary addresses. Use addresses up to word 4096 in files 4 and greater for yourmost frequently used element addresses.

Using a Selectable Timed Interrupt

8-1

8 Using a Selectable Timed Interrupt

A selectable timed interrupt (STI) tells the processor to periodically interrupt programexecution (due to an elapsed timer) to run an STI program once to completion. Then,the processor resumes executing the original program file from where it wasinterrupted. For example, you might want to use an STI to check the status of yourPLC–5 on the Data Highway link. You can also use an STI to perform immediateblock transfers to local I/O.

This chapter shows you how to set up and use a selectable timed interrupt (STI).


8-2

Writing STI Ladder Logic

Follow these guidelines when writing ladder logic for an STI program file:

• Store the STI program in a ladder file.

• Make sure the interrupt interval you specify (in word S:30) is longer than theexecution time of the STI program. If it is not, an STI overlap occurs and theprocessor sets a minor fault bit at word 10, bit 2 of the status file.

• Note that the processor’s watchdog timer continues to run while the processor runsan STI program.

Note If the interrupt occurs during the execution of an instruction, the processor stopsexecuting the instruction, scans the interrupt file once to completion, and then resumesexecuting the instruction. In effect, execution of an STI is transparent to programexecution time unless you specify too short an interval. An interval that is too shortcan cause the watchdog timer to time out or cause excessively long program scans.

Using a Selectable Timed Interrupt

8-3

Setting Up an STI

To set up an STI, you need to:

• Create the ladder file and enter the ladder logic

• Store the location (file number) of the STI program in the processor status file,S:31

• Store the setpoint (interval) in S:30

Use ladder logic or the processor configuration screens to enter this information. Seethe PLC–5 A.I. Series Software Reference manual.

Storing the Location of the STI File in the Processor Status FileThe table below shows what to store in the processor status file for STI operation.

STI Characteristic: Explanation:

Setpoint (interval) Address S:30 – enter the setpoint of the STI in milliseconds (1 –32,767). If you do not use an STI, enter 0.

Program file number Address S:31 – enter the file number of the ladder file thatcontains the STI program.

Entering a 0 in this field disables the interrupt.

For example, you could enter a 7 in S:31 and a 15 in S:30. This will cause theprocessor to execute ladder file 7 every 15 milliseconds.

You can use only one STI at any particular time. However, you can enable or disablethe interrupt, or change to a different interrupt file, or change the time betweeninterrupts using ladder logic to change the values in word 30 and word 31 of theprocessor status file.

Note For Original PLC-5 processors: If you disable the STI through ladder logic (byplacing a 0 in word 30) and then later re–enable the STI, it could take the processor aslong as 255 milliseconds before the processor enables the STI.

Note For New Platform PLC-5 processors: If you disable the STI through ladder logic (byplacing a 0 in word 30), it could take the processor up to 100ms to re–enable the STI.If you disable the STI by writing a 0 to word 31, the processor uses the value in word30 to determine how often to check for a non–zero value in word 31.


8-4

STI programs lengthen the program scan by an amount equal to the interrupt delaymultiplied by the number of times the interrupt occurs during the program scan.

If you are using a New Platform PLC-5 processor, note that the STI last scan time andSTI maximum scan time are stored in the status file (S:53 and S:54 respectively).

Block Transfers Used Within an STIYou can program immediate block transfers to a local I/O chassis using the STIprogram; the block transfer executes as if it was an immediate block transfer in a ladderprogram.

Original PLC-5 Processors

Do not use the STI for block transfers to remote I/O because the STI can lengthenprogram scan. If you program a block transfer in an STI to a remote I/O chassis, theSTI delays program scan until the processor completes the immediate block transfer. Ifthe immediate block transfer fails, the program scan could stop for 1/2 second, haltingmachine control.

New Platform PLC-5 processors

You can use the STI for a block transfer to remote I/O in New Platform PLC-5processors. Remote block transfer instructions in an STI cause the processor to resumeexecuting lower priority ladder programs while waiting for the block transfer tocomplete. If you want the STI to run to completion before returning to your main logicprogram, include a UID (User Interrupt Disable) and UIE (User Interrupt Enable)instruction pair in your STI program file. Place the block-transfer instruction inside ofa UID/UIE pair.

!

Using a Processor Input Interrupt

9-1

9 Using a Processor Input Interrupt

New Platform Processors Only

You can use a processor input interrupt (PII) as an event-driven interrupt or in high–speed processing applications. For example, use a PII if you need to count inputsquickly to track production (such as in a canning line). Another instance in which youwould use a PII is if your application calls for an immediate input update when a part isseen on a conveyor, and then requires an immediate output update to perform the nextaction (for example, when a part moving down a conveyor line is detected, you mayneed to stop it so the next piece can be added).

Your PII program can contain these immediate update instructions to complete thehigh–speed control function. As your ladder program is running and the inputcondition occurs, the processor interrupts program execution and runs the PII programfile. Then, the processor resumes executing the program file from where it wasinterrupted.

This chapter shows you how to set up and use a processor input interrupt (PII).


9-2

Writing PII Ladder Logic

Follow these rules when writing ladder logic for a PII program file:

• Store the PII program in a ladder file.

• Make sure the input condition (to cause the interrupt) doesn’t occur faster than theexecution time of the PII program. If a second input condition occurs before theinterrupt program has finished executing for the first input condition, a PII overlapoccurs and the processor sets a minor fault bit at S:10/12.

The timing for a PII is as follows:

♦ 1 ms to switch to the PII task

♦ PII ladder logic execution time

♦ 1 ms to return to executing the control program

Since you need to allow at least 1 ms to run your PII logic, define a PII time of atleast 3 ms to help prevent PII overlaps.

• Be aware that the processor’s watchdog timer continues to run while running a PIIprogram.

• A PII can detect an event within 100 µs; however, you must allow at least 3 msbetween successive PII events.

Note If the interrupt occurs during the execution of an instruction, the processor stopsexecuting the instruction, scans the interrupt file once to completion, then resumesexecuting the instruction. In effect, execution of a PII is transparent to programexecution time unless you program too many too often. Too many PIIs too often cancause the watchdog timer to time out or cause excessively long program scans.

Consider the following guidelines when you create your PII:

• Do not use 2-slot addressing when using PIIs.

• Do not use 1771-IG or -IGD, 8- and 16-point TTL modules for the PII. Use the1771-IQ16 input module instead. Since the module’s input delay filter isselectable, you can set the delay to 0 or about 200 µs.

• Avoid using a block-transfer module in the processor-resident rack with a PIIconfigured because you could miss an input pulse while a block-transfer of data isin progress. If you need to use block-transfers, however, make sure that a PII inputpulse is at least 400 µs which causes the block-transfer not to affect the PII.


9-3

• Online editing affects the performance of a PII routine. A PII cannot interrupt theprocessor while it is managing its memory due to the online edits being made. ThePII input must be on for an amount of time slightly greater than the actual timerequired to complete the online edits. If not, the PII does not execute.

• Clear S:51 in one of two ways:

♦ using a CLR instruction (see the example on page 9-5)

♦ placing a MOV (move) instruction on the last rung in the PII file. Move a 0into S:51 to reset the PII bits before finishing the PII file.

Note If S:51 is not cleared, a PII overlap bit is set on that status page, causing aminor fault.


9-4

PII Application Examples

You can use a PII program in one of two ways, counter mode or bit transition mode.These are described below.

Using Counter ModeUsing counter mode, you make use of the New Platform PLC-5 processor's internalcounter. Configure the PII with a preset value so that the hardware counts your inputcondition and then runs the PII when the preset equals the accumulated value.

The actual PII ladder logic then only needs to contain the output that you want to occur.

Using Bit Transition ModeUsing bit transition mode, you configure the PII to occur every time the input conditionis true (versus counting x input conditions and then running the PII). To get the sameresult as counter mode, you would have to include a counter in your PII ladder programto count the input events, and then set the output when the counter reaches the presetvalue.

Bit Transition Mode Example

For example, you want to count tablets as they leave the production line at a rate of 100tablets per second. The machinery packs 100 tablets per package. Assume an opticalswitch detects each tablet.

The PII program must:

• Count 100 tablets per group

• Set an output at the 100th tablet

• Reset the counter for the next group


9-5

CUCOUNTER UP

Counter

Preset

Accum

C5:0

100 DN

C5:0

DN

Output

CTU

RES

Output C5:0

U

C5:0.CU

0

CLR

CLEAR

Destination S:51

The output image bit remains set until the next count.


9-6

Setting Up a PII

To set up a PII, you need to:

• Store the configuration information of the PII program in the processor status file

• Create the ladder file and enter the ladder logic

Use the processor configuration screens to enter this information.

PII configuration changes are not put into effect until the processor goes from Programto Run or Test mode. Also, if the input word number specified (S:47) is not in the localrack or if there is not an input module in the slot addressed, a minor fault bit (S:10/11)is set at mode transition.

For more information on using the processor configuration screens to enter thisinformation, see the processor configuration chapter in the PLC–5 A.I. Series SoftwareReference manual.

Configuring the PIITo configure a PII, you need to specify the information shown in the table below:

PIICharacteristic:

StatusFile Word:

Description:

program filenumber

S:46 Enter the number of ladder file that contains the PIIprogram.

module group S:47 Enter the assigned rack number and I/O group number ofthe input to monitor (for example 21 for rack 2, group 1).Do not enter the address.

bit mask S:48 For each module group bit (specified in S:47 above):Enter 0001 (1 in hexadecimal) to monitor the bitEnter 0000 (0 in hexadecimal) to ignore the bit.

compare value S:49 Each module group (specified in S:47) has a bit used wencontrolling a PII through bit transition. For a false to truetransition to count (bit trigger), enter 0001 (hexadecimal).For a true to false transition to count (event trigger), enter0000 (hexadecimal).


9-7

PIICharacteristic:

StatusFile Word:

Description:

down count S:50 Enter a preset value to determine how many instances ofa condition will occur before the interrupt. Valid range is 0– 32,767. Enter a 0 or 1 if you want the interrupt to occurevery time.

For example, in the PII Application Example on page 9-4,you would enter 100 in S:50.

For more information on setting these values on the Processor Configuration screen, seethe processor configuration chapter in the PLC–5 A.I. Series Software Referencemanual.

Block Transfers Used Within a PIIYou can use the PII for a block transfer to remote I/O in New Platform PLC-5processors. Remote block-transfer instructions in a PII cause the processor to resumeexecuting lower priority ladder programs and STIs while waiting for the block transferto complete. If you want the PII to run to completion before returning to your mainlogic program, include a UID (User Interrupt Disable) and UIE (User Interrupt Enable)instruction pair in your PII program file. Place the block-transfer instruction inside of aUID/UIE pair.


9-8

Monitoring a PII

When the PII is generated, the processor updates the PII Return Mask and the PIIAccumulator in the status file. Use the processor status screen to monitor PIIs. Forinformation on using the processor status screen, refer to the PLC-5 A.I. SeriesSoftware Reference manual. The PII related status addresses are described below.

PII Return MaskThe PII return mask (S:51) displays the bit transitions that caused the interrupt. Youcan then use this information to condition other rungs in your ladder program.

Note If one of these bits is already set (that is, a previous interrupt set the bit), the processorsets a minor fault (S:10/12) to indicate a possible PII overlap.

If you want to monitor this overlap, make sure the last rung in your PII program clearsthis return mask in the status file.

PII AccumulatorThe PII Accumulator (S:52) displays the number of conditions that occurred before theinterrupt. This value should match the value in the counter field of your configurationinformation. If these values do not match:

• The interrupts are not executing when they are supposed to

• You are trying to count too many events

• The events are happening too quickly to count

PII Scan TimesThe processor stores the scan times of the PII routine in:

• Last scan time – S:55

• Maximum scan time – S:56

Writing a Fault Routine

10-1

10 Writing a Fault Routine

You can write a fault routine that the processor runs when it detects a major fault. Ifyour processor faults, you can tell the processor to interrupt the current program, runyour fault routine, resetting the conditions for running your process. Then you canhave the processor continue with the original program.

This chapter shows you how to set and write a fault routine and how to protect yourprocessor from powering up in run mode after a power loss.


10-2

Using Fault Routines

You can use a fault routine to specify how a processor responds to a major fault. Youcan also use a fault routine to provide protection from powering up in run mode whenthe processor recovers from a power loss.

Responses to a Major FaultWhen the processor detects a major fault, the processor immediately interrupts thecurrent program. If a fault routine exists (specified in S:29 as a fault routine), theprocessor runs that fault routine program.

Depending on the type of fault, the processor:

• returns to the current ladder program file if the processor can recover from thefault

• enters fault mode if the processor cannot recover from the fault

For example, the following rung includes an instruction which causes a major fault:

] [

A B C

Causes amajor fault

In the example above, the processor runs the fault routine after detecting the fault. Ifthe fault routine resets the faulted bits, the processor returns to the next instruction inthe program file following the one that faulted (instruction B) and continues executingthe remainder of the rung.

If you do not program a fault routine for fault B, the processor immediately faults.

The bits in word 11 of the processor status file indicate the type of major fault. Thefollowing table describes the fault associated with each bit.


10-3

This bitin S:11: Indicates this type of major fault:

00 corrupted program file (see fault codes 10–19 in the table on page 10-4)

01 corrupted address in ladder program (see fault codes 20–29 in the table onpage 10-4)

02 programming error (see fault codes 30–49 in the table on page 10-4)

03 processor detected an SFC fault (see fault codes 71–79 in the table on page10-4)

04 processor detected an error when assembling a ladder program file (see faultcode 70 in the table on page 10-4); duplicate LBLs found

05 start–up protection fault . The processor sets this major fault bit whenpowering up in Run mode if the user control bit S:26/1 is set. If your faultroutine does not reset this bit, the processor inhibits startup.

06 peripheral device fault

07 user–generated fault; processor jumped to fault routine (see fault codes 0–9in the table on page 10-4)

08 watchdog faulted

09 system is configured wrong (see fault codes 80-88 in the table on page 10-4)

10 recoverable hardware error

11 * MCP does not exist or is not a ladder or SFC file

12 * PII file does not exist or is not a ladder or SFC file

13 STI file does not contain ladder logic or does not exist

14 fault routine does not contain ladder logic or does not exist

15 faulted program file does not contain ladder logic

* This fault applies to New Platform PLC-5 processors only.

Major Fault CodesThe following table lists major fault codes. The processor stores the fault code in word12 of the processor status file.


10-4

This faultcode: Indicates this fault: The fault is:

00 – 09 reserved for user–defined fault codes

10* run–time data table check failed

11* bad user program checksum

12 bad integer operand type, restore new processor memory file

13 bad mixed mode operation type, restore new processor memory file

14 not enough operands for instruction, restore new processor memory file

15 too many operands for instructions, restore new processor memory file

16 corrupted instruction, probably due to restoring an incompatibleprocessor memory file

17 can’t find expression end; restore new processor memory file

18 Missing end of edit zone; restore new processor memory file

19* download aborted

20 you entered too large an element number in an indirect address

21 you entered a negative element number in an indirect address

22 you tried to access a non-existent program file

23 you used a negative file number, you used a file number greater than thenumber of existing files, or you tried to indirectly address files 0, 1, or 2

24 you tried to indirectly address a file of the wrong type

Recoverable – thefault routine caninstruct theprocessor to clearthe fault and thenresume scanningthe program.

A fault routineexecutes when anyof these faultsoccur.

30 you tried to jump to one too many nested subroutine files

31 you did not enter enough subroutine parameters

32 you jumped to an invalid (non–ladder) file

33 you entered a CAR routine file that is not 68000 code

Non-recoverable –the fault routine willbe executed butcannot clear majorfault bit 2.

34 you entered a negative preset or accumulated value in a timerinstruction

35 you entered a negative time variable in a PID instruction

36 you entered an out–of–range setpoint in a PID instruction

37 you addresses an invalid module in a block transfer, immediate input, orimmediate output instruction

Recoverable

38 you entered a return instruction from a non–subroutine file

39* FOR instruction with missing NXTNon-recoverable

40 the control file is too small for the PID, BTR, BTW, or MSG instruction Recoverable


10-5


41* NXT instruction with missing FOR

42 you tried to jump to a non-existent label

43* file is not an SFC

44 error using SFR. This error occurs if:

• you tried to reset into a simultaneous path

• you specified a step reference numer that is not found or is not tiedto a step (it is a transition)

the previous SFR to a different step is not complete


45 invalid channel number entered

46 – 69 reserved

70 the processor detected duplicate labels

71 the processor tried to start an SFC subchart that is already running

72 the processor tried to stop an SFC subchart that isn't running

73 the processor tried to start more than the allowed number of subcharts

74 SFC file error detected

75 the SFC has too many active functions

76 SFC step loops back to itself

77 the SFC references a step, transition, subchart, or SC file that ismissing, empty, or too small

78 the processor cannot continue to run the SFC after power loss

79 you tried to download an SFC to a processor that cannot run SFCs



80 you incorrectly installed a 32–point I/O module in a 1–slot configuration(Original PLC-5 processors)

you have an I/O configuration error (New Platform PLC-5 processors)

81 you illegally set an I/O chassis backplane switch by setting both switch 4and 5 ON

82* illegal cartridge type for selected operation. This error also occurs if theprocessor doesn't have a memory module, but the backplane switchesare set for a memory module. Make sure the backplane switches arecorrect (set switch 6 ON and switch 7 OFF if the processor doesn't havea memory module).

83* user watchdog fault

84* error in user–configured adapter mode block transfer

85* memory module bad

86* memory module is incompatible with host



10-6


87* scanner rack list overlap

88 Scanner channels are overloading the remote I/O buffer; too much datafor the processor to process. If you encounter fault code 88, review theguidelines for assigning racks in the Allen-Bradley documentation thatcame with your processor. Specifically, make sure you:

• group together 1/4-racks and 1/2-racks of each logical rack. Do notintersperse these with other rack numbers.

if using complementary I/O addressing, treat complementary rackaddresses individually when grouping racks; primary rack numbers areseparate from complement rack numbers.


90 Sidecar module extensive memory test failed. Call your Allen-Bradleyrepresentative for service

91 sidecar module undefined message type

92 sidecar module requesting undefined pool

93 sidecar module illegal maximum pool size

94 sidecar module illegal ASCII message

95 sidecar module reported fault, which may be the result of a bad sidecarprogram or of a hardware failure

96 sidecar module not physically connected to the PLC-5 processor

97 sidecar module requsted a pool size that is too small for PC3 command

(occurs at power-up)

98 sidecar module first/last 16 bytes RAM test failed

99 sidecar module-to-processor data transfer faulted

100 processor-to-sidecar module transfer failed

101 sidecar module end of scan transfer failed

102 the file number specified for raw data transfer through the sidecarmodule is an illegal value

103 the element number specified for raw data transfer through the sidecarmodule is an illegal value

104 the size of the transfer requested through the sidecar module is an illegalsize

105 the offset into the raw transfer segment of the sidecar module is anillegal value

106 sidecar module transfer protection violation; for PLC-5/26, -5/46, and -5/86 processors only



200 ControlNet output transfer missed

201 ControlNet input data missed

Recoverable


10-7


202 ControlNet diagnostic data missed

203 ControlNet schedule transmit data overflow

204 ControlNet configuration too complex for the PLC-5 processor

205 ControlNet configuration exceeded PLC-5 bandwidth

* This fault applies only to New Platform PLC-5 processors.

Note If the PLC–5 processor detects a fault in the fault routine (double fault condition), thePLC–5 goes directly to fault mode without completing the fault routine.


10-8

Programming a Fault Routine

If you choose to program a fault routine, first examine the major fault informationrecorded by the PLC–5 and decide whether to do the following before the PLC–5processor automatically goes to fault mode:

• Set an alarm

• Clear the fault

• Shutdown in an orderly manner

Upon detecting a major fault, the processor immediately suspends the program file itwas running and, if programmed, runs the fault routine file once to completion. If theprocessor does not run a fault routine, or the fault routine does not clear the fault, theprocessor automatically switches to fault mode.

Set an AlarmYou may need an alarm to signal when a major fault occurs. Put this rung first in yourfault routine program and combine it with a counter.

outputalarm

You can also set an alarm in your fault routine to signal when the fault routine clears amajor fault.

Clearing the FaultIf you decide to clear the fault in the fault routine, place the ladder logic for clearingthe fault at the beginning of the fault routine. You can compare the fault code with areference.

Compare the Fault Code with a Reference

Identify the possible major faults and then select only those your application will let yousafely clear. These are your reference fault codes.


10-9

From the fault routine, examine the major fault code that the processor stores in S:12.Use an FSC instruction to compare the fault code to the reference file that contains“acceptable” fault codes (word–to–file comparison). If the processor finds a match, theFSC instruction sets the found (.FD) bit in the specified control structure. Use a CLRinstruction to clear the fault in S:11. Then jump to the end of the fault routine toquickly complete running the fault routine.

In the drawing below, #N10:0 is the reference file.

JMP

CLR

CLEAR

Dest S:11

0

RES

R6:0

] [R6:0

FD

10

] [LBL

10

TND

EN

FSC

FILE SEARCH/COMPARE

Control

Length

Position

Mode

R6:0

20

0

ALL

DN

ERExpression

S:12 = #N10:0

•••

•••

END


10-10

The processor completes the scan of the fault routine. If the routine clears S:11, theprocessor returns to the program file and resumes program execution. If the faultroutine does not clear S:11, the processor executes the rest of the fault routine and goesinto FAULTED mode.

Note If the fault routine clears the major fault, the processor completes the fault routine andreturns to the next instruction in the program file after the one that contained thefaulted instruction. The remainder of the rung with the faulted instruction is executedas if the rung were false. It appears that the fault never occurred. The cycle ofrecurring fault routine execution continues until you correct the major fault.

Using Shutdown LogicShutdown programming considerations should include the following:

• Store initial conditions and reset other data to achieve an orderly start–up later.

• Monitor the shutdown of critical outputs. Use looping if needed to extend thesingle fault routine scan time up to the limit of the logic processor watchdog timerso your program can confirm that critical events took place.

Testing a Fault RoutineTo test a fault routine, use a JSR instruction to the fault routine. Send a fault code asthe first parameter of the JSR instruction. The processor stores the fault code in statusword 12 and sets the corresponding bit in word 11.

You may detect and set your own faults using fault codes 0–9 or by using theprocessor–defined fault codes 12–80.


10-11

Setting Up a Fault Routine

You can write multiple fault routine programs and store them in multiple fault routinefiles, but the logic processor runs only one fault routine program when the PLC–5detects a major fault. The number of the fault routine the PLC–5 runs is stored in word29 of the processor status file. Typically, you enter a fault routine file number with theprogramming software and change the specified fault routine file from the ladderprogram.

To set up a fault routine, you need to:

• Enable the fault routine

• Change the specified fault routine from ladder program, if necessary

• Create the program file and enter fault routine logic

Enabling a Fault RoutineTo enable a fault routine, store the program file number (3–1999), of the file thatcontains the fault routine logic, in word 29 of the processor status file. When theprocessor encounters a major fault, the processor runs the fault routine logic to handlethe fault.

If you do not specify a program file number, the processor immediately enters faultmode after detecting a fault.

Changing the Fault Routine from Ladder LogicYou can change the specified fault routine from ladder logic by copying a new faultroutine file number into word 29 of the processor status file.

The following drawing shows an example program for changing the fault routine filenumber.

MOV

MOVE

Source

Dest

12

S:29


10-12

Be sure not to corrupt the program-file number of the fault routine, nor use thesame file for any other purpose. If the file number you specify results in a non-existent fault routine, the processor immediately enters fault mode after detecting afault. Unexpected machine operation may result with damage to equipment and/orinjury to personnel.

Clearing a Major FaultYou can clear a major fault with one of the following methods:

• Use the programming software to clear the major fault.

For more information about using the programming software to clear major faults,see the PLC–5 A.I. Series Software Reference manual.

• Turn the keyswitch on the PLC–5 processor from REM to PROG to RUN.

Note Clearing a major fault does not correct the cause of the fault. The PLC–5 processormight continue to repeat the fault cycle until you correct the cause(s) for the majorfault.

!


10-13

Setting Power–Up Protection

You can set your processor so that after a power loss the processor does not come up inrun mode. Bit 1 in word 26 of the processor status file sets power–up protection. Thetable below shows the states for this bit.

If S:26/1 is: Then after power loss:

Set (1) the processor scans the fault routine before returning to normal programscan

Reset (0) the processor powers up directly at the first rung on the first program file

Set word 26, bit 1 manually from the Processor Status screen (see the PLC–5 A.I. SeriesSoftware Reference manual), or you can latch this bit through ladder logic. When set,the processor scans the fault routine once to completion after the processor recoversfrom a power loss. You can program the fault routine to determine whether theprocessor’s status will let the processor respond correctly to ladder logic and whether toallow or inhibit the startup of the processor.

Allowing or Inhibiting StartupBit 5 of status word 11 controls whether the processor can start up after a power loss.After a power loss, the processor automatically sets this bit. The table below showshow you can change this bit from your fault routine.

If the Fault RoutineMakes S:11/5: Then:

Set (1) the processor faults at the end of scanning the fault routine;leave this bit set to inhibit startup.

Reset (0) the processor resumes scanning the processor memory file;reset this bit to allow startup

Note You can use JMP and LBL instructions to scan only the portion of the fault routineassociated with a particular fault or power–up condition.

Using Adapter Mode

11-1

11 Using Adapter Mode

An Original PLC-5 processor in adapter mode can communicate with the local I/Ochassis and with a supervisory processor. A New Platform PLC-5 processor can scanlocal I/O and remote I/O and communicate with a supervisory processor.

If you have your processor configured for adapter mode, use this chapter forinformation on how a PLC–5 processor transfers data.


11-2

Using Adapter Mode

Adapter mode communication allows you to connect independent programmablecontrollers via the remote 1771 I/O communication network for distributed control.You can monitor status between the supervisory PLC-5 processor and the adapterPLC-5 processor at a consistent rate. That is, the throughput of the remote I/Ocommunication network is unaffected by programming terminals and other non–controlrelated communications, such as message instruction transmissions, on the DH+ link.

Supervisoryprocessor

Adapter modeprocessor

1771 I/O

DL40

remote I/O link

message display

•••

Using Adapter Mode

11-3

Operating in Adapter Mode

In adapter mode:

• Your PLC–5 processor appears to the supervisor as a remote I/O adapter

♦ in a 8– or 16–slot chassis for an Original PLC-5 processor

♦ in a 4–, 8–, 12– or 16–slot chassis for a New Platform PLC-5 processor

• Your PLC–5 processor transfers I/O data and status data using discrete transfersand block transfers

• An Original PLC-5 processor scans ladder logic, monitors and controls its ownlocal I/O

• A New Platform PLC-5 processor scans ladder logic, monitors and controls itslocal I/O and remote I/O simultaneously (due to the different channelconfigurations)

• Your PLC–5 processor provides concurrent communication over Data HighwayPlus

If the supervisory processor is a PLC–3 processor, the 1775–S4A or 1775–S4B scannermust be series B, revision A or later.

Configuring an Original PLC-5 Processor for Adapter ModeWhen you configure your processor for adapter mode, you set switch assemblies SW1and SW2, as described in the 1785 PLC–5 Family Programmable Controllers -Hardware Installation Manual (Allen–Bradley Publication 1785–6.6.1). Follow thesesteps to configure your processor:

1. Select adapter mode on switch assembly SW1.

2. Assign a rack address (rack number 0-77 octal) on switch assembly SW2. (Therack number range is determined by the processor type of the supervisory processorwhich can be a PLC-3, PLC-5 or PLC-5/250 processor.) The supervisory processoruses this address to reference the adapter–mode processor.

3. Specify the simulated chassis size, either a half or full rack, and the correspondingfirst I/O group on switch assembly SW2. The chassis size and first I/O groupdetermine the number of discrete data words (4 words for a half rack, 8 words for afull rack) the processor transfers to and from the supervisory processor during thesupervisory processor’s remote I/O scan.


11-4

The actual size of the chassis has no bearing on the simulated size of the chassis.

Note In adapter mode, the processor reserves rack 3 I/O image tables (I:30-37and O:30-37) for I/O communication with the supervisory processor.

4. If you use 1/2–slot addressing with a 16–slot I/O rack, you need to use rack 3 I/Oimage tables of the adapter mode processor for backplane communication withlocal I/O. In this case, create an adapter image file. (See page 11-9 in thischapter)

Configuring a New Platform PLC-5 Processor for Adapter ModeTo configure communications for a New Platform PLC-5 processor, use the ProcessorConfiguration and Channel Configuration screens. The default channel for adaptermode is 2A. To configure your New Platform processor, see the PLC–5 A.I. SeriesSoftware Reference manual.

Using Adapter Mode

11-5

Transferring Discrete I/O and Block Data

There are three methods for transferring data in adapter mode:

• Discrete I/O transfer (using rack 3)

• Discrete I/O transfer (using an adapter image file)

• Block transfer

The processor performs the transfer of discrete I/O and block data in the same way.The processor scans the processor memory file to read inputs and control outputs. Theprocessor scans local I/O and block data during the I/O scan and the I/O update issynchronous to the program scan. The drawing below shows how the processortransfers discrete I/O in adapter mode.

Scanner

Supervisor

OtherRacks

Remote I/OBuffer

LocalRack

Local I/O

Remote I/OScan

Remote I/O

x y

x y

read inputs

write outputs

read inputs

write outputs

I/O Scan

Housekeeping

ProgramScan

Immediate I/OIOT (x)IIN (y)

End

Adapter ModeProcessor

Ada

pter

1-3

ms

typi

cal


11-6

The adapter processor and the supervisory processor automatically transfer discrete databetween themselves via the supervisory processor’s remote I/O scan. During eachremote I/O scan:

• if the supervisory processor is an Original PLC-5, it transfers either 4 or 8 words(depending on whether the adapter processor is configured as half rack or full rack)of its output image table to the corresponding input image file of the adapterprocessor. If you are using a New Platform processor, it transfers 2, 4, 6 or 8words depending on whether the adapter processor is configured as a 1/4, 1/2, 3/4or full rack)

• if the adapter processor is an Original PLC-5, it transfers 4 or 8 words of its outputimage file to the corresponding input image table of the supervisory processor. Ifyou are using a New Platform processor, it transfers 2, 4, 6 or 8 words dependingon whether the adapter processor is configured as a 1/4, 1/2, 3/4 or full rack.

The following drawing shows the transfers between the supervisory output image tableand the adapter input image file, and between the adapter output image file and thesupervisory input image table.

Using Adapter Mode

11-7

0003040710131417 0003040710131417

0003040710131417 0003040710131417

Word*01234567

Word*01234567

Supervisory Processor Adapter-Mode ProcessorI:30 - I:37 (or adapter image file)

Supervisory Processor Adapter-Mode ProcessorO:30 - O:37 (or adapter image file)

Supervisory ProcessorPLC-2 0X0-0X7PLC-3 OXX0-OXX7PLC-5 O:X0-O:X7

Supervisory ProcessorPLC-2 1X0-1X7PLC-3 IXX0-IXX7PLC-5 I:X0-I:X7

Output ImageTable

Input ImageFile

Input ImageTable

Output ImageFile

* Word 0 in an Original PLC-5 processor is reserved for block transfer and status; ifyou are using a New Platform PLC-5 processor, bits 00-07 are available for user data

Note If data from the supervisory processor is intended to control outputs of the adapterprocessor, the ladder logic in the adapter processor must move the data from theadapter processor’s input image table (I/O rack 3 or the adapter image file) to itsoutput image table (local I/O) with XIC and OTE instructions for bit data or MOV andCOP instructions for word data.

If you want the supervisory processor to read data from a data file in the adapterprocessor, ladder logic in the adapter processor must move that data to the adapterprocessor’s output image table (I/O rack 3 or the adapter image file) for transfer to thesupervisory processor.


11-8

Programming Discrete Data Transfers

For the supervisory processor to read data from the adapter processor, you have to makesure the adapter processor moves the correct data into the output image file (or theadapter image file) for the adapter processor. For the adapter processor to use datafrom the supervisory processor, the adapter processor has to move incoming data fromits input image file.

Using Rack 3Rack 3 is the default discrete transfer file for Original PLC-5 processors. If you areusing a New Platform processor, you can use any file for discrete transfer, includingrack 3.

Typically, each output instruction in one processor should have a corresponding inputinstruction in the other processor. The rack number determines the addresses you use:

• The ladder logic in the supervisory processor uses the rack number (0-77 octal) ofthe adapter processor. (The rack number range is determined by the processor typeof the supervisory processor which can be a PLC-3, PLC-5 or PLC-5/250processor.)

• Condition the ladder logic with bit 10 octal (if using rack 3 I/O image). When set,this bit indicates a communication failure between the adapter and supervisoryprocessors.

• The ladder logic in the adapter processor uses I:031-037 for input data and O:031-037 for output data, unless you specify a special adapter image file. To specifyrack 3 for New Platform PLC-5 processors, use input I:024 and output 0:024decimal; the processor interprets these as I:030 and O:030 in octal.

Using Adapter Mode

11-9

Creating an Adapter Image File - Original PLC-5 ProcessorsIf you use 1/2–slot addressing in a 16–slot chassis, you need rack 3 for scanning localI/O on the adapter processor. In this case, you can create an adapter image file fortransferring data. Before you create an adapter image file, make sure these conditionsare true:

• The PLC–5 processor is in adapter mode.

• The adapter–mode processor is in a 1771-A4B I/O chassis.

• You are using 1/2–slot addressing.

• You have not inhibited rack 3 by setting the rack inhibit bit 3 in processor statusword 27

To create the adapter image file, create a 16–word integer file. This file must be 16words regardless of whether you use 4–word or 8–word transfers. This file must be aunique integer file, for use only as an adapter image file. Words 0-7 are used foroutput; words 8-15 are used for input. Bits are numbered in decimal 0-15 for eachword.

To tell the processor which file is the adapter image file, enter the file number in word25 of the processor status file. You enter this file number on the Processor Statusscreen. For more information about the Processor Status screen, see the section onusing status data in the Troubleshooting and Diagnostics chapter of the PLC–5 A.I.Series Software Reference manual.

Condition the ladder logic with bit 8, word 0 of the adapter image file. When set, thisbit indicates a communication failure between the adapter and supervisory processors.

Do not program block transfers to a supervisory processor if you created anadapter image file. For more information about block transfers, see page 11-14 inthis chapter.

Creating an Adapter Image File - New Platform PLC-5 ProcessorsTo create an adapter image file for a New Platform processor, use the channelconfiguration screen. You will need to specify an input source—the starting addressfor adapter input, and an output source—the starting address for adapter output. Forboth the input source and the output source, enter a data table file number and astarting element number in decimal.

The following table shows two examples of input source and output source entries.

!


11-10

Sample Entry Starting Address

input source 010:050 adapter inputs start at N10:50

output source 011:050 adapter outputs start at N11:50

input source 012:016 adapter inputs start at N12:16

output source 012:000 adapter outputs start at N12:0 and end at N12:15

The processor determines the number of words used by the file(s) according to the sizeof the chassis:

ChassisSize:

WordLength:

ChassisSize:

WordLength:

1/4 2 3/4 6

1/2 4 full 8

For more information on configuring a channel for adapter mode, see the PLC–5 A.I.Series Software Reference manual.

Transferring Bits between Supervisory (PLC-2) and AdapterProcessors

The drawing below shows ladder logic for transferring bit 17 of the supervisoryprocessor’s output image word 7 and bit 16 of the adapter processor’s output imageword 5. The X represents the adapter processor’s rack number; rack 3 is the simulatedrack for the adapter processor. This example assumes 1–slot or 2–slot hardwareaddressing. The supervisory processor is a PLC-2 processor.

Transferring Bits Using Rack 3 in the Adapter Processor

0X7

171X5

16

I:037

17O:035

16

Supervisory Processor (PLC-2) Adapter Processor (PLC-5)

Using Adapter Mode

11-11

When the supervisory processor sets its output image bit 0X7/17, input image bitI:037/17 in the adapter processor is automatically set. In the same way, when theadapter processor sets output image bit O:035/16, input image bit 1X5/16 in thesupervisory processor is automatically set.

The drawing below shows ladder logic if you created an adapter image file because youneed rack 3 for local I/O. This example uses N51 as the adapter image file.

Transferring Bits Using Your Own Adapter Image File

0X7

17

1X5

16

N51:15

15N51:05

14

Supervisory Processor (PLC-2) Adapter Processor (PLC-5)

For Original PLC-5 processors, words 0-7 in the integer file represent output, words 8-15 represent input. For New Platform PLC-5 processors, input source and outputsource entries determine input and output words.

Determining the Status of the Adapter Processor

Supervisor Adapter Adapter processor sends toSupervisory processor

The supervisory processor receives status bits (see the table below) from the adaptermode processor in word 0 of the input image table for the rack that the adapterprocessor is emulating:

This status bit of theadapter being set: Indicates this Condition:

Octal Decimal

10 8 data not valid

15 13 Adapter processor is in Program or Test mode

The supervisory processor should monitor the rack fault bits for the rack the adapterprocessor is emulating to determine the status of the remote I/O link.


11-12

Determining the Status of the Supervisory Processor

Supervisor Adapter Supervisory processor sends toAdapter processor

The PLC–5 processor in adapter mode sets status bits (see the table below) in I:030 (orword 0 of the adapter image file) of the adapter processor’s data table. These bits tellthe adapter mode processor the status of the supervisory processor and the integrity ofthe remote I/O communication link.

Status Bits of the Supervisory Processor Set in the Adapter Processor’s Data Table

This bit being set: Indicates this Condition:

Rack 3 InputImage Table

(octal)

Adapter InputImage File (decimal)

10 8 the adapter processor detects a communication failure orreceives a reset command from the supervisory processor

11 9 the adapter processor receives a reset command from thesupervisory processor (processor in Program or Testmode)

13 11 the adapter processor is powering up; this bit is reset withthe first communication from the supervisory processor

15 13 the adapter processor detects a communication failure (forexample, no communication activity on the remote I/Ocommunication link within the last 100 msec.)

Using Adapter Mode

11-13

Programming Considerations for Using AdapterMode

In a distributed control system where your process is controlled by several independentprogrammable controllers, you must make sure that your program considers the statusof the PLC-5 processors and the integrity of the communication link by using the statusbits that the supervisory and adapter mode processor provide for each other (see thetables on pages 11-11 and 11-12).

For example, how should your process respond if:

• there is an incremental degradation of the systems control due to the loss of one ofthe programmable controllers

• the supervisory processor is in Program mode and someone manually activates avalve normally controlled by the supervisory processor

• the adapter processor faults

The adapter processor can monitor the status of the supervisory processor by examiningthe status bits in the first word of the data being transferred from the supervisoryprocessor (see page 11-12).

The supervisory processor can monitor the status of the adapter processor by examiningthe status bits in the first word of the data being transferred from the adapter processor(see page 11-11). The supervisory processor can also monitor the rack fault bits for therack the adapter is emulating to determine the integrity of the remote I/Ocommunications between the supervisor and the adapter processors. For moreinformation on rack fault bits, see the PLC–5 A.I. Series Software Reference manual.


11-14

Programming Block Transfers - Original PLC-5Processors

To transfer blocks of data between an adapter processor and a supervisory processor,the adapter processor must have a BTW instruction to respond to the BTR from thesupervisory processor (and a BTR to respond to the supervisory processor’s BTW). Forexample, when the supervisory processor enables a BTR instruction, the adapterprocessor responds by enabling a BTW instruction. The supervisory processor controlsthe transfer; the adapter processor responds to the request. The drawing on thefollowing page shows an example of block transfer programming between an adapterand supervisory processor.

Using Adapter Mode

11-15

Example: Adapter/Supervisor Block Transfer Programming for an AdapterProcessor in Rack XX and a PLC-3 Supervisory Processor

BLOCK TRANSFER READRackGroupModuleControl Block

300

N7:10Data FileBT Length

N7:10040

Continuous Y

BTR

BLOCK TRANSFER READRackGroupModuleControl

0XX0

0=LOWFB001:0000

Data FileLength

FB002:00000

BLOCK TRANSFER WRITERackGroupModuleControl

0XX0

0=LOWFB001:0000

Data FileLength

FB003:00000

BTW

BLOCK TRANSFER WRITERackGroupModuleControl Block

300


N7:2008

BTW

Continuous Y

Adapter-mode Processor

1771 I/OChassis

Remote I/O LinkSet forRack XX

BTR

Supervisory Processor (PLC-3)

Addressing Tips for Block TransfersThe following table lists some addressing tips for programming block transfers betweenan adapter processor and a supervisory processor.


11-16

BTR/BTW Parameter: BTR/BTW in Supervisor: BTR/BTW in Adapter:

Rack PLC–2/30: 1-7 octalPLC–3: 0-77 octalPLC–5/25: 0-7 octal

image rack 3

Group, module must be 0 must be 0

Length must be 0 number of words transferred

Continuous yes (PLC–5 and PLC–5/250 only) yes

To guarantee the correct destination of block transfer data, program only one set ofbi-directional block transfers between the supervisory and adapter processors.

Note If you are using an Original PLC-5 processor, set the supervisory processor’scommunication rate for remote I/O to 57.6K baud. If you have a New Platformprocessor, you may be able to use 115K or 230K baud depending on what the otherdevice supports.

Remember that block transfers between adapter and supervisory processors transferdata between data table addresses. If you want to transfer local I/O data of the adaptermode processor to a supervisory processor or if you want to transfer data from thesupervisory processor to local I/O of the adapter mode processor, you must use blocktransfer instructions within the adapter processor to move the data in or out of the datafile used in the adapter block transfer instruction.

The following drawing shows data transfers from a supervisory processor to an adapterprocessor and to a local block transfer module, and vice versa.

!

Using Adapter Mode

11-17

Example: Block Transfer from Supervisory Processor (PLC-3) to Adapter Processor to LocalBlock Transfer Module and Vice Versa

BLOCK TRANSFER WRITERackGroupModuleControl

20

0=LOWFB001:0000

Data FileLength

FB002:00000

BLOCK TRANSFER READRackGroupModuleControl

20

0=LOWFB001:0000

Data FileLength

FB003:00000

BTR


300


N7:10040

Continuous Y


300


N7:1508

BTW

Continuous Y

BTW BTR

Data FileFB002

0000

0039

Data FileFB003

0000

0007

Data File N7

N7:100

N7:139

N7:150

N7:157

// //

To BTModule *

From BTModule *

Supervisory ProcessorAdapter-mode Processorin Supervisory Processor'sRemote I/O Rack 2

BT Module in LocalI/O Rack 0, I/O Group 2Module 0 *

Block Transfers over Remote I/O Link Local BT over chassis backplane


020


N7:10040

Continuous Y

BTW


020


N7:1508

BTR

Continuous Y

(PLC-3)

If you transfer block data with a supervisory processor, you cannot use 1/2–slotaddressing with a 1771-A4B chassis because the adapter processor needs the rack 3 I/Oimage table for block transfer communication.

Do not try block transfers to a supervisory processor when the adapter processoruses rack 3 for scanning local I/O (when you create your own adapter image file).Using rack 3 addresses under this condition will result in unpredictable machineoperation with possible damage to equipment or personnel.

!


11-18

Example Ladder Logic

The following figures show example ladder logic for block transfers between an adapterprocessor and a supervisory processor.

Supervisory Processor (PLC–2/30, PLC–3, PLC–5, or PLC–5/250)Enter the following parameters in the block transfer instructions in the supervisoryprocessor:

• set the length to 0

• set the continuous bit for continuous operation (PLC–5 and PLC–5/250 only)

• use the remote I/O rack number for which you configure the adapter processor

• use 0 for the group and module numbers

• condition the use of BTR data with a “data valid” bit (see the table on page 11-11)

Using Adapter Mode

11-19

Example Block Transfer in PLC–2/30 Supervisory Processor

ENBLOCK TRANSFER READDATA ADDR

MODULE ADDRBLOCK LENGTHFILE

031

2000

240-337

Store Bit

DN

PLC-5 adapter-mode processor in rack 2

ENBLOCK TRANSFER WRITE

DATA ADDRMODULE ADDRBLOCK LENGTH

FILE

030200

0

140-237

Store Bit

DN

U

BTW Done Bit

07

Store Bit

L

BTR Done Bit

120

Store Bit

FILE TO FILE MOVE

COUNTER ADDRESS

POSITION

033

0

BTR Done Bit Data Valid Bit

120

06

07

020

120

07

06

020

120

06120

06

120

10

FILE LENGTHFILE A:

64240-377

FILE R:RATE PER SCAN

400-47764


11-20

Example Block Transfer in PLC–3 Supervisory Processor

LEBTRBLOCK XFER READRACKGROUPMODULE

DATA

200

#B2:0

DN

B1:0

15

LENGTH

CNTL

0

#B1:0 ER

BTR Done Bit

LEBTWBLOCK XFER WRITERACKGROUPMODULE

DATA

200

#B3:0

DN

LENGTH

CNTL

0

#B1:0 ER

17

Read Request

ENMVFFILES FROM A TO RSOURCEDESTINCOUNTERMODE

#B2:0#B4:0

C5ALL

DN15

LENGTHPOSITION

640

ER

BTR Done Bit Data Valid Bit


B1:0

B1:0 I:020

10

Using Adapter Mode

11-21

Example Block Transfer in PLC–5 Supervisory Processor

ENBTR

BLOCK TRNSFR READRACKGROUPMODULECONTROL BLOCK

20

0

N7:10

DN

DATA FILELENGTH

N7:100

0

ER


UN7:15

12

N7:15

15

UN7:10

12

N7:10

15

CONTINUOUS Y

ENBTW

BLOCK TRNSFR WRITERACKGROUPMODULECONTROL BLOCK

200

N7:15

DN

N7:2000

ER

DATA FILELENGTHCONTINUOUS Y

BTR Error Bit

BTW Error Bit

BTR Enable Bit

BTW Enable Bit

COPCOPY FILESOURCEDESTINLENGTH

#N7:100#N7:200

64

12

BTR Error Bit Data Valid BitN7:10 I:020

10


11-22

Example Block Transfer in PLC–5/250 Supervisory Processor

EN002

00

BR020:0

DN

1BTD1:00

ER


BR020:0

EN

YES

EN002

00

BW020:0

DN

1BTD2:00

ER

YES

BTRBLOCK TRNSFR READRACK

GROUPMODULE

CONTROL BLOCK

DATA FILE

BT LENGTH

CONTINUOUS

BT TIMEOUT 3

BTWBLOCK TRNSFR WRITE

RACKGROUPMODULE

CONTROL BLOCK

DATA FILEBT LENGTH

CONTINUOUS

BT TIMEOUT 3

/BW020:0

EN/

BR030:0

EN/

BW030:0

EN/

1R0:0

64

BTR Error Bit Data Valid BitBR020:0

EN

I:020

10

0ALL

FILE ARITH/LOGICALCONTROL

LENGTH

POSITIONMODE

DESTIN

EXPRESSION

#1N0:0

1BTD1:0

EN

DN

ER

Using Adapter Mode

11-23

Adapter Processor (PLC–5/15, –5/25)Enter the following parameters in the block transfer instructions in the adapterprocessor:

• Use 3 for the rack, 0 for the group, and 0 for the module

• Set the continuous bit for continuous operation

• Condition the use of BTR data with status bits from the supervisory processor

Example Block Transfer for PLC–5 Processor in Adapter Mode

EN3

0

0N7:10

DN

N7:100

40

ER

UN7:15

12

N7:15

15

UN7:10

12

N7:10

15

BTR

BLOCK TRNSFR READRACK

GROUP

MODULECONTROL BLOCK

DATA FILE

LENGTH

CONTINUOUS Y

EN3

00

N7:15

DN

N7:2008

ER

BTWBLOCK TRNSFR WRITERACK

GROUPMODULE

CONTROL BLOCK

DATA FILELENGTH

CONTINUOUS Y

BTR Error Bit

BTW Error Bit

BTR Enable Bit

BTW Enable Bit

COP

COPY FILE

SOURCEDESTINLENGTH

#N7:100#N7:200

40

12

BTR Error BitN7:10I:030

10

I:030

11

I:030

12

I:030

15

Status Bits


11-24

Adapter Processor (New Platform Processors)If you have a New Platform PLC-5 processor, you do not need to use ladder logic; youcan configure the adapter channels from the channel configuration screens. See thePLC–5 A.I. Series Software Reference manual.

Using Scanner Mode

12-1

12 Using Scanner Mode

A PLC–5 processor in scanner mode transfers discrete I/O and block data with localand remote I/O chassis. If you have your processor configured for scanner mode, referto this chapter for information on how a PLC–5 processor in scanner mode transfersdata. This chapter also gives information on how to handle I/O rack faults for local andremote I/O in scanner mode.

Operating in Scanner Mode

In scanner mode, the processor scans the processor memory file to read inputs andcontrol outputs. The processor scans local I/O during the I/O scan which issynchronous to the program scan. The processor scans remote I/O during a separatescan which is asynchronous to the program scan (but updates the data table from theremote I/O buffer synchronously to the program scan).

Configuring an Original PLC–5 Processor for Scanner ModeWhen you configure your processor for scanner mode you use switch assembly SW1, asdescribed in the 1785 PLC–5 Family Programmable Controllers - HardwareInstallation Manual (Allen–Bradley publication 1785–6.6.1). Select scanner mode onswitch assembly SW1.

Configuring a New Platform PLC–5 Processor for Scanner ModeTo configure a New Platform processor for scanner mode, use the ProcessorConfiguration screen. For more information on configuring your processor, see thePLC–5 A.I. Series Software Reference manual.


12-2

Transferring Discrete Data

The processor scans local I/O synchronously to the program scan. The drawing belowshows how the processor scans local I/O and transfers discrete data.

Rack 3

Remote I/OBuffer

LocalRack

Local I/O

Remote I/OScan

Remote I/O

x y

x y

read inputs

write outputs

read inputs

write outputs

I/O Scan

Housekeeping

ProgramScan

Immediate I/OIOT (x)IIN (y)

End

Rack 2

Rack 1

Ada

pter

Ada

pter

Ada

pter

1-3

ms

typi

cal

The processor:

• Presents all discrete I/O data synchronously to the program scan.

• Scans discrete I/O data in the local I/O chassis synchronously to the program scan.

• Scans discrete I/O data in remote I/O chassis asynchronously to the program scan.The remote I/O scan transfers discrete I/O data between remote I/O adapters in I/Ochassis and the remote I/O buffer in the processor.

• Performs housekeeping once per program scan:

♦ Original PLC-5 processor: 3 ms maximum; typically 1.5 ms

♦ New Platform PLC-5 processor: 4.5 ms

Using Scanner Mode

12-3

Transferring Block DataThe processor transfers blocks of data to and from its local and remote I/O chassiswhen operating in scanner mode. The processor performs block transfersasynchronously to the program scan. The processor also interrupts the program scanasynchronously to momentarily access BTW and BTR data files. The processorperforms one remote block transfer per addressed rack per remote I/O scan. Thedrawing below shows how the processor handles transferring block data to local andremote I/O.

Rack 4

LocalRack 0

Remote I/OScan

Remote I/O

I/O Scan

Housekeeping

ProgramScan

End

Rack 2

Rack 1

One transfer perremote I/O scan



* Interruptfrom STI orFault Routine

BTR or BTW Data

BTRequests

Q

A*

BTR or BTW Data

BTRequests

Q

A *

BTR or BTW Data

BT Requests

Q

A*

BTR or BTW Data

BT RequestsQ

A*

Q = QueueA = Active

Buffer

I/O Scan

MultipleBlock Transfers

Q

AOne transfer perremote I/O scan

and 3

BTR or BTW Data

BT Requests

*

2-slotaddressing

1-slotaddressing

2-slotaddressing

Ada

pter

Ada

pter

Ada

pter


12-4

Queued Block Transfer RequestsIf your ladder program requests more than one block transfer to or from the same I/Ochassis in the same program scan, the processor queues the requests. Original PLC-5processors can handle up to 17 requests per chassis; New Platform processors canhandle up to 128 remote block transfer requests.

After the processor queues the requests, an Original PLC-5 processor runs the blocktransfers in the order they are requested. The only exception is a block transfer requestin a fault routine or STI (see the drawing on page 12-6). Since a New Platformprocessor can request many block transfers to a single chassis at the same time, theadapter device chooses the order in which the block transfers execute. The exception isa block transfer request in a fault routine, STI or PII (see the drawing on page 12-8).

The processor has an active area. The processor places a block transfer in the activearea when the processor takes the request off the queue. The processor places a blocktransfer request directly in the active area only if the queue is empty.

Block Transfers to Local I/OBlock transfers to local I/O follow these procedures:

• Block transfer requests are queued for the addressed local I/O rack.

• The active buffer handles all block transfer modules whose block transferinstructions were enabled in the program scan continuously via the queue scan inthe order the requests were queued.

• The processor momentarily interrupts program scan when the active bufferperforms a block transfer request to access the block transfer data file.

• Block transfers can finish and the done bit can be set anytime during the programscan.

The processor runs all enabled block transfers to local I/O continuously as each blocktransfer request enters the active buffer. The processor does not wait for the I/O scan toqueue the requests.

Block Transfers to Remote I/OBlock transfers to remote I/O follow these procedures:

• Block transfer requests are queued for each addressed remote I/O rack.

• Each active buffer transfers one data block per remote I/O scan.

• The processor momentarily interrupts program scan when the active bufferperforms a block transfer request to access the block transfer data file.

Using Scanner Mode

12-5

If program scans are two or three times longer than remote I/O scans, the processor canrun two or three remote block transfers per program scan and interrupt the programscan two or three times.

Block Transfers in Fault Routines or Selectable Timed Interrupts(STIs)

If the processor runs a fault routine or a selectable timed interrupt (STI) that containsblock transfers, the processor performs these block transfers immediately uponcompleting any block transfers currently in the active buffer, ahead of block transferrequests waiting in the queue.

The block transfers in a fault routine or an STI should only be between the processorand local I/O.

The program scan stops when an Original PLC-5 processor runs a fault routine orSTI with a block transfer instruction to a remote chassis. The delay for a blocktransfer could be unacceptable for your application.

However, for a New Platform PLC-5 processor, the MCP resumes processing whilethe PII or STI is waiting for the block transfer to complete.

!


12-6

Block Transfer SequenceOriginal PLC-5 Processors

The drawing below shows the sequence the processor follows to run a block transfer inan Original PLC-5 processor. (If you are using a New Platform processor, see page 12-8.)

2Q17 Bufferfor 17 BTRequests

3a, 3b, 5Active BT

area

4a, 4b I/O Chassis

1, 7Ladder

Program

6 STI

DataFiles

Request

Priority Request

Data

Data

Request and Outgoing DataAcknowledgementand Incoming Data

Pair of buffersper assignedrack address

The following steps describes the numbered sections in the drawing above.

1. Ladder logic enables the block transfer.

2. The processor places the block transfer request in the queue, or in the active bufferif the queue is empty. (If the queue is full, the request is ignored until the nextscan.)

Using Scanner Mode

12-7

3. If the block transfer is a:

a. BTW: The processor interrupts the program scan momentarily to transferdata from the BTW file to the active buffer. The active buffer transfers therequest and outgoing data to the local I/O module or to the remote I/O adapter.

b. BTR: The active buffer sends the block transfer request to the local I/Omodule or remote I/O adapter. In the same local block transfer update or inthe next remote I/O scan, the active buffer receives the block transferacknowledgment and incoming data. The processor interrupts the programscan momentarily to transfer incoming data to the BTR file one word at atime; therefore, some ladder logic could execute in between word transfers tothe BTR file. We recommend that you buffer your BTR data with a file–to–file move or a copy instruction using a BTR done bit to condition the rung ifyou need file integrity of the data.

4. If the block transfer is to:

a. Local I/O: The processor continuously runs block transfer requests for alllocal I/O modules in the order the processor queues the requests.

b. Remote I/O: The processor runs one block transfer request for one blocktransfer module per rack address per remote I/O scan.

5. The processor clears the active buffer and the active buffer accepts the next requestafter the buffer receives a confirmation of a valid read or write.

6. When the processor enables a fault routine or STI, the processor runs any blocktransfer program in the fault routine or STI ahead of any block transfer requests inthe queue, as soon as the active buffer completes any block transfer currently in theactive buffer. The program scan is stopped until the STI or fault routine blocktransfer is complete.

7. The block transfer process runs asynchronously to the program scan, so data canchange during a program scan.


12-8

Block Transfer SequenceNew Platform PLC-5 Processors

The drawing below shows the sequence the processor follows to perform a blocktransfer in a New Platform PLC-5 processor.

2

3a, 3b, 5Active BT

4a, 4b I/O Chassis

1, 7Ladder

Program

6 STI

DataFiles

Request

Priority Request

Data

Data

Request and Outgoing DataAcknowledgementand Incoming Data

Block Transferprocessing

PII

Holding area

area

The following steps describes the numbered sections in the drawing above.

1. Ladder logic enables the block transfer.

2. The processor examines the block transfer request. If a request already exists forthe slot, the processor places the request in the Holding area.

Using Scanner Mode

12-9

3. If the block transfer is a:

a. BTW: The processor interrupts the program scan momentarily to transferdata from the BTW file to the active buffer. The active buffer transfers therequest and outgoing data to the local I/O module or to the remote I/O adapter.

b. BTR: The active buffer sends the block transfer request to the local I/Omodule or remote I/O adapter. In the same local block transfer update or inthe next remote I/O scan, the active buffer receives the block transferacknowledgement and incoming data. The processor interrupts the programscan momentarily to transfer incoming data to the BTR file one word at atime; therefore, some ladder logic could execute in between word transfers tothe BTR file. We recommend that you buffer your BTR data with a file–to–file move or a copy instruction using a BTR done bit to condition the rung ifyou need file integrity of your data.

4. If the block transfer is to:

a. Local I/O: The processor continuously runs block transfer requests for alllocal I/O modules in the order the processor queues the requests.

b. Remote I/O: The processor runs one block transfer request for one blocktransfer module per rack address per remote I/O scan.

5. The processor clears the active buffer and the active buffer accepts the next requestfrom the Holding area after the buffer receives a confirmation of a valid read orwrite.

6. When the processor enables a fault routine, STI or PII, the processor runs anyblock transfer program in the fault routine, STI or PII ahead of any block transferrequests in the holding area, as soon as the active buffer completes any blocktransfer currently in the active buffer. The program scan is stopped until the STIor fault routine block transfer is complete.

7. The block transfer process runs asynchronously to the program scan, so data canchange during a program scan.

Block Transfer Sequence with Status BitsThe following explanations describe how the ladder logic and the I/O scanner handleblock transfers with status bits.


12-10

Ladder logic:

• Detects that the rung containing a block transfer is enabled

• Sets the enable bit (.EN, bit 15)

• Detects the status of the read/write bit (.RW, bit 07)

• Places the block transfer in the active buffer if the queue is empty; the processorsets the start bit (.ST, bit 14) and begins the transfer

• Places the block transfer in the queue if the active buffer is not empty; theprocessor sets the enabled waiting bit (.EW, bit 10)

If the queue is full, block transfer requests may not occur in the order the ladder logicrequests the transfers. The processor sets the enabled waiting bit (.EW, bit 10) whenthe request enters the queue.

I/O scanner:

• Transfers the request to or from the I/O chassis after the request reaches the activebuffer

• Detects whether the module responds; if the module does not respond, theprocessor sets the no response bit (.NR, bit 09)

If there is no response and the timeout bit (.TO, bit 08) is reset, the processor re–queues the request until the watchdog timer times out (4 seconds). If there is noresponse and the .TO bit is set, the scanner retries the request one more time beforesetting the .ER bit.

• If the request is a:

♦ BTW: transfers the data to the module

♦ BTR: moves data from the module to the BTR data file one word at a time

• Sets the done bit (.DN, bit 13) upon completion of a valid transfer; sets the error bit(.ER, bit 12) if there were errors

• Checks the status of the continuous bit (.CO, bit 11); if set and no error occurred,the scanner re–queues the block transfer

• Notifies the active buffer to accept the next request

For a list of block transfer error codes, see the Allen-Bradley documentation that camewith your processor.

Using Scanner Mode

12-11

Block Transfer Timing: Original PLC-5 Processors

The time to complete a block transfer in an Original PLC-5 processor depends on:

• Instruction run time

• Waiting time in the queue

• Transfer time

Instruction Run TimeThe time in milliseconds it takes the processor to perform a block transfer instructiondepends on these formulas:

Write: Read:

310 + 11.2Q + 5.4W 250 + 11.2Q

where:Q represents the number of queued block transfer requests to the same I/O chassis

with the continuous bit setW represents the number of words to transfer

Waiting Time in the QueueThe waiting time in the queue is the sum of the transfer times yet to occur before theblock transfer request (for which you are calculating time) to the same I/O chassis.

Transfer TimeThe transfer time in milliseconds between the active buffer and the module starts whenthe processor sets the start bit and ends when the processor sets the done bit. Thetransfer time depends on these formulas:

Write Read

local 0.9 + 0.1W local 0.9 + 0.1W

remote (57.6K baud) 13 + 30C + 0.3W remote (57.6Kbaud)

9 + 30C + 0.3W

remote (115K baud) 13 + 21.3C + 0.3W remote (115K baud) 9 + 21.3C + 0.3W

where:C represents the number of remote I/O chassisW represents the number of words to transfer


12-12

Block Transfer Timing: New Platform PLC-5Processors

The time to complete a block transfer in a New Platform processor depends on:

• Instruction run time

• Waiting time in the queue

• Transfer time

Instruction Run TimeThe time it takes the processor to perform a block transfer instruction is the same for aread or a write: 450 microseconds.

Waiting Time in the Holding AreaThe waiting time in the holding area is the sum of the transfer times yet to occur beforethe block transfer request (for which you are calculating time) to the same I/O chassis.

Transfer TimeThe transfer time in milliseconds between the active buffer and the module starts whenthe instruction sets the start bit and ends when the instruction sets the done bit. Thetransfer time depends on this formula (and is the same for a read or a write):

local 0.9 + 0.1W

remote (57.6K baud) 4 + 8C + 0.3W

remote (115K baud) 4 + 4.6C + 0.15W

where:C represents the number of remote I/O chassisW represents the number of words to transfer

Using Scanner Mode

12-13

When the Processor Detects a Major Fault

In general, if the processor detects a hardware fault or other run–time error, it sets amajor fault bit and stops scanning I/O and the program. The outputs remain in theirlast state or they are de–energized, based on how you set the last state switch in the I/Ochassis (1771–A1B, –A2B, –A3B, –A4B).

Note In the PLC–5 processor’s local chassis, outputs are reset - regardless of the last stateswitch setting - when one of the following occurs:

• Processor detects a run-time error• You set a status file bit to reset a local rack• You select program or test mode

To decide how to set this switch, evaluate how the machines in your process will beaffected by a fault. For example, how will the machine react to outputs remaining intheir last state or to outputs being automatically de–energized? What is each outputconnected to? Will machine motion continue? Could this cause the control of yourprocess to become unstable?

To set this switch, see the 1785 PLC–5 Family Programmable Controllers - HardwareInstallation Manual (Allen–Bradley Publication 1785–6.6.1).


12-14

When a Resident Local I/O Rack Faults

The chassis that contains the PLC–5 processor is the “resident” local I/O rack. If aproblem occurs with the chassis’ backplane, the input and output data table bits for theresident local I/O rack are left in their last state. The processor sets a minor fault andcontinues scanning the program and controlling I/O.

Your ladder program should monitor the I/O rack fault bits and take the appropriaterecovery action (covered later in this chapter).

If a resident local I/O rack fault occurs and you have no recovery methods, theinput image table and outputs for the faulted rack remain in their last state.Injuries to personnel and damage to machinery may result.!

Using Scanner Mode

12-15

When a Remote I/O Rack Faults

In general, when a remote I/O rack faults, the processor sets an I/O rack fault bit andthen continues scanning the program and controlling I/O. The outputs in the faultedrack remain in their last state or they are de–energized, based on how you set the laststate switch in the I/O chassis (1771–A1B, –A2B, –A3B, –A4B).

If outputs are controlled by inputs in a different rack and a remote I/O rack faultoccurs (in the inputs rack), the inputs are left in their last non-faulted state. Theoutputs may not be properly controlled and injuries to personnel and damage tomachinery may result. Make sure you have recovery methods in place.

!


12-16

Recovering from a Resident Local I/O or RemoteI/O Rack Fault

In the PLC–5 processor, you can monitor I/O rack faults using PLC–5 status bits andthen recover from the fault using a fault routine or ladder logic.

Using I/O Status File Bits to Monitor Rack FaultsThere are two types of status bits used to display information about your I/O system:global status bits and the I/O status file.

Using Global Status Bits

The global status bits are set if a fault occurs in any one of the logical racks. See thetable below to determine the number of bits.

Processor: Possible Logical Rack Bits:

PLC–5/10, –5/12, –5/15 4

Orig

.

PLC–5/25 8

PLC-5/11, -5/20 4

PLC-5/30 8

PLC–5/40 16

New

Pla

tform

PLC–5/60, -5/80 24

Each bit represents an entire rack, no matter how many chassis make up a rack.(Remember that you can have up to four chassis configured as quarter racks to make upone logical rack.) These bits are stored in the lower eight bits of status file words 7 and27 for Original processors and words 7, 32 and 34 for New Platform processors.

For more information on global status bits, see the PLC–5 A.I. Series SoftwareReference manual.

Using the I/O Status File

The I/O status file is used to monitor the racks in your I/O system. This file contains 2words of status bits for every rack configured in your system. The data file number thatcontains this I/O information is stored in word 16 (low byte) of the status file. Youmust enter this information on the Processor Status screen (Original PLC-5) or theProcessor Configuration screen (New Platform).

Using Scanner Mode

12-17

For more information on the I/O status file, see the PLC–5 A.I. Series SoftwareReference manual.

Using Fault Routine and Ladder Logic to RecoverYou may want to configure an I/O rack fault as a minor fault if you have theappropriate fault routine and ladder logic to perform an orderly shutdown of the system.You can program ladder logic in several ways to recover from a I/O rack fault. Thesemethods are:

• User–generated major fault

• Reset input image table

• Fault zone programming

User–generated Major Fault

Using this method, you jump to a fault routine when a remote I/O rack fault occurs. Inother words, if the status bits indicate a fault, you program the processor to act as if amajor fault occurred (that is, jump to the fault routine). You then program your faultroutine to stop the process or perform an orderly shutdown of your system. When theprocessor executes the end–of–file instruction for the fault routine, a user–generatedmajor fault is declared. For more information on fault routine programming, seeChapter 10- Writing a Fault Routine.

Reset Input Image Table

With this method, you monitor the status bits and, if a fault is detected, you programthe processor to act as if a minor fault occurred. After the status bits indicate a fault,use the I/O Status screen to inhibit the remote rack that faulted. You then use ladderlogic to set or reset critical input image table bits according to the output requirementsin the non–faulted rack.

If you reset input image table bits, during the next I/O update, the input bits are setagain to their last valid state. To prevent this from occurring, your program should setthe inhibit bits for the faulted rack. The global inhibit bits control the input images ona rack by rack basis; the partial rack inhibit bits control the input images on a 1/4 rackbasis.

This method requires an extensive and careful review of your system for recoveryoperations. For more information on inhibiting I/O racks, see the PLC–5 A.I. SeriesSoftware Reference manual.


12-18

Fault Zone Programming

Using fault zone programming, you disable sections of your program with MCR(Master Control Reset) zones. Using the status bits, you monitor your racks; when afault is detected, you control the program through the rungs in your MCR zone. Withthis method, outputs within the MCR zone must be non–retentive to be de–energizedwhen a rack fault is cleared.

For more information on the MCR instruction and MCR zones, see the Instruction SetReference.

Programming Through a Serial Port

13-1

13 Programming Through a SerialPort

New Platform PLC-5 processors have a serial port that can be used to connect theprocessor to a terminal that supports ASCII DF1 protocol or to any device that can sendor receive ASCII characters.

This serial port can operate in two modes: System Mode and User Mode. In SystemMode, you can connect to terminals, modems and 1770–KF2 series B modules. In UserMode, you can connect to ASCII terminals, modems, bar code readers, dataliners, etc.

This chapter gives you an overview of the different ways you can program through aserial port on a New Platform processor:

• System Mode

♦ Point–to–point

♦ DF1 slave

• User Mode

For more information on these communication options, see the Data Highway/DataHighway Plus Protocol and Command Set (Allen–Bradley Publication 1770–6.5.16).


13-2

System Mode

In system mode, the processor interprets a command from the other device. Use systemmode when you need to communicate with other devices on a Data Highway link.

In system mode, you can send data to a device using the message instruction or as anASCII string using the ASCII write instructions. (For more information on theseinstructions, see the PLC–5 A.I. Series Instruction Set Reference manual.)

Using system mode, you can use either of the following protocols:

• Point–to–point (or DF1)

• DF1 slave

Point–To–PointPoint–to–point is a basic serial protocol used when you need:

• Single–device to single–device connection

• Two–way simultaneous transmission needed

DF1 SlaveThe processor can function as a slave in a master/slave serial communication network.Master/Slave communications use a multidrop link with all nodes interfaced throughmodems. There may be from 2 to 256 nodes simultaneously connected to a single link.

One node is designated as the master, and it controls who has access to the link. (Forexample, a master can be a PLC–5/250, 1771–KE/KF or 1771–KGM). All other nodesare slaves and must wait for permission from the master before transmitting. Themaster can send and receive messages from all nodes on the link and to nodes on otherData Highway links connected to the multidrop, but a slave can only respond to themaster.

Programming Through a Serial Port

13-3

User Mode

In User mode, all received data is put into a buffer. In order to access this data, you useASCII instructions in your ladder program. Likewise, using ASCII instructions in yourladder program, you can then send ASCII string data to a processor or other device.

Note In User Mode, only ASCII instructions can be used; if you try to use a messageinstruction that references the serial port, the error (.ER) bit is set.


13-4

Changing Modes

You can configure channel 0 of the processor to change communication modes in twoways:

• Directly - through the Channel Configuration screen

• Remotely - by defining communication mode change characters that another devicecan send. You define the ASCII control characters to get the processor’s attentionand then switch modes.

For more information on switching modes, see the PLC–5 A.I. Series SoftwareReference manual.

Index

Index-i

Index

—A—Adapter Mode

block transfer examples..................... 11-18block transfers................................... 11-14configuring ......................................... 11-3operating............................................. 11-3transfer data........................................ 11-5transfer status.................................... 11-12

Addressingfrequently used files ............................ 7-14I/O image.............................................. 7-6indexed ............................................... 7-10indirect ................................................. 7-8logical................................................... 7-2mnemonics ........................................... 7-4symbolic ............................................. 7-12

Alarmfault routine ........................................ 10-8

Application Program Development Model ... 2-1

—B—Bit (data file) ............................................... 6-3

Block Transfer ........................................... 11-5addressing......................................... 11-15examples........................................... 11-18fault routine ........................................ 12-5local I/O.............................................. 12-4programming .................................... 11-14queued requests................................... 12-4remote I/O .......................................... 12-4scanner mode...................................... 12-3sequence (New Platform) .................... 12-8sequence (Original)............................. 12-6

STI ..................................................... 12-5timing for New Platform ................... 12-12timing for Original............................ 12-11

Branches...................................................... 5-7execution time....................................... 5-8nested ................................................... 5-7

—C—Clearing a Major Fault.................... 10-8, 10-12

Compare Fault Code to Reference .............. 10-8

Constructing Rungs ..................................... 5-5

Converting Machine Statements to LadderLogic .................................................... 5-2, 5-6

—D—Data Block................................................... 6-3

organizing ............................................ 6-4user-defined .......................................... 6-3

Data Fileorganizing ............................................ 6-4types of ................................................. 7-2

Data Storagebit ......................................................... 6-3concepts................................................ 6-1data block ............................................. 6-3element ................................................. 6-2file ........................................................ 6-2sub_element.......................................... 6-3type....................................................... 6-2user-defined .......................................... 6-3


Index-ii

Design Specificationchecking for completeness................... 3-13detailed analysis .............................2-2, 3-5example ................................................ 3-2functional.............................................. 2-2program development model ................. 2-1writing functional specification ............. 3-3

DF1 Slave .................................................. 13-2

Digital I/Oexample instructions ............................. 5-3

Discrete I/Otransfer data ............................... 11-5, 11-8

Drawing An SFC ......................................... 4-6

—E—Element (data file) ....................................... 6-2

Event_Driven Interrupts........................ See PII

Execution Time............................................ 5-8

—F—Fault Routine ............................................... 2-8

alarm .................................................. 10-8block transfer ...................................... 12-5changing specified file ...................... 10-11clearing a fault .................................... 10-8compare fault code .............................. 10-8power_up protection.......................... 10-13programming ...................................... 10-8setting up .......................................... 10-11shut down logic................................. 10-10startup............................................... 10-13testing ............................................... 10-10

Faultslocal I/O rack .................................... 12-14major (types of) ................................... 10-3major fault codes................................. 10-3remote I/O rack ................................. 12-15

remote I/O rack recovery ................... 12-16

File Boundary ............................................ 7-10

Filesdata storage........................................... 6-2frequently used.................................... 7-14

Functional Specification............................... 2-2writing .................................................. 3-3

—G—Gapping....................................................... 6-4

Global Status Bits .................................... 12-16

GOTOdefinition ............................................ 4-11rules.................................................... 4-11

GOTOs and Labels ...................................... 4-5

—I—I/O

discrete I/O data transfer ............ 11-5, 11-8image address ....................................... 7-6status file........................................... 12-16

Indexed Address ........................................ 7-10

Indirect Address........................................... 7-8

Instructionsarranging ..................................... 5-5, 5-10examples............................................... 5-3

—L—Labels

definition ............................................ 4-11rules.................................................... 4-11

Ladder Logicbranch................................................... 5-7PII......................................................... 9-2shut down ......................................... 10-10

Index

Index-iii

writing.................................................. 5-5

Local I/O Rackfaulting ............................................. 12-14

Logicbranch................................................... 5-7writing.................................................. 5-5

Logical Address........................................... 7-2mnemonic............................................. 7-4

—M—Machine Statements

converting to logic ......................... 5-2, 5-6

Main Control Program.......................... 2-2, 2-4configuring ........................................... 2-6disabling ............................................... 2-6execution .............................................. 2-4monitoring............................................ 2-7using interrupt programs....................... 2-8

Major Faultsclearing............................................. 10-12codes................................................... 10-3detecting ........................................... 12-13responses ............................................ 10-2

Memory Gapping......................................... 6-4

Mnemonic Addressing................................. 7-4

Multiple Main Programs See Main ControlProgram

—O—Organizing Data .......................................... 6-4

—P—PII ...................................................... 2-8, 3-11

application examples............................. 9-4bit transition mode ......................... 9-4, 9-6counter mode ........................................ 9-4

ladder logic........................................... 9-2monitoring............................................ 9-8program flow ...................................... 3-11setting up .............................................. 9-6

Placing Instructions ................................... 5-10

Point-to-Point ............................................ 13-2

Power_Up Protectionfault routine ...................................... 10-13

Power_Up Routineprogram flow ...................................... 3-11

Processor Input Interrupt ...................... See PII

Processor Status FileSTI settings........................................... 8-3

Processor Type............................................. 1-1

Program Flowapplication examples........................... 3-12considering program features .............. 3-11

Programming Features............................... 3-11

—R—Remote I/O Rack

faulting ............................................. 12-15recovering from fault ........................ 12-16

Rungcreating................................................. 5-5definition .............................................. 5-2writing.................................................. 5-5

—S—Scanner Mode

block transfer ...................................... 12-3configuring .......... 12-1, 12-2, 12-11, 12-12operating............................................. 12-1transferring data ................................. 12-2

Selectable Timed Interrupt................... See STI


Index-iv

Selection Branch...................................4-3, 4-9

Serial Portchanging modes .................................. 13-4DF1 slave communications.................. 13-1point_to_point communications .......... 13-1System mode....................................... 13-1User mode........................................... 13-1

SFCbuilding blocks...................................... 4-1drawing................................................. 4-6GOTOs and labels........................ 4-5, 4-11path....................................................... 4-2scan sequences .................................... 4-11selection branch .............................4-3, 4-9SFR instruction ................................... 4-12simultaneous branch..................... 4-4, 4-10special structures................................... 4-6step ....................................................... 4-1step actions ........................................... 4-2transition............................................... 4-2

SFR Instruction.......................................... 4-12

Shut Down Logic ..................................... 10-10

Simultaneous Branch ................................... 4-4post scan mode.................................... 4-10

SoftLogix 5 ................................................ 7-13

Specification, design example ...................... 3-2

Startup Fault Routine ............................... 10-13

Status File....................................... 7-15, 12-16

Step (SFC) ................................................... 4-1

Step Actions................................................. 4-2

STI ..................................................... 2-8, 3-11block transfer ...................................... 12-5program flow ...................................... 3-11setting up .............................................. 8-3setup in processor status file .................. 8-3

Structure Names ........................................ 7-13

Sub_Element................................................ 6-3

Symbol....................................................... 7-12

System Mode ............................................. 13-2

—T—Time_Driven Interrupts ....................... See STI

Timingblock transfer for New Platform ........ 12-12block transfer for Original................. 12-11

Transition (SFC).......................................... 4-2

Types (data storage) ..................................... 6-2

—U—User Mode ................................................. 13-3

—W—Writing

branch logic .......................................... 5-7rung logic.............................................. 5-5

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Allen Bradley-PLC5 Programming Guide

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