Page 1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
04 ~ 08
SCHEMATIC
ALTERA Cyclone IV Development & Education Board (DE0-Nano)
CONTENT
Cover Page, Placement,TOP
05 POWERSDRAM, EEPROMCLOCK, LED, BUTTON,SW, GPIOs, 2X13 HEADER, G-SENSOR, ADC
02 EP4CE22
POWER 1.2V, 2.5V, 3.3V04 MEMORY03 IN/OUT 09 ~ 11
01 TOP 01 ~ 03
1412 ~ 13
PAGE
Cyclone IV EP4CE22 BANK1..BANK8 , POWER , CONFIG
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE0-Nano Board
B
1 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE0-Nano Board
B
1 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
COVER PAGE B
DE0-Nano Board
B
1 14Wednesday, October 26, 2011
Page 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE0-Nano Board
B
2 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE0-Nano Board
B
2 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PLACEMENT B
DE0-Nano Board
B
2 14Wednesday, October 26, 2011
Page 3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DRAM_ADDR[12..0]DRAM_DQM[1..0]
DRAM_DQ[15..0]
DRAM_DQ[15..0]DRAM_ADDR[12..0]DRAM_DQM[1..0]
KEY[1..0]
SW[3..0]
LED[7..0]
KEY[1..0]
SW[3..0]
LED[7..0]DRAM_BA0DRAM_BA1DRAM_CAS_NDRAM_RAS_NDRAM_WE_NDRAM_CS_NDRAM_CKEDRAM_CLK
DRAM_BA0DRAM_BA1DRAM_CAS_NDRAM_RAS_NDRAM_WE_NDRAM_CS_NDRAM_CKEDRAM_CLK
JTAG_TMSJTAG_TCKJTAG_TDIJTAG_TDO
NSTATUSCONF_DONENCONFIGNCE
DATA0DCLKNCSOASDO
I2C_SCLKI2C_SDAT
G_SENSOR_CS_NG_SENSOR_INT
CLOCK_50
I2C_SCLK I2C_SDAT
I2C_SCLKI2C_SDAT
G_SENSOR_CS_NG_SENSOR_INT
ADC_SDATADC_CS_NADC_SADDRADC_SCLK
CLOCK_50
GPIO_0_IN[1..0]GPIO_0[33..0]
GPIO_1_IN[1..0]GPIO_1[33..0]
GPIO_2_IN[2..0]GPIO_2[12..0]
ADC_SDATADC_CS_NADC_SADDRADC_SCLK
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
TOP B
DE0-Nano Board
B
3 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
TOP B
DE0-Nano Board
B
3 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
TOP B
DE0-Nano Board
B
3 14Wednesday, October 26, 2011
PAGE 4 - 8
02 EP4CE22
NSTATUS
NCENCONFIG
TDI
TMS
TDO
TCK
DCLK
ASDONCSO
DATA0
CONF_DONE
LED[7..0]
SW[3..0]
ADC_SCLK
KEY[1..0]
CLOCK_50
DRAM_BA0DRAM_BA1
DRAM_CKEDRAM_CLK
DRAM_ADDR[12..0]DRAM_DQ[15..0]
DRAM_DQM[1..0]
G_SENSOR_INT
DRAM_CAS_N
ADC_SADDR
DRAM_WE_NDRAM_CS_N
ADC_CS_N
G_SENSOR_CS_N
ADC_SDAT
DRAM_RAS_N
I2C_SDATI2C_SCLK
GPIO_1_IN[1..0]
GPIO_0[33..0]
GPIO_2_IN[2..0]
GPIO_1[33..0]
GPIO_0_IN[1..0]
GPIO_2[12..0]
PAGE 12 - 13
04 MEMORY
DRAM_DQM[1..0]DRAM_DQ[15..0]DRAM_ADDR[12..0]
DRAM_CLKDRAM_CKE
DRAM_BA0DRAM_BA1DRAM_CAS_N
DRAM_CS_NDRAM_WE_NDRAM_RAS_N
I2C_SDATI2C_SCLK
PAGE 14
05 POWER
PAGE 9 - 11
03 IN/OUT
ADC_SCLK
LED[7..0]
CLOCK_50
KEY[1..0]
SW[3..0]
G_SENSOR_INT
ADC_SADDR
ADC_SDATADC_CS_N
G_SENSOR_CS_NI2C_SDATI2C_SCLK
GPIO_1_IN[1..0]
GPIO_0[33..0]
GPIO_2_IN[2..0]
GPIO_0_IN[1..0]
GPIO_1[33..0]
GPIO_2[12..0]
Page 4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BANK 1BANK 2
KEY1
DRAM_DQ3DRAM_DQ6DRAM_DQ5
DRAM_DQ4
DRAM_DQ1DRAM_DQ0
DRAM_DQ15
DRAM_ADDR0
DRAM_ADDR12
DRAM_ADDR11
DRAM_ADDR9
DRAM_ADDR8
DRAM_ADDR10
LED4
LED5
LED6
SW0
LED7
G_SENSOR_CS_N
LED[7..0]
G_SENSOR_INT
KEY[1..0]
DRAM_ADDR[12..0]
DRAM_DQ[15..0]
SW[3..0]
DRAM_RAS_NDRAM_CAS_N
I2C_SDATI2C_SCLK
DRAM_WE_N
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK1 & BANK2 B
DE0-Nano Board
B
4 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK1 & BANK2 B
DE0-Nano Board
B
4 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK1 & BANK2 B
DE0-Nano Board
B
4 14Wednesday, October 26, 2011
U1A
EP4CE22F17
DQS2L/CQ3L,CDPCLK0B1
DIFFIO_L3pC2
DIFFIO_L4ND1
IO1_0G5
DIFFIO_L5pF2
DIFFIO_L5nF1
DIFFIO_L6p/DQS0L/CQ1L,DPCLK0G2
DIFFIO_L6nG1
CLK1/DIFFCLK_0nE1
IO/VREFB1N0F3
U1B
EP4CE22F17
DIFFIO_L7p/DQ1LJ2
DIFFIO_L7n/DQ1LJ1
DIFFIO_L10pK2
DIFFIO_L10n/DQ1LK1
DIFFIO_L11p/DQS1L/CQ1L#,DPCLK1L2
DIFFIO_L11n/DQ1LL1
DIFFIO_L13p/DQ1LN2
DIFFIO_13n/DQ1LN1
DIFFIO_L15p/DQ1LP2
DIFFIO_L15n/DM1L/BWS#1LP1
IO2_0/DQS3L/CQ3L#,CDPCLK1R1
RUP1/DQ1LK5
RDN1/DQ1LL4
IO/VREFB2N0L3
CLK2/DIFFCLK_1pM2
CLK3/DIFFCLK_1nM1
Page 5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BANK 3BANK 4
GPIO_1_IN0GPIO_1_IN1
DRAM_DQ11
DRAM_DQ12
DRAM_DQ13DRAM_DQ14
DRAM_DQ8
DRAM_DQ10
DRAM_DQM1
DRAM_DQ9
DRAM_DQ2
DRAM_DQ7
DRAM_DQM0
DRAM_ADDR4
DRAM_ADDR5
DRAM_ADDR2
DRAM_ADDR7
DRAM_ADDR6
DRAM_ADDR1 GPIO_128
GPIO_125GPIO_122
GPIO_114
GPIO_115
GPIO_112
GPIO_111
GPIO_16
GPIO_19GPIO_18
GPIO_14GPIO_13
GPIO_15
GPIO_12GPIO_11
GPIO_110
GPIO_113
GPIO_17
SW1DRAM_ADDR3 CLOCK_50
DRAM_CLK
DRAM_ADDR[12..0]
DRAM_DQ[15..0]
SW[3..0]
DRAM_DQM[1..0]GPIO_1[33..0]
GPIO_1_IN[1..0]
DRAM_BA0
DRAM_BA1DRAM_CKE
DRAM_CS_N
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK3 & BANK4 B
DE0-Nano Board
B
5 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK3 & BANK4 B
DE0-Nano Board
B
5 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK3 & BANK4 B
DE0-Nano Board
B
5 14Wednesday, October 26, 2011
U1C
EP4CE22F17
DIFFIO_B1pN3
DIFFIO_B1n/DM3B/BWS#3BP3
DIFFIO_B2p/DQ3BR3
DIFFIO_B2nT3
IO3_0/DQS1B/CQ1B#,CDPCLK2T2
PLL1_CLKOUTpR4
PLL1_CLKOUTnT4
DIFFIO_B4p/DQ3BN5
DIFFIO_B4n/DQ3BN6
IO3_1/DQ3BM6
IO/VREFB3N0P6DIFFIO_B5p/DQS3B/CQ3B#,DPCLK2
M7
DIFFIO_B6p/DQ3BR5
DIFFIO_B6nT5
DIFFIO_B7p/DQ3BR6
DIFFIO_B7nT6
IO3_2/DQ3BL7
DIFFIO_B8p/DQ3BR7
DIFFIO_B8n/DQS5B/CQ5B#,DPCLK3T7
DIFFIO_B9n/DQ3BL8
DIFFIO_B10n/DM5B/BWS#5BM8
DIFFIO_B11p/DQ5BN8
DIFFIO_B12n/DQ5BP8 CLK14/DIFFCLK_6n
T8CLK15/DIFFCLK_6pR8
U1D
EP4CE22F17
DIFFIO_B14n/DQ5BN9
DIFFIO_B16p/DQ5BR10
DIFFIO_B16n/DQS4B/CQ5B,DPCLK4T10
DIFFIO_B17p/DQ5BR11
DIFFIO_B17nT11
DIFFIO_B18p/DQ5BR12
DIFFIO_B18n/DQ5BT12
IO4_0/DQS2B/CQ3B,DPCLK5P9
IO/VREFB4N0P11DIFFIO_B20p
R13
DIFFIO_B20n/DQ5BT13
RUP2M10
RDN2N11
DIFFIO_B23p/DQ5BT14
DIFFIO_B23n/DQS0B/CQ1B,CDPCLK3T15
DIFFIO_B24pN12
PLL4_CLKOUTpP14
PLL4_CLKOUTnR14
CLK12/DIFFCLK_7nT9CLK13/DIFFCLK_7pR9
Page 6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BANK 5
BANK 6
KEY0
GPIO_2_IN0GPIO_2_IN1
GPIO_2_IN2
GPIO_24
GPIO_25GPIO_26
GPIO_21
GPIO_23
GPIO_210
GPIO_28GPIO_29GPIO_212GPIO_211
GPIO_10
GPIO_132GPIO_133
GPIO_130
GPIO_127
GPIO_123
GPIO_121
GPIO_120GPIO_119
GPIO_118
GPIO_124
GPIO_131
GPIO_126
GPIO_129GPIO_116
GPIO_117
SW3
GPIO_1[33..0]
KEY[1..0] GPIO_2_IN[2..0]
GPIO_2[12..0]
SW[3..0]
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK5 & BANK6 B
DE0-Nano Board
B
6 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK5 & BANK6 B
DE0-Nano Board
B
6 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK5 & BANK6 B
DE0-Nano Board
B
6 14Wednesday, October 26, 2011
U1E
EP4CE22F17
RUP3/DM1R/BWS#1RN14
RDN3/DQ1RP15
DIFFIO_R15n/DQS3R/CQ3R#,CDPCLK4P16
DIFFIO_R15p/DQ1RR16
DIFFIO_R13n/DQ1RN16
DIFFIO_R13p/DQ1RN15
IO/VREFB5N0L14
DIFFIO_R12p/DQ1RL13
DIFFIO_R11n/DQ1RL16
DIFFIO_R11pL15
DIFFIO_R10n/DQ1RK16
DIFFIO_R10p/DQS1R/CQ1R#,DRCLK6K15
DIFFIO_R9n/DEV_OEJ16
DIFFIO_R9p/DEV_CLRnJ15
DIFFIO_R8n/DQ1RJ14
DIFFIO_R7n/DQ1RJ13
CLK6/DIFFCLK_3pM15
CLK7/DIFFCLK_3nM16
U1F
EP4CE22F17
DIFFIO_R5n/INIT_DONEG16
DIFFIO_R5p/CRC_ERRORG15
IO6_0F13
DIFFIO_R4n/nCEOF16
DIFFIO_R4p/CLKUSRF15
IO6_1/DQS0R/CQ1R,DPCLK7B16
IO/VREFB6N0F14
IO6_2D16
IO6_3/PADD23D15
DIFFIO_R1n/PADD20/DQS2R/CQ3R,CDPCLK5C16
DIFFIO_R1pC15
CLK4/DIFFCLK_2pE15
CLK5/DIFFCLK_2nE16
Page 7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BANK 7
BANK 8
LED0
GPIO_0_IN1GPIO_0_IN0
LED3
LED1LED2
GPIO_029
GPIO_031GPIO_027
GPIO_025
GPIO_022
GPIO_023
GPIO_024
GPIO_026
GPIO_028
GPIO_020GPIO_018GPIO_021
GPIO_015
GPIO_016
GPIO_010
GPIO_013
GPIO_014
GPIO_07GPIO_08
GPIO_011
GPIO_05GPIO_06
GPIO_02GPIO_03
GPIO_019
GPIO_017
GPIO_09GPIO_04GPIO_012
GPIO_00GPIO_01
GPIO_032
GPIO_033GPIO_030
GPIO_20
GPIO_22GPIO_27
SW2
GPIO_2[12..0]
LED[7..0]SW[3..0]
ADC_CS_NADC_SCLK
ADC_SDAT
GPIO_0[33..0]
GPIO_0_IN[1..0]
ADC_SADDR
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK7 & BANK8 B
DE0-Nano Board
B
7 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK7 & BANK8 B
DE0-Nano Board
B
7 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 BANK7 & BANK8 B
DE0-Nano Board
B
7 14Wednesday, October 26, 2011
U1H
EP4CE22F17
DIFFIO_T11p/PADD17/DQS5T/CQ5T#,DPCLK10C8
IO8_0/DQ3TD8
DIFFIO_T10n/DATA2/DQ3TE8
DIFFIO_T10p/DATA3F8
DIFFIO_T9n/PADD18/DQ3TA7
DIFFIO_T9p/DATA4/DQ3TB7
IO/VREFB8N0C6
DIFFIO_T7n/DATA14/DQS3T/CQ3T#,DPCLK11A6
DIFFIO_T7p/DATA13/DQ3TB6
IO8_1/DATA5/DQ3TE7
DIFFIO_T6p/DATA6/DQ3TE6
DIFFIO_T5n/DATA7/DQ3TA5
DIFFIO_T5p/DATA8/DQ3TB5
DIFFIO_T4n/DATA9D6
DIFFIO_T3n/DATA10/DM3T/BWS#3TA4
DIFFIO_T3p/DATA11B4
DIFFIO_T2nA2
DIFFIO_T2pA3
IO8_2D5
IO8_3/DATA12B3
PLL3_CLKOUTpD3
PLL3_CLKOUTnC3
CLK11/DIFFCLK_4pB8
CLK10/DIFFCLK_4nA8
U1G
EP4CE22F17
DIFFIO_T24nC14
DIFFIO_T24p/DQ5TD14
DIFFIO_T23nD11
DIFFIO_T23p/DQS0T/CQ1T,CDPCLK6D12
DIFFIO_T22nA13
DIFFIO_T22p/DQ5TB13
PLL2_CLKOUTnA14PLL2_CLKOUTpB14
RUP4E11
RDN4E10
DIFFIO_T21n/DQ5TA12
DIFFIO_T21p/DQ5TB12
DIFFIO_T20n/DQ5TA11
DIFFIO_T20p/PADD0/DQ5TB11
IO/VREFB7N0C11
DIFFIO_T19n/PADD1A15
DIFFIO_T17p/PADD4/DQS2T/CQ3T,DPCLK8F9
DIFFIO_T16n/PADD5/DQ5TA10
DIFFIO_T16p/PADD6/DQ5TB10
DIFFIO_T15n/PADD7/DQ5TC9
DIFFIO_T15p/PADD8/DM5T/BWS#5TD9
DIFFIO_T13p/PADD12/DQS4T/CQ5T,DPCLK9E9
CLK9/DIFFCLK_5pB9
CLK8/DIFFCLK_5nA9
Page 8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
POWER & GND
CONFIGURATIONAS Fast POR configuration
at 3.0- or 2.5-VTMS
TDI
TDO
TCK
NSTATUS
NCE
NCONFIG
TDITMS
TDO
TCK
DCLK
ASDONCSODATA0
CONF_DONE
VCC1P2 VCCD_PLLVCC2P5 VCCA
VCC1P2
VCCD_PLL
VCC3P3
VCCD_PLLVCCA
VCC3P3 VCC3P3
VCC1P2 VCC1P2VCC1P2VCC1P2 VCC1P2VCC1P2
VCCA
VCCA
VCCA
VCCA
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 POWER and CONFIGURATION B
DE0-Nano Board
B
8 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 POWER and CONFIGURATION B
DE0-Nano Board
B
8 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EP4CE22 POWER and CONFIGURATION B
DE0-Nano Board
B
8 14Wednesday, October 26, 2011
U1J
EP4CE22F17
TCKH3
TMSJ5
TDIH4
TDOJ4
DCLKH1
nSTATUSF4
nCONFIGH5
nCEJ3
ASDOC1
nCSOD2
DATA0H2
CONF_DONEH14
MSEL0H13
MSEL1H12
MSEL2G12
R10
0DNI
C13
0.1u
C3
2.2n
C2
2.2n
C20
0.1u
R9
0
C26
0.1u
C8
0.47u
C32
0.1u
R4 TBDDNI
C19
0.1u
C24
0.1u
C10
0.1u
R5
10K
C4
4.7n
C22
0.1u
C21
0.1u
C12
0.1u
C17
0.1u
C35
10u
C28
0.1u
C16
0.1u
L2 BEADL1 BEAD
C6
10n
C15
0.1u
C31
0.1u
C30
0.1u
U1I
EP4CE22F17
GN
DH
7
GN
DH
8
GN
DH
9
GN
DH
10
GN
DJ7
GN
DJ8
GN
DJ9
GN
DJ1
0
GN
DF
6
GN
DF
10
GN
DJ1
1
GN
DK
8
GN
DK
6
GN
DL
9
GN
DL
10
GN
DL
11
GN
DK
12
GN
DG
11
GN
DB
2
GN
DB
15
GN
DC
5
GN
DC
12
GN
DD
7
GN
DD
10
GNDE4
GNDE13
GNDG4
GNDG13
GNDK4
GNDK13
GNDM4
GNDM13
GNDN7
GNDN10
GNDP5
GNDP12
GNDR2
GNDR15
GNDE2
GNDH16
GNDH15
GNDA1M5
GNDA2E12
GNDA3E5
GNDA4M12
VCCINTF7
VCCINTF11
VCCINTG6
VCCINTG7
VCCINTG8
VCCINTG9
VCCINTG10
VCCINTH6
VCCINTH11
VCCINTJ6
VCCINTK7
VCCINTK11
VCCINTL6
VCCINTK9
VCCINTK10
VCCINTM9
VCCINTM11
VCCINTJ12
VCCA1L5
VCCA2F12
VCCA3F5
VCCA4L12
VCCD_PLL1N4
VCCD_PLL2D13
VCCD_PLL3D4
VCCD_PLL4N13
VC
CIO
1E
3
VC
CIO
1G
3
VC
CIO
2K
3
VC
CIO
2M
3
VC
CIO
3P
4
VC
CIO
3P
7
VC
CIO
3T
1
VC
CIO
4P
10
VC
CIO
4P
13
VC
CIO
4T
16
VC
CIO
5K
14
VC
CIO
5M
14
VC
CIO
6E
14
VC
CIO
6G
14
VC
CIO
7A
16
VC
CIO
7C
10
VC
CIO
7C
13
VC
CIO
8A
1
VC
CIO
8C
4
VC
CIO
8C
7
C36
10u
C5
4.7n
C29
0.1u
C37
TBDDNI
C9
0.47u
R6
10K R71K
R8
0DNI
C23
0.1u
C18
100u
C33
0.1u
R2
0DNI
C1
100u
C25
0.1u
R1
0
C34
0.1u
C7
10n
C14
0.1u
C11
0.1u
R11 1K
DNI
C27
0.1u
R3
0
Page 9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LED2LED1
LED3
LED0
LED4
LED7LED6LED5
KEY0KEY1
SW0SW1SW2SW3
LED[7..0]
CLOCK_50
KEY[1..0]
SW[3..0]
VCC3P3
VCC3P3
VCC3P3
VCC3P3
VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & LED & BUTTON & SWITCH B
DE0-Nano Board
B
9 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & LED & BUTTON & SWITCH B
DE0-Nano Board
B
9 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
CLOCK & LED & BUTTON & SWITCH B
DE0-Nano Board
B
9 14Wednesday, October 26, 2011
R13
2K
LED3 LEDG Y1
50MHZ
VCC4
OUT3
GND2
EN1
C40
1n
RN2 1201234 5
678
RN3
10K
1 2 3 45678
U2
SN74AUC17
1A1
2A3
3A5
4A9
5A11
6A13
1Y2
2Y4
3Y6
4Y8
5Y10
6Y12
GND7
VCC14
ETP15
C41
0.1u
LED7 LEDG
LED0 LEDG
KEY0
TACK_SW_RA
4 3
21
RN1 1201234 5
678
C38
0.1u
R12
100K
R15
2K
KEY1
TACK_SW_RA
4 3
21
R14
100K
LED6 LEDG
LED5 LEDG
LED4 LEDG
C39
1n
LED2 LEDG
ON
1
SW1
SW-DIP8
1234
8765
LED1 LEDG
Page 10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPIO - 0 GPIO - 1
GPIO - 2
GPIO_032GPIO_031
GPIO_07
GPIO_012
GPIO_0_IN1GPIO_0_IN0
GPIO_011
GPIO_016GPIO_014
GPIO_020GPIO_019
GPIO_010
GPIO_022
GPIO_026
GPIO_030
GPIO_017GPIO_015
GPIO_06
GPIO_00
GPIO_024
GPIO_013
GPIO_09
GPIO_021
GPIO_033
GPIO_029
GPIO_025
GPIO_023
GPIO_02
GPIO_018
GPIO_028
GPIO_08
GPIO_05GPIO_04
GPIO_027
GPIO_03
GPIO_132GPIO_131
GPIO_17
GPIO_112
GPIO_1_IN1GPIO_1_IN0
GPIO_111
GPIO_116GPIO_114
GPIO_120GPIO_119
GPIO_110
GPIO_122
GPIO_126
GPIO_130
GPIO_117GPIO_115
GPIO_16
GPIO_10
GPIO_124
GPIO_113
GPIO_19
GPIO_121
GPIO_133
GPIO_129
GPIO_125
GPIO_123
GPIO_12
GPIO_118
GPIO_128
GPIO_18
GPIO_15GPIO_14
GPIO_127
GPIO_13
GPIO_2_IN1GPIO_20GPIO_22GPIO_24GPIO_26GPIO_28GPIO_210GPIO_212
GPIO_2_IN0GPIO_2_IN2GPIO_21GPIO_23GPIO_25GPIO_27GPIO_29GPIO_211
GPIO_01 GPIO_11
Analog_In0Analog_In4
Analog_In6Analog_In3
Analog_In5Analog_In7
Analog_In1
Analog_In2
GPIO_0[33..0]
GPIO_0_IN[1..0]
GPIO_2[12..0]
GPIO_2_IN[2..0]
GPIO_1[33..0]
GPIO_1_IN[1..0]
VCC_SYS
VCC3P3
VCC_SYS
VCC3P3
VCC3P3
Analog_In[7..0]
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIOs & 2X13 Header B
DE0-Nano Board
B
10 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIOs & 2X13 Header B
DE0-Nano Board
B
10 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIOs & 2X13 Header B
DE0-Nano Board
B
10 14Wednesday, October 26, 2011
JP2
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
JP3
2X13 HEADER
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
JP1
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
Page 11
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Digital Accelerometer
ADC_IN0ADC_IN1ADC_IN2ADC_IN3ADC_IN4ADC_IN5ADC_IN6ADC_IN7
ADC_IN1Analog_In1
ADC_IN2Analog_In2
ADC_IN3Analog_In3
ADC_IN4Analog_In4
ADC_IN5Analog_In5
ADC_IN6Analog_In6
ADC_IN7Analog_In7
ADC_IN0Analog_In0
G_SENSOR_CS_N
G_SENSOR_INT
I2C_SCLK
I2C_SDAT
ADC_SDAT
ADC_SCLK
ADC_SADDR
ADC_CS_N
VCC_VS
VCC3P3
VCC3P3
VCC_VS
VCC_VS
VCC_VSVCC3P3
AGND
AGNDAGND
AGND
VCC3P3_VA
VCC3P3VCC3P3_VA
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VCC3P3
Analog_In[7..0]
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
G-Sensor & ADC B
DE0-Nano Board
B
11 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
G-Sensor & ADC B
DE0-Nano Board
B
11 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
G-Sensor & ADC B
DE0-Nano Board
B
11 14Wednesday, October 26, 2011
U3
ADXL345
VDD1
GND2
RESERVED3
GND4
GND5
VS6
CS_n7
INT18INT29NC10RESERVED_111SDO_ALT_ADDRESS12SDA_SDI_SDIO13SCL_SCLK14
R26 22
C45
0.1u
R22 22
C47 1u
C54
1n
U4
ADC128S022CIMTX
IN04
IN15
IN26
IN37
IN48
IN59
IN610
IN711 SCLK
16
DOUT15
DIN14
CS_n1
VA
2
VD
13
AG
ND
3
DG
ND
12
C44
1u
C43
0.1u
C42
1u
R16 49.9
R62 0DNI
C49 0.1u
C53
0.1u
C48
1nR21
2.2KDNI
R24 22
C57
1n
R17 22
R18
2.2KDNI
R27 22
L4
BEAD
C55
1n
R20 22
R25 22
C50
1n
L3 BEAD
C51
1n
R28 22
C46
1n
C56
1n
R19 10K
C52
4.7u
Page 12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DRAM_ADDR3
DRAM_ADDR0
DRAM_ADDR2DRAM_ADDR1
DRAM_ADDR10
DRAM_DQM0
DRAM_DQ5
DRAM_DQ0
DRAM_DQ7DRAM_DQ6
DRAM_DQ3DRAM_DQ2
DRAM_DQ4
DRAM_DQ1
DRAM_ADDR12
DRAM_ADDR5
DRAM_ADDR7DRAM_ADDR6
DRAM_ADDR8
DRAM_ADDR11
DRAM_ADDR4
DRAM_ADDR9
DRAM_DQM1
DRAM_DQ8
DRAM_DQ15
DRAM_DQ11
DRAM_DQ9DRAM_DQ10
DRAM_DQ13DRAM_DQ14
DRAM_DQ12
DRAM_DQM[1..0]
DRAM_DQ[15..0]
DRAM_ADDR[12..0]
DRAM_CLKDRAM_CKE
DRAM_BA0DRAM_BA1
DRAM_WE_NDRAM_CAS_NDRAM_RAS_NDRAM_CS_N
VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE0-Nano Board
A
12 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE0-Nano Board
A
12 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM B
DE0-Nano Board
A
12 14Wednesday, October 26, 2011
U5
SDRAM 16Mx16
A023
A124
A225
A326
A429
A530
A631
A732
A833
A934
nCAS17
nRAS18
LDQM15
nWE16
nCS19
CKE37 CLK38
UDQM39
D02
D14
D25
D37
D48
D510
D611
D713
D842
D944
D1045
D1147
D1248
D1350
D1451
D1553
A1236
BA020
VD
D1
VD
D2
7
VS
S2
8
VS
S4
1
A1022
VD
DQ
3
VD
DQ
9
VD
DQ
43
VD
DQ
49
VS
SQ
6
VS
SQ
12
VS
SQ
46
VS
SQ
52
A1135
BA121
VS
S5
4V
DD
14
C62
0.1u
C63
0.1u
C58
0.1u
C64
0.1u
C59
0.1u
C60
0.1u
C61
0.1u
Page 13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C ADDRESS W/R = 0xA0/0xA1
I2C_SCLKI2C_SDAT
VCC3P3
VCC3P3VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EEPROM B
DE0-Nano Board
A
13 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EEPROM B
DE0-Nano Board
A
13 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
EEPROM B
DE0-Nano Board
A
13 14Wednesday, October 26, 2011
R351K
R30
0
DNI
R341K
C65
0.1u
R29
0
DNI
R33
2K
R31
0
DNI
A1A0
VSSA2
VCC
SDASCL
WP
U6
24LC02B
4 56
87
123
9R361K
R32
2K
Page 14
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_SYS Range:
3.3 ~ 5.5 V
2.5V/150mA
POWER
3.3V/1.5A
1.2V/1.5A
Input Power Range:
3.6 ~ 5.7 V
5V Power from USB Port
VCC2P5
VCC_SYS
VCC3P3
VCC3P3
VCC3P3
VCC3P3 VCC1P2
VCC_SYS
VCC5_USB
VCC3P3
VCC1P2
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
1.2V & 2.5V & 3.3V B
DE0-Nano Board
B
14 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
1.2V & 2.5V & 3.3V B
DE0-Nano Board
B
14 14Wednesday, October 26, 2011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2007 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
1.2V & 2.5V & 3.3V B
DE0-Nano Board
B
14 14Wednesday, October 26, 2011
C67
10u
C72
10u
R45
0DNI
FID6
REG2
LP5900SD-2.5
VIN6
GN
D3
VOUT1
VEN4
PA
D7
NC12
NC25
C69
0.47u
J6
1X4 HEADER
DNI
1234
FID1
R60 0
C73
10u
D7
PMEG2010AEB
FID7
R38
1.2K
R49
4.99K
MH3
REG3
LP38500SD-ADJ
IN2
IN3
IN4
GN
D1
OUT5OUT6OUT7
ADJ8
DA
P9
C74
0.1u
D2
LEDB
R40
120
C70
0.47u
FID5FID4
J2
SIP2 DNI
1 2
FID8
MH4
R48
4.99K
J5
1X4 HEADER
DNI
1234
REG1
LP38500SD-ADJ
IN2
IN3
IN4
GN
D1
OUT5OUT6OUT7
ADJ8
DA
P9
D5
PMEG2010AEB C68
0.1uC66
10u
R47
10K
R37
5.36KD6
PMEG2010AEB
J1
SIP2 DNI
1 2
R46 0
FID2 FID3
MH1
C71
0.1u
R61 0
JP4
Power - HDR
12
MH2
D8
PMEG2010AEB
