DOCUMENT INFORMATION ...................................................................................................................................................... 4
LIST OF TERMS AND ABBREVIATIONS .............................................................................................................................................. 4
1.1 OVERVIEW ........................................................................................................................................................................... 5 1.2 TOP LEVEL ARCHITECTURE ................................................................................................................................................. 5
2 INSTALLING THE EXAMPLE DESIGN ............................................................................................................................. 6
3 SYSTEM REQUIREMENT .................................................................................................................................................... 8
5 CLOCK AND RESET DISTRIBUTION .............................................................................................................................. 12
5.1 SYSTEM CLOCKING ............................................................................................................................................................ 12 5.2 RESET ................................................................................................................................................................................ 12
7.2.1 Impulse Response of Channel Filter LTE20: ............................................................................................................ 24 7.2.2 Impulse Response of Channel Filter LTE20: ............................................................................................................ 27 7.2.3 Sine Wave Result of Channel Filter LTE20 using Matlab: ....................................................................................... 27 7.2.4 Sine Wave Result of Channel Filter LTE20 using Modelsim:................................................................................... 30
7.3 LMS INTERFACE: ............................................................................................................................................................... 31 7.4 VERIFICATION METHODOLOGY ON BOARD ......................................................................................................................... 32 7.5 TEST DATA VERIFICATION .................................................................................................................................................. 33 7.6 SIGNAL GENERATOR DATA VERIFICATION .......................................................................................................................... 36
8 SET UP THE HARDWARE AND CONFIGURE THE FPGA .......................................................................................... 39
8.1 SET UP LIME CYCLONE IV STREAM BOARD AND LMS7002 EVM BOARD TESTING PLATFORM ....................................... 39 8.2 CONFIGURE LMS7002 EVM BOARD................................................................................................................................. 41 8.3 CONFIGURE CYCLONE IV DEVICE ..................................................................................................................................... 42 8.4 LMS INTERFACE LOOPBACK TEST ..................................................................................................................................... 43
10 REVISION HISTORY ....................................................................................................................................................... 48
`
Document Information
List of Terms and Abbreviations
BFM - Bus Functional Model
DDC - Digital Downlink Convert
DUC - Digital Uplink Convert
`
1 Introduction
1.1 Overview
Altera-Lime Connectivity and DUC/DDC Design Example is to demonstrate connectivity between Cyclone IV
Stream development kit with Lime Field Programmable RF development kit through FMC connector, and it also is
used to demonstrate software defined radio solution on Altera low cost FPGA.
1.2 Top Level Architecture
The Figure 1-1 show the high level block diagram of Altera-Lime Connectivity and DUC/DDC Design Example in
FPGA. This design example contains two main functional blocks, they are Channel Filter LTE20 block and LMS
interface block. Channel Filter LTE20 block is digital band-pass filter, which is used to shape 20M LTE signal. Since
the input data sample rate of Channel Filter LTE20 block is the same with the output data sample rate, Channel Filter
LTE20 block can be reused for the downlink data path and the uplink data path. LMS interface block is the bridge
between Cyclone IV Stream development kit with Lime Field Programmable RF development kit, which uses DDIO
interface to transfer the data. Lime LMS7002 integrate NCO Mixer inside, so there is no NCO Mixer needed in the
design example, if you want to migrate the design to connect with another external RF development kit without NCO
Mixer inside, you should add NCO Mixer in FPGA.
Figure 1-1 Top Level Block Diagram
Cyclone IV Stream DevKit
Channel Filter LTE20
Channel Filter LTE20
Channel Filter LTE20
Channel Filter LTE20
LMSinterface
LMS7002
DAC
DAC
ADC
ADC
30.72MSPS
30.72MSPS
30.72MSPS
30.72MSPS
30.72MSPS
30.72MSPS
30.72MSPS
30.72MSPS
Mixer
Mixer
`
2 Installing the Example Design
You can download the design example files from the Altera-Lime Connectivity and DUC/DDC Design Example web page. Figure 2-1 shows the directory structure for the design example files after you extract them from the .par file.
Do not use spaces or special characters in the path name.
Figure 2-1 Design Example Directory Structure
<path>
Channel_Filter_LTE20
Installation directory. Contains files listed in Table2
Top-level file and all design file folder
Channel filter LTE20 design file for DDC
Channel_Filter_LTE20_down
Channel filter LTE20 design file for DUC
lms
LMS interface design file
ip
Altera Megacore IP file
other
rtl
Error detection and frequency difference detection file
Channel_Filter_LTE20
All DSP Builder design file
Channel filter LTE20 DSP builder design file for DDC
Channel_Filter_LTE20_down
Channel filter LTE20 DSP builder design file for DUC
DSPBuilder
Configuration file is used for configuring Lime
LMS7002 EVM board based on 30.72MHz TCXO
Lime_Configuration_File
Libraries
DSP Builder Libraries for design example project
Table 2-1 shows the files in the top-level directory:
The external interface of the reference design is LMS interface, which forms a bridge between Altera Cyclone IV
Stream development kit and Lime EVM board. Altera Cyclone IV Stream board also needs a working clock, which has
the required 0ppm difference with respect to LMS7002 working clock. Considering about the 0ppm difference
requirement, I prefer this clock is from Lime EVM board through FMC connector.
4.1 Overview
LMS interface contains two functional blocks, they are LMS_TX block and LMS_RX block. LMS_TX block is used to
transfer the output data of Channel Filter LTE20M module to ASSP LMS7002 on Lime EVM board, LMS_RX block is
used to receive the output data of LMS7002 in Lime EVM board to Channel Filter LTE20M module. LMS interface
block diagram is shown as Figure 4-1.
Figure 4-1 LMS interface Block Diagram
LMS interface
reset
Chan_id_txdata[0]
LMS_TX
LMS_RXul_rx_data[11:0]
{IQSELEN1TX,DIQ1TX[11:0]}
MCLK1TX(61.44MHz)
MCLK2RX(61.44MHz)
{IQSELEN2RX,DIQ2RX[11:0]}
reset
Chan_id_rxdata[1:0]
dl_tx_data[11:0]
clk_122m88
clk_122m88
FCLK2RX(61.44MHz)
FCLK1TX(61.44MHz)
4.1.1 Pin List Table:
The Table 4-1 shows the interface pin list of LMS_interface block in Cyclone IV FPGA.
Table 4-1 LMS_Interface Pin List
LMS Interface Pin List
Signal Name Width IO standard Direction Description
`
IQSELEN1TX 1 3.3V LVCMOS Output Downlink TX IQ data flag, 1: TX data is I, 0: TX data is Q
MCLK1TX 1 3.3V LVCMOS input Downlink DDIO TX data working clock, clock frequency is 61.44MHz
DIQ1TX 12 3.3V LVCMOS Output Downlink Transmitting IQ data
MCLK2RX 1 3.3V LVCMOS input uplink DDIO RX data working clock, clock frequency is 61.44MHz
IQSELEN2RX 1 3.3V LVCMOS input uplink RX IQ data flag, 1: RX data is I, 0: RX data is Q
DIQ2RX 12 3.3V LVCMOS input uplink receiving IQ data
FCLK1TX 1 3.3V LVCMOS Output Downlink TX data output clock, clock frequency is 61.44MHz
FCLK2RX 1 3.3V LVCMOS Output uplink RX data output clock, clock frequency is 61.44MHz
4.2 Interface Configurations
4.2.1 LMS TX interface
4.2.1.1 Overview
LMS_TX block is a downlink bridge between Channel Filter LTE20M and ASSP LMS7002, which is used to transfer
the output data of Channel Filter LTE20M to ASSP LMS7002 on Lime EVM board. The IO standard of the LMS_TX
block input/output port is 3.3V LVCMOS, and the clock frequency of interface is 61.44MHz. The data interface is
double data rate output port.
4.2.1.2 Block Diagram
The Figure 4-2 show the block diagram of LMS_TX interface in Cyclone IV FPGA.
Figure 4-2 LMS_TX interface Block Diagram
`
reset
Chan_id_txdata[0]
LMS_TXdl_tx_data[11:0]
clk_122m88 {IQSELEN1TX,DIQ1TX[11:0]}
MCLK1TX(61.44MHz)
FCLK1TX(61.44MHz)
PLL
DDIO1
0
Tx_clk(61.44M)
4.2.2 LMS RX interface
4.2.2.1 Overview
LMS_RX block is the uplink bridge between LMS7002 in Lime EVM board to Channel Filter LTE20M, which is used
to transfer the output data of ASSP LMS7002 on Lime EVM board to Channel Filter LTE20M. The IO standard of the
LMS_TX block input/output port is 3.3V LVCMOS, and the clock frequency of interface is 61.44MHz. The data
interface is double data rate input port.
4.2.2.2 Block Diagram
The Figure 4-3 shows the block diagram of LMS_RX interface in Cyclone IV FPGA.
Figure 4-3 LMS_RX interface Block Diagram
LMS_RXul_rx_data[11:0]
reset
Chan_id_rxdata[1:0]
clk_122m88
MCLK2RX(61.44MHz)
{IQSELEN2RX,DIQ2RX[11:0]}
PLL
Clk_122m88
rx_clk(61.44M)
`
5 Clock and Reset Distribution
5.1 System Clocking
There are two clock inputs from Lime EVM board through FMC connector, I will choose one clock input as system
clock. The required clock frequency is 122.88MHz, the input clock frequency is 61.44MHz, so we need use a PLL to
generate 122.88MHz clock for system. The Figure 5-1 shows the clock distribution block diagrams in Cyclone IV
FPGA.
Figure 5-1 Clock distribution block diagram
PLL0MCLK2RX(61.44MHz)
Clk_122m88(122.88MHz)
Rx_clk(61.44MHz)
PLL1MCLK1TX(61.44MHz) tx_clk(61.44MHz)
5.2 Reset
To make the whole system work properly, perform global reset on FPGA design after clock is stable, the reset pin is
from In-System Source and Probe Editor. The global reset is also controlled by detection circuity, if there is error after
you load the FPGA image, the detection circuitry will perform automatic reset on FPGA design. Only when the
automatic reset does not work, you need to manually reset FPGA design using In-System Source and Probe Editor.
`
6 Functional Block Description
6.1 Channel Filter LTE20:
Channel Filter LTE20 block is 87 taps digital band-pass filter, which is used to shape 20M LTE signal. To minimize the deviation introduced by digital filter calculation, the data width of input data to Channel Filter LTE20 is 16bit. To accommodate the LMS interface, for uplink data path, we will add 4bit to LSB bit of LMS_RX output data to form 16bit data to feed Channel Filter LTE20 block, for downlink data path, we will use another Scale block to truncate output data of filter to 12bit to feed the LMS_TX interface. So the Channel Filter LTE20 for uplink data path has only one different scale block with Channel Filter LTE20 for downlink data path, considering the difference will not affect the function, the data path and verification methodology are the same, we will only describe the Channel Filter LTE20 for uplink data path. The coefficients of filter are shown in Table 6-1.
The Table 6-2 shows the interface port list of Channel Filter LTE20 block in Cyclone IV FPGA.
Table 6-2 Channel Filter LTE20 interface port list
Interface Port List Table
Signal
Name
Width Direction Description
Clk_122m88 1 input Module working clock, clock frequency is 122.88MHz
reset 1 input Active high reset control signal
Data_in 15 input Module input data signal
Chan_id_in 2 input Input data Channel ID indicator signal
valid_in 1 input Input data valid indicator signal, 1:input data is valid, 0:input data is in valid,
Data_out 15 output Module output data signal
Chan_id_out 2 output Output data Channel ID indicator signal
valid_out 1 output output data valid indicator signal, 1: output data is valid, 0: output data is in
valid,
`
6.1.4 Clocking/Reset Scheme
This section provides implementation details and requirements on the clocks and resets for the function module:
6.1.4.1 Clock Requirements
The working clock of this module is 122.88MHz, this clock is generated by PLL.
6.1.4.2 Reset Requirements
To make the Channel Filter LET20M work properly, make sure the input data is valid, then de-assert the reset signal of this block.
6.1.5 Detailed Block Descriptions
Channel Filter LTE20 block is digital band-pass filter, which is used to shape 20M LTE signal. The development tools of this module is DSP builder associated with Matlab R2013a. The module include two submodule, one is the FIR filter, the other is the bus width scale module. The FIR filter is 87 taps single rate FIR filter, which is used to shape 4 channel 20M LTE signal. The bus width scale module is used to scale the bus width from FIR filter, it will scale data bus width from 30bit to 15bit. The number of input channel is four, the working clock is 122.88MHz, the sample rate of signal is 30.72MHz, so the four channel data can be handled within the single data flow.
6.2 LMS interface:
LMS interface forms a bridge between Altera Cyclone IV Stream development kit and Lime EVM board. LMS interface contains two functional blocks, they are LMS_TX block and LMS_RX block.
6.2.1 LMS TX
6.2.1.1 LMS_TX block interface Diagram:
The Figure 6-3 shows the block interface diagrams of LMS_TX block in Cyclone IV FPGA.
Figure 6-3 Functional Block Diagram
DDIO_TX
MCLK1TX(61.44MHz)
{IQSELEN1TX,DIQ1TX[11:0]}dl_ddrin_h[12:0]
dl_ddrin_l[12:0]
RAMClk_122m88
dl_tx_data[11:0]
Chan_id_txdata[0]
6.2.1.2 LMS_TX Block Interface Timing:
The Figure 6-4 show the block interface diagrams of LMS_TX block in Cyclone IV FPGA.
The Table 6-3 shows the interface port list of LMS_TX block in Cyclone IV FPGA.
Table 6-3 LMS_TX block Interface Port List
LMS_TX block Interface Port List Table
Signal Name Width Direction Description
Clk_122m88 1 input Module working clock, clock frequency is 122.88MHz
reset 1 input Active high reset control signal
dl_tx_data 12 input Module input data signal, from Channel Filter LTE20M
Chan_id_txdata 2 input Input data Channel ID indicator signal
valid_in 1 input Input data valid indicator signal, 1:input data is valid, 0:input data is in valid,
IQSELEN1TX 1 Output Downlink TX IQ data flag, 1: TX data is I, 0: TX data is Q
MCLK1TX 1 input Downlink DDIO TX data working clock, clock frequency is 61.44MHz
DIQ1TX 12 Output Downlink Transmitting IQ data
`
6.2.1.4 LMS_TX block Clocking/Reset Scheme
This section provides implementation details and requirements on the clocks and resets for the function module:
Clock Requirements
There are two working clock in this block, they are 122.88MHz and 61.44MHz, the clock of 122.88MHz is generated by PLL, the clock of 61.44MHz is from Lime EVM board.
Reset Requirements
There are no special reset requirements.
6.2.1.5 LMS_TX Detailed Block Descriptions
LMS_TX block receives the data from Channel Filter LTE20M, and sends the data to LMS7002 in Lime EVM board. The input clock frequency is 122.88MHz, and output clock frequency is 61.44MHz. LMS_TX block uses a BRAM to realize data transfer between 122.88MHz clock domain and 61.44MHz clock domain. These two clock both sources from LMS7002, while there phase relationship is not deterministic. Gray code is used in BRAM depth calculation.
The input data width of BRAM is 13, which is made up with the input 12 bit data width and bit 1 of the input channel id. The output data width of BRAM is 26. The data interface between FPGA and LMS7002 is double data rate output port, so LMS_TX block utilizes DDIO_TX IP to realize the double data rate transfer on the output port. The 13 bit output data includes the 12 bit data and IQ_SEL indication.
The BRAM depth is 32. Watermark is set to 16. Read address will be reset if the watermark is beyond (14, 18) range.
6.2.2 LMS_RX
6.2.2.1 LMS_RX block interface Diagram:
The Figure 6-5 shows the block interface diagrams of LMS_RX block in Cyclone IV FPGA.
Figure 6-5 Functional Block Diagram
DDIO_RX
MCLK2RX(61.44MHz)
{IQSELEN2RX,DIQ2RX[11:0]}ul_ddio_h[12:0]
ul_ddio_l[12:0]
RAM
Clk_122m88
ul_rx_data[11:0]
Chan_id_rxdata[1:0]
6.2.2.2 LMS_RX Block Interface Timing:
The Figure 6-6 shows the block interface diagrams of LMS_RX block in Cyclone IV FPGA.
The Table 6-4 shows the interface port list of LMS_RX block in Cyclone IV FPGA.
Table 6-4 LMS_RX block Interface Port List
LMS_RX block Interface Port List Table
Signal Name Width Direction Description
Clk_122m88 1 input Module working clock, clock frequency is 122.88MHz
reset 1 input Active high reset control signal
MCLK2RX 1 input uplink DDIO RX data working clock, clock frequency is 61.44MHz
IQSELEN2RX 1 input uplink RX IQ data flag, 1: RX data is I, 0: RX data is Q
DIQ2RX 12 input uplink receiving IQ data
ul_rx_data 12 output Module output data signal
Chan_id_rxdata 2 output Output data Channel ID indicator signal
valid_out 1 output output data valid indicator signal, 1: output data is valid, 0: output data is in
valid,
FCLK2RX 1 output uplink RX data output clock, clock frequency is 61.44MHz
`
6.2.2.4 LMS_RX block Clocking/Reset Scheme
This section provides implementation details and requirements on the clocks and resets for the function module:
Clock Requirements
There are two working clock in this block, they are 122.88MHz and 61.44MHz, the clock of 122.88MHz is generated by PLL, the clock of 61.44MHz is from Lime EVM board.
Reset Requirements
There are no special reset requirements.
6.2.2.5 LMS_RX Detailed Block Descriptions
LMS_RX block receives data of LMS7002 in Lime EVM board, and send data to Channel Filter LTE20M. The input clock frequency is 61.44 MHz, and output clock frequency is 122.88MHz. LMS_RX block uses a BRAM to realize data transfer between 122.88MHz clock domain and 61.44MHz clock domain. These two clock both sources from LMS7002, while there phase relationship is not deterministic. Gray code is used in BRAM depth calculation.
The output data width of DDIO_RX is 13bit with 12bit data and 1bit IQ flag. The input data width of BRAM is 26, the data width is 24bit and the IQ flag width is 2bit. The output data width of BRAM is 13.The output data of LMS_RX contains the 12 bit data output and 2 bit channel indication which is made up with 1 bit IQ flag and 1 bit ram read address.
The BRAM depth is 32. Watermark is set to 16. Read address will be reset if the watermark is beyond (14, 18) range.
6.2.3 Test_Module
6.2.3.1 Test_Module Block Interface Diagram
NA. Refer to detailed description for detail.
6.2.3.2 Test_Module Block Interface Timing
The Figure 6-7 shows the block interface timing of Test_Module block in Cyclone IV FPGA.
Figure 6-7 Test_Module Block Interface Timing
X ~X Y ~Y
Clk_122m88
O_data[11:0] X+3 ~(X+3) Y+5 ~(Y+5)
0 1 2 3o_data[1:0] 0 1 2 3
Output data
O_en
6.2.3.3 Test_Module Pin List Table
The Table 6-5 shows the interface port list of Test_Module block in Cyclone IV FPGA.
`
Table 6-5 LMS_RX block Interface Port List
Test_Module block Interface Port List Table
Signal Name Width Direction Description
Clk_122m88 1 input Module working clock, clock frequency is 122.88MHz
reset 1 input Active high reset control signal
o_en 1 output Ouput enable signal, always high
o_num 2 output Output channel number, increment from 0 to 3 and loop
o_data 12 output Output data,
i_en 1 input Input enable signal, always high.
i_num 2 input Input channel number, increment from 0 to 3 and loop
i_data 12 input Input data.
o_error 4 output The error indication of the 4 channels input data.
6.2.3.4 Test_Module block Clocking/Reset Scheme
Test Module works at 122.88M Hz clock domain.
6.2.3.5 Test_Module Detailed Description
Test Module generates data at output port shown as 6.2.3.2 . Once the Test module receives the same data pattern it sends out. The error indication will be cleared. This module is used for test LMS interface. Refer to Verification plan for detail.
6.3 Error Detect Module
chan_id_err_det
Channel ID error detection module is used to detect the DDC input channel ID and output channel ID, if there is error when comparing DDC input channel ID with DDC output channel ID, detection circuitry will initiate first stage reset circuitry to reset the LMS interface, uplink Channel Filter LTE20 and downlink Channel Filter LTE20. If the first stage reset can not work, it will trigger second stage reset to reset all the logic in the design.
pll_lock_det
PLL lock detection module is used to detect the PLL0 and PLL1 output lock signal, if PLL0 or PLL1 unlock, this module will output a status signal for customer. If the output status signal is high, PLL0 and PLL1 is not locked stably, if the output status signal is low, PLL0 and PLL1 is locked stably.
ppm_det
PPM difference detection module is used to detect clock frequency PPM difference between MCLK1TX and MCLK2RX. If there is clock frequency PPM difference between MCLK1TX and MCLK2RX, this module will output the according PPM difference based on the detection result. The PPM difference result are within 20 PPM difference,
`
more than 800PPM difference but within 160 PPM difference, more than 160PPM difference. If the PPM difference result is with than 20PPM difference, FPGA LED1(LD10) on Stream Board will be illuminating, otherwise, FPGA LED1(LD10) will be OFF.
`
7 Verification Plan Description
7.1 Overview
The verification plan of Altera-Lime Connectivity and DUC/DDC Design Example includes two phases. The first phase is the functional simulation during code design phase, which is to make sure the design’s function is correct. The second phase is the verification on development kit, which is used to demonstrate the DDC/DUC solution on low cost FPGA and Lime programmable RF board’s capability. Considering the simulation time and complexity of the design, the functional simulation is performed on each module individually. The test bench of each module is developed by the design owner of each module.
To accommodate the LMS interface, for uplink data path, we will add 4bit to LSB bit of LMS_RX output data to form 16bit data to feed Channel Filter LTE20 block, for downlink data path, we will use another Scale block to truncate output data of filter to 12bit to feed the LMS_TX interface. So the Channel Filter LTE20 for uplink data path has only one different scale block with Channel Filter LTE20 for downlink data path, considering the difference will not affect the function, the data path and verification methodology are the same, we will only describe the Channel Filter LTE20 for uplink data path.
7.2 Channel Filter LTE20:
Channel Filter LTE20 block is digital band-pass filter, which is used to shape 20M LTE signal. For digital filter, they are two approaches for functional verification, the first one is to generate an impulse signal to feed into the Channel Filter LTE20, the output of channel filter should be the coefficient of Channel Filter LTE20 or the integer multiple of the coefficient of Channel Filter LTE20. The second one is to generate a Sine Wave signal to feed into the Channel Filter LTE20, the output of channel filter should be the Sine Wave signal. The number of input channel is four, the working clock is 122.88MHz, the sample rate of signal is 30.72MHz, so the four channel data is handled within the single data flow, so if we use Sine Wave signal to feed into the Channel Filter LTE20, we need to process the data into each channel data using Matlab, then we will use Matlab to compare wave between the input data and output data to verify the function of Channel Filter LTE20. We will use both approaches above to verify the design.
7.2.1 Impulse Response of Channel Filter LTE20:
The impulse response of Channel Filter LTE 20 is to generate an impulse signal to feed into the Channel Filter LTE20, the output of channel filter is the coefficient of Channel Filter LTE20, the simulation result in Modelsim is same with Channel Filter LTE20 coefficients which is quantized to 2^15 except center tap, this is caused by quantized precision, it is within our expectation. The simulation is shown as Table 7-1.
Table 7-1 Output data of Channel Filter LTE20
Tap Output data Coefficients quantize to 2^15
1 43 43
2 8 8
3 -39 -39
4 37 37
5 10 10
6 -48 -48
`
7 19 19
8 53 53
9 -73 -73
10 -4 -4
11 92 92
12 -67 -67
13 -62 -62
14 135 135
15 -33 -33
16 -137 -137
17 149 149
18 48 48
19 -220 -220
20 118 118
21 171 171
22 -277 -277
23 15 15
24 321 321
25 -274 -274
26 -167 -167
27 462 462
28 -167 -167
29 -425 -425
30 543 543
31 82 82
32 -733 -733
33 493 493
34 516 516
35 -1050 -1050
36 205 205
37 1220 1220
38 -1327 -1327
39 -578 -578
40 2559 2559
41 -1517 -1517
42 -3517 -3517
43 9709 9709
44 20260 20261
45 9709 9709
46 -3517 -3517
47 -1517 -1517
48 2559 2559
`
49 -578 -578
50 -1327 -1327
51 1220 1220
52 205 205
53 -1050 -1050
54 516 516
55 493 493
56 -733 -733
57 82 82
58 543 543
59 -425 -425
60 -167 -167
61 462 462
62 -167 -167
63 -274 -274
64 321 321
65 15 15
66 -277 -277
67 171 171
68 118 118
69 -220 -220
70 48 48
71 149 149
72 -137 -137
73 -33 -33
74 135 135
75 -62 -62
76 -67 -67
77 92 92
78 -4 -4
79 -73 -73
80 53 53
81 19 19
82 -48 -48
83 10 10
84 37 37
85 -39 -39
86 8 8
87 43 43
`
7.2.2 Impulse Response of Channel Filter LTE20:
The impulse response of Channel Filter LTE 20 is to generate an impulse signal to feed into the Channel Filter LTE20, the output of channel filter is the coefficient of Channel Filter LTE20. From the simulation output wave in Modelsim, the result is within our expectation. The simulation is shown as Figure 7-1.
Figure 7-1 Input/Output Wave in Modelsim
7.2.3 Sine Wave Result of Channel Filter LTE20 using Matlab:
The Sine Wave result of Channel Filter LTE 20 is to generate a Sine Wave signal to feed into the Channel Filter LTE20, the output of channel filter should be the Sine Wave signal. The number of input channel is four, the working clock is 122.88MHz, the sample rate of signal is 30.72MHz, so the four channel data is handled within the single data flow, so we use the same Sine Wave signal to feed into four channels of Channel Filter LTE20, the output result of each channel of Channel Filter LTE20 should be the same.
From the simulation result in the Matlab, the simulation result is within our expectation. The input Sine Wave is shown as Figure 7-2, the output Sine Wave is shown as Figure 7-3, the output Sine Wave of each is shown as Figure 7-4.
Figure 7-2 Input Sine Wave of Channel Filter LTE20
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Figure 7-3 Output Sine Wave of Channel Filter LTE20
`
Figure 7-4 Output Sine Wave of each Channel
`
7.2.4 Sine Wave Result of Channel Filter LTE20 using Modelsim:
The Sine Wave result of Channel Filter LTE 20 is to generate a Sine Wave signal to feed into the Channel Filter LTE20, the output of channel filter should be the Sine Wave signal. The number of input channel is four, the working clock is 122.88MHz, the sample rate of signal is 30.72MHz, so the four channel data is handled within the single data flow, so we use same Sine Wave signal to feed into four channels of Channel Filter LTE20, the output wave of four channels of Channel Filter LTE20 should be the same, and they should all be Sine Wave. From the simulation wave result, the simulation result is within our expectation. The simulation waveform is shown as Figure 7-5.
Figure 7-5 Input/Output Sine Wave in Modelsim
`
7.3 LMS interface:
LMS interface will be simulated by Modelsim. PRBS data stream will be inserted to channels and the test will get passed once the PRBS patter is locked by PRBS monitor module. It is also verified the scenario that the LMS interface clock and FPGA internal clock does not start at the same time. This scheme is used in both directions. LMS interface simulation block diagram is shown as Figure 7-6.
Figure 7-6 LMS Interface Simulation Block Diagram
Tb_LMS_RX
PRBS Gen1LMS RX
(DUT)PRBS Gen2
Mux
PRBS Mon1
PRBS Mon2
DeMux
Tb_LMS_TX
PRBS Mon1LMS TX
(DUT)PRBS Mon2
Demux
PRBS Gen2
PRBS Gen2
Mux
PRBS pattern locked figure is shown as Figure 7-7. Sync_loss signal will be cleared once it gets locked.
`
Figure 7-7 LMS interface Simulation Waveform
7.4 Verification methodology on board
When the functional simulation is completed, we will move to verification on board. Due to lack of spectrum analyzer, and LIME
LMS7002 integrate internal NCO test data generator, NCO test data generator can generate Sine Wave signal. The verification has
two stages, they are test data verification and signal generator data verification.
In the first test data verification stage, we will use LMS7002 to generate Sine Wave signal to feed into FPGA on antenna 0 and
antenna 1, FPGA will receive the data through LMS interface and output to uplink Channel Filter LTE20 on antenna 0 and
antenna 1, uplink Channel Filter LTE20 on both antennas will shape the data and transfer it to downlink Channel Filter LTE20 on
both antennas. We will sample the uplink Channel Filter LTE20 and downlink Channel Filter LTE20 input and output data,
compare the spectrum between received data and NCO test data using Matlab.
`
In the second signal generator data verification stage, we will use Signal Generator to generate Sine Wave signal to feed into
FPGA on antenna 0 and antenna 1, FPGA will receive the data through LMS interface and output to uplink Channel Filter LTE20
on antenna 0 and antenna 1, uplink Channel Filter LTE20 will shape the data and transfer it to downlink Channel Filter LTE20.
We will sample the LMS7002 device output data using oscilloscope, compare the spectrum between received data and
transmitting data using Matlab.
The verification data path is shown as blue arrow in Figure 7-8.
Figure 7-8 Verification Data Path Block Diagram
Cyclone IV Stream DevKit
Channel Filter LTE20 ant1
Channel Filter LTE20 ant0
Channel Filter LTE20 ant0
Channel Filter LTE20 ant1
LMSinterface
LMS7002
DAC_ant1
DAC_ant0
ADC_ant0
ADC_ant1
30.72MSPS
30.72MSPS
30.72MSPS
30.72MSPS
NCO_test_data/30.72MSPS
30.72MSPS
30.72MSPS
Mixer_ant1
Mixer_ant0
Mixer_ant1
Mixer_ant0
NCO_test_data
NCO_test_data/30.72MSPS
SMA Cable
Mux in FPGA
Oscilloscope/Spectrum Analyzer
Signal Generator
SMA Cable
SMA Cable
SMA Cable
7.5 Test data verification
In the first test data verification stage, we will use LMS7002 to generate clk/8 Sine Wave signal to on antenna 0 and generate
clk/4 Sine Wave signal antenna 1. We sample the uplink Channel Filter LTE20 and downlink Channel Filter LTE20 input and
output data, compare the spectrum between received data and NCO test data using Matlab. Clk/8 Sine Wave signal frequency
should be 3.84MHz, Clk/4 Sine Wave signal frequency should be 7.68MHz, due to FFT result precision, there is small frequency
difference in the matlab, it is within our expectation.
The spectrum waveforms of uplink DDC input in Matlab are shown in Figure 7-9 and Figure 7-10.
Figure 7-9 Chan0 Spectrum at uplink DDC input
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-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
x 107
-160
-140
-120
-100
-80
-60
-40
-20
0
X: 3.817e+06
Y: 0
freq(MHz)
dB
ChanA Spectrum
Figure 7-10 Chan1 Spectrum at uplink DDC input
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
x 107
-150
-100
-50
0X: -7.725e+06
Y: 0
freq(MHz)
dB
ChanB Spectrum
The output of uplink DDC is the same with input of downlink DUC, we only analyze the DDC output data. The spectrum
waveforms of uplink DDC output in Matlab are shown in Figure 7-11and Figure 7-12.
Figure 7-11 Chan0 Spectrum at uplink DDC output
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-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
x 107
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
X: 3.78e+06
Y: -3.33
freq(MHz)
dB
ChanA Spectrum
Figure 7-12 Chan1 Spectrum at uplink DDC output
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
x 107
-250
-200
-150
-100
-50
0
X: -7.68e+06
Y: 0
freq(MHz)
dB
ChanB Spectrum
The spectrum waveforms of downlink DUC output in Matlab are shown in Figure 77.5-13 and Figure 7-14.
Figure 7-13 Chan0 Spectrum at uplink DUC output
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-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
x 107
-160
-140
-120
-100
-80
-60
-40
-20
0
X: 3.817e+06
Y: 0
freq(MHz)
dB
ChanA Spectrum
Figure 7-14 Chan1 Spectrum at uplink DUC output
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
x 107
-150
-100
-50
0X: -7.725e+06
Y: 0
freq(MHz)
dB
ChanB Spectrum
7.6 Signal generator data verification
In the second signal generator data verification stage, we will use Signal Generator to generate 805MHz Square Wave signal to
feed into LMS7002 EVM board on antenna 0 and antenna 1, FPGA will receive the data through LMS, Channel Filter LTE20 will
shape the data and transfer it the LMS7002 device, LMS7002 device transfer the data into oscilloscope through the SMA cable,
`
we observe the result in the oscilloscope and sample the data using oscilloscope, equivalently compare the spectrum between
received data and transmitting data using Matlab, it is within our expectation.
The waveforms of LMS7002 output in Matlab are shown in Figure 7-15 and Figure 7-16.
Figure 7-15 LMS7002 Chan0 output data
0 1 2 3 4 5 6 7 8 9 10
x 105
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3Chan0 Data
-1 -0.5 0 0.5 1
x 105
-100
-80
-60
-40
-20
0
X: 4884
Y: 0
freq(MHz)
dB
X: -4884
Y: 0
Figure 7-16 LMS7002 Chan1 output data
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0 1 2 3 4 5 6 7 8 9 10
x 105
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3Chan1 Data
-1.5 -1 -0.5 0 0.5 1 1.5 2
x 105
-70
-60
-50
-40
-30
-20
-10
0
X: -4884
Y: 0
freq(MHz)
dB
X: 4884
Y: 0
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8 Set up the Hardware and Configure the FPGA
This section describes how to set up Lime Cyclone IV Stream Board and Lime LMS7002 EVM Board, and configure Cyclone IV device and LMS7002 EVM Board.
8.1 Set Up Lime Cyclone IV Stream Board and LMS7002 EVM Board Testing Platform
The Cyclone IV Stream board and LMS7002 EVM Board Hardware Set Up is shown as Figure 8-1.
Figure 8-1 Cyclone IV Stream Board and LMS7002 EVM Board Hardware Set Up
To set up the Lime Cyclone IV Stream Board and Lime LMS7002 EVM Board, perform the following steps:
1. Ensure you disconnect the power cable from the Lime Cyclone IV Stream Board and Lime LMS7002 EVM board.
2. Connect one end of the USB-Blaster cable to the USB port on your PC, connect the other end of the USB Blaster cable to the 10-pin header labeled (JTAG) on the Cyclone IV Stream Board.
3. Connect one end of the Mini USB cable to the USB port on your PC, connect the other end of the Mini USB cable to the Mini USB port on the LMS7002 EVM Board.
4. Connect the FMC interface connector port(J21) on Lime Cyclone IV Stream Board to FMC interface connector port(J6) on the Lime LMS7002 EVM Board.
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5. Connect the SMA cable from the LNAL_A port(X3) and LNAL_B port(X10) on the Lime LMS7002 EVM Board to the Signal Generator, connect the SMA cable from the TX2_A port (X2) and TX2_B port(X9) on the Lime LMS7002 EVM Board to the Oscilloscope/Spectrum Analyzer.
6. Connect the power cable from Agilent Power Module to Power port(J8) on the Lime LMS7002 EVM board. The output voltage must be set to 5.0V. Power on the Agilent Power Module, Enable Voltage output, so that the LED labeled LD3 illuminates. Connect the power cable to the Cyclone IV Stream board.
7. Connect the power cable to the Cyclone IV Stream board. Change the switch to the ON position so that the LED labeled POWER illuminates.
8. The Cable Connection on Cyclone IV Stream board and LMS7002 EVM Board is shown as Figure 8-2.
Figure 8-2 Cable Connection on Cyclone IV Stream Board and LMS7002 EVM Board
For details about installing the USB Blaster software driver on the host PC (located at <quartus_install_dir>\quartus\drivers\usb-blaster), refer to the USB-Blaster Download Cable User Guide.
For details about installing the software driver on the host PC for LMS7002 EVM Board, detailed information about the Cyclone IV Stream Board and LMS7002 EVM board, refer to the STREAM&LMS7002EVB User Guide. You can get the documentation and installation package through the below link: https://github.com/myriadrf/Stream.
To configure the LMS7002 EVM board, download the CIV_Stream_LMS7_61MHz_800M_30M72.ini file to the LMS7002 EVM board by following these steps:
1. Go to Design_Kit_Package\Unite7002_Design_Kit_Package_v.4.1\GUI folder, open control_LMS7002.exe.
2. On the Options menu, click Connections Settings. In the pop-up window, select the proper COM port for LMS7002 device, and then click OK. The Control LMS7002 GUI will begin to connect to LMS7002 EVM board. The Status window displays the result of connection. A message appears as shown in Figure 8-3 when the connection is OK.
Figure 8-3 Connection Successful Status
3. On the File menu, click Open. Navigate to Design_Kit_Package\Unite7002_Design_Kit_Package_v.4.1\GUI directory, load CIV_Stream_LMS7_61MHz_800M_30M72.ini file.
4. In the Control LMS7002 window, Click ‘GUIChip’ button. The Control LMS7002 GUI will begin to configure on the LMS7002 EVM board. The Status window displays the result of configuration. A message appears as shown in Figure 8-4 when the configuration is complete.
Figure 8-4 LMS7002 Configuration Successful Status
5. Go to ‘CLKGEN’ Tab, and click ‘Calculate’ and ‘Tune’ button. The Control LMS7002 GUI will begins to configure VCO on the LMS7002 EVM board. The Status window displays the result of configuration. A message appears as shown in Figure 8-5 when the configuration is complete.
Figure 8-5 Clock Generator Configuration Successful Status
6. Go to ‘SXT/SXR’ tab, and click ‘Calculate’, then select ‘B/SXT’ and click ‘Calculate’, finally click ‘Tune’ button. The Control LMS7002 GUI will begin to configure TX/RX NCO the LMS7002 EVM board. The Status window displays the result of configuration. A message appears as shown in Figure 8-6 when the configuration is complete.
Figure 8-6 TX/RX NCO Configuration Successful Status
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8.3 Configure Cyclone IV Device
To configure the Cyclone IV Device, download the Altera_Lime_SDR_demo.sof file to the Lime Stream board by following these steps:
1. In the Quartus II software, on the Tools menu, click Programmer.
2. On the File menu, click Save As.
3. Navigate to the design installation directory, and in the Save As dialog box, type Altera_Lime_SDR_demo.cdf in the File Name box.
4. In the Save as type list, select Chain Description File.
5. Click Save.
6. In the Programmer window, select JTAG in the Mode list.
7. Click Hardware Setup to configure the programming hardware. The Hardware Setup dialog box appears.
8. In the Hardware column, click USB-Blaster [USB-0].
9. In the Currently select hardware, select USB-Blaster [USB-0].
10. Click Close to exit the Hardware Setup dialog box.
11. Click Add file, browse to the design installation directory, click Altera_Lime_SDR_demo.sof, and click Open.
12. Turn on Program/Configure for Altera_Lime_SDR_demo.sof.
13. Click Start. The Programmer begins to download the configuration data to the FPGA. The Progress field displays the percentage of data that downloads. A message appears when the configuration is complete.
14. After the configuration complete, FPGA_LED0(LD9), FPGA_LED1(LD10), FPGA_LED2(LD11) illuminate when the FPGA logic work successfully.
If you do not use a licensed version of the Altera-Lime Connectivity and DUC/DDC Design Suite, a message appears indicating that you are running a time-limited configuration file on your target hardware.
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8.4 LMS Interface Loopback test
This test is intended to test the LMS interface.
8.4.1 Hardware environment
1. Connect the LMS7002EVB and Lime Stream board.
2. Connect Lime Stream board to Laptop with USB cable
3. Connect LMS7002EVB to laptop with USB Blaster.
4. Power up LMS7002EVB and Lime stream board.
5. Cable is not a must for loopback test.
6. The Hardware Environment is shown as Figure 8-7.
Figure 8-7 LMS Loopback Test HW Setup
8.4.2 Setting LMS7002 GUI
1. Board Initialization
Go to Design_Kit_Package\Unite7002_Design_Kit_Package_v.4.1\GUI folder, start control_LMS7002.exe
On the “Option” menu, click “Connection Setting” . In the pop-up window, select corresponding COM port, and
then click OK
o Expected result: “Connection Board on COMxx” shows in console window.
`
On the File menu, click on “Open” button.
Navigate to Design_Kit_Package\Unite7002_Design_Kit_Package_v.4.1\GUI directory, Open
CIV_Stream_LMS7_61MHz_800M_30M72.ini file.
Click on “GUI-->Chip”
Choose tab “CLKGEN”, click on “Calculate” , and then click on “Tune”
o Expected result: “VCO Coarse tuning CGEN finishes” shows in console window.
Choose tab SXT/SXR
o In the top-right of the GUI, select “A/SXR” option in “configuring channels” window, click on
Button “Calculate”
o Select “B/SXT” option, click on Button “Calculate”, and then click on “Tune”.
o Expected result: “VCO tuning SCT/SXR finished” shows in console window.
2. GUI Loopback setting snap shots are from Figure 8-8 to Figure 8-11:
Figure 8-8 LMS Loopback Test GUI Step1
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Figure 8-9 LMS Loopback Test GUI Step2
Figure 8-10 LMS Loopback Test GUI Step3
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Figure 8-11 LMS Loopback Test GUI Step4
8.4.3 Setting FPGA
Open Signal Tap II and downloading FPGA
Open In-System Source and Probe, and setting bit2 of Source[9:0] as ‘1’. (FPGA Test mode enable)
8.4.4 Expected Result
In inst_test_module instance, o_error is “0000”, the correct result in Signal Tap II is shown as Figure 8-12.
Figure 8-12 LMS Loopback Test Expected Result
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9 Conclusion
The Altera-Lime Connectivity and DUC/DDC Design Example demonstrates connectivity between Cyclone IV Stream development kit with Lime Field Programmable RF development kit through FMC connector, and it also demonstrates software defined radio solution on Altera low cost FPGA. The design uses DSP builder tools to realize Digital Intermediate Frequency design throughout the wireless system. DSP builder tools allow for high-performance push-button hardware description language (HDL) generation of digital signal processing (DSP) algorithms directly from the Simulink environment. You can easily migrate the design among different device family, and you can also easily modify the design to accommodate your application. It will greatly reduce your development cycle and your development cost, it is of great advantage for time to market of your product.
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10 Revision History
shows the revision history for the Reference Design Document: Altera-Lime Connectivity and DUC/DDC Design Example.
Table 10-1 Reference Design Document Revision History
Version Date Change Summary
1.0 July 2015 First release of this Reference Design Document.
