ALTERA MEGAFUNCTION PARTNERS PROGRAM...

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CatalogALTERA MEGAFUNCTION PARTNERS PROGRAM

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About this Catalog

May 1996

AMPP Catalog Contents

This catalog provides an introduction to the Altera Megafunction Partners Program, a description of each AMPP megafunction, and a listing of corporate profiles and contact information for each AMPP partner.

Each megafunction description includes a functional description as well as features or compliance to standards. When available, fitting and performance statistics are also provided. Megafunctions are grouped into the following functional areas:

■ Bus interfaces■ Microperipherals■ Processors and controllers■ Communications■ Digital signal processing■ Miscellaneous functions

Each AMPP partner profile includes specialization, capabilities, contact information, and a list of megafunctions. Some products listed in the AMPP partner profiles are available for non-Altera device architectures or design flows. Not all products are available for Altera devices. Many of the AMPP partners maintain a world-wide web (WWW) site that contains their most current corporate and product information. WWW site addresses are included with each partner’s contact information.

For additional details on available megafunctions, performance, verification support, or licensing, designers should contact the AMPP partners directly. For more information on joining the AMPP program as an intellectual property vendor, please contact:

AMPP Marketing Program ManagerTel: (408) 894-7174Fax: (408) 435-1394E-mail: [email protected]

Altera Corporation iii

About this Catalog

How to Contact Altera

For additional information about Altera products, consult the sources shown in the table below. For information on how to contact an Altera sales office, see the “Altera Sales Offices” section in this catalog.

Abbreviations The AMPP Catalog uses the following abbreviations:

A1S All 1sADC Analog-to-digital converterADPCM Adaptive Differential Pulse Code ModulationAHDL Altera Hardware Description LanguageALU Arithmetic logic unitAMPP Altera Megafunction Partners ProgramASIC Application-specific integrated circuitASPEC Application-specific processor engine coreASSP Application-specific standard productATM Asynchronous Transfer ModeBCT Binary Coded TernaryBER Bit error rateCAD Computer aided designCAS Channel associated signalingCCITT International Telegraph and Telephone Consultative

CommitteeCGA Color graphics adapterCIS Card information structureCISC Complex instruction-set computingCMOS Complementary metal-oxide siliconCODEC Coder/decoderCPU Central processing unit

Information Type Access U.S. & Canada All Other Locations

Literature Altera Express (800) 5-ALTERA (408) 894-7850

Altera Literature Department (408) 894-7144 (408) 894-7144

Non-Technical Customer Service Telephone Hotline (800) SOS-EPLD (408) 894-7000

Fax (408) 954-8186 (408) 954-8186

Technical Support Telephone Hotline (8 a.m. to 5 p.m. PST)

(800) 800-EPLD(408) 894-7000

(408) 894-7000

Fax (408) 954-0348 (408) 954-0348

Bulletin Board Service (408) 954-0104 (408) 954-0104

Electronic Mail [email protected] [email protected]

FTP Site ftp.altera.com ftp.altera.com

CompuServe go altera go altera

General Product Information Telephone (408) 894-7104 (408) 894-7104

World-Wide Web http://www.altera.com http://www.altera.com

iv Altera Corporation

About this Catalog

Corporate

1

Profiles

CRC Cyclic redundancy checkCRT Cathode-ray tubeDAC Digital-to-analog converterDCT Discrete cosine transformDFT Discrete Fourier transformDMA Direct-memory accessDRAM Dynamic random access memoryDSP Digital signal processingDSS Digital satellite systemDUT Device under testEAB Embedded array blockECL Emitter-coupled logicEDA Electronic Design AutomationEDIF Electronic Design Interface FormatEEPROM Electrically erasable programmable read-only memoryEGA Enhanced Graphic AdapterEISA Extended industry-standard architectureEPLD Erasable Programmable Logic DeviceFCS Frame Check SequenceFFT Fast Fourier transformFIFO First-in first-outFIR Finite impulse responseFISP Foundry Independent Standard ProductFLEX Flexible Logic Element MatriXGUI Graphical user interfaceHDL Hardware description languageHDLC High-level data link controllerHEC Header error controlIC Integrated circuitIEEE Institute of Electrical and Electronic EngineersIIR Infinite impulse responseI/O Input/outputIP Intellectual propertyISA Industry-standard architectureISDN Integrated services digital networkJPEG Joint Photographic Experts GroupLAN Local-area networkLAPB Link Access Procedure BalancedLAPD Link Access Procedure of the D ChannelLCD Liquid crystal displayLIFO Last-in first-outLSI Large-scale integrationLUT Look-up tableMAC Multiplier-accumulatorMAX Multiple Array MatriXMDA Monochrome display adapterMII Media Independent Interface

Altera Corporation v

About this Catalog

MPEG Motion Pictures Expert GroupNAN Not a numberOEM Original equipment manufacturerPC Personal computerPCI Peripheral component interconnectPCM Pulse-code modulationPCMCIA Personal Computer Memory Card International

AssociationPHY Physical layerPIC Programmable interrupt controllerPIT Programmable interrupt timerPLD Programmable logic devicePPP Point-to-point protocolRAM Random access memoryRAMDAC Random access memory digital-to-analog converterRISC Reduced instruction set computersROM Read-only memoryRTL Register transfer levelSAR Segmentation and reassemblySIG Special interest groupSRAM Static random access memorySVCL Standard Component VHDL LibraryUART Universal asynchronous receiver/transmitterUSART Universal synchronous/asynchronous

receiver/transmitterUSB Universal serial busUTOPIA Universal test and operations physical layer interface

for ATM data path interfaceVCI Virtual channel identifierVGA Video Graphics ArrayVHDL VHSIC hardware description languageVLSI Very large-scale integrationVME Versa Module EurocardVPI Virtual path identifierWAN Wide-area networkWWW World-wide webWYSIWYG What-you-see-is-what-you-getXMidi Extended musical instrument digital interface

vi Altera Corporation

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Contents

May 1996

About this Catalog .......................................................................................................................................... iiiAMPP Catalog Contents ....................................................................................................................... iiiHow to Contact Altera .......................................................................................................................... ivAbbreviations ......................................................................................................................................... iv

Section 1: Introduction ............................................................................................................................... 1

Overview...................................................................................................................................................1About AMPP.............................................................................................................................................1About the Megafunctions .......................................................................................................................2Licensing Terms .......................................................................................................................................4Using Megafunctions...............................................................................................................................4

Section 2: Bus Interfaces ........................................................................................................................... 5

EC100 PCI Bus Slave................................................................................................................................664-Bit PCI Bus Master..............................................................................................................................732-Bit PCI Bus Master..............................................................................................................................832-Bit PCI Bus Target...............................................................................................................................9EP100 PowerPC Bus Slave ....................................................................................................................10EP201 PowerPC Bus Master .................................................................................................................11EP300 PowerPC Arbiter ........................................................................................................................12MPCMCIA MegaMacro ........................................................................................................................13

Section 3: Microperipherals ....................................................................................................................15

8237 DMA Controller ............................................................................................................................16DMA Controller .....................................................................................................................................17

Section 4: Processors & Controllers.................................................................................................... 19

V6502 Microprocessor ...........................................................................................................................20VZ80 Microprocessor ............................................................................................................................212910A Microprogram Controller .........................................................................................................22M8051 MegaMacro Microcontroller....................................................................................................238051 Microcontroller..............................................................................................................................24EXcore-S080 Package.............................................................................................................................25

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Section 5: Communications ................................................................................................................... 27

Speedbridge ........................................................................................................................................... 28M16C450 UART..................................................................................................................................... 29M16550A UART .................................................................................................................................... 30RF-G704 Synchronous Framer/Deframer ......................................................................................... 31RF-G721 ADPCM Transcoder ............................................................................................................. 32RF-HDLC Controller ............................................................................................................................ 33RF-BRIM Basic Rate Interface.............................................................................................................. 34GF-RSC Reed Solomon CODEC ......................................................................................................... 35GF-LILAC Linked List Access Controller ......................................................................................... 36ATM Cell Delineation........................................................................................................................... 37ATM Cell Translation & Routing........................................................................................................ 38ATM Cell HEC Generator/Check ...................................................................................................... 39ATM Switch ........................................................................................................................................... 40UTOPIA Interface.................................................................................................................................. 41

Section 6: Digital Signal Processing .................................................................................................. 43

Programmable FIR Filter...................................................................................................................... 441-D Symmetric FIR Filter ..................................................................................................................... 451-D Median Filter .................................................................................................................................. 462-D FIR Filter.......................................................................................................................................... 47IIR Biquad Filter .................................................................................................................................... 48Laplacian Sharpening Filter (3 × 3).................................................................................................... 49Laplacian Edge Detector (3 × 3) ......................................................................................................... 50JPEG Decoder ........................................................................................................................................ 51JPEG Encoder......................................................................................................................................... 52Fast Fourier Transform......................................................................................................................... 53

Section 7: Miscellaneous Functions ................................................................................................... 55

Micro VGA Controller.......................................................................................................................... 56XM-01...................................................................................................................................................... 57XM-Blocks .............................................................................................................................................. 58IEEE-754 Floating Point........................................................................................................................ 59

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Contents

Section 8: AMPP Partner Profiles......................................................................................................... 61

3Soft Corporation...................................................................................................................................62Advancel Logic Corporation................................................................................................................64CAST, Inc.................................................................................................................................................65Digital Design & Development............................................................................................................67Eureka Technology ................................................................................................................................68Excellent Design Inc...............................................................................................................................70Infinite Solutions, Inc.............................................................................................................................72Integrated Silicon Systems Ltd.............................................................................................................74Logic Innovations, Inc. ..........................................................................................................................76Object Oriented Hardware ...................................................................................................................77Sierra Research and Technology, Inc. .................................................................................................79Silicon Engineering, Inc.........................................................................................................................80SIS Microelectronics, Inc. ......................................................................................................................82Synova Incorporated .............................................................................................................................84VAutomation Inc....................................................................................................................................85Virtual Chips, Inc. ..................................................................................................................................87

Section 9: Altera Sales Offices ...............................................................................................................89

Altera Corporation ix

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Introduction

May 1996

Overview Historically, designers used Boolean equations and schematic capture to develop low-density designs. As device densities rose above 10,000 gates, designers turned to high-level hardware description languages (HDLs)—such as VHDL and Verilog HDL—to improve productivity. With the advent of 100,000-gate programmable logic devices (PLDs), designers now require ready-made, pre-tested functional blocks that implement specific functions in a system-level design. Megafunctions fulfill that need.

Megafunctions can be instantiated in integrated circuit (IC) designs to implement specific functions such as bus interfaces, microprocessors, and digital signal processing (DSP) functions. While design engineers could develop these functions “from scratch,” it is often more time- and cost-effective to license a function that has been targeted for a specific architecture. As a result, reusable designs have been a key part of the gate array market for many years.

About AMPP The Altera Megafunction Partners Program (AMPP), established in August 1995, was created to bring the advantages of design reuse to users of Altera PLDs. AMPP is an alliance between Altera and developers of synthesizable megafunctions that encourages megafunction development. Altera provides technical information and training to the AMPP partners, who create commonly used megafunctions that are targeted for Altera devices. Altera has a strong commitment to Altera customers, the AMPP partners, and the success of the intellectual-property market in the PLD design environment.

To help the AMPP partners develop high-quality functions that are targeted for Altera devices, Altera holds an AMPP Developers Conference—an intensive two-day training course—for all AMPP partners. Follow-up training is offered as needed. The course covers the following subjects:

■ MAX+PLUS II software■ Altera device architectures■ Targeting and optimizing megafunctions for Altera devices■ Producing and packaging megafunctions

Altera Corporation 1

Introduction

About the Megafunctions

AMPP megafunctions are targeted for specific Altera device architectures. The targeting process typically involves setting compilation and synthesis options to achieve optimum density and performance. The megafunctions are then refined until they are as fast and small as possible.

Available Formats

The AMPP partners can provide megafunctions in the following formats:

■ VHDL■ Verilog HDL■ Altera Hardware Description Language (AHDL)■ Post-synthesis AHDL

Post-synthesis AHDL files, provided by most AMPP partners, reduce the possibility of unexpected changes occurring during the design process. For more information on available design file formats, designers should contact the AMPP partners directly.

Package Contents

Each packaged megafunction includes some or all of the following information, depending on the vendor:

■ Encrypted post-synthesis AHDL file (<function name>.tdf), VHDL, Verilog HDL, or AHDL file

■ Symbol File (<function name>.sym) for use in MAX+PLUS II schematics

■ List of critical timing parameters■ Documentation■ Authorization key(s)

In addition, some AMPP partners supply simulation models and verification suites, which can include simulation models that can be used in third-party EDA tools prior to MAX+PLUS II design processing, or with test vectors to check design functionality. Each partner offers a different level of design verification support. Designers should contact the AMPP partner directly for more information.

2 Altera Corporation

Introduction

Corporate

1

Profiles

Encryption

AMPP megafunctions are typically shipped in encrypted format to protect the partners’ intellectual property. Megafunction decryption is performed by the MAX+PLUS II software. MAX+PLUS II must be authorized to process a particular megafunction before design processing; the decryption key is supplied to customers when they license the megafunction from the AMPP partner.

Performance Characteristics

Performance characteristics incorporate on- and off-device I/O pin delays for Altera devices. When a megafunction is used with other logic or megafunctions, the I/O pin delays do not apply if all megafunctions and logic are combined in a single device. That is, performance typically improves because device interconnect delays are not necessary.

Performance and density characteristics in this catalog apply to megafunctions compiled as stand-alone designs, and are provided for general-purpose design requirements. Additional logic synthesis may affect the performance or density of a megafunction, particularly when the function is combined with other megafunctions or logic. Megafunctions shipped as post-synthesis AHDL files have minimal chance of performance or density variations as additional design processing is not required. Megafunctions supplied as VHDL, Verilog HDL, or AHDL source files may experience beneficial or adverse changes in performance or density, depending on the design and the target device. Timing cannot be determined definitively until synthesis of the final design is complete.

1 The performance characteristics of designs targeted for FLEX 10K devices are reported using the fastest speed grade (i.e., -5) device and simulation models available at the time of publication. FLEX 10K devices with a faster speed grade will be available in the future; contact the AMPP partners for the most current performance characteristics.

Warranty

The megafunctions in this catalog as well as other functions available from the AMPP partners are provided on an as-is basis without warranty by Altera. The AMPP partners may offer guarantees or warranties for design performance or functionality; contact the individual AMPP partners for details.


Introduction

The functional specifications in this catalog are supplied by the AMPP partners and are based on the MAX+PLUS II software version available at the time of publication. Subsequent versions of MAX+PLUS II or megafunction design modifications may affect density or performance characteristics. Contact the AMPP partners for the latest design statistics.

Licensing Terms Each AMPP partner specifies the megafunction licensing terms, such as:

■ Authorization codes and installation instructions■ Time-period during which access to the megafunction will be

granted■ Access to the source code for the megafunction

License details are not included in this catalog. Designers should contact the AMPP partners directly for additional licensing information.

Using Megafunctions

For design flows that use third-party EDA tools, designers can instantiate megafunctions in a design by specifying the function and port names in the HDL design file. During design processing, the EDA tool includes the megafunction in an EDIF netlist file. MAX+PLUS II compiles the resulting EDIF netlist file for the desired Altera device architecture. For MAX+PLUS II design flows, the designer simply inserts an instance of the megafunction in the design file.

After using the megafunction in a design file, the designer can use MAX+PLUS II to control how the design is compiled. For example, designers can

■ Apply the WYSIWYG logic synthesis style to the megafunction(s) in the design, ensuring that MAX+PLUS II will not further synthesize the megafunction

■ Set megafunction timing constraints so that critical path requirements are met during place and route

During compilation, MAX+PLUS II recognizes the function as an encrypted AMPP megafunction and verifies the function’s licensing. Then, MAX+PLUS II processes the megafunction and stores it directly in the design database.

f For more information on using MAX+PLUS II, go to MAX+PLUS II Help.


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Bus Interfaces

May 1996

EC100 PCI Bus Slave.........................................................................................................................................664-Bit PCI Bus Master.......................................................................................................................................732-Bit PCI Bus Master.......................................................................................................................................832-Bit PCI Bus Target........................................................................................................................................9EP100 PowerPC Bus Slave .............................................................................................................................10EP201 PowerPC Bus Master ..........................................................................................................................11EP300 PowerPC Arbiter .................................................................................................................................12MPCMCIA MegaMacro .................................................................................................................................13


Bus Interfaces

EC100 PCI Bus SlaveVendor: Eureka TechnologyAvailability: Now

The EC100 peripheral component interconnect (PCI) bus slave megafunction provides an interface between a target device and the PCI bus. This megafunction performs all data transfer functions the target device requires to process requests from other PCI master devices. To maximize bandwidth, the EC100 megafunction supports write buffer and burst data transfer.

The EC100 megafunction translates all PCI access information for the target device to a 486-style internal bus. Address and data parity checking and data parity generation are handled automatically, and all necessary PCI configuration registers are supported. Configuration accesses are processed locally without propagating into the slave interface.

Design File Format

Compilation Statistics

Note:(1) Contact Eureka Technology for this compilation statistic.

Format Target Architecture

MAX FLEX 8000 FLEX 10K

VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v

Optimization MAX FLEX 8000 FLEX 10K

Logic Cells fMAX Logic Cells fMAX Logic Cells EABs fMAX

Speed Note (1) Note (1) 185 33 MHz 190 33 MHz

Area


Bus Interfaces

Bus

2

Interfaces

64-Bit PCI Bus MasterVendor: Logic Innovations, Inc.Availability: June 1996

The 64-bit PCI bus master megafunction is implemented in VHDL- and Verilog HDL-based design files that are optimized for the Altera FLEX 10K device family. This megafunction is implemented at the

Preliminary Information

0-wait, 33-MHz, PCI bus maximum speed.

The following features are provided with the 64-bit PCI bus master megafunction:

■ Silicon-proven core■ Complete PCI test bench■ PCI SIG 2.1 compliance checklist■ Full-speed (0 wait, 33 MHz) burst mode support

(264 MByte/second)■ Integral 16 × 64 bit SRAM buffer■ Fully documented source code and user manual■ Customization services■ Evaluation card/board level schematics

Design File Format




VHDL v

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed 924 8 33 MHz

Area


Bus Interfaces

32-Bit PCI Bus MasterVendor: Logic Innovations, Inc.Availability: Now

The 32-bit PCI bus master megafunction is implemented in VHDL- or Verilog HDL-based design files that are optimized for the Altera FLEX 10K device family. This megafunction is implemented at the 0-wait, 33-MHz, PCI bus maximum speed.

The following features are provided with the 32-bit PCI bus master megafunction:


(132 MByte/second)■ Fully documented source code and user manual■ Customization services ■ Evaluation card/board-level schematics

Design File Format




VHDL v

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed 574 4 33 MHz

Area


Bus Interfaces

Bus

2

Interfaces

32-Bit PCI Bus TargetVendor: Logic Innovations, Inc.Availability: Now

The 32-bit PCI bus target megafunction is implemented in VHDL- or Verilog HDL-based design files that are optimized for the Altera FLEX 10K device family. This megafunction is implemented at the 0-wait, 33-MHz, PCI bus maximum speed.

The following features are provided with the 32-bit PCI bus target megafunction:


(132 MByte/second)■ Fully documented source code and user manual■ Customization services ■ Evaluation card/board level schematics

Design File Format




VHDL v

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed 365 33 MHz

Area


Bus Interfaces

EP100 PowerPC Bus SlaveVendor: Eureka TechnologyAvailability: Now

The EP100 PowerPC bus slave megafunction provides a slave memory controller and supports standard asynchronous SRAM devices. The EP100 megafunction is designed for the PowerPC host bus and works with any 60x-compliant bus architecture. It allows a memory subsystem built with standard SRAM to be connected to the PowerPC host bus. To achieve the highest possible bandwidth, the EP100 megafunction also emulates data bursting capability.

To improve system performance, the EP100 megafunction supports advanced features of the PowerPC bus, such as address pipelining, address retry, and separate arbitration for the address and data buses. The EP100 function also supports both single beat and burst data transfer, and allows address pipelining with two outstanding memory accesses. The EP100 megafunction interfaces with external memory devices. To provide the highest possible bandwidth at a given frequency, the EP100 megafunction factors in delays on and off the device.

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed 99 24 MHz 138 48 MHz 145 23 MHz

Area 122 30 MHz 124 19 MHz


Bus Interfaces

Bus

2

Interfaces

EP201 PowerPC Bus MasterVendor: Eureka TechnologyAvailability: Now

The EP201 PowerPC bus master megafunction is an external master that resides directly on the PowerPC host bus. The EP201 megafunction is designed for the PowerPC host bus and works with any 60x-compliant bus architecture. A simple and efficient back bus provides an interface to the internal logic that initiates bus access. At the same time, the EP201 megafunction automatically handles all the PowerPC bus protocols.

To improve system performance, the EP201 megafunction supports advanced features of the PowerPC bus, such as address pipelining, address retry, and separate arbitration for the address bus and data bus. The EP201 function also supports both single beat and burst data transfers, and allows address pipelining with two outstanding memory accesses.

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed 33 40 MHz 53 50 MHz 56 40 MHz

Area 43 35 MHz 48 28 MHz


Bus Interfaces

EP300 PowerPC ArbiterVendor: Eureka TechnologyAvailability: Now

The EP300 PowerPC arbiter megafunction arbitrates the PowerPC address and data buses to allow multiple bus masters or processors to co-exist on the host bus. The EP300 megafunction is designed for the PowerPC host bus and works with any 60x-compliant bus architecture. The EP300 can be used as a stand-alone function or it can be incorporated on the host bus with the bus master or slaves. Both fixed and round-robin priority schemes can be implemented with the arbiter.

To improve system performance, the EP300 megafunction supports advanced features of the PowerPC bus, such as address pipelining, address retry, bus parking, and separate arbitration for the address and data buses. This megafunction allows address pipelining with two outstanding memory accesses.

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed 38 40 MHz 65 62 MHz 62 32 MHz

Area 55 42 MHz 57 26 MHz


Bus Interfaces

Bus

2

Interfaces

MPCMCIA MegaMacro Vendor: 3Soft CorporationAvailability: Q3 1996

The MPCMCIA MegaMacro megafunction implements the logic required to interface a PCMCIA card to a PCMCIA 2.0 host adapter. This function contains seven configuration registers that allow


support of an 8- or 16-bit common memory interface and an 8- or 16-bit I/O interface. Base addresses and window size setups can be programmed and stored in up to 128 bytes of CIS memory, which can be uploaded from an EEPROM, ROM, or FLASH memory device.

The MPCMCIA MegaMacro megafunction is often used with either the M16C450 or M16550A universal asynchronous receiver/transmitter (UART) as the front-end to a PCMCIA card modem. However, the software interface is flexible and can support different peripheral and memory device formats.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area


Notes:

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Microperipherals

May 1996

8237 DMA Controller .................................................................................................................................... 16DMA Controller ............................................................................................................................................. 17


Microperipherals

8237 DMA ControllerVendor: CAST, Inc.Availability: July 1996

The 8237 direct-memory access (DMA) controller megafunction improves system performance by allowing information to be transferred between external devices and the system memory.

Preliminary Information The 8237 megafunction implements four DMA channels, each of

which can be individually programmed to autoinitialize to its original condition following an end of process event. Additional DMA channels can be implemented in a design by cascading other 8237 megafunctions.

Design File Format




VHDL v v

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area


Microperipherals

Bus

2

Interfaces

DMA ControllerVendor: CAST, Inc.Availability: June 1996

The DMA controller megafunction allows information to be transferred between external devices and the system memory. This megafunction complements the performance and architectural


capabilities of the M68000 microprocessor family by quickly and efficiently moving blocks of data.

This megafunction implements all functions, including the four independent DMA channels, with programmable priority.

Design File Format




VHDL v v

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area


Notes:

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Processors & Controllers

May 1996

V6502 Microprocessor ................................................................................................................................... 20VZ80 Microprocessor .................................................................................................................................... 212910A Microprogram Controller ................................................................................................................. 22M8051 MegaMacro Microcontroller............................................................................................................ 238051 Microcontroller...................................................................................................................................... 24EXcore-S080 Package..................................................................................................................................... 25



V6502 MicroprocessorVendor: VAutomation Inc.Availability: Now

The V6502 megafunction is a high-performance, 8-bit microprocessor. This megafunction is functionally based on the Rockwell R65C02. Therefore, this megafunction is code-compatible with the R65C02.

The V6502 megafunction has been completely redesigned using the latest high-speed design techniques to produce a high-performance microprocessor with a minimal gate count. This megafunction is easily integrated with application-specific logic, FLEX 10K memory, and other megafunctions from VAutomation. The V6502 megafunction provides the following features:

■ Code-compatible with the Rockwell R65C02 ■ 70 instructions, 210 opcodes, 15 addressing modes■ 8-bit ALU with binary and decimal arithmetic■ 64-Kbyte addressing capability■ Fully synchronous and static design■ Bit manipulation instructions■ Assemblers and C compilers available from third-party

developers

Design File Format


Note:(1) Contact VAutomation for this compilation statistic.



VHDL v v

Verilog HDL v v

AHDL

Post-synthesis AHDL

v v



Speed Note (1) Note (1) 1703 8.4 MHz

Area 891 7.4 MHz



Bus

2

Interfaces

VZ80 MicroprocessorVendor: VAutomation Inc.Availability: Now

The VZ80 megafunction is a powerful, medium-gate-count microprocessor that includes block transfers, bit test, set, and reset instructions. The VZ80 megafunction is functionally based on the Zilog Z80. Therefore, the VZ80 megafunction is code-compatible with the Zilog Z80.

Fast context switch capability is possible with an entire auxiliary register set. The megafunction is easily integrated with application-specific logic, memory functions in FLEX 10K embedded array blocks (EABs), and other functions from VAutomation. The VZ80 megafunction provides the following features:

■ Code-compatible with the Zilog Z80■ 158 instructions, 10 addressing modes■ 8-bit ALU with binary and decimal arithmetic■ 64-Kbyte addressing capability■ Fully synchronous and static design■ Powerful block transfer and search instructions■ Bit test, set, and reset instructions■ Alternate register set■ Assemblers and C compilers available from third-party

developers

Design File Format


Note:(1) Contact VAutomation for this compilation statistic.



VHDL v v

Verilog HDL v v

AHDL

Post-synthesis AHDL

v v



Speed Note (1) Note (1) 2170 6.0 MHz

Area 2091 5.5 MHz



2910A Microprogram ControllerVendor: CAST, Inc.Availability: June 1996

The 2910A microprogram controller megafunction is an address sequencer that controls the execution sequence of microinstructions stored in microprogram memory.

Preliminary Information The 2910A megafunction provides conditional branching to

microinstructions within its 4096-microword range. A five-deep LIFO stack provides microsubroutine linkage and looping capability.

Design File Format




VHDL v v v

Verilog HDL

AHDL

Post-synthesis AHDL

v v v



Speed

Area



Bus

2

Interfaces

M8051 MegaMacro MicrocontrollerVendor: 3Soft CorporationAvailability: Q4 1996

The M8051 MegaMacro megafunction is an 8-bit microcontroller with one serial port and two 16-bit timer/counter channels. The M8051 megafunction supports up to 256 bytes of data memory and


up to 64 Kbytes of program memory in either RAM or ROM. The M8051 megafunction has idle and power-down modes to reducepower consumption.

The M8051 MegaMacro megafunction is code- and timing-compatible with the industry-standard 8051 microcontroller. Therefore, existing application code can run unchanged and new code can be developed with third-party tools. To use this megafunction, application code must be stored in external RAM or ROM. If a RAM is used for program memory, application code can be loaded with a memory download mode.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v



Speed

Area



8051 MicrocontrollerVendor: CAST, Inc.Availability: July 1996

The 8051 microcontroller megafunction implements the following features:


■ 8051 instruction set■ 128 × 8 RAM■ 32 I/O lines■ Two 16-bit counter/timers■ A five-source, two priority level nested interrupt structure■ A serial I/O port for multi-processor communications, I/O

expansion, or a full duplex UART■ Chip clock circuits

Design File Format




VHDL v

Verilog HDL

AHDL

Post-synthesis AHDL

v



Speed

Area



Bus

2

Interfaces

EXcore-S080 PackageVendor: Excellent Design Inc.Availability: Q3 1996

The EXcore-S080 package includes a Z80 function-compatible 8-bit CPU megafunction and standard peripherals. The standard peripherals include 82xx-compatible megafunctions, i.e., 8251


USART, 8254 programmable time and counter, 8255 programmable parallel interface, 8259 programmable interrupt controller, and 8237 DMA controller functions.

The EXcore-S080 package includes a fully synchronous CPU megafunction written in Verilog HDL. This megafunction is a RISC-based design that can execute the maximum number of instructions in one processor cycle. The 10-MHz EXcore-S080 package has a throughput equal to a 40-MHz standard Z80 CPU.

Design File Format




VHDL

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed

Area


Notes:

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Communications

May 1996

Speedbridge .....................................................................................................................................................28M16C450 UART...............................................................................................................................................29M16550A UART ..............................................................................................................................................30RF-G704 Synchronous Framer/Deframer...................................................................................................31RF-G721 ADPCM Transcoder .......................................................................................................................32RF-HDLC Controller ......................................................................................................................................33RF-BRIM Basic Rate Interface........................................................................................................................34GF-RSC Reed Solomon CODEC ...................................................................................................................35GF-LILAC Linked List Access Controller ...................................................................................................36ATM Cell Delineation.....................................................................................................................................37ATM Cell Translation & Routing .................................................................................................................38ATM Cell HEC Generator/Check ................................................................................................................39ATM Switch .....................................................................................................................................................40UTOPIA Interface ...........................................................................................................................................41

Communications

SpeedbridgeVendor: SIS Microelectronics, Inc.Availability: Now

The Speedbridge megafunction is an asynchronous FIFO buffer that can transfer data across an asynchronous interface. SIS Microelectronics will customize the megafunction’s width and depth to meet user requirements.

The read and write ports for this megafunction contain synchronous enables for accessing their respective functions. Both read and write ports have independent clocks. Each port contains an enable that allows the clocks to run without read or write operations.

The FIFO full flag is synchronous to the write clock; the FIFO buffer empty flag is synchronous to the read clock. Although no overflow or underflow error flag is present, these conditions can be identified external to the megafunction through the FIFO full and empty flags. If overflow occurs (a write operation when the FIFO is full), only the new data is lost. If underflow occurs (a read operation when the FIFO is empty), the data presented for the underflow will be undefined. Once new data is written to the megafunction, the data appears on the output of the megafunction and may be captured after the synchronization period. Compilation statistics are for the Speedbridge megafunction configured with 16 bytes of depth.

Design File Format


Note:(1) Contact SIS Microelectronics for this compilation statistic.



VHDL

Verilog HDL v v

AHDL

Post-synthesis AHDL

v v



Speed 478 16 MHz Note (1) Note (1) Note (1)

Area 439 13 MHz


Communications

Bus

2

Interfaces

M16C450 UARTVendor: 3Soft CorporationAvailability: Q2 1996

The M16C450 UART MegaMacro megafunction provides an interface between a microprocessor and a serial communication channel. This megafunction contains a programmable baud rate


generator, double-buffered receiver and transmitter asynchronous serial communication channels with programmable interruptcontrol, and a modem signal interface.

The M16C450 megafunction is functionally based on the industry-standard 16C450 UART device. Therefore, the megafunction is code- compatible with the 16C450 device. External-level conversion buffers are required to use the megafunction as an RS-232 port.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area


Communications

M16550A UARTVendor: 3Soft CorporationAvailability: Q3 1996

The M16550A UART MegaMacro megafunction provides an interface between a microprocessor and a serial communication channel. This megafunction contains a programmable baud rate


generator, receiver and transmitter asynchronous serial communication channels with separate 16 byte FIFO buffers, FIFOthreshold control logic, programmable interrupt control, and a modem signal interface.

The M16550A megafunction is functionally based on the industry-standard 16550A UART device. Therefore, the megafunction is code- compatible with the 16550A device. External-level conversion buffers are required to use the megafunction as an RS-232 port.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v



Speed

Area


Communications

Bus

2

Interfaces

RF-G704 Synchronous Framer/DeframerVendor: Object Oriented HardwareAvailability: Q2 1996

The RF-G704 synchronous framer/deframer reference Foundry Independent Standard Product (FISP) is a fully synthesizable VHDL function implementing CCITT recommendation G.704 (G.732,


G.733) for 1544 and 2048 Kbits/second links. The megafunction can be configured to support one or more of the following structures: E1, T1-D4, and T1-ESF. The E1 structure supports CAS signaling extraction and insertion, CRC4 checking and generation, and E-bit checking and generation. Access is also provided to the Sa-bits. The T1 structure supports both T1-D4 and T1-ESF frame structures to allow recovery of robbed bit signaling, as well as CRC6 checking and generation. Both the E1 and T1 structures support remote alarms, and generate both clock loss and AIS alarms. The E1 and T1 structures also support frame alignment, CRC and E-bit error monitoring and have integral BER monitors.

Primary I/O data interfaces to the outside world via elastic stores, allowing easy system integration. The FISP is written in RTL VHDL and can be supplied in a variety of target netlist files. Associated functions include the GF-REO Timeslot Reorderer Generic FISP, which allows timeslots to be reordered (including CAS signaling) to and from the elastic stores before insertion or after extraction from the bearer. Also available is the RF-X50 rate conversion reference FISP, which allows 48 Kbits/second and 56 Kbits/second channels to be carried in T1/E1 frame structures.

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed

Area


Communications

RF-G721 ADPCM Transcoder Vendor: Object Oriented HardwareAvailability: Q2 1996

The ADPCM transcoder reference FISP is a fully synthesizable VHDL function compliant with CCITT recommendation G.721. The megafunction has an optimized version of the proprietary DSP


engine. The megafunction can process a single full-duplex 64 Kbits/second channel by performing an encode and a decode every 125 µs. User-accessible register bits allow configuration for u-law or A-law companding, and 8-bit PCM or 14-bit linear interfacing. Other register bits can be set to make the transcoder either pass data transparently or just perform companding (G.711 compliant). The megafunction is fully synchronous with an interrupt-driven transcoding process, which allows the data clock to be asynchronous with respect to the system clock. The FISP has separate serial interfaces for the PCM and ADPCM data.

The FISP is written in register transfer level (RTL) VHDL and can be supplied in a variety of target netlist files. Dual channel operation (still full duplex) can be achieved by simply doubling the data RAM size and clock rate. Other features such as tone generation and detection can be added to the megafunction using the spare processing power of the DSP engine. A similar megafunction, RF-G726, is also available that is fully compliant with CCITT recommendation G.726. The RF-G726 megafunction compresses or decompresses 64 Kbits/second to and from 40, 32, 24, and 16 Kbits/second.

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed

Area


Communications

Bus

2

Interfaces

RF-HDLC ControllerVendor: Object Oriented HardwareAvailability: Q2 1996

The RF-HDLC controller reference FISP implements a single-channel HDLC protocol. The megafunction contains a full duplex transceiver with independent receive and transmit sections for bit-


level HDLC protocol operations. The RF-HDLC function transmits and receives data in frames consisting of a frame start flag; address, control data, and FCS fields; and an end flag. The FCS is calculated using a standard CCITT-CRC polynomial. To prevent flags from being imitated by data, all transmit data is subject to zero insertion; inserted zeros are automatically removed on reception. The FCS is automatically calculated on transmit and checked on receive. The FISP can be used to implement the bit-level tasks of many common protocols such as Q.921 (LAPD) for ISDN, Q.922 for frame relay applications, X.25 (LAPB) for WAN applications, SS #7 for exchange signaling, and RFC 1548 (PPP) for router and internet applications.

The FISP is written in RTL VHDL and can be supplied in a variety of target netlist files. Available options include an extended 32-bit FCS with enhanced error detection, address matching logic, a microprocessor register block, and minimum frame checking logic. Receive and transmit data can be transferred to and from memory by adding standard FIFO buffers, a 2-channel DMA controller (GF-DMA-2), or a Linked List Access Controller (GF-LILAC).

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed

Area


Communications

RF-BRIM Basic Rate InterfaceVendor: Object Oriented HardwareAvailability: Q2 1996

The RF-BRIM basic rate interface megafunction is a fully synthesizable VHDL function implementing CCITT recommendation I.430 (digital section only). This megafunction acts


as a complete digital Layer 1 ISDN solution and can be connected to an ISDN S/T interface using an inexpensive line driver module. The RF-BRIM megafunction provides a complete digital interface to the S/T reference points, which supports 192 Kbits/second (2B+D+overhead) full duplex data transmission on a four-wire balanced transmission channel. This megafunction also performs related timing and synchronization functions, activation and deactivation procedures, D-channel resource allocation and prioritization, power down handling, and comprehensive loopback testing modes. A simple PCM interface is provided for easy integration with other system functions.

The FISP is written in RTL VHDL and can be supplied in a variety of target netlist files. Associated functions include the RF-HDLC/DMA and RF-HDLC/FIFO HDLC controller FISPs, which allow processing of Layer 2 LAPD frames, and the GF-LILAC Linked List Access Controller FISP, which allows automatic targeted payload distribution within a system.

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed

Area


Communications

Bus

2

Interfaces

GF-RSC Reed Solomon CODECVendor: Object Oriented HardwareAvailability: Q2 1996

The GF-RSC Reed Solomon CODEC generic FISP megafunction is a fully synthesizable VHDL function implementing a Reed-Solomon forward error-correcting coder/decoder. This megafunction


supports the correction of errors and erasures (i.e., errors at known positions). The encoding and decoding sections are independentand can be implemented separately. The error-correcting core can be optimized for the number of errors and erasures to be corrected and for the primitive and generator polynomials.

By choosing the appropriate values for the primitive and generator polynomials, the GF-RSC megafunction can be made compatible with Intelsat IESS-308 Revision 6B and RTCA DO-217 Appendix F, Revision D. The GR-RSC megafunction supports both burst and continuous operation modes. Various architectures and clocking schemes can be chosen at compile time to trade-off between design size and speed. An optional statistics gathering block can be added to the decoder megafunction to provide information about the error rates in the channel.

The FISP is written in RTL VHDL and can be supplied in a variety of target netlist files. Associated functions include the GF-VIT Viterbi CODEC, the GF-INT interleaver, and the GF-DINT deinterleaver.

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed

Area


Communications

GF-LILAC Linked List Access ControllerVendor: Object Oriented HardwareAvailability: Q2 1996

The GF-LILAC Linked List Access Controller reference FISP provides a generic DMA-based interface to various packet-oriented communications controllers. Mixed protocols can be supported,


including ARCnet, ETHERNET, and HDLC. The megafunction interfaces to a flexible queue of buffers in memory, which may be linear or circular, and can be linked statically or dynamically. Incoming data frames can be sent to one of four receive queues, depending on queue information passed from the protocol engine. On transmit, data and header/footer information can be contained in separate memory areas, allowing large and contiguous data buffers to be dynamically split over several frames. Receive data can be split to extract fixed length headers from payload. Messages can span multiple data buffers in receive queues.

The FISP is written in RTL VHDL and can be supplied in a variety of target netlist files. Associated functions include the HDLC controller core (RF-HDLC) and ARCnet controller core (RF-ARCNET). Other protocol engines are in development and stand-alone protocol engines can be accommodated through an external interface.

Design File Format




VHDL v v v

Verilog HDL v v v

AHDL

Post-synthesis AHDL

v v v



Speed

Area


Communications

Bus

2

Interfaces

ATM Cell DelineationVendor: Logic Innovations, Inc.Availability: June 1996

The Asynchronous Transfer Mode (ATM) cell delineation megafunction accepts bit- and byte-data stream, unformatted data. This megafunction performs cell delineation through a header check


(HEC check). The data is output in byte-wide format with a start of cell signal. The output can connect to the Logic Innovation UTOPIA interface megafunction. The ATM megafunction performs a HEC check, identifies a start of cell signal, and begins passing ATM cells. The ATM cell delineation megafunction includes the following features:

■ Silicon-proven core■ Full-speed, 50-MHz operation■ Fully documented source code and user manual■ Customization services■ Evaluation card/board level schematics

Design File Format




VHDL v

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed 52 50 MHz

Area


Communications

ATM Cell Translation & RoutingVendor: Logic Innovations, Inc.Availability: June 1996

The ATM cell translation and routing megafunction takes in a cell from the switch, grabs the header information, and performs a VPI and VCI translation look-up. A three-entry search (as opposed to the


standard two-entry search) is performed in an external 64K SRAM containing the translation table. The three-entry approach permits awide variety of VPI/VCI combinations that cannot be translated with a two-entry method. Cell headers are modified to contain the new VPI/VCI data, and then routed into SRAM queues using tag information in the translation table entry. Input ATM cells require the header to be translated using VPI, VCI, and other header information.

The ATM cell translation and routing megafunction contains the following features:

■ Silicon-proven core■ Full-speed, 50-MHz operation■ Three-entry VPI and VCI translation look-up■ External 64K SRAM support■ Fully documented source code and user manual■ Customization services ■ Evaluation card/board level schematics

Design File Format




VHDL v

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed 987 50 MHz

Area


Communications

Bus

2

Interfaces

ATM Cell HEC Generator/CheckVendor: Logic Innovations, Inc.Availability: June 1996

The ATM cell HEC generator/check megafunction calculates the HEC for outgoing cells, and calculates and checks the HEC for incoming cells. The megafunction provides a hardware mechanism


that checks the 5-byte (40 bits) header HEC in parallel at full speed on each clock. The input and output circuits are similar, except theirdata flows are reversed. The HEC generator is required for the cell delineation process.

The ATM cell HEC generator/check megafunction contains the following features:

■ Silicon-proven core■ Full-speed, 50-MHz operation■ Full-speed, 5-byte (40-bit) clock-by-clock compare■ Fully documented source code and user manual■ Customization services ■ Evaluation card/board level schematics

Design File Format




VHDL v

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed 223 50 MHz

Area


Communications

ATM SwitchVendor: Logic Innovations, Inc.Availability: June 1996

The ATM switch megafunction takes incoming ATM cells from the physical layer interface, buffers them in a 3 × 53 byte internal FIFO, and performs HEC checks, cell delineation, cell translation, and


external cell FIFO operations for 123 cells of 53 bytes each. The ATM switch megafunction has integrated the Logic Innovation ATM HECGenerator/Checker, ATM Cell Delineation, ATM Cell (VPI/VCI) Translation, ATM Cell FIFO, and glue functions. This megafunction is optimized for the Altera FLEX 10K device family.

The ATM switch megafunction includes the following features:

■ Silicon-proven core■ Full-speed, 50-MHz operation■ Integral 3 × 53 byte internal FIFO■ Fully documented source code and user manual■ Customization services ■ Evaluation card/board level schematics

Design File Format




VHDL v

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed 1536 2 50 MHz

Area


Communications

Bus

2

Interfaces

UTOPIA InterfaceVendor: Logic Innovations, Inc.Availability: June 1996

The UTOPIA interface megafunction provides both input and output, and 16- and 8-bit data bus implementation. This megafunction also provides the ATM standard bus interface used to


connect ATM building blocks and byte-wide, start of cell signal, and UTOPIA interface functions. This megafunction incorporates a 53-byte FIFO buffer for each direction of data transfer.

The UTOPIA interface megafunction includes the following features:

■ Silicon-proven core■ Full-speed, 50-MHz operation■ Dual 3 × 53 byte internal FIFO buffers■ Fully documented source code and user manual■ Customization services available■ Evaluation card/board level schematics available

Design File Format




VHDL v

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed 35 2 50 MHz

Area


Notes:

®

Digital SignalProcessing

May 1996

Programmable FIR Filter................................................................................................................................441-D Symmetric FIR Filter ...............................................................................................................................451-D Median Filter ............................................................................................................................................462-D FIR Filter ...................................................................................................................................................47IIR Biquad Filter ..............................................................................................................................................48Laplacian Sharpening Filter (3 × 3)...............................................................................................................49Laplacian Edge Detector (3 × 3) ....................................................................................................................50JPEG Decoder ..................................................................................................................................................51JPEG Encoder...................................................................................................................................................52Fast Fourier Transform...................................................................................................................................53


Digital Signal Processing

Programmable FIR FilterVendor: Integrated Silicon Systems Ltd.Availability: Now

The programmable finite impulse response (FIR) filter megafunction uses parallel unsigned binary data and provides full output precision. This megafunction is targeted for speech and audio processing applications.

Integrated Silicon Systems can customize the data and coefficient wordlengths, and the number of filter taps to meet user requirements. Filter coefficients are either symmetric or antisymmetric, and are reprogrammable with a bit-parallel unsigned binary data format.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v



Speed 563 7 171 kHz

Area 446 6 162 kHz



Bus

2

Interfaces

1-D Symmetric FIR FilterVendor: Integrated Silicon Systems Ltd.Availability: Contact ISS

The 1-D symmetric FIR filter megafunction has symmetric coefficients that can be reprogrammed during operation. This FIR megafunction is ideal for speech and audio processing


Integrated Silicon Systems can customize the number of filter taps and the data and coefficient wordlengths to meet user requirements. The data and coefficient words are in two’s complement bit parallel format.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area



1-D Median FilterVendor: Integrated Silicon Systems Ltd.Availability: Contact ISS

The 1-D median filter megafunction performs data smoothing operations in speech and audio processing applications. This megafunction implements a standard median filter function, in which the output of a (2n + 1) tap median filter is the (n + 1)th largest


magnitude (the median value).

Integrated Silicon Systems can customize the number of filter taps and the data wordlengths to meet user requirements. The data words are in two’s complement bit parallel format.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area



Bus

2

Interfaces

2-D FIR FilterVendor: Integrated Silicon Systems Ltd.Availability: Contact ISS

The 2-D FIR filter megafunction implements an m × n FIR filter function targeted for image and video processing applications. The 2-D FIR filter megafunction has fixed coeffiecients, enabling a more efficient implementation. The line delays in the design must be off


the device, which makes the n data lines available in parallel.

Integrated Silicon Systems can customize the number of filter taps (both horizontally and vertically) and the data and coefficient wordlengths to meet user requirements.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area



IIR Biquad FilterVendor: Integrated Silicon Systems Ltd.Availability: Q3 1996

The infinite impulse response (IIR) Biquad filter megafunction is a second-order filter that can be used to build any IIR filter. Integrated Silicon Systems can customize the data and coefficient wordlengths to meet user requirements.


Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area



Bus

2

Interfaces

Laplacian Sharpening Filter (3 × 3)Vendor: Integrated Silicon Systems Ltd.Availability: Contact ISS

The Laplacian sharpening filter megafunction is a two-dimensional filter targeted towards real-time front-end image processing applications. The data words are in bit-parallel unsigned binary format to meet the requirements of most video analog-to-digital


converters (ADCs). To use the Laplacian sharpening filter megafunction, the design’s three data lines must be implemented in parallel, and the required line delays must be implemented off the device.

Integrated Silicon Systems can customize the data wordlengths to meet user requirements.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area



Laplacian Edge Detector (3 × 3)Vendor: Integrated Silicon Systems Ltd.Availability: Q3 1996

The Laplacian edge detector megafunction is a two-dimensional filter targeted towards real-time front-end image processing applications. The data words are in bit-parallel unsigned binary format to suit the output of most video ADCs. To use the Laplacian edge detector


megafunction, the design’s three data lines must be implemented in parallel, and the required line delays must be implemented off the device.

Integrated Silicon Systems can customize the data wordlengths to meet user requirements.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v v



Speed

Area



Bus

2

Interfaces

JPEG DecoderVendor: Synova IncorporatedAvailability: Q4 1996

The JPEG decoder megafunction provides a high-speed hardware implementation of the JPEG baseline image decompression algorithm. This megafunction is targeted for real-time image


compression and decompression applications.

The JPEG decoder megafunction contains the following features:

■ High-speed JPEG decoder■ On-chip buffer RAM■ Programmable tables■ Programmable inverse DCT coefficients■ 12-bit input data width

Design File Format




VHDL

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed

Area



JPEG EncoderVendor: Synova IncorporatedAvailability: Q4 1996

The JPEG encoder provides a high-speed hardware implementation of the JPEG baseline image compression algorithm. This megafunction is targeted for real-time image compression and


decompression applications.

The JPEG encoder megafunction contains the following features:

■ High-speed JPEG encoder■ On-chip buffer RAM■ Programmable tables■ Programmable DCT coefficients■ 8-bit input data width

Design File Format




VHDL

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed

Area



Bus

2

Interfaces

Fast Fourier TransformVendor: Synova IncorporatedAvailability: Q3 1996

The fast Fourier transform (FFT) megafunction is a high-speed radix-2 implementation of the FFT. This megafunction includes the radix-2 butterfly, address generator, and controller. This


megafunction provides a variety of configuration options, including word width, transform length, and data format.

The fast Fourier transform megafunction contains the following features:

■ Radix-2 FFT■ On-chip buffer RAM■ Off-chip buffer for larger transform lengths■ Configurable data width■ Configurable data format (fixed and floating point)■ Configurable data type (complex or real)■ Configurable maximum transform length■ Programmable transform length

Design File Format




VHDL

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed

Area


Notes:

®

MiscellaneousFunctions

May 1996

Micro VGA Controller................................................................................................................................... 56XM-01............................................................................................................................................................... 57XM-Blocks ....................................................................................................................................................... 58IEEE-754 Floating Point ................................................................................................................................ 59


Miscellaneous Functions

Micro VGA ControllerVendor: Silicon Engineering, Inc.Availability: Q3 1996

The Micro VGA controller megafunction is a VGA-compatible video graphics controller targeted for embedded ASIC applications. This megafunction provides high-integration, high-resolution graphics


output for IBM PS/2-, PC/AT-, and PC/XT-compatible systems. Thismegafunction also delivers high-resolution graphics of 800 × 600 elements with 16 colors.

The Micro VGA controller megafunction is fully compatible with IBM VGA in all modes, Hercules graphics, EGA, CGA, MDA, and IBM BIOS. A flicker-free enhancement is provided for all modes. The Micro VGA megafunction supports an external digital-to-analog look-up table (LUT).

Design File Format


Note:(1) Contact Silicon Engineering for this compilation statistic.



VHDL

Verilog HDL v

AHDL

Post-synthesis AHDL

v




Speed Note (1) Note (1) 28.8 MHz

Area



Bus

2

Interfaces

XM-01Vendor: Digital Design & DevelopmentAvailability: Now

The XM-01 megafunction is a minimal implementation of a double-buffered send and receive XMidi UART. In addition to the BCT basic transmission, this megafunction performs bit mapping for channel encoding and decoding, and assures line coherency, line control and line sensing on the OUT and THRU outputs. Dual clock dividers allow independent baud rates up to 250 Kbaud for the receiver and transmitter. This megafunction supports both polling and interrupt modes.

The XM-01 megafunction is compact and designed to fit in an Altera EPM7128 device. An additional standard UART must be added for full bidirectional capability. The XM-01 megafunction cannot handle extended operand coding. Therefore, the host MCU must perform the extended operand coding.

Design File Format




VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v


Logic Cells fTYP Logic Cells fTYP Logic Cells EABs fTYP

Speed 125 8 MHz

Area



XM-BlocksVendor: Digital Design & DevelopmentAvailability: End 1996

The XM-Blocks package enables designers to tailor an XMidi communication system to meet different design requirements. This package includes a BCT transmitter and receiver (both with XM Channel encoding/decoding), cascadable clock dividers, a 17-bit-


wide FIFO slice, and a fully static XM operand encoder/decoder.

This package can be expanded to any number of receivers or transmitters, and to different FIFO depths. Complementary functions—such as a channel filter—can be added to the XM-Blocks package.

Design File Format


Note:(1) Contact Digital Design & Development for this compilation statistic.



VHDL

Verilog HDL

AHDL

Post-synthesis AHDL

v


Logic Cells fTYP Logic Cells fTYP Logic Cells EABs fTYP

Speed Note (1) Note (1) 32 MHz

Area



Bus

2

Interfaces

IEEE-754 Floating PointVendor: Synova IncorporatedAvailability: Q4 1996

The floating-point megafunction implements the IEEE 754-1985 standard for floating-point arithmetic. This megafunction supports both single and double precision arithmetic and provides a variety


of configuration options that can trade-off between performance and gate count.

The IEEE-754 floating point megafunction includes the following features:

■ Configurable data path■ Double and single precision■ Configurable performance (pipeline levels and multiplier

speed)■ IEEE 754-1985 compliant■ Flush-to-zero or gradual underflow■ Add, subtract, multiply, and divide functions■ Support for quiet and signaling NANs

Design File Format


Note:(1) Contact Synova for this compilation statistic.



VHDL

Verilog HDL v

AHDL

Post-synthesis AHDL

v



Speed Note (1) Note (1) 32 MHz

Area


Notes:

AMPP Partner Profiles

May 1996

®

3Soft Corporation............................................................................................................................................62Advancel Logic Corporation .........................................................................................................................64CAST, Inc..........................................................................................................................................................65Digital Design & Development.....................................................................................................................67Eureka Technology .........................................................................................................................................68Excellent Design Inc........................................................................................................................................70Infinite Solutions, Inc......................................................................................................................................72Integrated Silicon Systems Ltd......................................................................................................................74Logic Innovations, Inc. ...................................................................................................................................76Object Oriented Hardware ............................................................................................................................77Sierra Research and Technology, Inc. ..........................................................................................................79Silicon Engineering, Inc..................................................................................................................................80SIS Microelectronics, Inc. ...............................................................................................................................82Synova Incorporated ......................................................................................................................................84VAutomation Inc.............................................................................................................................................85Virtual Chips, Inc. ...........................................................................................................................................87



3Soft Corporation1001 Ridder Park DriveSan Jose, CA 95131-2314Tel. (408) 451-5700Fax (408) 451-5690E-mail [email protected] http://www.3Soft.com

37 Parkfield, Chorley Woods,Herts, WD3 5AZ EnglandTel. 44 1923-285264Fax 44 1923-285212E-mail [email protected] http://www.3Soft.com

Overview

3Soft develops and markets a library—called MacroWare—of architecture-independent, complex megafunctions. The megafunctions are ready-made and tested for integrated circuit (IC) and systems designers worldwide. Designers can use the MacroWare library with multiple EDA tools and process technologies, which speeds the design process.

The MacroWare library is a suite of over 30 reusable megafunctions called MegaMacros. The MegaMacros use an average of 7,000 gates each. Most popular LSI and VLSI functions are implemented and tested as MegaMacros. The 3Soft library differs from ASIC vendors’ libraries because each MegaMacro is a generalized logic representation of a complex function designed for multiple process technologies. Individual library functions are available in RTL, VHDL, Verilog HDL, and architecture-independent netlist files, allowing a high degree of portability across different process technologies.

Available Products

3Soft provides the megafunctions summarized in the following table. Not all products are available for Altera devices. Contact 3Soft for availability.



Notes: (1) All gate counts are approximate and will vary from process to process.(2) Gate count excludes RAM and ROM.

MegaMacro Description Gates (1)

M320C50 High-performance digital signal processor 40,000 (2)

M82C206 Integrated peripherals controller 17,779 (2)

M320C25 High-performance digital signal processor 16,550 (2)

M82365SL PCMCIA card interface controller 17,000

M85C30 SCC 2-channel enhanced serial communications controller with FIFO functions 16,429

M79C90 Ethernet LAN controller 15,000

M82530 SCC 2-channel advanced serial communications controller 12,112

MFDC High-performance PC-compatible floppy disk controller system (82077SL) 10,435

M53CF94 Enhanced SCSI-II controller 9,663

M765A Extended features floppy disk controller megafunction for FM and MFM formats 9,226

M8052 High-performance, industry-compatible 8-bit microcontroller, 3 timers, serial I/O 8,735 (2)

M8051 High-performance, industry-compatible 8-bit microcontroller, 2 timers, serial I/O 7,927 (2)

M16550A UART with FIFO function 6,523

M1284 IEEE 1284 parallel port 4,000

M8237A General-purpose programmable four-channel DMA controller 3,684

M8254 Extended-feature, 3-channel programmable interval timer (PIT) 3,004

M8042 8-bit peripheral interface microcontroller with timer (slave microcontroller) 3,359 (2)

M8048 Compact, embedded industry-compatible 8-bit microcontroller with timer 3,311 (2)

M8253 Extended-feature, 3-channel programmable interval timer (PIT) 2,811

M6845 General-purpose CRT controller 2,580

MPCMCIA PCMCIA PC card interface 2,500

M8251A USART 2,118

M146818 Ultra-low-power realtime clock with up to 114 bytes of RAM 1,985 (2)

M16C450 PC-compatible UART 1,995

M8250B PC-compatible UART 1,974

M8259A 8-channel cascadable programmable interrupt controller (PIC) 1,573

M8490 SCSI for 5380 compatible asynchronous SCSI interfacing 1,443

MI2C I2C bus interface 1,402

MDDS24 Enhanced high-margin floppy and tape data separator for data rates to 2 Mbit per second

1,249

M91C360 High-margin floppy and tape data separator for data rates to 1.25 Mbit per second 1,235

M91C36 High-margin floppy disk data separator for data rates to 1.25 Mbit per second 1,022

M8255 General purpose programmable peripheral interface 1,035

M8868A Compact UART 760

M6402 Compact UART 750



Advancel Logic Corporation1735 North First StreetSan Jose, CA 95112Tel. (408) 453-0600Fax (408) 453-0685E-mail [email protected] http://www.advancel.com

Overview

With the increase in design complexity, reduced time-to-market for new products, and the need to reduce system cost through high-level integration, system-on-a-chip has become a reality. As a result, designers require large, ready-made building blocks.

Advancel develops and sells synthesizable building blocks, i.e., megafunctions, for the data communications industry. These blocks can be included in a design before logic synthesis. Based upon technical expertise and design experience, Advancel is focusing on asynchronous transfer mode (ATM) megafunctions.

ATM presents many difficult issues for designers because of evolving communications standards. To simplify this problem, Advancel offers megafunctions created in Verilog HDL and VHDL that can be incorporated into a design at the register transfer level before synthesis. Designers can easily modify the source code to add new functionality.

Designers can use Advancel megafunctions to achieve high-level integration, as well as to reduce device cost and time-to-market.

Available Products

Advancel provides the megafunctions summarized in the following table. Not all products are available for Altera devices. Contact Advancel for availability.

Advancel™Logic Corporation

Megafunction Description

ALC-ATM-101 Sonet ATM UNI processor

ALC-ATM-103 Segmentation and reassembly (SAR) processor

ALC-ATM-104 Clock synthesis and recovery unit

ALC-ATM-106 Quad Sonet UNI processor



CAST, Inc.24 White Birch DrivePomona, NY 10970Tel. (914) 354-4945Fax (914) 354-0325E-mail [email protected] http://www.cast-inc.com

Overview

CAST focuses on maximizing the success of VHDL designs by supplying high-quality, high-value megafunctions for VHDL simulation and synthesis. CAST provides a total modeling solution for VHDL design by delivering and supporting VHDL libraries with thousands of accurate, reliable, affordable functions ready for use by designers worldwide. CAST supplies maintenance and support programs, including a models on request (MOR) service, as well as a variety of VHDL training programs and consulting services.

CAST pre-packaged libraries feature the Standard Component VHDL Library (SCVL) series. Developed for system and device designers, SCVL includes simulation models for 3,000 memory devices and 2,500 standard ECL and TTL devices.

The V-Custom Series library provides affordable VHDL megafunctions of processors, complex functions, and specialized devices. Featuring in-stock models such as the Pentium and Pentium Pro processors from Intel and a variety of network and memory controllers, coprocessors, and timers, the V-Custom Series library grows every month. Check the CAST world-wide web page for information on newly added megafunctions.

If a megafunction is not currently available, CAST can create custom megafunctions on request. The CAST VHDL experts work closely with designers to produce the exact VHDL megafunctions required, from complex processor functions to specialized peripheral devices. CAST delivers the best available combination of up-front economy, long-term value, and personalized support.



Available Products

CAST provides the megafunctions and simulation models summarized in the following table. Not all products are available for Altera devices. Contact CAST for availability.


6809 Microprocessor

DMA Controller Controller

8080 8-bit microprocessor

8085AH Microprocessor

8031/8051 Controller

8031AH/8051AH Controller

8032AH/8052AH Controller

8751H/8751H-8 Controller

8203 64K dynamic RAM controller

8237/8257 Programmable DMA controller family

8253 Programmable interval timer

8254 Programmable interval timer

8255A Programmable peripheral interface

82586 Local area network coprocessor

8259A Programmable interrupt controller

82596 Local area network coprocessor



Digital Design & Development18A Godshuis Street, 1861 Meise, BelgiumTel. 32 2-270-2797Fax 32 2-270-1905E-mail 73261.530@

compuserve.comWWW http://ourworld.compuserve.com/homepages/eric_lukac_kuruc/ddd.htm

Overview

Digital Design & Development produces eXtended MIDI (XMidi) megafunctions, an improved version of the MIDI communication system. XMidi utilizes both hardware and software to overcome the limitations of traditional MIDI systems, while remaining completely compatible with existing MIDI systems.

XMidi upgrades conventional MIDI in two ways:

■ Expanding traditional MIDI functions and capabilities■ Adding numerous new functions previously unavailable

Digital Design & Development provides the expertise to assist designers in understanding XMidi and integrating the system’s functions in custom products.

Available Products

Digital Design & Development provides the megafunctions and supporting products summarized in the following table. Not all products are available for Altera devices. Contact Digital Design & Development for availability.


XM-DEV XMidi development board

XM-PC ISA-PC to XM-DEV interface board and software

XM3V710 XMidi programmed EPM7128

XM-01 Basic XMidi function

XM-Blocks Modular function system for XMidi implementation



Eureka Technology4962 El Camino RealSuite 108Los Altos, CA 94022Tel. (415) 960-3800Fax (415) 960-3805E-mail [email protected]

As design cycles become shorter, time-to-market is critical for a successful development project. Every product must meet aggressive design goals with limited resources and tight schedules. Eureka Technology provides sophisticated design capabilities to assist logic designers. By offering reusable megafunctions, custom design services and simulation models for PLD and ASIC designs, Eureka Technology can help designers to reduce costs and shorten design times to meet time-to-market demands.

Eureka Technology supplies products for the computer, communications, and semiconductor industries, and offers megafunctions for the following areas:

■ PowerPC bus controller functions■ PCI bus controller functions

These functions are designed to handle complex PowerPC and PCI bus systems, respectively, and to provide a simple, efficient interface to the user’s internal design. Designers can use these megafunctions to reduce design costs and quickly master the PowerPC and PCI bus systems. All models are available as both Verilog HDL and VHDL source files as well as post-synthesis AHDL files.

The designer can customize Eureka Technology megafunctions for specific system requirements. In addition, Eureka Technology can provide user-specific features on request. By offering customized design services, Eureka Technology can quickly expand the user’s design capabilities to meet market demands.

To be successful, complex systems must be evaluated effectively before being committed to silicon. Not only should each individual ASIC be verified through functional simulation, but system level simulation should be an integral part of the design process. Eureka Technology offers simulation models as well as megafunctions to help system designers verify every aspect of their systems before silicon implementation.



Eureka Technology design engineers have a wide variety of design expertise and are knowledgeable in many design areas, including:

■ PLD and ASIC design■ PowerPC bus systems■ PCI bus systems■ PC architecture and chip set■ Cache and memory controllers■ CPU and embedded controller megafunctions■ Specialized memory devices

Eureka Technology provides support for the following IC development phases:

■ Top-down design methodologies■ Behavioral modeling■ Synopsys logic synthesis■ PLD and ASIC implementation■ VHDL and Verilog HDL simulation■ Functional verification



Excellent Design Inc.2-3-19, ShinyokohamaKouhoku-kuYokohama-Shi, Kanagawa, 222 JapanTel. 81 45-474-9410Fax 81 45-474-9413E-mail [email protected]

Overview

Excellent Design Inc. supports semiconductor vendors and ASIC developers with VLSI design and advanced EDA tool development. Excellent Design provides high-performance, high-quality VLSI designs and development environments using the knowledge of ASIC designers, system architecture engineers, and EDA tool engineers. Excellent Design is also a worldwide supplier of state-of-the-art application-specific standard products (ASSPs) and EDA tools for ASIC-based technologies.

Reusable designs are an important goal in design and architecture development, which is the main purpose of process-independent design. To achieve this goal, Excellent Design employs the top-down design methodology commonly used in device system design, as well as researching and developing a cell library that can be mapped to different device processes and architectures.

Excellent Design uses a “bottom-up oriented top-down” method, in which a circuit is synthesized from its behavioral description (top-down) while physical layout for the circuit is mapped on the target process technology (bottom-up) to complete the library. This method is useful for fabless integrated circuit designers.

With the following methodology, Excellent Design can support all phases of custom circuit development.

■ Providing strong relationships with international companies who supply advanced architectures

■ Developing original ASSP devices■ Supplying an advanced design environment and libraries■ Supporting ASIC vendors and users by combining EDA tools,

system, and software technologies

EXCELLENT DESIGN INC.



Available Products

Excellent Design provides the megafunctions summarized below. Not all products are available for Altera devices. Contact Excellent Design for availability.

CPU Megafunctions

■ Z80-compatible CPU■ 8086-compatible CPU■ 68000-compatible CPU

CPU Peripherals

■ 8237-compatible DMA controller■ 8251-compatible serial interface■ 8254-compatible timer and counter■ 8255-compatible parallel interface■ 8259-compatible interrupt controller■ Graphic controller■ High-end graphics engine■ Image processing controller■ Video controller (video encoder and decoder)■ ECC device using Reed Solomon■ Parametric cell generator (RAM, ROM, and multipliers)

Future Products

■ Three-dimensional graphics engine■ Geometry processor■ Rendering engine■ Application-specific processor engine megafunction (ASPEC)■ High-performance original RISC CPU megafunction



Infinite Solutions, Inc.3333 Bowers AvenueSuite 280Santa Clara, CA 95054Tel. (408) 986-1686Fax (408) 986-1687E-mail [email protected]

Overview

Infinite Solutions, Inc. (ISI) provides high-performance, low-cost, energy-efficient digital signal processing (DSP) megafunctions, and a complete set of tools for implementing cost-effective DSP applications. As market windows shrink, it is difficult for designers to develop the technology required to bring a product quickly to market. Using ready-made megafunctions permits designers to focus on developing core competencies. ISI offers DSP megafunctions with three to four times the performance of existing DSP functions for similar cost and power.

DynaMo Architecture

Logic design during the past decade has emphasized digital data processing. Accordingly, existing architectures are mainly targeted towards general-purpose computing. With technology advancing towards higher integration and lower cost, new data types—such as voice and video—are becoming more and more accepted. Processing these data types will be the main focus of the next decade. DSP requires low-power, low-cost, and high-performance designs. Existing architectures usually optimize only one of these three requirements. Thus, there is a need for a new type of architecture that equally addresses these requirements.

The ISI DynaMo architecture addresses this need. The DynaMo architecture is based on the principles of both RISC and CISC, and employs a RISC foundation that is specifically tailored to provide industry-leading DSP performance, including:

■ Innovative register file architecture suitable for DSP applications■ Fast and powerful bit manipulation mechanisms■ Fast nested interrupts and context switching■ Efficient power management■ Minimal (4-bit) instruction set, resulting in smaller, cheaper

implementations

Development Environment

Infinite Solutions provides designers with software and hardware tools to integrate DSP megafunctions easily. Infinite Solutions supplies an assembler, C compiler, architectural simulator, performance simulator, in-circuit emulator, and evaluation board to enable designers to implement applications quickly and efficiently.

Infinite Solutions, Inc.



Available Products

Infinite Solutions provides a series of implementations—based on the DynaMo architecture—that are suitable for the power, price, and performance needs of different DSP markets. Green is the first of the series, targeting medium-range applications such as wireless communication, speech processing, modems, embedded control, and multimedia. Green is a low-cost, 16-bit fixed-point implementation optimized for DSP applications and includes features that enable it to excel in microcontroller applications. The Green megafunction’s high performance and low power makes it an ideal choice for real-time applications such as cellular phones, pagers, and other wireless products. Not all products are available for Altera devices. Contact Infinite Solutions for availability.



Integrated Silicon Systems Ltd.29 Chlorine GardensBELFAST, BT9 5DL, Northern IrelandTel. 44 1232-664-664Fax 44 1232-669-664E-mail [email protected] http://www.ISS-DSP.com

Overview

Integrated Silicon Systems Ltd. (ISS) specializes in advanced DSP ASICs and DSP ASIC megafunctions. ISS provides VLSI architectures for DSP as well as arithmetic and design automation, giving designers a unique competitive advantage in all aspects of advanced DSP design and implementation.

ISS is establishing synergistic global relationships with major systems and semiconductor companies to bring innovative technical expertise to the DSP industry in the form of leading-edge products.

ISS provides the following products and services:

■ DSP silicon libraries for ASICs and PLDs, including libraries from device level to complete DSP algorithm level

■ DSP application-specific standard products (ASSPs), including DSP ASIC megafunctions

■ DSP device design and consulting services, utilizing a novel algorithm-to-architecture-to-device design process to produce quality designs optimized for area, performance, and power consumption

■ DSP design automation tools, including tools for custom DSP ASIC megafunctions



Available Products

ISS provides the megafunctions summarized in the following table. Not all products are available for Altera devices. Contact ISS for availability.


Altera Megafunctions FIR filters, IIR filters, median filters, and front-end image processing functions. Optimized for implementation in Altera FLEX 10K and FLEX 8000 devices.

DSP Algorithm Library MPEG encoders/decoders, JPEG encoders/decoders, and G.7xx encoders/decoders. Available as individual megafunctions for highly efficient silicon implementations.

DSP Function Library FIR filters and IIR filters as well as DCT, DFT, and FFT functions. Available as individual parameterizable VHDL functions. These functions are synthesized to produce highly-efficient silicon implementations through the use of third-party standard cells.

DSP Arithmetic Operator Library

Floating-point and fixed-point variants of multipliers, adders, accumulators, dividers, and square root operators. Available individually or as a library of parameterized VHDL designs.

DSP Component Library Basic DSP building blocks, including delay operators, comparators, and type converters. Available individually or as a complete library of parameterized functions.

Support Devices Library Efficient implementations of microprocessor interfaces, microcontroller interfaces, bus interfaces, bus controllers, and memory controllers. Enables ISS libraries to be used in building complete ASIC designs.



Logic Innovations, Inc.6205 Lusk BoulevardSan Diego, CA 92121Tel. (619) 455-7200Fax (619) 455-7273E-mail [email protected] http://www.logici.com

Logic Innovations, Inc., a turn-key engineering development firm, has developed over 500 systems for OEM release and custom, industrial use. Logic Innovations products are used in set-top boxes; hand-held and laptop computers; MPEG-2 systems; cable TV and DSS/DVB TV systems; cable TV test equipment; wireless communications; in-flight entertainment systems for commercial aircraft; supercomputers; laser printers; PCI; ATM; PCMCIA; EISA and ISA computers; and industrial environments such as VME and multi-bus.

Megafunctions—such as PCI bus and ATM functions—are developed using Logic Innovations’ product development experience. This approach differs from “model farms” where software engineers create megafunctions from specifications. Logic Innovations megafunctions derive from real-world applications created by experienced hardware and device designers and are optimized VHDL and Verilog HDL implementations targeted for programmable logic. Logic Innovations megafunctions are verified in working products before being released to designers. The megafunctions use architecture-specific constraints and constructs as required for optimized routing. The synthesized megafunctions are efficient, require minimal gate count, and provide full-speed operation.

Logic Innovations provides the following competitive advantages:

■ Technology-driven, expert design solutions■ Low-cost VHDL and Verilog HDL design files■ Optimized models for programmable logic■ Fully documented design files and manuals■ Evaluation boards■ Model customization services■ Turn-key hardware and software development services■ Ten-year record of satisfied customers



Object Oriented Hardware10-16 Tiller RoadDocklands, London E14 8PXEngland, UKTel. 44 (0) 7000 664664Fax 44 (0) 7000 664329E-mail [email protected] http://www.ooh.com

Overview

Object Oriented Hardware (OOH) designs, develops, and distributes synthesizable HDL megafunctions via the Foundry Independent Standard Product (FISP) program. FISP functions are designed to be portable between foundries—all of the functions can be targeted to any PLD or ASIC.

OOH concentrates on providing solutions for the multimedia industry, including FISP megafunctions for image processing, image compression, integrated services digital networks (ISDN), asynchronous transfer mode (ATM) functions, satellite communications, mass storage systems, encryption, audio processing, and virtual reality.

All FISP megafunctions are parameterized, and can be reused and customized, i.e., configured according to user requirements. OOH can develop additional features or create currently unavailable functions as needed to meet the needs of a specific application.

FISP megafunctions provide the following advantages:

■ FISP megafunctions can be merged with other design functionality and implemented on a single device.

■ Modifications or enhancements are easily implemented.■ Designs are supplied in VHDL, Verilog HDL, EDIF netlists, or any

vendor-specific netlist file.■ Designs are fully configured, synthesized, and tested at the gate level.■ Design times and development risks are greatly reduced.

OOH supplies three broad categories of FISP megafunctions.

■ Generic FISP megafunctions implement universal functions such as UARTs, interrupt controllers, modem components, and telecommunications echo cancellers.

■ Device FISP megafunctions implement industry standard device functions such as those used in the computer and telecommunications industries.

■ Reference FISP megafunctions implement specific standards such as G.721/G.722 ADPCM, PCMCIA, ISDN, and JPEG.



Available Functions

OOH provides the megafunctions summarized below. Not all products are available for Altera devices. Contact OOH for availability.

The following Reference FISP megafunctions are available:

■ HDLC-FIFO HDLC controller■ HDLC-DMA HDLC controller■ I.430 BRIM ISDN s-interface■ G.704 synchronous framing structure■ G.732 synchronous framing structure■ G.733 synchronous framing structure■ X.50 multiplexing interface■ G.711/G.712 CODEC■ G.721/G.726 QUAD speech compression■ Reed Solomon CODEC (~10 Mbyte/second)■ G.722 7-KHz audio CODEC■ G.727 5/4/2 Kbps ADPCM CODEC ■ G.728 CELP CODEC■ ANSI/ATA878.1 ARCNET-DMA controller token bus LAN■ ANSI/ATA878.1 ARCNET-FIFO controller token bus LAN

OOH also provides the following Generic FISP megafunctions:

■ DMA controller■ UART with FIFO function (asynchronous and synchronous)■ Priority interrupt controller■ Pulse width modulator■ Asynchronous FIFO function■ Synchronous FIFO function■ PIO■ Timer/counter■ Galois field multiplier■ Generic interleaver■ Generic de-interleaver■ Generic cyclic redundancy code (CRC) generator■ 68000 micro-personality module■ H8 micro-personality module■ SH micro-personality module■ 8051 micro-personality module■ ARM 7 micro-personality module■ Watchdog■ HardCODE scaleable RISC-based DSP engine■ 1/4 VGA LCD/CRT controller■ Linked list access controller (LILAC)■ Generic DRAM bus state controller



Sierra Research and Technology, Inc.6035 Kerrmoor DriveWestlake Village, CA 91362Tel. (818) 991-1509Fax (818) 991-1508E-mail [email protected]

Overview

From concept to silicon, Sierra Research and Technology, Inc. (Sierra) offers standard designs and custom design services for networking, data communications, CPU megafunctions, and storage devices. Sierra supports customer-initiated projects including complex systems, analog circuits, mixed analog-digital design, and digital circuit design.

Sierra provides device, board, and system designs for semiconductor, systems, and peripherals companies. Licensed semiconductor companies can manufacture and distribute Sierra’s 622-Mbs ATM and 100-Mbs ethernet technology. Currently, Sierra is developing several CPU megafunctions from the 68xx and R3xxx families.

With a variety of EDA tools for simulation, synthesis, and layout, Sierra can perform layout for gate array, standard cell, or custom device methodologies. Sierra also provides access to leading-edge prototyping technology, i.e., building limited quantities of large devices that run at speed in the final package. This technology aids systems houses and other designers who require engineering samples before first device fabrication.

With megafunctions, designers save money, improve time-to-market, and are assured high-quality designs. Sierra uses the latest EDA design tools and methodology to ensure that designs work correctly the first time.

Available Products

Sierra provides the megafunctions summarized below. Not all products are available for Altera devices. Contact Sierra for availability.

■ S68xx —68xx CPU megafunctions■ SR3xxx—MIPS R3xxx CPU megafunctions■ Fast ethernet controller—10- to 100-Mbs ethernet controller for PCI to

MII bus■ Fast ethernet PHY—10- to 100-Mbs TX physical■ Fast ethernet MAC—10- to 100-Mbs ethernet MAC■ OC12 ATM SAR—622-Mbs ATM segmentation and reassemble

Sierra Research andechnology, Inc.T



Silicon Engineering, Inc.269 Mt. Hermon RoadScotts Valley, CA 95066Tel. (408) 438-5330 Fax (408) 438-8509E-mail [email protected] http://www.sei.com

Silicon Engineering, Inc. (SEI) provides custom and semi-custom integrated circuit (IC) design capability and technology licenses for the systems, semiconductor, and consumer electronics industries.

For the past decade, SEI has applied system knowledge and design expertise to a variety of application areas, including super-integrated graphics and multimedia chipsets, disk drive controllers, memory controllers, RAMDACs, high-speed SRAM, networking chipsets, embedded controllers, and consumer game controllers. Designs range in complexity from 10,000 to 2 million gates. Recent projects include a three-dimensional graphics controller, 64-bit RISC CPU, 200-MHz RAMDAC, 5-ns embedded dual-port SRAM, 3-V disk controller, GUI accelerator, laser printer engine, ethernet controller, and an audio device. SEI can use a range of information as the starting-point for new designs—from marketing requirement documents to pre-existing designs requiring modification.

SEI utilizes industry-standard methodologies and tools from Cadence, Synopsys, Viewlogic, and Mentor Graphics to match the designer’s environment. A top-down and well-structured design methodology is followed throughout the design cycle in order to minimize design time and ensure first-pass success. Using industry-standard tools augmented with proprietary tools enables SEI to rapidly design ASICs and ASSPs implemented in gate array, standard cell, or high-density PLDs. SEI can then convert these same designs to full, custom ICs for production quantities.

SEI implements designs for any performance level or production volume. Depending on the device specification and marketing requirements, SEI can recommend the most appropriate implementation device. Silicon suppliers used by SEI include LSI Logic, VLSI Technology, Toshiba, SMOS, Samsung, IBM Microelectronics, AT&T, TSMC, UMC, AMI, NEC, Chartered Semiconductor, OKI Semiconductor, and Altera.

In addition to being a charter member of AMPP, SEI is an IBM Microelectronics Division ASIC Design Center and an Authorized Design Center for LSI Logic. SEI also maintains excellent relationships with a number of other major ASIC and wafer suppliers.



SEI has the following systems expertise:

■ Two-dimensional and three-dimensional (2-D/3-D) imaging■ Graphics chipsets■ High speed RAMs and DACs

– RAMDAC– DAC, ADC, PLL– SRAMs

■ Communications chipsets– Ethernet– ATM

■ Storage chipsets– Disk controller– Motor controller

■ Consumer chipsets– IR-based communication– Voice recognition and synthesis

The following technology licenses are available:

■ AMPP megafunctions■ Verilog HDL megafunctions■ Full custom megacells■ EDA point tools■ Standard cell libraries■ Memory arrays

SEI offers the following services:

■ Gate array and standard cell design■ Full custom and layout design■ Technology conversions■ EDA tools and library development■ Mixed analog/digital design■ PLD design



SIS Microelectronics, Inc.P.O. Box 14321500 Kansas Ave. Suite 1DLongmont, CO 80501

Product Information:Tel. (303) 776-1667

x223Fax (303) 776-5947E-mail [email protected]

Technical Support:Tel. (303) 776-1667

x226Fax (303) 776-5947E-mail [email protected]

Overview

SIS Microelectronics, Inc. (SIS) provides a partnership between system designers and silicon vendors by providing partner companies with the equivalent of an “in-house” silicon supplier. SIS supports the system development process from concept to production.

SIS supplies silicon solutions for the embedded-processor market. SIS is currently shipping three “off-the-shelf” ASICs that reduce the cost and time-to-market of laser printers. The most recent product is the SFBC-licensed memory compression technology from Adobe Systems, Inc.

SIS provides a variety of megafunctions, including ASSPs, integrated circuit (IC) megafunctions, processor interfaces, and laser printer engine drivers.

Available Products

SIS provides the megafunctions summarized below. Not all products are available for Altera devices. Contact SIS for availability.

Silicon-Proven IC Megafunctions

■ Speedbridge—Speed matching FIFO function for Altera devices

Application-Specific Standard Products (ASSPs)

■ SMEMC—Highly integrated memory/peripheral controller ■ SLPC—Peripheral controller for laser printer applications■ SFBC—Adobe-licensed frame buffer compression technology

(memory reduction for laser printers)

Processor Interfaces

■ VR4300■ Intel 960Cx/Jx■ IDT Orion ■ AMD 29030/040■ DMA controller■ DRAM controller■ ROM/SRAM controller



Laser Printer Engine Printer Drivers

■ Timer/counter■ Interrupt controller■ 450/550 UART■ 1284 parallel port■ RLE compression engine■ 32-bit multiplier ■ Serial EEPROM interface



Synova Incorporated1333 Gateway DriveSuite 1017Melbourne, FL 32901Tel. (407) 728-8889Fax (407) 728-9587E-mail [email protected]

Overview

Synova provides megafunctions and turn-key ASIC services in commercial and radiation-hardened CMOS processes.

Available Products

Synova provides the megafunctions summarized below. Not all products are available for Altera devices. Contact Synova for availability.

The current megafunctions include:

■ JPEG encoder■ JPEG decoder■ IEEE-754 floating-point function■ Fast Fourier transform function

In addition, Synova offers standard radiation-hardened products including:

■ Radiation-hardened 32-bit microprocessor■ Radiation-hardened peripheral interface controller■ Embedded microprocessor ASIC



VAutomation Inc.20 Trafalgar SquareSuite 443Nashua, NH 03063Tel. (603) 882-2282 Fax (603) 882-1587E-mail [email protected] WWW http://www.

VAutomation.com

Overview

VAutomation’s synthesizable hardware description language (HDL) megafunctions provide designers with solid, stable, easy-to-use standard functions such as microprocessors or microperipherals. These functions allow the designer to concentrate on unique value-added technology without re-inventing standard functions. Combining VAutomation megafunctions with other functional blocks and custom logic can produce systems-on-a-chip.

The designer can target VAutomation megafunctions for any architecture, including PLDs, ASICs, gate arrays, or standard cells, with voltages ranging from 5 V to 2.8 V and processes such as CMOS (from 1 µm to 0.35 µm or smaller), BiCMOS, ECL, and GaAs. VAutomation AMPP megafunctions are designed to allow prototyping in Altera PLDs and later migration to a custom device in a suitable target architecture.

VAutomation uses strictly synchronous HDL designs with D flipflops and logic gates that are reliable and easy to synthesize and analyze; feedback loops, multi-cycle paths, latches, and flipflop clear or set pins are not used.

Most VAutomation megafunctions are available in VHDL in the VSource form for design re-targeting. However, megafunctions can be converted to Verilog HDL on request. Due to language restrictions, some verification suite features are not available in Verilog HDL. Verification suites are typically more robust in VHDL, but the Verilog HDL megafunctions have nearly the same functionality.



Available Products

VAutomation provides the megafunctions summarized in the following table. Not all products are available for Altera devices. Contact VAutomation for availability.


V6502 High-performance 8-bit microprocessor

VZ80 High-performance 8-bit microprocessor

V8086 Intel-compatible 16-bit microprocessor

V186 Intel/AMD-compatible 16-bit microprocessor

V960 Ethernet LAN controller

V526 High-level data link controller (HDLC)



Virtual Chips, Inc.2107 N. First StreetSuite 100San Jose, CA 95131Tel. (408) 452-1600U.S. (888) 4VCHIPSFax (408) 452-0952E-mail [email protected] http://www.vchips.com

Overview

Virtual Chips, Inc. develops, markets, and supports fully synthesizable cores and test environments based on computer-industry standards. These functions are modeled after standard products, and include the features, documentation, and support necessary to ensure smooth integration into customer designs. Virtual Chips offers a product line that meets the full range of PCI application requirements, as well as comprehensive PCI bus test environments. Additionally, simulation models for speciality memories are available. Future products will meet the universal serial bus, IEEE 1394 and cardbus standards.

Portfolio Features & Benefits

Virtual Chips provides 24 application-optimized PCI cores, available off-the-shelf in both Verilog HDL and VHDL formats. These functions are:

■ Designed for large burst-mode transfers at full PCI speed, providing improved drawing speed for graphics applications and full-duplex operation for communications applications.

■ Stable cores that are proven in silicon, building on the verification and refinements performed by a large base of users.

■ Developed, maintained, and supported by highly experienced PCI system designers, permitting designers to focus development resources on product differentiation.

A simple, straightforward application interface isolates the application from the PCI bus protocol. Designers can integrate functions into an application and begin running PCI cycles in hours, rather than months.



Available Functions

Virtual Chips provides the products summarized below. Not all products are available for Altera devices. Contact Virtual Chips for availability.

Virtual Chips provides the following PCI cores:

Test Environments

■ PCI bus test environment (Verilog HDL, VHDL)■ 32-bit cardbus test environment (Verilog HDL, VHDL)

Speciality Memories

■ NEC 16M SDRAM (Verilog HDL, VHDL)■ NEC 16M EDO DRAM (Verilog HDL, VHDL)■ NEC 16M/8M Rambus DRAM (Verilog HDL, VHDL)■ NEC RAC (Rambus ASIC Cell) (Verilog HDL, VHDL)■ NEC 64M 2/4 Bank SDRAM (Verilog HDL, VHDL)■ Oki 2Mx8 SDRAM (Verilog HDL)■ Fujitsu 16M SDRAM (VHDL)■ Hitachi 16M SDRAM (Verilog HDL, VHDL)■ Hitachi 4M SDRAM (Verilog HDL, VHDL)■ Hitachi 16M SGRAM (Verilog HDL, VHDL)

Application Bus Widths Asynchronous with FIFO Functions

Synchronous with FIFO Functions

Synchronous without FIFO

Functions

Satellite(VHDL and Verilog HDL)

32-bit PCI bus to 32-bit application v v v

32-bit PCI bus to 64-bit application v v v64-bit PCI bus to 32-bit application v v v64-bit PCI bus to 64-bit application v v v

Host Bridge(VHDL and Verilog HDL)

32-bit PCI bus to 32-bit application v v v32-bit PCI bus to 64-bit application v v v64-bit PCI bus to 32-bit application v v v64-bit PCI bus to 64-bit application v v v


®

Altera Sales Offices

May 1996

Altera RegionalSales Offices

NORTHERN CALIFORNIA(CORPORATE HEADQUARTERS)Altera Corporation2610 Orchard ParkwaySan Jose, CA 95134-2020TEL: (408) 894-7000FAX: (408) 433-3943

Altera Corporation2290 N. First Street, Suite 212San Jose, CA 95131TEL: (408) 894-7900FAX: (408) 894-7979

SOUTHERN CALIFORNIAAltera Corporation15375 Barranca Pkwy., Suite B-201 Irvine, CA 92718 TEL: (714) 450-0262FAX: (714) 450-0263

Altera CorporationOlympic Plaza Executive Center11500 West Olympic Blvd., Suite 400Los Angeles, CA 90064TEL: (310) 312-4507FAX: (310) 312-4508

Altera Corporation5355 Mira Sorrento Place, Suite 100San Diego, CA 92121TEL: (619) 597-7518FAX: (619) 597-7418

COLORADOAltera CorporationDenver Technology Center7900 East Union Avenue, #1100Denver, CO 80237TEL: (303) 694-5352FAX: (303) 694-5351

GEORGIAAltera Corporation1580 Warsaw RoadRoswell, GA 30076TEL: (770) 643-2530 FAX: (770) 643-2542

ILLINOISAltera Corporation475 N. Martingale Road, Suite 420Schaumburg, IL 60173TEL: (708) 240-0313FAX: (708) 240-0266

Altera Corporation

MARYLANDAltera Corporation9891 Broken Land Parkway, Suite 300Columbia, MD 21046TEL: (410) 312-5708FAX: (410) 309-0720

MASSACHUSETTSAltera Corporation238 Littleton RoadSuite 207Westford, MA 01886TEL: (508) 392-1100FAX: (508) 392-1157

MINNESOTAAltera Corporation2850 Metro Drive, Suite 250Bloomington, MN 55425TEL: (612) 851-7861FAX: (612) 858-7258

NEW JERSEYAltera Corporation575 State Highway 28 Raritan, NJ 08869TEL: (908) 526-9400FAX: (908) 526-5471

NORTH CAROLINAAltera Corporation5511 Capital Center Drive, Suite # 110Raleigh, NC 27606TEL: (919) 852-1004FAX: (919) 852-0809

OHIOAltera Corporation7784 Reynolds RoadMentor, OH 44060TEL: (216) 946-8211FAX: (216) 946-8155

OREGONAltera CorporationPointe Five Executive Suites11000 S.W. Stratus St., Suite 330-17Beaverton, OR 97008TEL: (503) 643-8447FAX: (503) 644-2345

TEXASAltera Corporation5080 Spectrum Drive, Suite 812WDallas, TX 75248TEL: (214) 701-2330FAX: (214) 701-2331

89

Altera Sales Offices

Altera Regional Sales Offices(Continued)

TEXAS (continued)Altera Corporation9430 Research Blvd.Echelon IV, Suite 400Austin, TX 78759TEL: (512) 343-4542FAX: (512) 418-1186

90

ONTARIOAltera Corporation300 March Road, Suite 601BKanata, Ontario K2K 2E2CanadaTEL: (613) 599-3141FAX: (613) 599-3143

Altera International Sales Offices

UNITED STATES(CORPORATE HEADQUARTERS)Altera Corporation2610 Orchard ParkwaySan Jose, CA 95134-2020USATEL: (408) 894-7000FAX: (408) 433-3943

(408) 894-7755

UNITED KINGDOM(EUROPEAN HEADQUARTERS)Altera UK LimitedHolmers Farm WayHigh WycombeBuckinghamshireHP12 4XFUnited KingdomTEL: (44) 1 494 602 000FAX: (44) 1 494 602 001

NORTHERN EUROPEAltera UK LimitedHolmers Farm WayHigh WycombeBuckinghamshireHP12 4XFUnited KingdomTEL: (44) 1 494 602 020FAX: (44) 1 494 602 021

FRANCEAltera France13 Avenue Morane Saulnier-Le Mermoz78140 VelizyFranceTEL: (33) 1 34 63 07 50FAX: (33) 1 34 63 07 51

GERMANYAltera GmbHMax-Planck-Str. 5 D-85716 UnterschleissheimGermanyTEL: (49) 89 3218 250FAX: (49) 89 3218 2579

HONG KONGAltera Hong KongSuite 1008, Tower 1China Hong Kong City33 Canton Road, TsimshatsuiKowloon, Hong KongTEL: (852) 2377-0218FAX: (852) 2377-2811

ITALYAltera ItaliaCorso Lombardia 75Autoporto Pescarito10099 San Mauro, Torinese (Torino)ItalyTEL: (39) 11 223 8588FAX: (39) 11 223 8589

JAPANAltera Japan, Ltd.Shinjuku Mitsui Bldg.2-1-1, Nishi-ShinjukuShinjuku-ku, Tokyo 163-04JapanTEL: (03) 3340-9480FAX: (03) 3340-9487

KOREAAltera KoreaYoundang Bldg., Suite 501 144-23 Samsung-dong, Kangnam-KuSeoul, Korea 135-090TEL: (82) 2 538-6895FAX: (82) 2 538-6896

Altera Corporation

AMPP CatalogMay 1996 M-CAT-AMPP-01

Altera, MAX, MAX+PLUS, MAX+PLUS II, FLEX, FLEX 10K, FLEX 8000, AHDL, and EPM7128 are trademarks and/or service marks of AlteraCorporation in the United States and/or other countries. Altera Corporation acknowledges the trademarks of other organizations for their respectiveproducts or services mentioned in this document, specifically: Advancel is a trademark of Advancel Logic Corporation. 3Soft, MacroWare, andMegaMacro are registered trademarks of 3Soft Corporation. SCVL, SCVL-S, MOR Maintenance, V-Custom Service, and V-Custom Models aretrademarks of CAST, Inc. VAutomation is a trademark of VAutomation Inc. FISP is a registered trademark of Object Oriented Hardware. Virtual Chipsis a trademark of Virtual Chips.

Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this document. Altera advises itscustomers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customeris current. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty. Testingand other quality control techniques are used to the extent Altera deems such testing necessary to support this warranty. Unless mandated bygovernment requirements, specific testing of all parameters of each device is not necessarily performed. In the absence of written agreement to thecontrary, Altera assumes no liability for Altera applications assistance, customer’s product design, or infringement of patents or copyrights of thirdparties by or arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any patent right, copyright, or otherintellectual property right of Altera covering or relating to any combination, machine, or process in which such semiconductor devices might be or areused.

Altera’s products are not authorized for use as critical components in life support devices or systems without the express written approval of thepresident of Altera Corporation. As used herein:

1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whosefailure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in asignificant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure ofthe life support device or system, or to affect its safety or effectiveness.

Products mentioned in this document are covered by one or more of the following U.S. patents: 5,498,975; 5,495,182; 5,493,526; 5,493,519; 5,477,474;5,463,328; 5,444,394; 5,438,295; 5,436,575; 5,436,574; 5,434,514; 5,432,467; 5,414,312; 5,399,922; 5,384,499; 5,376,844; 5,375,086; 5,371,422; 5,369,314;5,359,243; 5,359,242; 5,353,248; 5,352,940; 5,350,954; 5,349,255; 5,341,308; 5,341,048; 5,341,044; 5,329,487; 5,317,212; 5,317,210;5,315,172; 5,309,046; 5,301,416; 5,294,975; 5,285,153; 5,280,203; 5,274,581; 5,272,368; 5,268,598; 5,260,611; 5,260,610; 5,258,668;5,247,478; 5,247,477; 5,243,233; 5,241,224; 5,237,219; 5,220,533; 5,220,214; 5,200,920; 5,187,392; 5,166,604; 5,162,680; 5,144,167;5,138,576; 5,128,565; 5,121,006; 5,111,423; 5,097,208; 5,091,661; 5,066,873; 5,045,772; 4,969,121; 4,930,107; 4,930,098; 4,930,097;4,912,342; 4,903,223; 4,899,070; 4,899,067; 4,871,930; 4,864,161; 4,831,573; 4,785,423; 4,774,421; 4,713,792; 4,677,318; 4,617,479;4,609,986; 4,020,469; and certain foreign patents.

Copyright © 1996 Altera Corporation. All rights reserved.

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