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Real-Time Hardware in the Loop Simulation of Aerospace Power Systems

Julio C. G. Pimentel* Dept. of Electrical and Computer Eng., Laval University, Ste-Foy, QC, G1K7P4, Canada

and

Yosef G. Tirat-Gefen† Aerospace Division, Castel Research Inc., Fairfax, VA, 22031, USA

[Abstract] This paper presents new results obtained with a real-time simulator for aerospace power systems capable of hardware in the loop simulation. This means that the model under test runs in real-time in the simulator and it can drive and receive signals from a real system through its analog and digital interfaces. The simulator uses low cost reconfigurable computing infrastructure (e.g. embedded processors and FPGAs) and it is capable of having simulation steps on the order of 0.4 microseconds, that is suitable to represent typical modern aerospace power systems. As an example, we realize the simulation of a sequential switching shunt series regulator (S4R) system using Matlab/Simulink and compare it to the results produced by the FPGA based simulator.

Nomenclature BCR = Battery Charge Regulator BDR = Battery Discharge Regulator DRTPSS = Digital Real-Time Power System Simulator EFSM = Extended Finite State Machine ESA = European Space Agency FPGA = Field Programmable Gate Array GEO = Geosynchronous Earth Orbit GUI = Graphical User Interface HIL = Hardware In the Loop PCU = Satellite Power Conditioning Unit PE = Processing Element S3R = Sequential Switching Shunt Regulator S4R = Sequential Switching Shunt Series Regulator SEPS = Spacecraft Electrical Power System UPS = Universal Power Switch

I. Introduction odern aerospace applications include many types of mission-critical systems. These systems are very expensive and sensitive to manipulation. Operating a system outside its safety margins may damage it beyond

repair, or cause some serious defects that may be costly to fix. Another important aspect is the time and effort spent to design, set up and fine-tune these systems, which can affect the budget and schedule of the design and build of the aircraft. One of these systems is the spacecraft electrical power system (SEPS), which is complex and has a high manufacturing cost. Therefore, it is essential to realize simulation studies to better understand and validate the design of SEPS. Many simulation tools have been used to analyze SEPS. These tools can be circuit-oriented

* E-mail: jpiment@ieee.org, Senior Member IEEE † Lead Scientist, e-mail: yosefgavriel@computer.org, 610 North Main Street #288, Blacksburg, VA, Senior Member IEEE, Member AIAA.

M

5th International Energy Conversion Engineering Conference and Exhibit (IECEC) 25 - 27 June 2007, St. Louis, Missouri

AIAA 2007-4716

Copyright © 2007 by Aerospace Division, Castel Research Inc. Published by the American Institute of Aeronautics and Astronautics, Inc., with permission.

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EquipmentUnderTest

DigitalRealTime

Simulator

(processing)(Z-1)

AnaAna

Ana

Dig

Dig

SamplingZ-1

Z-1

SamplingFigure 1. General architecture of a DRTPSS

packages such as the many SPICE-like simulators [7][13], signal-flow simulators such as MatLab/Simulink [15] or EASY5 [17], and application-specific software such as the EBLOS (“Energy Budget Low Orbit Satellite”) computer program [1]. Because of the increasing complexity of modern SEPS, it has also become important to build virtual prototypes prior to the construction of the real system. Such prototypes are used to validate the proper operation of the SEPS control strategy and its interaction with the remaining modules of the spacecraft system. Such a virtual prototyping tool should help to optimize the system architecture, component choices, and the system performance in terms of efficiency, power density, cost, and lifetime. A DRTPSS is an appropriate tool to perform these tasks.

A general architecture of the DRTPSS is shown in the Figure 1. It consists of a library of device models and a representation of the power system network modeled, for example, using the nodal or the state-space formulations and coded in a high-level programming language; and a high-performance digital computer that uses some sort of parallel processing topology [10-12]. At the beginning of every timestep, the simulator acquires new data from the interface inputs through digital channels or through the A/D interface cards, and sends out the simulated physical variables through output digital channels or the D/A interface cards. The input and output signals minimum sampling frequency is given by Nyquist’s Law, and must be bigger than twice the signal bandwidth. In practice, it should be at least one order of magnitude bigger than the signal bandwidth. If the minimum time step, that the simulator can attain, is smaller than the minimum sampling period required by the application, than the simulator can be used as a virtual prototype of the real sub-system and can replace it. Therefore, when testing a new controller, we can implement it in the simulator and connect the model to the real arm actuator or vice-versa. This strategy is called hardware in the loop (HIL) simulation, reducing cost and development time.

Previous work studied the design and testing of spacecraft power systems using the VTB (“Virtual Test Bed”)

simulation environment [1]. VTB is capable of handling natural power flow, signal and data coupling between devices and offers a combination of both topological and mathematical expressions in a model formulation. VTB provides a very flexible graphical user interface and powerful capabilities for modeling and co-simulation [1]. Nevertheless, VTB was designed to run in a microprocessor on a software based platform. Therefore, VTB is subjected to the processor-memory hardware paradigm (Read-Modify-Write) and the inter-processor communication overhead experienced with the present technology creates a bottleneck, making it difficult to further reduce the minimum simulation timestep. VTB is somewhat flexible to allow for the integration of custom add-on modules as a way to speed up the simulation. However, the limitations inherent to its microprocessor-based design approach can not be easily solved.

In order to achieve shorter time steps, we use a reconfigurable architecture based on state-of-the-art high density

FPGAs such as Xilinx Virtex family. Recently, new advances in the IC technology allowed the development of a new generation of FPGA devices that are much bigger and faster than previous ones. These new FPGAs can have more than 5 million gates and run at clock frequencies higher than 500 MHz [14]. We have developed a DRTPSS and a methodology which are entirely based on high density FPGA devices and an HDL design flow. The simulator is capable of simulating small and medium size power networks with very high natural frequencies. The methodology exploits the intrinsic parallelism of FPGA’s internal architecture, its high bandwidth low-latency switch fabric, and the parallelism inherent to power system models to implement an automatic mapping of the power system network to the FPGA internal resources. Therefore, rather than simulating the power system model in software, it is simulated directly in hardware. This approach can produce a speed up of more than one order of magnitude greater than that of a software based approach [10-12].

The simulator presented in this paper is capable of simulating a variety of different applications. The existent

models include power electronics devices, transfer functions, digital controllers, motion control functions, etc. If the modules in the library are not sufficient, more modules can be easily added to the simulator library. The simulator is

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SimPowerSystemSimulinkLibrary

VHDLSystemLibrary

SimPowerSystemSimulink

GenVhdl

ValidateVHDLLibrary

User

Power SystemSpec

Non linearSub-circuit

LinearSub-circuit

C/C++ Or FPGAFPGA

Scheduler

Figure 2. FPGA Real-Time Simulator Programming Flow

capable of simulating fly-by-wire and other aerospace power systems. This includes, but is not limited to, simulation of embedded digital controllers, power electronics energy management systems and motion control applications.

Modern power systems use very high frequency converters to maximize power density (ratio between power and

volume). To achieve the necessary accuracy, it is mandatory that the simulation time step be short enough. Otherwise, the simulation may produce erroneous results, add artificial jitter to the generated signals or in certain cases can cause the power system controller to become unstable. Our experimental results show that the simulator can achieve a time step less than 0.4 microseconds, which is smaller than the commercial real-time simulators, and that it can simulate PWM converters with carrier frequencies higher than 10 kHz.

The paper is organized as follows. The next two sections present a short description of the FPGA real-time simulator programming flow and its high level architecture. Afterwards, we discuss the S4R SEPS and present the simulation results generated using Matlab/Simulink. Finally, we realize the simulation of the S4R system using the FPGA simulator and compare the results to those produced with Matlab/Simulink.

II. FPGA Real-Time Simulator Programming Flow Figure 2 shows the FPGA simulator

programming flow. The interface and configuration parameters of the modules in the VHDL System Library (“VHDL - VHSIC Hardware Description Language”) are compatible with their counterparts existing in the SimPowerSystem and Simulink libraries [15]. These VHDL modules were developed and tested using a model-based methodology that consists of the following steps:

i) A model of the module micro-architecture is designed taking into account its implementation in a FPGA;

ii) Afterwards, this model is validated using Simulink;

iii) After the behavior of the model attains the expected accuracy, the model is coded in VHDL;

iv) Then its VHDL implementation is simulated using an HDL simulator such as Modelsim [16] and the results are compared to the Simulink simulations;

v) Finally, if the two simulations agree then the module is stored in the VHDL System Library.

The modules can be modeled using many different types of formulations such as electrical circuits, state

machines, transfer functions, linear and nonlinear mathematical equations, algorithms, etc. This fact enables the FPGA simulator to be used in many different applications. As shown in Table I, currently, the VHDL library includes many modules for power electronics and motion control applications. New modules can be added to the library to enable the simulator to address others applications such as spacecraft power and control systems.

The user utilizes Simulink’s GUI to draw the schematic of the electrical power system (or the schematic model

of the system under test in case of others applications). A proprietary tool called GenVhdl reads the Simulink power network schematic, the VHDL libraries, as well as data provided by the user and automatically generates the VHDL code that implements the real time simulation. The derived VHDL code can be simulated offline by a commercial HDL simulator such as Modelsim and synthesized with general commercial EDA tools using an FPGA design and implementation flow such as Xilinx ISE [14]. The simulator was tested using a Xilinx XUP VirtexIIPro FPGA Board [14]. Nevertheless, the generated VHDL code is independent of the FPGA device. Therefore, it can be implemented by others types of FPGA devices that provide the resources needed to implement the specified system.

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Linearsub-circuit

ControlVoltageCurrent

VoltageCurrent

VoltageCurrent

VoltageCurrent

VoltageCurrent

VoltageCurrent

Scheduler

Non linear sub -circuits

State Space(Ad, Bd, Cd, Dd)

Control Control

Non linearSub-circuit

Non linearSub-circuit

Non linearSub-circuit

Non linearSub-circuit

Non linearSub-circuit

Non linearSub-circuit

Control

Figure 3. FPGA Simulator High Level Architecture

Voltages

EOC

LogicalSignals

Sub

CircuitCurrents

Voltages

Currents

LogicalSignals

RSTCLKS_CLKF_CLKENSTCREG

RSTCLK

EOC1

EOC2

EOCn Scheduler

EN

STC_l

STC_nl

REG_l

REG_nl

III. FPGA Real-Time Simulator High Level Architecture The logical resources included in modern FPGAs, such as the Virtex family from Xilinx [14], include high speed

SRAM memories, a large number of registers and combinational logic and multipliers among others. These resources make FPGAs a convenient platform to implement systems. These resources include a large number of parallel small specialized processors; distributed memory access algorithms; high control logic and finite state machines as well as very high throughput DSP functions. In addition to that, the FPGA switch matrix allows the exchange of a high amount of data between modules at very high clock frequency and with very small latency. The FPGA simulator explores these features to solve the bottleneck issues present in the parallel microprocessor based architectures and provide a more scalable solution to the implementation of real-time simulation algorithms. This section presents a short description of the FPGA simulator high level architecture. A more detailed description can be found in [10-12].

A. Computational Model – Coarse Grain Dataflow Architecture The FPGA simulator architecture is shown in Figure 3. It is based on a data flow processing model where the

processing elements (PEs) are independent objects, and each one computes its function independently. The interconnection between them is extracted from the system schematics drawn using Matlab/Simulink. The PEs are interconnected through their input and output ports so that the inputs of a sub-circuit can only change at the end of a time step. The outputs of the PEs depend only on their inputs and their internal states. At the end of each time step the PEs transfer their newly calculated values (voltages, currents, logical signals, etc.) to the next PE. The simulation scheduler synchronizes the functioning of all PEs, and it is responsible for coordinating the following tasks: simulation initialization; generation of the multiple timesteps reference clocks; synchronization of the simulation and exchange data between linear and nonlinear PEs. All PEs follow the same standard interface shown in Figure 3. PEs are modeled as an EFSM [10-12]. The variables exchanged between PEs are part of the PE data path which is implemented in VHDL using pipelined MAC units (Multiply-And-Accumulate). The remaining signals are part of the control path and are intended to send information to or receive information from the scheduler. The PE control path is implemented as finite state machines that control the data path and the interface to the scheduler.

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entity DiscPIController isgeneric (NBits:natural:=8; NBitsRadix:natural:=8; NBitsCoef:natural:=8; PIType:natura :=0; NCycles:natural:=1; A1:natural:=1; A2:natural:=1; Init:natural:=0; UpperBound:integer:=1; LowerBound: integer:=0 ); port (CLK: in STD_LOGIC; RST: in STD_LOGIC; EN: in std_logic; STC: in std_logic; Reg_output: in std_logic; Verr: in std_logic_vector (NBits-1 downto 0); Vcont: out std_logic_vector (NBits-1 downto 0); EOC: out std_logic ); Figure 4. PI controller entity declaration

B. PE Modeling The PEs are stored in the simulator system library as

parameter-driven VHDL entities what allows them to be used in different types of circuits and applications. As an example, Figure 4 shows the VHDL entity declaration of a PI controller module. The generic clause is used to define the configuration parameters of the module. The port clause defines the input and output signals that are part of the data and the control path. PEs can be modeled using many types of formulations such as electrical circuits, state machines, transfer functions, linear and nonlinear mathematical equations, algorithms, etc.

Because of the real-time constraint, real-time simulators

use fixed timestep. A UPS (shown in Figure 5a) is a topology that is often used in power electronics. It is used in the S4R system as the pairs M2/D2 and M3/D3. A UPS is composed of a MOS switch and a flywheel diode. When the MOS switch is turned on or turned off, the energy and current conservation cause the flywheel diode to turn off or to turn on respectively. The commutation is done so that there is no discontinuity of the voltage or the current across the UPS. If the MOS switch and the flywheel diode are simulated independently, during switching, this nonlinear behavior combined with one or two timesteps delay originated by the decoupling could cause simulation errors and possibly instability. To mitigate these problems, the UPS EFSM (shown in figure 5c) coordinates the PE data path to ensure the current through the UPS will be redistributed respecting voltage and current Kirschoff’s laws as well as energy conservation. The operation of the UPS requires the following conditions to hold: 1) the MOS switch and the flywheel diode can not be turned on at the same time; 2) every time Q1 is on the associated diode D2 is turned off and vice-versa; 3) If Gate=1 then Q1 is on; 4) Current Ia can not be subject to sudden changes.

Figure 5b shows the electrical equivalent of the MOS switch. The flywheel diode electrical equivalent can be

easily inferred from the MOS switch model. The MOS switch is modeled as an non-ideal switch in parallel with a RC snubber [5][6]. The input and output variables are respectively (Gate, Vds) voltages and the averaged and instantaneous Ids currents. When turned off, it is an ideal switch so that Ids(n)=0. Otherwise, when it is turned on it is modeled by a series RLV circuit. The voltage Kirschoff’s law and the continuous time transfer function H(s) of the two port RLV network are given by Eq. (1) and Eq. (2) respectively.

( ) ( ) ( ) ( )ds f on ds on dsdV t V t R I t L I tdt

= + ⋅ + ⋅ (1)

( ) (1/ )( )( ) ( ) 1 ( / )

ds on

ds f on on

I s RH sV s V s s L R

= =− + ⋅

(2)

Using backward Euler discretization rule we can write Eq. (3) where Ts is the simulation timestep. This discretized set of time-domain equations are implemented in hardware using an FPGA design flow and a digital filter methodology [10-12].

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Solar Array 1

Solar Array 2

Solar Array n

PayloadEnergyStorageSystem

Main BusRegulator

System

Power Distribution and Control Unit

Figure 6. High Level Architecture of a Typical SEPS

1 2( ) ( ) ( 1))ds ds dsI n A V n A I n= ⋅ + − where sonon

on

sonon

s

TRLLA

TRLTA

+=

+= 21 , (3)

IV. The SEPS under Test: S4R System The SEPS is part of the Power Conditioning Unit which is the system that controls the overall electrical power

flow in a satellite [6]. Satellite PCUs have experienced a significant evolution in the last two decades driven mainly by the lifetime requirements demanded for the new telecom spacecrafts. These systems evolved from the unregulated systems used in the first satellites to the regulated systems [1] [2] [3] [4]. Besides, some topologies and control methods have been developed in order to satisfy the hard regulations imposed by the aerospace regulatory agencies and companies. These systems are very expensive and sensitive to manipulation. Operation outside safety margins may cause some serious defects that may be costly to fix, or completely incapacitate the satellite. Simulations, and more recently HIL simulation, have been employed as a way to reduce these risks and the total development cost.

Figure 6 shows the high level architecture of a

typical SEPS. Its primary power source is normally a solar array. Presently, the energy storage system use rechargeable batteries and nonlinear loads, one or more voltage or current regulators and a power distribution and control unit which manages the operation of the whole power system. Previous generations of GEO telecom satellites used NiH2 batteries. Nowadays, they are being changed by Li-ion technology because of its higher energy-to-weight ratio (Wh/kg) and lower thermal dissipation, higher energy efficiency, and very low self-discharge. Most SEPS use shunt regulators to limit the power bus voltage by dissipating the excess solar array power to ground. There are many proposed topologies such as sequential shunt system, partial shunt system, digital shunt system, etc. [6]. One important topology of SEPS is the S4R system [6] which has been chosen to be the system under test.

ψ

sample!{VQ1=inp}[STC==1]

store!{out=Ib1}[Reg==1]

turnon !{Ib1=Ib1+Is1}[P2]

{Ib1=Icalc1}

turnoff!{Ib1=0}[P4]

Icalc1=f(Ron1,Lon1,Rs1,Cs1)

Rs1

Rs2

Cs1

Cs2D2

Q1

G1

+

-

AIb1

Ib2

Q1 switching sequenceIs1

Is2

Ia turningon!{Ib1=Is1-Ib2}[P1]

turningoff!{Ib1=Is2}[P3]

Q1_on = VQ1>0 and G1=1D2_on = not(Q1_on) and …...

D S

Gate

D S

Gate

Cs1 Rs1

Cs1 Rs1

Ron Lon

Ib1 = f(Vds, Vf, Ron, Lon, Rs1, Cs1)

Vf

Is1 = f(Vds, Vf, Ron, Lon , Rs1, Cs1)

(a) Electrical Model (b) MOS Switch electrical equivalent (c) Pwer Switch EFSM Model Figure 5. Modeling of the Power Switch PE

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Vcmp1 Vcmp2 Vcmpn

VMEAVBEA

Main Bus CurrentBattery Bus Current Power cell n

Power cell 2

Power cell 1

+ +

+VMEA Itotal

Ipcn

Ipc2

Ipc1Ipc

2 Ipc

n Ipc

Bus or BatteryComparators

Figure 8. S4R System Power Stage Ladder Model

SwitchLogic

n

Ipcn

Power Cell n

SwitchLogic

n

Ipcn

Power Cell 1

LoadBatteryPI

control

Integrator

VMEA

VBEA

Figure 7. Basic Architecture of a S4R system

A. Functioning of the S4R system The S4R system is an evolution of the more traditional S3R system and was introduced by the ESA in the late

nineties. [4] [5]. It implements a spacecraft payload bus shunt regulator and battery charger architecture operating in a bang-bang control mode [5] [6], where the classical PWM DC/DC converters used as BCR and BDR are substituted by some series regulators. By removing the BCR and BDR and replacing them by series regulators provides some important advantages such as mass reduction, increase of the efficiency of the power converters, etc. Different from a S3R system which has three main control loops, a S4R system has two main control loops: the Main Error Amplifier (“MEA”) for the main bus voltage regulator and the Battery Error Amplifier (“BEA”) for the battery charging regulator. This architecture simplifies the overall design by reducing the number of control loop domains [6]. Similarly to the S3R system, the S4R architecture does not use inductors what is becoming important for SEPS because better yields can he achieved. The bulky storage inductors used in the PWM battery chargers impose a serious limitation to the power/mass coefficient accounting for lower yields. Figure 7 shows the basic architecture of a S4R system.

The S4R system is a sequential switching shunt series regulator. Each of its power cell can drive its associated

Solar Array Section (“SAS”) into three possible positions: i) Supply the SAR current to the main bus; ii) Drive it to charge the batteries; iii) Shunt the SAR current to ground. The main bus voltage is regulated by a PI controller. On the other hand, it has been found that the battery bus

voltage is better regulated by an integrator. Both bang-bang controllers are implemented by hysteretic comparators. The delta of the hysteresis voltages is defined based on mechanical and electrical performances over 1 orbit and the main bus response for the maximum payload of 4kW.

The solar array is composed of an array of individual panels. Each panel handles part of the overall current consumed by the main bus load. Each S4R power cell includes a solar panel and two hysteretic comparators driving a three-state power switch. The hysteretic comparators are driven by the bus error signal and battery error signal controllers. From a dynamic point of view, the bus and battery loops are designed to operate in an inverse sequence. Also, the main bus regulator has higher priority than the battery charge regulator. In the S4R system, the main bus regulator starts with the lower power cells and takes control of upper cells as the payload increases. On the other hand, the battery charge regulator starts with the last power cell and takes control of the underneath cells as required by the battery charging current and those panels are not already taken by the main bus regulator. Therefore, the hysteretic comparators are designed so that the lower end

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of its delta voltage is equal to the upper end of the comparator in the underneath power cell. Therefore, the S4R system can be modeled as a ladder where each power cell is a thread of the ladder as shown in Figure 8. As we can see, this system can operate in two different modes depending on the main bus load and battery charging requirements:

i) The load regime where the main bus and the battery bus are regulated with different solar panels is called the medium load range and it is characterized by the fact that the two control loops are independent.

ii) The load regime where both subsystems, and therefore both control loops, compete for the same panel is called the maximum load range. Further information about the operation of a S4R system can be found in [5], [6] and [7].

B. Matlab/Simulink Simulation of S4R System The model shown in Figure 9 is a 4 power cells S4R system. The power cells detailed schematic including the

switch logic is shown in Figure 10. The value of the model devices are shown in the appendix. These values were used to produce the simulation results shown in Figure 11 to 13. In the model, the ideal switch is used to set to payload requirements. When the ideal switch is open, the load on the main bus is defined by resistor RLoad1 which corresponds to load condition of 12.5% of the main bus maximum total current. By closing the ideal switch, the main bus load is defined by the parallel of RLoad1 and RLoad2 and corresponds to a load condition of 81.25% of its maximum capacity.

The first situation is the medium load range explained in the previous section. It occurs when the power

consumption is low enough so that the main bus and the battery charging regulators use different power cells to regulate their respective bus. In this condition, the switching pattern is a two-position switching that involves commutating between the main or the battery bus and the ground. As we can see in Figure 11, the power cell 1 is switched between servicing the main bus or directed to the ground. The power cell 4 is switched between servicing the battery charger bus or directed to the ground. The remaining power cells are always connected to ground. As explained in the previous section in this load regime both subsystems are considered independent.

The second situation corresponds to the maximum load range. It describes the behavior of the system when the

payload requires a large power consumption and there is no solar panel shunted to the ground. Also, the input power is large enough to supply the loads and to charge the battery. However, there will be dependence between the two control loops in one of the four power cells. In this condition, the new switching pattern is a three-position switching

Main Bus

Battery Bus Main Bus Load

SolarPower Cells

Sequential Switching Shunt Series Regulator - S4R

VBEA Integrator

VMEA PI Controller

Continuous

pow ergui

v +-

Vout

v +-

VRSense

-C-

VPiRefBus

-C-

VIntRefBat

In1

In2

Conn2

Conn1

SolarArray4

In1

In2

Conn2

Conn1

SolarArray3

In1

In2

Conn2

Conn1

SolarArray2

In1

In2

Conn2

Conn1

SolarArray1

Scope1

Scope

RSense

RLoad2RLoad1

PGen

-K-

KpPiBus

-K-

KiPiBus

-K-

KIntBat

-K-

KBus

1s

Integrator1

1s

Integrator

g m

1 2

IdealSwitch

i+ -

IBus1

i+ -

IBus

CBus

Bat36V

Add3

Add1Add

Vout

Verror

VMEA

VMEA

VRSense

VBEA

VBEA

IBat

IBus

Figure 9. Matlab/Simulink Model of the S4R System

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0 0.01 0.02 0.03 0.04 0.050

0.5

1

IBat

s4r1cell - Matlab/SymPowerSystems Simulation

0 0.01 0.02 0.03 0.04 0.050

5

10

VR

Sen

se

0 0.01 0.02 0.03 0.04 0.05

2.83

3.23.43.63.8

VB

EA

time(seconds)

Figure 12. S4R Battery Bus Simulation Results

that involves commutating between the main bus, the battery bus and the ground. Therefore, the two control loops are not independent anymore. Besides, in order to maintain a regulated voltage on the main bus the control strategy should implement loop priorities. When both control loops are demanding the solar section the bus regulation will prevail against battery regulation.

0 0.01 0.02 0.03 0.04 0.05

2

4

6

VM

EA

s4r1cell - Matlab/SymPowerSystems Simulation

0 0.01 0.02 0.03 0.04 0.050

2

4

IBus

0 0.01 0.02 0.03 0.04 0.0549.5

50

50.5

Vou

t

time(seconds)

Figure 11. S4R Main Bus Simulation Results

Power Switch #1

Power Switch #2

Solar Power Cell

Switch Logic

Main BusHystheresis

Battery BusHystheresis

2Conn2

1Conn1

NOT op3

AND

op2

AND

op1

g

ds

M3

g ds

M2

Isar2

D3

D2

Bus_Hist1

Bat_Hist

2In2

1In1

Vthy 1

Figure 10. Solar power cell model with switch logic

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0.021 0.0215 0.022 0.0225 0.023 0.0235 0.024

6

6.5

7

VM

EA

s4r1cell - Matlab/SymPowerSystems Simulation

0.0215 0.022 0.0225 0.023 0.0235 0.024

3

3.5

4IB

us

0.0215 0.022 0.0225 0.023 0.0235 0.024

49.9

50

50.1

Vou

t

time(seconds) Figure 13. S4R Bus error voltage, shunt switch driving signal and busvoltage ripple. 50V bus voltage and 81.25% bus load (3.25A @ 4A maximum)

0.035 0.036 0.037 0.038 0.039 0.0449.8

50

50.2

Vou

t

S4r4CellGenVhdl1b - FPGA simulation @ Ts = 1us

0.035 0.036 0.037 0.038 0.039 0.04

0204060

Vbr

idge

1

0.035 0.036 0.037 0.038 0.039 0.04

0204060

VIp

ane

l

0.035 0.036 0.037 0.038 0.039 0.04

0204060

VB

ridg

e2

0.035 0.036 0.037 0.038 0.039 0.04-1.5

-1-0.5

00.5

Ibrid

ge2

0.035 0.036 0.037 0.038 0.039 0.04-0.5

00.5

11.5

IBus

time(seconds)

Figure 14. S4R Main Bus Simulation Results – Load = 100ohms (Payload of 12.5%)

V. Experimental Results Here we present the simulation results of the simulation of the S4R of section IV using the FPGA real-time

simulator. The simulations were done for two payload scenarios: light load operating condition; and heavy load operating condition. The test environment consists of an AMD XP2400+ microcomputer and a Digilent Inc. XUP Virtex II Pro Development FPGA Card with a 2VP30-7-FF896 Virtex II Pro FPGA. The schematic of the simulation model was generated using Matlab/Simulink. The VHDL simulation and the FPGA synthesis/implementation phases were realized using Modelsim HDL simulator v6.1b from Mentor Graphics and ISE Development System v8.1i from Xilinx respectively.

A. Light Load Operating Condition In order to achieve the required accuracy,

the FPGA real-time simulations were set to use a time step of 1 µs. The light load operating condition corresponds to a system payload of 12.5% of the main bus total capacity. In the case of the S4R system under test each solar cell has a nominal current of 1A. Therefore, the light load condition corresponds to an average output current of 0.5A at a regulated output voltage of 50V.

As shown in Figure 14 the system needs

only one solar array to provide the required power to the load. The other three solar arrays are shunted to the ground. The 1A current driven by the lower solar array is modulated by the bang-bang controller to provide the main bus current IBus. The IBus turn on and turn off time is such that its average value is equal to 0.5A The main bus PI controller regulates the

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0.03 0.035 0.04 0.045 0.0549.5

50

50.5

Vou

t

S4r4CellGenVhdl4b - FPGA simulation @ Ts = 1us

0.03 0.035 0.04 0.045 0.050

5

IBus

time(seconds)Figure 15. S4R Main Bus Simulation Results – Load = 15.38 ohms(Payload of 81.25%)

output voltage Vout in the range 49.85V to 50.1V as shown in Figure 14. In the same figure, VBridge1 and VBridge2 are the voltages on the MOS switch M2 and the diode D2 shown in Figure 10. IBridge2 is the current to the ground across the M2 MOS switch.

B. Heavy Load Operating Condition The light load operating condition has also used a time step of 1 µs. It corresponds to a system payload of

81.25% of the main bus total capacity which is equivalent to an average output current of 3.25A at a regulated output voltage of 50V. As we can see in Figure 15, the three lower solar arrays are continuously connected to the main bus, and the fourth solar array is modulated by the bang-bang controller to generate the average output current required by the system load. The output is regulated by the main bus PI controller to stay in the range specified by the design (from 49.8V to 50.2V). As we can see, the simulation results produced by the FPGA real-time simulator are in agreement with the results generated using Matlab/Simulink presented in section IV and the design specifications presented in [5-9]. These references provide further information about the design specification as well as some additional simulation results.

VI. Conclusion This paper presented the real-time simulation of a S4R SEPS. The S4R system is a topology proposed as a

replacement for the S3R topology, which has been used for many decades as an electrical power system for space applications, mainly in commercial GEO satellites. Interdisciplinary models of power switches and control modules were developed, validated and implemented in VHDL using a model-based methodology.

A Matlab/Simulink model of the S4R system was developed and validated by Simulink simulations. A newly

developed tool, called GenVhdl was then used to translate the Matlab/Simulink model into a reconfigurable computing architecture implemented in VHDL. This VHDL representation can be mapped to an FPGA device using commercial FPGA development tools such as Xilinx ISE. It can be seen from the experimental results that the FPGA simulations produce results comparable to the Matlab/Simulink simulations.

In the near future, we will develop a VHDL model for the solar array and a more detailed model for the battery

system to be added to the FPGA real-time simulator system library.

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% Solar Array parmeter definition NSar = 4; % number of power cells (SAS) MaxISas = 2.0; % maximum value of the power cell current TypISas = 1.0; % typical value of the power cell current ZoMax = 0.25; % Main Bus output impedance % Definition of the Main Bus parameters RLoadMax = 25; % maximum load impedance RLoadMin = 250e-3; % minimum load impedance CBus = 500e-6; % laod capacitance VBus = 50; % bus voltage DeltaVBus = 0.01 * VBus; % bus voltage ripple (set to 1%) LoadFactor1 = 12.5 / 100; % percentage of the total current LoadFactor2 = 81.25 / 100; % percentage of the total current RLoad1 = VBus / (LoadFactor1 * NSar * TypISas); Reqq2 = VBus / (LoadFactor2 * NSar * TypISas); RLoad2 = 1 / ((1 / Reqq2) - (1 / RLoad1)); % Definnition of battery parameters VBat = 3 * 12; % battery voltage BatCap = 62; % battery capacity in Ah IMaxBatCharge = 1.5; % max. battery charging current

% definition of parameters of the Main Bus control loop RaBus = 6.8e+3; % Ra of the Main Bus transducer RbBus = 1.0e+3; % Rb of the Main Bus transducer RabBus = (RaBus*RbBus)/(RaBus+RbBus); % parallel of (RaBus, RbBus)VPiRefBus = 6.41; % reference voltage of the Main Bus PI controller R1PiBus = RabBus+620; % R1 of the Main Bus PI controller R2PiBus = 47e+3; % resistance R2 of the Main Bus PI controller C2PiBus = 3.3e-9; % Capacitance C2 of the Main Bus PI controller VHystRefBus = 6.41; % ref. voltage of the Main Bus hystheresis controller R1HystBus = 1.0e+3; % R1 of the Main Bus hystheretic controller R2HystBus = 30.0e+3; % R2 of the Main Bus hystheretic controller KBus = RbBus/(RaBus+RbBus); % gain of the Main Bus transducer KpPiBus = R2PiBus/R1PiBus; % gain KP of the PI controller KiPiBus = 1.0 / (R1PiBus * C2PiBus); % gain KP of the PI controller VHHystBus = VHystRefBus+(15*(R1HystBus/(R1HystBus+R2HystBus))); VLHystBus = VHystRefBus-(15*(R1HystBus/(R1HystBus+R2HystBus))); VDeltaHystBus = (VHHystBus - VLHystBus); % definition of parameters of the battery control loop VIntRefBat = 0.1; % reference voltage of the battery bus controller R1IntBat = 1.5e+3; % resistance of the battery bus controller C1IntBat = 100e-9; % Capacitance of the battery buscontroller RSense = 12; % feedback sensor on the battery VHystRefBat = 6.41; % ref. voltage of the battery bus hystheresis controllerR1HystBat = 1.0e+3; % R1 of the battery bus hystheretic controller R2HystBat = 27.0e+3; % R2 of the battery bus hystheretic controller KIntBat = 1/(R1IntBat*C1IntBat); % gain KP of the battery bus cont. VHHystBat = VHystRefBat+(15*(R1HystBat/(R1HystBat+R2HystBat))); VLHystBat = VHystRefBat-(15*(R1HystBat/(R1HystBat+R2HystBat))); VDeltaHystBat = (VHHystBat-VLHystBat);

Appendix Here we list the parameter values for devices of the S4R system used in the simulations.

Acknowledgments J. C. G. Pimentel thanks Xilinx Inc. for its support providing the FPGA development software tools and the XUP

Virtex II Pro Development board used for the simulation and the experimental results.

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