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AMICSA 02/09/2008
Philippe AYZAC – THALES ALENIA SPACEJorge GUILHERME – MIPS / CHIPIDEA
Original Co-Design of VASP, a Space Qualified Mixed-Signal ASIC
by Space Industry & Consumer IP provider
AMICSA 02/09/2008
Page 2
AGENDA
HIVAC project to provide a versatile Video Signal Processor : VASP
Selection of a technology for VASP
From hardening guidelines …
… to design hardening (100% CHIPIDEA , 6 slides : report the hardening handling at design level)
Qualifying and quantifying radiation hardness of VASP
Analog intellectual property and reusability of analog circuits in space : conditions for success
AMICSA 02/09/2008
Page 3
HIVAC project
HIVAC project is an ESA co-funded project contract n°19872/06/NL/JA Phase 1 (Specification - Architecture – Feasibility - Technology selection)
07/2006 to 07/2007 Phase 2 (Detailed Design and Tests) :
on-going since 12/2007 Prototypes planned for beginning of 2009 Results planned before end of 2009
This project is based on innovative organization of partnership between: THALES ALENIA SPACE, as prime contractor, is the European leader for
Satellite Systems and since 1993 the company has been designing and developing an important series of space used Mixed-Analog ASICs. THALES ALENIA SPACE is a major actor in the field of camera detection electronics for Earth Observation and Scientific missions.
CHIPIDEA-MIPS Analog Business Group, as design partner, is a world leading analog/mixed-signal intellectual property provider. CHIPIDEA does not have experience in design hardening.
AMICSA 02/09/2008
Page 4
HIVAC project
HIVAC project is aiming at the design, the development and the validation of a high performances video signal processing ASIC namely the Video Acquisition Signal Processor (VASP) and related module (HIVAC) accommodating CCD and CMOS detectors :
CCDdetector
CMOSdetector
CCD biases
Line shiftphase drivers
Output registerphase drivers
Slow clocks
Coresequencer
Phase driversupply regulators
CMOS biases
CMOS clockbuffers
Master clock
VASP
HIVAC MODULE
Supply filters
Space wire I/ fs
Programmingdata
clocks
Digital testpoint
SYNCHROSecondary
power supplies
DC correction /preamplification
CCD video input
CMOS video input
Slow chains
CCDdetector
CMOSdetector
CCD biases
Line shiftphase drivers
Output registerphase drivers
Slow clocks
Coresequencer
Phase driversupply regulators
CMOS biases
CMOS clockbuffers
VASP
HIVAC MODULE
Supply filters
Space wire I/ fs
Programmingdata
clocks
Digital testpoint
SYNCHROSecondary
power supplies
DC correction /preamplification
CCD video input
CMOS video input
Slow chains
ExternalMasterClock
Local Oscillator
analogtelemetries
AMICSA 02/09/2008
Page 5
HIVAC project
VASP design is based on high performances analog block functions for signal conditioning and digital block functions for SpaceWire RMAP signal interfacing :
Video chain ADC
OffsetCorrection &Regulation
MUX3
2
2
4
Config Registers
RMAP ProtocolManagement
VASP
Testpoints
Offsetregulation
clocks
I²C
8
(To/from external sequencer)
Power Supply(GND and 3.3V)
Differential Video inputs(2 channels)
Slow Analog
Linesynchro
clock
PLL
Config data
2
Synchronizationclocks
LOBT
Space WireCodec
2
2Data/ strobe Rx
Data/ strobe Tx
TBD
Load externalsequencernext CONF
2
Pseudo diff Video inputs(1 channel)
FIFO Buffer
I²C link
1 + 16
Videoclock
+data
2
external masterclock
2
(From externalsequencer)
(To externalsequencer)
(From externalsequencer)
DIGITAL BLOCKS
4
video chainclocks
clocks enable
tick_out
time_out
632
3232
32
SEQUENCER
Videomodeenable
2
+ inputs
- input
Slow channel selection2
2
channelselection
TBD Digital test(SCAN, BIST)
VoltagereferencesVoltage references
3
TBD
2 VASP state
Globalreset
Main VASP’s specifications :
Power Supply 3.3V
CCD and CMOS detector compatibility
Pixel frequency 0.1Mhz to 3Mhz
ADC resolution 16 bits
INL < ±1LSB
DNL < ± 0.5LSB
Total noise at unity gain 2 LSB RMS
Programmable gain from 1 to 8
Spacewire Interface @ 100Mbps min
Consumption 350mW typ
Latch-up immunity > 70Mev/mg/cm² LET
TID hardness > 50Krad(Si)
Package is CQFP 164 pins
AMICSA 02/09/2008
Page 6
HIVAC project
Technical challenge due to the high level of VASP required performances : high resolution analog processing + high speed digital on the same chip + space hardened
Organization challenges to share the best know-how from each partner to succeed : video signal processing for space application radiation hardening high performances analog and mixed design
THALES ALENIA SPACE tasks : Requirements for VASP and HIVAC module Technology survey. The final selection is made with agreement of ESA and MIPS /
CHIPIDEA Hardening guidelines and support for implementation Support for radiation characterization HIVAC module design, manufacturing and validation Validation of VASP in the HIVAC module
MIPS / CHIPIDEA tasks : VASP ASIC design : architectural analysis, detailed mixed design Prototypes procurement (MLM foundry foreseen) Electrical Tests and characterization Total Ionization Dose characterization Single Events characterization
AMICSA 02/09/2008
Page 7
Selection of a technology for VASP
No qualified mixed technology is available !
A pragmatic approach agreed with ESA and CHIPIDEA to select the technology for VASP : Identify all accessible technologies : via european MPW centers or known
partners Short list of 7 technologies max to avoid a too wide analysis : european
source, 3.3V power supply, digital density, maturity 6 groups of criterion having there own relative weight Analysis and notation of each short listed technology Final choice in the 3 technologies having the higher notation
AMICSA 02/09/2008
Page 8
Selection of a technology for VASP
Short listed technologies : Mainly CMOS 0.35µm : 0.35µm are very mature technologies used for
commercial growing markets such as medical and new generation automotive. The perenniality is high because 0.35µm appears to be the CMOS basic standard for High Voltage compatible technologies (smart power, smart sensors, etc…). Finally, because widely available, it guarantees a probable good level of portability of the design.
MPW Center Manufacturer Technology name Description AMI Semiconductor C035M CMOS 0.35µm
EUROPRACTICE AMI Semiconductor I3T80 CMOS 0.35µm High Voltage EUROPRACTICE and CHIPIDEA
UMC 1P5M CMOS 0.25µm, thick gate oxide 3.3V (short listed even if CHIPIDEA has an outdated design kit and experienced difficulties with an old design kit)
AMS S35D4M5 BiCMOS SiGe 0.35µm EUROPRACTICE and CMP AMS H35B4D3 CMOS 0.35µm High Voltage + thick M4
+ 2 poly CMP ST Microelectronics BICMOS6G BiCMOS SiGe 0. 35µm PARTNER XFAB XH035 CMOS 0.35µm High Voltage
AMICSA 02/09/2008
Page 9
Selection of a technology for VASP
Selection criterion : Accessibility :
Foundry nationality, Process perenniality, Low volume production access Low cost prototyping :
Prototyping foundry type (MPW, MLM), Number of MPW runs / year, Delay for prototypes delivery, Prototyping costs (based on a VASP figure)
High-reliability Low volume production and Qualification : Available back-end resources, Low volume silicon production and qualification
costs (based on a VASP figure) Technical Characteristics :
Process characteristics versus radiation (EPI substrate, retrograde wells, buried layer, salicidation, substrate isolation option, oxides thickness), temperature range, simulation models temperature range, electrical performances of MOS, RES, CAP, digital integration
Radiation environment Existing radiation characterization (TID, SEL and SEU)
Design Kit and models Compatibility with CHIIDEA and THALES’s EDA flow (analog, digital and mixed) Availability of enough accurate models for MOS (BSIM3, MM9) for fine analog
simulation
AMICSA 02/09/2008
Page 10
Selection of a technology for VASP
3 technologies having the higher notation : 1/3
STM BICMOS6G : This technology is very mature and perennial : STM doubled the
production in 2007. STM provides prototyping with MLM (no MPW available directly with STM).
STM BICMOS6G could be the best guarantee for space environment withstanding and HR back-end. STM proposes (with charge) a process improvement that allows to shift TID from 100krad to 300krad for digital.
STM BICMOS6G cannot be selected as baseline for VASP regarding MPW run stop on 2008 (through CMP) and higher costs for low volume production.
Even if it involves higher costs, direct foundry and back-end via STM allow risk sharing (i.e. in case of quality problem on wafer or during back-end).
AMICSA 02/09/2008
Page 11
Selection of a technology for VASP
3 technologies having the higher notation : 2/3
XFAB XH035 : This high voltage technology offers a wide range of potential application,
including a good compatibility to handle obsolescence of 5V analog ASIC (i.e. availability of 5V mos, vertical PNP and vertical isolated NPN).
Direct access to XFAB or via partners offers suitable flexibility (MPW (4 runs/year, MLM) even if not accessible via MPW centers. The MLM at reasonable cost could be very interesting regarding schedule constraints.
The availability of the design kit in most popular tools environment (CADENCE, MENTOR, TANNER, SYNOPSYS models) allows a wide range of cooperation with university, laboratory, small company, etc…
Low cost MPW access is available with XFAB but cannot be used several times if no volume is ordered (min 24 wafers) : it is clear that XFAB do not want to make business with only MPW or MLM. However, a scheme as 1 or 2 MPW + one lot of 24 wafers for FM production could be acceptable (no commitment for lot foundry is required to access MPW or MLM run).
AMICSA 02/09/2008
Page 12
Selection of a technology for VASP
3 technologies having the higher notation : 3/3
AMIS I3T80 : The technical choice of AMIS I3T80 by SODERN for SPADA in a
previous project (cf AMICSA 2006) confirms that 0.35µm CMOS is a good technological target. The DK developed for TANNER by SODERN is not yet available (distribution via EUROPRACTICE under analysis) and it does not cover the digital cells.
Furthermore, for a complex mixed design as VASP, TANNER cannot be considered as a suitable verification and extraction tool regarding the other widely used tools (CALIBRE, ASSURA)
I3T80 does not provide HSPICE analog models. Due to its incompatibility with CHIPIDEA’s tools (cf HSPICE), AMIS I3T80 is
not proposed as a backup technology.
AMICSA 02/09/2008
Page 13
Selection of a technology for VASP
Final choice :
BASELINE BACKUP Technology XFAB XH035 STM BICMOS6G
STM BICMOS6G : From a technical point of view, taking into account all available information,
BiCMOS6G is the only one technology fulfilling all space application need (environment withstanding and HR backend). However, BiCMOS6G cannot be selected as baseline technology in the frame of VASP/HIVAC contract because of costs and perenniality of MPW access through CMP.
XFAB XH035 : By making the best trade-off between cost, technical characteristics,
technology and access perenniality, risk regarding space environment withstanding, XFAB XH035 is selected to be the baseline for VASP design.
AMICSA 02/09/2008
Page 14
From hardening guidelines …
Hardening approach : The technology for VASP design (XFAB XH035) has not been fully qualified for space
environment (only total dose tested up to 107krad on an analog design). So the effective withstanding of a complex mixed design can not be guaranteed.
So, “à priori” hardening by design techniques shall be used to minimize as much as possible the risk on space environment withstanding.
THALES ALENIA SPACE provided to CHIPIDEA hardening guidelines covering the following aspects, at several levels : design kit configuration/adaptation, architecture, cells design, layout, elementary cells:
Description of Radiation Effects : charge accumulation in oxide, single events Hardening at digital design level Hardening at analog design level Hardening example (a band-gap and its AOP) Radiation testing : TID, SE following ESCC 9000 standard
THALES ALENIA SPACE provided to CHIPIDEA Design Kit adaptation (and its related user manual) to handle ELT MOS : layout example (ELT MOS, inter-digitized differential pair and mirror), EXTRACTION and LVS rules, representative simulation models.
THALES ALENIA SPACE provides support to CHIPIDEA during the overall project : at architecture, design, simulation and layout levels, electrical test, TID test, SE test.
AMICSA 02/09/2008
Page 15
From hardening guidelines …
Hardening at digital design level : TID : use of the standard cells, excluding all gates having more than 3 serial MOS SEL : the junction isolated standard cells library (low noise) is selected because
providing a possible intrinsic SEL immunity. IOs layout will be improved. SEU : FSM implementation, TMR, EADC for RAM SET : 0.35µm technology is considered SET insensitive A set of standard cells are forbidden : internal tri-state, flip-flop without reset, etc… Floor plan : insert guard rings with highest contact density
Hardening at analog design level : hardening from architectures trade-off to layout TID and ELDRS in bipolar SET : limited bandwidth, switched capacitor design, saturation recovery TID in MOS : design margins to reduce VT drift impact, ELT MOS to suppress bird-
beak effect Forbidden analog cells : lateral bipolar transistors, P+ diffusion resistors Layout : systematic use of ELT MOS, systematic guard ring strategy
AMICSA 02/09/2008
Page 16
From hardening guidelines …
Hardening example : a band-gap designed by CHIPIDEA has been hardened by THALES ALENIA SPACE at beginning of design phase to be used as « good practice » design example hardening by design does not disturb performances
Band-gap voltage = f(temperature)
Hardened Band-Gap
Original Band-Gap
Band-gap voltage = f(power-supply (3.3V ±5%))
Hardened Band-Gap
Original Band-Gap
AMICSA 02/09/2008
Page 17
… to design hardening
Design Kit adaptation to handle ELT MOS : Layout : development of a parameterized PCELL following THALES example Layout example for inter-digitized differential pair and mirror, EXTRACTION and LVS rules, Representative simulation models, User manual
Encountered difficulties with design-kit : Some pcell bugs in the design-kit : DMIM capacitor, Hrpoly resistor Design kit frequently updated (3 times / year) :
Requires analysis to decide to follow or not : is the used subset of cells impacted ?
Requires update of rules files (integration of ELT MOS) : difficult process to get the source files from XFAB (only compiled rules delivered in design-kit)
• We decided to stick during the whole project to the version 3.0.5, issued in November 2007
AMICSA 02/09/2008
Page 18
… to design hardening
Analog Design Hardening Constrains: ELT MOS
Limits minimum W/L of transistors Increases charge injection due to non-minimum devices To limit charge injection non-minimum capacitors had to be used in
switched capacitor circuits Non symmetrical device requires careful circuit orientation, and
provides one low parasitic capacitance node (the internal one) that can ease design performances
Increases area Increases consumption
Minimum branch current in a device Increase power due to higher parasitic capacitance Increases area to keep ELT MOS with minimum overdrive voltage
Vt voltage drifts : Biasing, gain, GBW margins Drive Comparators architecture choice and operating
AMICSA 02/09/2008
Page 19
Analog Design Hardening Constrains:
Layout Increases area : guard rings, minimum number of contacts (reliability) Design kit adaptation for hardening only available with Diva rules :
• DRC and LVS of top layout done with macro blocks
• No extraction rules for RCX, only parasitic capacitance
AMICSA 02/09/2008
Page 20
Digital Design Hardening Constrains:
TMR insertion in registers, EDAC on RAM blocks FSM encoding, avoid blocking states Automated process to ensure a reproductible process for synthesis, TMR
insertion, timings extraction and place&route TMR increases area and power Increases delay in data signals, more load on clock tree Low noise Standard cell choice limits maximum clock frequency in
Space Wire (100Mbps)
As a consequence at VASP chip level : Estimated device area is high : 85 mm2 Power consumption target can not be reached. Space Wire data rate is limited at 100Mbps
AMICSA 02/09/2008
Page 21
Qualifying VASP
Qualification according to ESCC Generic Specification No. 9000 (1/6) Chart F 1 - General Flow chart for VASP ASIC procurement
Special in-process Controls
Production Control
Wafer Lot Acceptance(VASP F2)
EWS @ room temperature(VASP F2)
Screening Tests(VASP F3)
Qualification TestSubgroups 1, 2 & 3
(VASP F4 )Lot Validation Testing
Deliverable Components(Encapsulated form)
Die Assembly(VASP F2)
Encapsulation(VASP F2)
Color code
Xfab
Die inspection partner
Packing partner
EWS partner
Screening partner
Qualification partner
VASP could be delivered as qualified packaged component or naked dice
AMICSA 02/09/2008
Page 22
Qualifying VASP
Qualification according to ESCC Generic Specification No. 9000 (2/6) Chart F 2 - Production Control
Wafer Lot acceptance
EWS @ room Temperature
Special in process Control
Encapsulation
EWS at room temperature
Wafer Sawing
Dice visual insp.
Documentation
Internal Visual Inspection (Pre-encapsulation Inspection)
Bond Strength (Pre-encapsulation Inspection)
Die Shear (Pre-encapsulation Inspection)
Die assembly
Bonding
Documentation
Dimension Check
Weight
Documentation
Seal test
Marking
Process Monitoring Review
SEM Inspection
Documentation
Mask making
Circuit Wafer processing
Components Lot Manufacturing
Color code
Xfab
Die inspection partner
Packing partner
EWS partner
Screening partner
Not applicable
Qualification partner
Cover sealing
Wafer Lot acceptance
EWS @ room Temperature
Special in process Control
Encapsulation
EWS at room temperature
Wafer Sawing
Dice visual insp.
Documentation
Internal Visual Inspection (Pre-encapsulation Inspection)
Bond Strength (Pre-encapsulation Inspection)
Die Shear (Pre-encapsulation Inspection)
Die assembly
Bonding
Documentation
Dimension Check
Weight
Documentation
Seal test
Marking
Process Monitoring Review
SEM Inspection
Documentation
Mask making
Circuit Wafer processing
Components Lot Manufacturing
Color code
Xfab
Die inspection partner
Packing partner
EWS partner
Screening partner
Not applicable
Qualification partner
Cover sealing
Wafer Lot acceptance
EWS @ room Temperature
Special in process Control
Encapsulation
EWS at room temperature
Wafer Sawing
Dice visual insp.
Documentation
Internal Visual Inspection (Pre-encapsulation Inspection)
Bond Strength (Pre-encapsulation Inspection)
Die Shear (Pre-encapsulation Inspection)
Die assembly
Bonding
Documentation
Dimension Check
Weight
Documentation
Seal test
Marking
Process Monitoring Review
SEM Inspection
Documentation
Mask making
Circuit Wafer processing
Components Lot Manufacturing
Color code
Xfab
Die inspection partner
Packing partner
EWS partner
Screening partner
Not applicable
Qualification partner
Cover sealing
AMICSA 02/09/2008
Page 23
Qualifying VASP
Qualification according to ESCC Generic Specification No. 9000 (3/6) Chart F 3 - Screening Tests
Electrical measurements
Mechanical tests
High Temperature Stabilisation Bake
Temperature Cycling
Particle Impact Noise Detection (PIND)
Parameter Drift Values (Initial Measurements)
Power Burn-in
Parameter Drift Values (Final Measurements)
High and Low Temperatures Electrical Measurements
Room Temperature Electrical Measurements
Check for Lot Failure
Seal (Fine and Gross Leak)
External Visual Inspection
Solderability
VASP F3 – Screening Tests
Components From Production Control
Components from production control
Color code
Xfab
Die inspection partner
Packing partner
EWS partner
Screening partner
Qualification partner
Electrical measurements
Mechanical tests
High Temperature Stabilisation Bake
Temperature Cycling
Particle Impact Noise Detection (PIND)
Parameter Drift Values (Initial Measurements)
Power Burn-in
Parameter Drift Values (Final Measurements)
High and Low Temperatures Electrical Measurements
Room Temperature Electrical Measurements
Check for Lot Failure
Seal (Fine and Gross Leak)
External Visual Inspection
Solderability
VASP F3 – Screening Tests
Components From Production Control
Components from production control
Color code
Xfab
Die inspection partner
Packing partner
EWS partner
Screening partner
Qualification partner
AMICSA 02/09/2008
Page 24
Qualifying VASP
Qualification according to ESCC Generic Specification No. 9000 (4/6) Chart F 4 - Qualification and Periodic Tests
Mechanical Shock
Vibration
Constant Acceleration
Seal
Intermediate and End-Point Electrical Measurements
External Visual Inspection
VASP F4a – Subgroup 1 - Environmental/Mechanical
Thermal Shock
Moisture Resistance
Constant Acceleration
Seal
Intermediate and End-Point Electrical Measurements
External Visual Inspection
VASP F4b – Subgroup 1 - Environmental/Mechanical
Components Terminal Strength
Internal Visual Inspection
Bond Strength
Die Shear
VASP F4d – Subgroup 3 - Assembly/Capability
Components Operating Life 2000 Hours
Seal
Intermediate and End-Point Electrical Measurements
External Visual Inspection
VASP F4c – Subgroup 2 - Endurance
Permanence of Marking
50 componens
Color code
Xfab
Die inspection partner
Packing partner
EWS partner
Screening partner
Not applicable
Qualification partner
AMICSA 02/09/2008
Page 25
Qualifying VASP
Qualification according to ESCC Generic Specification No. 9000 (5/6) Chart 5 - Flow Chart for Radiation (TID) Qualification and Lot Acceptance Testing
Serialize radiation test samples
Electrical test @ RT
Irradiation @ specified dose rate
Electrical test @ RT
RT Anneal Under Bias24h
pass
fail
Multipleexposures
Accelerated Ageing Under Bias
168h @ 100ºC
Electrical test @ RT
pass
fail
Reject lot
Reject lot
Accept lot
Initial electrical test (low and High temperature)
Burn-in
If screening (chartF3) already
performed
At low dose rate : 36 rad(Si)/h < dose rate < 360 rad(Si)/h
1 reference + 10 samples : 5 biased 5 not biased (all IOs connected together
to GND)
AMICSA 02/09/2008
Page 26
Qualifying VASP
Qualification according to ESCC Generic Specification No. 9000 (6/6) Chart 6 - Flow Chart for Radiation (SEE) Qualification and Lot Acceptance Testing
Serialise radiation test sample
Electrical test @ RT
Heavy Ions exposure (~ 5 at diferent LET or energy)
DUT
SEE : SEU characterisation SEL immunity (LET 70 MeV/mg/cm2)Electrical tests @ RT
pass
failReject lot
Accept lot
Initial electrical test (low and High temperature)
Burn-in
If screening (chart F3) already
performed
ESA will give access to one of their SEE radiation test facilities (HIF in Belgium preferably, or RADEF in Finland).
SEU test will allow to characterize the behavior with and without hardening.
The latchup immunity of VASP shall be tested up to a LET of 70 MeV/mg/cm² (use 37° tilt with Xenon) .
AMICSA 02/09/2008
Page 27
Analog intellectual property & reusability
Such partnership is based on the unavoidable sharing of know-how : video signal processing for space application radiation hardening from architecture down to basic cells high performances analog and mixed design (analog front-end, 16 bits ADC, complex
digital)
… but shall protect the intellectual property of each contributor. The main
critical points are : Find a good balance in know-how sharing : win-win approach Design result remains the CHIPIDEA’s intellectual property or need specific contract
negotiation Accommodate the difference in business models between leader for Satellite Systems
and a world's leading analog/mixed-signal intellectual property provider
Efficient reusability for analog blocks requires : the stability in technology choice. A versatile and perennial 0.35µm CMOS as XFAB
XH035 appears to be able to cover larger requirements than VASP, thanks to the available options : 5V compatibility, RAM, high voltage.
Design Kit availability, configuration and stability a long term access to IP blocks
AMICSA 02/09/2008
Page 28
End
Thank you for your attention
See you at AMICSA 2010 with test results …
Philippe AYZAC – THALES ALENIA SPACE
Jorge GUILHERME – MIPS / CHIPIDEA