Amkor keynote Bring 3D Integration to packaging mainstream - Amkor Keynote - Lee.pdf · Bringing 3D...

Enabling aMicroelectronic

World®

Bringing 3D Integration to

Packaging Mainstream

Bringing 3D Integration to

Packaging Mainstream

World®

MEPTEC Nov__ 2012Choon Lee Technology HQ, Amkor

TSMC reveals plan for 3DIC design based on silicon interposer & TSV(Jun 8th 2010)

Elpida, PTI & UMC to partner for 3DIC commercialization of logic+DRAM stack with 28nm by 2011(Jun 23rd 2010)

Xilinx brings 3D TSV interconnects to commercialization phase in digital FPGA world (Oct 27th 2010)

3DIC memory with wide I/O interface is coming by 2013, says NOKIA (Sep 17th 2010)

Micron reveals “Hyper Memory Cube” 3DIC technology (Feb 18th 2011)

Samsung wide I/O memory for mobile products – A deeper look (Feb 28th 2011)

Highlighted TSV in Packaging

© 2011 Amkor Technology, Inc. Amkor Information for Controlled Release at MEPTEC 2

Samsung wide I/O memory for mobile products – A deeper look (Feb 28th 2011)

Micron, Samsung Form 3-D Memory Consortium, HMCC (Oct 6th 2011)

TSV

Vias “First”

Vias drilled in bare SiVias filled with Poly-Si

Possible via resistance issues

Front-End FAB Process

Vias “Early/Middle”

W-CVD orCu plated

Front-End FAB Process

Vias “Last” – Back Side

OSAT Process

3D IC Technology

© 2011 Amkor Technology, Inc. Amkor Information for Controlled Release at MEPTEC

Active Interposer

Passive Interposer

Passive Interposersubstrate

3

2.5D Interposer TSV


2.5D Interposer TSV

4

Interposer Benefit


Source : ITRI

Si Interposer Technology


Si Interposer AttributesDesign Rule

Oxide

Via 1

Via 2

Via 3

Ni – Au Pads

M1

M2

M3

M4

1µm M1

Also oxide layers

Nitride termination layer with patterned openings to Top Metal


to Si Spacing

Feature Spec Note

TSV Size 10 µm dia.

TSV Depth 100 µm

Metal 1 1 µm L / S /Th

Metal 2 & 3 2 µm L / S /Th

Metal 4 4 µm L / S /Th

Metal to Metal 1-2 µm spacing

Via 1-2 µm dia.

7

Interposers Increase Logic Capacity while Reducing Power

- Higher yields

- Over 2X FPGA capacity advantage

- 50% power reduction from 40nm

FPGAs

- 5X reduction in latency

- 100X improvement in inter-die

Si Interposer Applications - FPGA


From GSA Memory Conference, 2011…

- 100X improvement in inter-die

bandwidth/watt

- Passive silicon interposer

: Minimizes heat flux issues

: 20X denser wire pitch

: Utilizes 65 nm technology

8

• Very high memory bandwidth (>1 Tb/sec)

• Used for high performance server and super computer

Organic substrate

4 memory die

Heat spreader TIM

Logic die

200um bump pitch

Si Interposer Applications – Active


substrate

1000um bump pitch

Si TSV Interposer RF Module

Si Interposer as substrate – RF Module


Si Interposer Substrate : ‘A Si Interposer BGA PKG with Cu-filled TSV and Multi layer Cu Plating Interconnect’, Kouichi Kumagai et al, 2008 ECTC


3D Interposer Wafer Forecast by Application


Source : Yole, 2010

Interposer Supply Chain – Logistics

Wafer Finish –Can be at eitherFoundry or OSAT


Business Concerns :• Ownership of TSV related failures• Cost• Agreed to metric for good known good Wfr

Technical Concerns :• BOM Compatibility

� Same bump metallurgies� Same passivation materials

• Thin wafer handling / shipping

13

TSV RDL Bumping Packaging Test

Who Is Doing What?


Source : Yole, 2010

Alternative: Organic Interposer Through via by laser drilling or mechanical punchingOrganic core with 5ppm/k CTE

Core thickness: 60~300um available


Source : Samsung Electro-Mechanics

3D Device TSV


3D Device TSV

16


solder ball

Cu pillar bump

TSV

EMC

Substrate

NCP 1Logic die

Memory die

NCP 0

Cu pillar bump

TIM Heat spreader

Mobile Applications


solder ball

Wide I/O memory die ( ~1200ubumps, no TSV) 28nm (Cu pillar, 10um dia. TSV)Substrate (14 x 14 /12 x 12 mm) Die 2 Substrate interconnection : TCNCPDie 2 Die interconnection : TCNCP Heat spreader attach (exposed die molding) :optional

EMC

Substrate

Memory Applications


• DDR3 4Gb DIMM (1.066GHz) for server application is around $250

• DDR3 4Gb for PC is around $20

Process Flow – Memory Stacking


NCP dispensing and TC bonding 1 TC bonding 2, 3 and 4

MoldSolder ball attach

20

Process flow – Frontside bumping & thinning


TSV WaferFront Side BumpEdge TrimmingCarrier wafer

Adhesive CoatingBondingWafer Back grinding

21

Process flow – backside processing


Si EtchingPolymer Coating

TSV OpeningBack side Pad

22

Process flow – Carrier debonding


Carrier Slide OffAdhesive Cleaning

Film FrameFilm Frame Mounting

23

Application Driver Status Barrier

Image sensorsPerformance,Form factor

Production None

CPUs + memory Performance16nm Si node or beyond

Cost, process, yield, infrastructure

Cost, process, yield,

Key to 3D commercialization is a cost/performance ratio!

3D TSV Applications


GPUs + memory Performance 2014Cost, process, yield, infrastructure

FPGAs Performance 2014Cost, process, yield, infrastructure

Wide I/O memory with processor

Performance (bandwidth extension, lower power consumption),Form factor

2012~13

Cost, process, yield, KGD, infrastructure (including business logistics)

Memory (stacked)Performance,Form factor (z-height)

2012Cost, process, yield, assembly

Source : TechSearch, 2011

Technical issues


Technical issues

25

TSV Technical Issues in Packaging - 1 Wafer thinning and handling system

- Misaligned bonding (device to carrier)

- TSV Cu smearing & Non exposed TSV

- Cu contamination

- Device wafer crack: low mechanical properties

- Total Thickness control

Cu smearing

TTV controlTTV controlTTV controlTTV control


- Debonding without damage

- WSS Adhesive delaminationInterface Interface Interface Interface delaminationdelaminationdelaminationdelamination

Thin die Thin die Thin die Thin die HandlingHandlingHandlingHandlingCrackCrackCrackCrack

TSV Technical Issues in Packaging - 2 Backside of TSV wafer processing

- Non uniform TSV tip height (= non uniform Si recess etch)

- Most Appropriate Backside Passivation per options

- Si-Etching, Incomplete TSV exposure and surface uniformity

- Top/Bottom stress balancing for best warpage control

- Backside Inspection


TSV Technical Issues in Packaging - 3 Microbumping

- Microbump height uniformity

- Small CD passivation pattern opening

- 3D inspection, AOI difficulty

Thin wafer handling and shipping


Thin wafer handling and shipping

- Broken or cracked wafer

- Adhesive residue on the wafer front-side

- Incoming Inspection and cleaning

Assembly Assembly Assembly Assembly accuracyaccuracyaccuracyaccuracy

TSV Technical Issues in Packaging - 4 3D stacking and packaging

- Thin (and large) die pick up issue - cracking

- Adhesive overflow

- u-bump misalign

- Warpage control for both single dies and as stacked dies

- High throughput Reliable TC bonding


- Particle Control from inspection, testing to bonding

TSV Chip to Substrate Bonding by TCNCP


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