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Amplifier Design Tutorial

Introduction

This tutorial will set out the design stages required to design a theoretical microwave amplifierwith the following specification shown in Table 1:

Table 1 Required Specification

Parameter Units

Frequency 1.45 1.55 GHz

Gain 12.5 0.2 dBNoise Figure 2.0 dBOutput VSWR 1:1.5 (>13dB)Gain ripple < 1.5 dB

The first stage in the design process is to pick a suitable device. For X-Band and above GaAsMESFETS are used while at lower frequencies Bipolar devices are used if noise is not socritical. Try to pick a device design for the range of frequencies you require. Dont for exampleuse an X-band device for an LNA at UHF you are bound to run into stability problems. Alsopick a device that will give you plenty of gain margin to allow for noise mismatching etc.

For this design an Agilent AT41435 Bipolar transistor has been used. This device has > 14dBof gain at 2GHz with an associated noise figure of 1.

The ADS simulation shown in Figure 1has been setup to calculate K factor and plotminimum noise figure.

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StabFactStabFact1

StabFact1=stab_fact(S)

StabFactTerm

Term2

Z=50 Ohm

Num=2

sp_hp_AT-41435_1_19921201

SNP1

Noise Frequency="{0.10 - 4.00} GHz"

Frequency="{0.10 - 6.00} GHz"

Bias="Bjt: Vce=8V Ic=10mA"

S_Param

SP1

CalcNoise=yes

Step=

Stop=2.0 GHz

Start=1.0 GHz

S-PARAMETERS

TermTerm1

Z=50 Ohm

Num=1

Figure 1 ADS simulation to calculate K and minimum noise figure. The resistor-capacitor combination connected between the gate and source are to ensure that thedevice is unconditionally stable at 1.5GHz.

m1freq=1.526GHz

nf(2)=1.589

1.0 1.2 1.4 1.6 1.8 2.01.2

1.4

1.6

1.8

2.0

freq, GHz

nf(2) m1

freq1.000GHz1.053GHz1.105GHz

1.158GHz1.211GHz1.263GHz1.316GHz1.368GHz1.421GHz1.474GHz1.526GHz1.579GHz1.632GHz1.684GHz1.737GHz1.789GHz1.842GHz1.895GHz1.947GHz

StabFact10.9440.9500.958

0.9680.9800.9951.0121.0321.0561.0831.0971.0971.0981.1001.1041.1101.1161.1241.134

Figure 2 Results from the simulation shown in Figure 1, showing a K factor >= 1 at1.4GHz and a minimum noise figure of 1.65dB at our highest frequency of 1.6GHz.

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General Amplifier Design Procedure

Now that we have picked our device, stabilised it and checked its maximum available gain we

can begin the process of designing the LNA. This process consists of the following steps:-

(1) Evaluate the Rolletts stability factor to identify the possibility of instabilities depending onsource and load matching.

(2) Determine Bias conditions and circuit.

(3) If a specified gain is required at a single frequency then the gain circles can be plotted ona Smith chart and the associated source match can be read off and the corresponding loadmatch calculated. Careful consideration must be taken to the position of the source match inrelation to the stability circles.

(4) If a specified noise figure and gain at a frequency is required then the noise circles need to

be added to the gain circles from (ii). The source match required will be the intersection of therequired gain & noise circles. Again careful consideration must be given to the position of thesource match in relation to the stability circles.

(5) Once the required source impedance has been chosen the corresponding output matchrequired for best return loss can be calculated.

Gain & Noise Parameters

Using the S-parameters of the device it is possible to calculate the overall transducer gainwhich consists of three parts, the gain factor of the input (source) matching network, theactive device and the output (load) matching network:-

2

22

L

2

o

2

11

s

Los10

2

22

2

L

2

o

2

2

s

S1

1G

21G

S1

1G

-:followingthetosimplifiedbecan

equationsabovethedevice)stablea(and0=S12wherecaseunilateraltheFor

)G.G.G(10LOG=gainTransducerOverall

.1

1G

21G

.1

1G

=

=

=

=

=

=

S

S

S

L

s

sin

s

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For rough estimate of the maximum gain available we can assume that S12 = 0 therefore at1.5GHz (Assuming a bias of 8V @ 10mA) the estimated gain is:-

1.14dB=1.29=0.48-1

1=

S1

1G

13.31dB=21.43=4.63=S=G

0.68dB=1.17=0.38-1

1=

S1

1G

22

22

L

22

21o

22

11

s

=

=

Total available gain = 0.68 + 13.31 + 1.14 = 15.13dB

Constant Gain circles

G.D1

G.S.S+G.S.S2K-1pcirclegainofRadius

G.D1

*G.C=rcirclegainofLocation

S

dB)innotie(absolutedesiredGain=G=Gain

*SSC

SD

2

22

21122112

o

2

2o

2

21

11222

22

222

+=

+

=

=

Note the 0dB gain circle will always pass through the centre of the Smith chart.

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Constant Noise circles

Formula for calculation of noise circles:-

( )

1+N

-1+NN=iscirclefigurenoisetheofradiustheand

1N=circlefigurenoiseofCentre

noiseoptimumachievetotcoefficienReflection=

transistorofresistancenoiseEquivalent=R

)10=factor(noisefigurenoiseOptimumF

)10=factor(noisefigurenoiserequired=FWhere

1

Zo

4R

F-F=N

2

N

10

dBNF

min

10

NFdB

2

N

min

min

opt

opt

opt

opt

+

=

+

The values of Fmin, RN and opt are given in the manufacturers data sheet.

However remember that that the parallel feedback resistor will now have modified the devicenoise parameters.

Calculating these circles by hand is luckily not required these days, as this can beperformed using the CAD simulator but before we progress to gain & noise we need tocheck on the stability of the device.Refer to the stability tutorial for a discussion of stability circles etc.

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Specifically we need to find the no-go matching zones that may cause the circuit to oscillate ifwe place these matches to the device. Again this is best performed using the CAD the ADSsimulation shown in Figure 3 has the basic FET device with stability circle simulation boxes.

S_StabCircle

S_StabCircle1

S_StabCircle1=s_stab_circle(S,51)

SStabCircle

S_Param

SP1

CalcNoise=yes

Step=

Stop=2.0 GHz

Start=1.0 GHz

S-PARAMETERS

TermTerm2

Z=50 Ohm

Num=2

sp_hp_AT-41435_1_19921201

SNP1

Noise Frequency="{0.10 - 4.00} GHz"

Frequency="{0.10 - 6.00} GHz"

Bias="Bjt: Vce=8V Ic=10mA"

Term

Term1

Z=50 Ohm

Num=1

Figure 3 ADS setup to simulate the Agilent AT41435 using a S-parameter simulator andoutput the input stability circles.

The results from the ADS simulation (Figure 3) shows that the device is conditionally stableas the stability circles clip the edge of the smith chart so that there is a possibility of instability,if a match is placed on the device source with an impedance within the area of the smith chartcovered by the stability circle (as shown by the shaded area).

_ a rc e = . .freq=1.315789GHzimpedance = Z0 * (-0.004 + j0.004)

indep(S_StabCircle1) (0.000 to 51.000)

S_St

abCircle1

m1

Figure 4 Result of the circuit simulation showing the input stability circles. The stability

circles are outside the smith chart so that for any match applied to the device, thedevice will be unconditionally stable.

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We can now plot the gain circles and noise circles. The idea is to choose a matching point onthe 10dB source and load constant gain circles and ensure the input matching point is eitheron the 2dB noise circle or within it.

To perform the simulation we need to add the gain mismatch and noise mismatch simulatorboxes, note too that the noise feature has been switched on in the S-parameter simulator box.The simulation is shown inFigure 5.

S_Param

SP1

CalcNoise=yes

Stop=3.5 GHz

Start=0.5 GHz

S-PARAMETERS

sp_hp_AT-41435_1_19921201

SNP1

Noise Frequency="{0.10 - 4.00} GHz"

Frequency="{0.10 - 6.00} GHz"

Bias="Bjt: Vce=8V Ic=10mA"

SmZ1

smz1

smz_in=sm_z1(S,PortZ1)

smz_out=sm_z2(S,PortZ2)

EqnMeas

SmGamma2

smg2

match_output=sm_gamma2(S)

EqnMeas

SmGamma1

smg1

match_input=sm_gamma1(S)

EqnMeas

Term

Term2

Z=50 Ohm

Num=2

TermTerm1

Z=50 Ohm

Num=1

Figure 5 ADS simulation showing the modified S-parameter simulation box set toinclude noise. The other measurement boxes are:

SmGamma1 which, returns the simultaneous-match input-reflection coefficient.SmGamma2 which, returns the simultaneous-match output-reflection coefficient.Sm_z1 which, returns the simultaneous-match input impedance.

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Eqn num_NFcircles=4

Eqn NFstep_size=.1

Eqn Noise_circles=ns_circle(NFmin[m2]+NFstep_size*[0::num_NFcircles],NFmin[m2],Sopt[m2],Rn[m2]/50,51)

Eqn GAstep_size=1

Eqn GAcircles=ga_circle(S[m2],max_gain(S[m2])-GAstep_size*[0::num_GAcircles])

Eqn GAcircleMax=ga_circle(S[m2],max_gain(S[m2]))

Eqn num_GAcircles=6

Eqn Noise_circleMin=ns_circle(NFmin[m2],NFmin[m2],Sopt[m2],Rn[m2]/50,51)

Set step sizes andnumber of circles, here.

m1indep(m1)=4GAcircles=0.337 / 48.137gain=12.759112

impedance = Z0 * (1.335 + j0.75

m3indep(m3)=3Noise_circles=0.399 / 4 2.894ns figure=1.900000

impedance = Z0 * (1.463 + j0.94

indep(GAcircleMax) ( 0.000 to 51.000)

ax

GAcircleM

cir_pts (0.000 to 51.000)

GAcircles

m1

indep(Noise_circleMin) (0.000 to 51.000)

Noise_

circleMin

Noise_

circles

m3

m2indep(m2)=1500000000.000vs([0::sweep_size(freq)-1],freq)=33.00

400.M

600.M

800.M

1.00G

1.20G

1.40G

1.60G

1.80G

2.00G

2.20G

2.40G

2.60G

2.80G

3.00G

3.20G

3.40G

3.60G

0

20

40

60

80

100

freq, Hz

[0::sweep_

size(freq)-1]

m2

RF Frequency Selector

Figure 6 Data display setup to plot gain and noise circles. The slider m2 on the

frequency selector can be moved to display the noise and gain circles at otherfrequencies.

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m1indep(m1)=4

GAcircles=0.337 / 48.137gain=12.759112impedance = Z0 * (1.335 + j0.755)

m3indep(m3)=45

Noise_circles=0.252 / -30.384ns figure=1.900000impedance = Z0 * (1.490 - j0.406)

indep(GAcircleMax) (0.000 to 51.000)

GAcircleMax

cir_pts (0.000 to 51.000)

GAcircles

m1

indep(Noise_circleMin) (0.000 to 51.000)

Noise_circleMin

Noise_circles

m3

Figure 7 The diagram shows a smith chart with constant gain and noise circles plotted.The brown circles show the constant noise circles with the blue dot showing theoptimum noise point.The red circle shows the constant maximum available gain and the green circles are

the constant gain circles. Marker 1 has been placed on the 12.5dB constant gain circlewith the 2.0dB constant noise circle is indicated by marker 3. If we place a load atmarker 1 ie an impedance of 1.335+j0.75 to the input of the Bipolar transistor then weshould have an amplifier with 12.5dB of gain and a noise figure of

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The input matching circuit can be drawn onto a smith chart or it can be synthesised using theCAD. Using a program called WinSmith the input matching circuit has been generated using

ideal micro-strip lines defined by electrical length (these electrical lengths then need to beconverted to physical lengths depending on the characteristics and dimensions of the micro-strip substrate used.

Figure 8 Shows the WinSmith design of the input matching circuit design to provide a load of1.335+j0.755 ohms (ie 66.8+j37.8 ohms normalised to 50 ohms) to the base of the AT41435.

Figure 8 WinSmith plot of the proposed input matching circuit designed to present aload of 66.8+j37.8 ohms to the input of the AT41435. The line length from the FET gateto the stub is 102 degrees long and the stub has an electrical length of 36 degrees.

We can now simulate the circuit with the input matching circuit added to see if we get close tothe required gain and noise figure. To do this the ideal transmission lines have beenconverted into real micro-strip transmission lines (Er=9.9,H=25thou) using LineCalc. TheADS schematic is shown in Figure 9.

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MSUB

MSub1

Rough=0 mm

TanD=0

T=0 mm

Hu=1.0e+033 mm

Cond=1.0E+50

Mur=1

Er=9.6

H=25 mil

MSub

MLEF

TL2

L=7.96 mm

W=0.56 mm

Subst="MSub1"

MLIN

TL1

L=22.5 mm

W=0.56 mm

Subst="MSub1"Term

Term1

Z=50 Ohm

Num=1

sp_hp_AT-41435_1_19921201

SNP1

Noise Frequency="{0.10 - 4.00} GHz"

Frequency="{0.10 - 6.00} GHz"

Bias="Bjt: Vce=8V Ic=10mA"

S_Param

SP1

CalcNoise=yes

Step=

Stop=1.55 GHz

Start=1.45 GHz

S-PARAMETERS

Term

Term2

Z=50 Ohm

Num=2

Figure 9 ADS schematic of LNA with real matching circuit added to the input.

m2freq=1.500GHzdB(S(2,1))=11.887

1.44 1.46 1.48 1.50 1.52 1.54 1.56

11.4

11.6

11.8

12.0

12.2

12.4

12.6

freq, GHz

dB(S(2,1

))

m2

m1freq=1.550GHznf(2)=1.975

1.44 1.46 1.48 1.50 1.52 1.54 1.56

1.6

1.7

1.8

1.9

2.0

freq, GHz

nf(2)

m1

m3freq=1.501GHzdB(S(2,2))=-8.061

1.44 1.46 1.48 1.50 1.52 1.54 1.56

-8.3

-8.2

-8.1

-8.0

-7.9

-7.8

freq, GHz

dB(S(2,2

))

m3

Figure 10 Resulting simulation from the ADS schematic shown in Figure 9. As we cansee the gain and noise figures dont quite meet the requirements across our band ofinterest. However we have not added the load matching circuit, which we can now

calculate as the device is unconditionally stable.

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The current design has no matching on the output and as we require a good output returnloss we should match to S22* - Note S22 will now have been modified by adding the inputmatching circuit and will have to design the matching circuit to be the conjugate of S22

modified (This is because S22 is looking into the device and the conjugate will lookingtowards the matching circuit.

In order to improve the gain and noise response we need to provide the RL = ROUT* given by:

*

opt11

opt2112

22OUTL.S1

..SSS*RR

+==

freq

1.000GHz1.100GHz1.200GHz1.300GHz1.400GHz1.500GHz1.600GHz1.700GHz1.800GHz1.900GHz2.000GHz

S(1,1)

0.400 / -152.0000.396 / -158.4000.392 / -164.8000.388 / -171.2000.384 / -177.6000.380 / 176.0000.382 / 174.0000.384 / 172.0000.386 / 170.0000.388 / 168.0000.390 / 166.000

S(2,1)

6.730 / 85.0006.310 / 82.2005.890 / 79.4005.470 / 76.6005.050 / 73.8004.630 / 71.0004.412 / 68.8004.194 / 66.6003.976 / 64.4003.758 / 62.2003.540 / 60.000

S(1,2)

0.049 / 56.0000.052 / 56.6000.055 / 57.2000.057 / 57.8000.060 / 58.4000.063 / 59.0000.066 / 58.8000.070 / 58.6000.073 / 58.4000.077 / 58.2000.080 / 58.000

S(2,2)

0.510 / -30.0000.504 / -30.4000.498 / -30.8000.492 / -31.2000.486 / -31.6000.480 / -32.0000.476 / -33.0000.472 / -34.0000.468 / -35.0000.464 / -36.0000.460 / -37.000

Calculation is long winded but has been included here for completeness:

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( )

( )

( ) ( )

( ) ( )

( )( )**

OUTL

1-22

*

OUTL

*

OUTL

opt

*

opt11

opt2112

22OUTL

173.3089.032-0.4867.4095.1

1780.09832-0.48*RR

67.4092.1

089.0tan095.1089.0092.1r

polartobackconvertj0.0891.092j0.089-0.092-j01bewilltermbottomtheSo

j0.0890.092-44)j0.128sin(4)0.128cos(4-

jba-iequadrant3rdtheinbewillwhichcartesianto2240.128converttoneedWe

224128.01

1780.09832-0.48*RR

480.337*176381.01

480.337*714.63*590.06332-0.48*RR

480.337s

.S1

..SSS*RR

+=

+==

=

==+==

+=+

=

+==

+==

==

+==

( ) 370.402244.032.0244.032.0RoutTherefore

244.032.0)01.0088.0()254.0407.0(RhaveweSo

j0.010.088-

6.7)j0.089sin(.7)0.089cos(6173.3)-180j0.089sin(173.3)-800.089cos(1jsincosr

jbaiesector2ndthebewillcartesianto3.3710.089Convert

j0.254-0.4072)j0.48sin(3-)0.48cos(32jsincosr

jb-aiesector4ththebewillcartesianto32-0.48Convert

*

L

=+==

=++=

+

=+=+=+

+

==+

+

jj

jjj

The required output match is similar to the input match set for gain & noise performance. Theelectrical lengths were found to be line length = 100 deg with a stub of 39 degrees. The ADSsimulation of the complete amplifier is shown in Figure 11, with the resulting plots of thesimulation shown in Figure 12.

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m2freq=1.500GHzdB(S(2,1))=12.716

1.44 1.46 1.48 1.50 1.52 1.54 1.56

12.2

12.4

12.6

12.8

13.0

13.2

13.4

freq, GHz

dB(S(2,1

))

m2

m1freq=1.550GHznf(2)=1.924

1.44 1.46 1.48 1.50 1.52 1.54 1.56

1.65

1.70

1.75

1.80

1.85

1.90

1.95

freq, GHz

nf(2)

m1

m3freq=1.501GHzdB(S(2,2))=-34.519

1.44 1.46 1.48 1.50 1.52 1.54 1.56

-45

-40

-35

-30

-25

-20

freq, GHz

dB(S(2,2

))

m3

Figure 12 Simulation of the complete amplifier as shown in the schematic of Figure 11.Here we can see that we have a gain of 12.7dB and gain ripple of 1.02dB andassociated noise figure of 1.77dB at 1.5GHz (worst-case noise figure is at band-edge at1.92dB.The output return loss is >20dB at 1.45GHz.

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Final design

To physically realise the design we need to add the RF bias circuits and DC blocks. The RFbias circuits consist of wave inductive lines connected to a wave capacitive open-circuitstub (See tutorial on Bias Circuits for more details).

The final schematic layout of the amplifier together with the RF bias circuits is shown in Figure13.

As a final check it is a good idea to perform a wide-band analysis of the circuit to ensure thatat all frequencies S11 and S22 < 0. The wide-band plots of the circuit are shown in Figure 14.

AT41435

L = 7.6mm (36)

L = 21.2mm (102)

L = 22mm(100)

L = 8.6mm (39)

50-ohm chip resistor

Base Bias

Collector Bias

Figure 13 Final Amplifier schematic layout with RF bias circuits added, together withblocking capacitors.

As can be seen although the pass-band amplifier response is compliant with a pass-bandgain ripple of

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m2freq=1.503GHzdB(S(1,1))=-2.971

0 1 2 3 4 5 6 7 8 9 10

-20

-15

-10

-5

0 m2

m1freq=1.503GHz

dB(S(2,2))=-32.085

0 1 2 3 4 5 6 7 8 9 10

-40

-30

-20

-10

0

freq, GHz

dB(S(2,2

))

m1

freq, GHz

dB(S(1,1)

)

Figure 14 Results of S11 and S22 for the amplifier over a broad-band width (0.5 to10GHz). The output return is very good as we specifically matched the output to give agood-return loss. As the input was mismatched to give a particular gain & noise figurethe resulting return loss is poor. If this is deemed a problem, then either a balancedamplifier be used or an isolator added (NOTE in both cases this would add ~ 0.5dB tothe noise figure of the amplifier).