An-1084 Power MOSFET Basics

8/3/2019 An-1084 Power MOSFET Basics

http://slidepdf.com/reader/full/an-1084-power-mosfet-basics 1/13

www.irf.com 1AN-1084

Application Note AN-1084

Power MOSFET Basics

by Vrej Barkhordarian, International Rectifier

Table of Contents

Page Breakdown Voltage..............................................................................5

On-resistance.......................................................................................6

Transconductance................................................................................6

Threshold Voltage................................................................................7

Diode Forward Voltage ........................................................................7

Power Dissipation ................................................................................7

Dynamic Characteristics.......................................................................8

Gate Charge.........................................................................................10

dV/dt Capability....................................................................................11

This application note discusses the breakdown voltage, on-resistance, transconductance,threshold voltage, diode forward voltage, power dissipation, dynamic characteristics, gatecharge and dV/dt capability of the power MOSFET.



Power MOSFET BasicsVrej Barkho rdarian, Inte rnation al Rect ifier, El Segun do, Ca.

Discrete p ower MOSFETs

emp loy sem icondu ctor

process ing techniques th at a re

similar t o th ose of today's VLSI

circuits , a l though t he d evicegeometry, voltage an d cu rrent

levels are significantly different

from t he d esign u sed in VLSI

devices. The m eta l oxide

sem icond u ctor field effect

tra ns istor (MOSFET) is ba sed

on t h e origin al field-effect

t rans is to r in t roduced in the

70s. Figure 1 shows the

device sch ema tic, t ra ns fer

cha racterist ics and device

sym bol for a MOSFET. The

invention of th e powerMOSFET was pa rtly driven by

th e lim itations of bipolar power

ju nction tran sistors (BJ Ts)

which, un ti l recently, was th e

device of choice in power

electronics app licat ions.

Althou gh it is n ot poss ible to

define abs olu tely the opera t ing

bou nd ar ies of a p ower device,

we will loosely refer to t h e

power device as an y device

tha t can switch at least 1A.The b ipolar p ower tran sistor is

a current controlled device. A

large bas e drive curren t as

high a s on e-fifth of th e

collector cur rent is required to

keep th e device in th e ON

state .

Also, high er reverse b as e drive

curr ents a re required to obtain

fas t tu rn-off. Despite the very advan ced sta te of ma nu factu rability an d lower costs of BJ Ts, th ese

limitat ions h ave made th e bas e drive circu it design m ore comp licated a nd h ence more expensive tha n th e

power MOSFET.

SourceContact

FieldOxide

GateOxide

GateMetallization

DrainContact

n* Drain

p-Substrate

Channel

n* Sourcet ox

l

V GS

V T

00

I D

(a)

(b)

I D

D

SB(Channel or Substrate)

S

G

(c)

Figure 1. Power MOSFET (a) Schematic, (b) Transfer Characteristics, (c)Device Symbol.



Another BJ T l imitat ion is tha t both electrons a nd holes

contribute to condu ction. Presen ce of holes with their h igher

carrier l ifet ime cau ses the switching speed to be several orders of

m agnitu de slower tha n for a power MOSFET of similar size and

voltage ratin g. Also, BJ Ts su ffer from th erm al run awa y. Their

forward voltage drop decreas es with increasing tem peratu re

cau sing diversion of cur rent to a single device when several

devices a re pa ral leled. Power MOSFETs, on the other h an d, ar e

m ajority car rier devices with n o minority car rier injection. They

are s up erior to the BJ Ts in h igh frequen cy applicat ions where

switching power losses are importan t . Plus , they can withsta nd

simu ltaneous app licat ion of high cu rrent an d voltage withou t

u ndergoing dest ru ct ive fai lu re du e to second break down. Power

MOSFETs can also be paralleled easily because the forward

voltage drop increa ses with increasing tempera tu re, ensu ring an even distr ibu tion of cur rent a mon g all

components .

However, a t h igh brea kdown voltages (>200V) th e on-s ta te voltage dr op of th e power MOSFET becomes

higher th an th at of a s imilar s ize bipolar d evice with s imilar voltage rat ing. This m ak es it more attr active

to us e the bipolar p ower tran sistor at th e expense of worse h igh frequen cy performa nce. Figure 2 sh ows

th e presen t curr ent -volta ge lim itations of power MOSFETs and BJ Ts. Over tim e, new ma terials,structures and processing techniques are expected to raise these l imits.

2000

1500

1000

500

01 10 100 1000

Maximum Current (A)

H o l d o f f V o l t a g e ( V )

BipolarTransistors

MOS

Figure 2. Current-VoltageLimitations of MOSFETs and BJTs.

DrainMetallization

Drain

n+ Substrate

(100)

n- Epi Layer

Channelsn+pn+

p+ Body Region p+

Drift Region

G

S

D

SourceGateOxide

PolysiliconGate

SourceMetallization

Figure 3. Schematic Diagram for an n-Channel Power MOSFET and the Device.



Figure 3 s hows sch ema tic diagram an d Figu re 4 sh ows th e physical origin of the para si t ic components in

an n-cha nn el power MOSFET. The p ara si t ic J FET appea ring between th e two body imp lants restr icts

current flow when the depletion widths of the two adjacent body diodes extend into the drift region with

increa sing drain voltage. The pa ras it ic BJ T can ma ke th e device su sceptible to un wanted device tu rn-on

an d prem atu re breakdown. The ba se resistan ce RB mu st be m inimized thr ough carefu l design of the

doping and dista nce un der the sou rce region. There are several para si t ic capacitances a ss ociated with

the power MOSFET as sh own in Figure 3.

CGS is the ca pacitan ce du e to the overlap of the s ource a nd the ch an nel regions b y the polysilicon gate

and is independent of applied voltage. CGD consists of two parts, th e first is the ca pacitance a ss ociatedwith t he overlap of the p olysilicon gate an d th e si licon u nd ernea th in t he J FET region. The s econd pa rt is

the capa citan ce ass ociated with th e deplet ion region imm ediately u nd er the gate. CGD is a nonlinea r

fu n ction of voltage. Fina lly, CDS , the capacitance associated with the body-drift diode, varies inversely

with the squ are r oot of the dra in-source bias. There a re cu rrently two designs of power MOSFETs, u su ally

referred to as th e plan ar an d the trench designs. The plana r design h as a lready been introdu ced in th e

sch em atic of Figu re 3. Two var iations of th e tren ch p ower MOSFET ar e sh own Figure 5. The tren ch

techn ology has the a dvanta ge of higher cel l dens i ty bu t is more difficult to ma nu factu re tha n t he plan ar

device.

Metal

CGS2

Cgsm

LTO

CGD

R ChC

GS1

RB BJT

n-

p-

CDS

JFET

REPI

n-

n- Epi Layer

n- Substrate

Figure 4. Power MOSFET Parasitic Components.



BREAKDOWN VOLTAGE

Break down volta ge,

BVDS S, is th e voltage at

which the reverse-biased

body-drift diode brea ks

down and significant

curr ent s tarts to flow

between the source an ddrain by the avalanch e

mu lt iplicat ion process,

while the gate an d

source are sh or ted

together. Cur rent-voltage

characteristics of a

power MOSFET ar e

sh own in Figur e 6.

BVDSS is n orma lly

measu red a t 2 5 0µA dr ain

curren t . For drain

voltages below BVDS S

and with n o b ias on th egate, no chan nel is

formed u nder th e gate at

the su rface and the d rain

voltage is ent irely

su ppor ted by the

reverse-bias ed body-drift

p-n junction. Two related

phenomena can occur in

poorly designed an d

processed devices:

p u n ch - th ro u gh a n d

reach- th rough . Punch-

thr ough is observed

when the d eplet ion

region on th e sour ce side

of the body-drift p-n

jun ct ion rea ches the

sour ce region a t dra in

voltages below the ra ted

avalan che volta ge of th e

device. This pr ovides a

curren t pa th between

source and drain an d

cau ses a s oft breakdown

characterist ics as shownin Figu re 7. The leaka ge

current flowing between

source and drain is den oted by IDS S. There ar e t radeoffs to be mad e between RDS(on) that requ ires sh or ter

chan nel leng ths a nd pun ch- through avoidan ce that requ ires longer chann el leng ths .

The r each-th rough p hen omen on occurs when the d eplet ion region on th e drift side of the b ody-drift p-n

ju nction reach es th e epilayer-sub stra te interface before avalanch ing tak es place in the ep i. Once th e

deplet ion edge enters the h igh carr ier concentra t ion su bstr ate, a fur ther increase in d rain voltage will

cau se th e electric field to qu ickly reach th e critical valu e of 2x10 5 V/ cm where avalan ching begins .

Source

Gate

Source

GateOxide

Channel

Oxide

n- Epi Layer

n+ Substrate

(100)

Drain

(b)

G SS

Electron Flow

D

(a)

Figure 5. Trench MOSFET (a) Current Crowding in V-Groove Trench MOSFET,(b) Truncated V-Groove MOSFET



ON-RESISTANCE

The on-st ate res ista nce of a power MOSFET is m ade u p of several components as sh own in Figu re 8:

(1)

where:

Rsource = Source d iffus ion resistan ceRch = Chann el res i s tance

RA = Accum u lat ion resistan ce

RJ = "J FET" comp onen t-resist an ce of th e

region between the two body regions

RD = Drift region r esista nce

Rsu b = Subst ra te res i s tance

Wafers with substrate resistivities of up to

20mΩ-cm a re u sed for high volta ge

devices an d less tha n 5mΩ-cm for low

voltage devices.

Rwcml = Sum of Bond Wire resistance, the

Contact r es is tan ce between the s ource

an d dr ain Metal lizat ion a nd the si licon,

meta l lizat ion a nd Leadframe

contributions . These are norm ally

negligible in h igh voltage devices bu t ca n

becom e s ignificant in low volta ge devices.

Figure 9 sh ows t he r elat ive importan ce of

each of the compon ents to RDS(on) over th e

voltage spectru m. As ca n b e seen, a t h igh

voltages th e RDS(on) is dom inated by epiresistan ce and J FET component . This

componen t is h igher in h igh voltage

devices du e to the h igher res istivity or

lower ba ckgrou nd carrier concentra t ion in

th e epi. At lower voltages, th e RDS(on) is

dominated by the cha nn el res is tan ce and

the contribut ions from th e meta l to

sem icondu ctor contact , meta ll izat ion,

bond wires a nd leadframe. The s u bstra te contribution becomes more s ignifican t for lower brea kdown

voltage devices.

TRANSCONDUCTANCE

Tran scondu ctan ce, gfs, is a m easu re of the s ens it ivity of drain cu rrent to chan ges in gate-source bias.

This pa ram eter is norma lly quoted for a Vgs tha t gives a drain cu rrent equal to about one ha lf of the

ma ximu m cu rrent ra t ing value an d for a VDS that en su res operat ion in the consta nt cu rrent region.

Tran scondu ctan ce is influen ced by gate width, which increases in p roport ion to the a ct ive area as cell

dens ity increa ses. Cell densi ty ha s increas ed over the years from a roun d ha lf a m il lion per squ are inch in

1980 to around eight million for planar MOSFETs and around 12 million for the trench technology. The

limiting factor for even higher cell densities is the photolithography process control and resolution that

al lows contacts to be m ade to the s ource m etal lizat ion in th e center of the cel ls .

R R R R R R R RDS(on source ch A J D sub wcml) = + + + + + +

GateVoltage

7

6

5

4

IDS

VS VDS

LOCUS

3

2

1

0 5 10 150

5

10

15

20

25

(

S a t u r a t i o n

R e g i o n )

L i n e a r R e g i o n

N o r m a l i z e d D r a i n C u r r e n t

Drain Voltage (Volts)

Figure 6. Current-Voltage Characteristics of Power MOSFET



Channel length also affects t ransconductance. Reduced

cha nn el length is ben eficial to both gfs a nd on-resistan ce,

with p u nch -thr ough a s a t ra deoff. The lower limit of th is

length is s et by th e ab ility to contr ol th e dou ble-diffu sion

process an d is aroun d 1-2m m t oday. Fina l ly the lower the

gate oxide thickness the higher gfs.

THRESHOLD VOLTAGE

Thr esh old volta ge, Vth , is defined as th e minimu m gate

electrode bias r equired to s trongly invert th e su rface

u nder th e poly an d form a condu cting chan nel between

the source and the dra in regions. Vth is u su al ly measu red

at a dr ain-source curr ent of 250µA. Common values are

2-4V for h igh volta ge devices with th icker gate oxides , an d

1-2 V for lower volta ge, logic-com pa tible devices with

th inn er gate oxides . With power MOSFETs finding incr eas ing u se in portab le electronics an d wireless

commu nications where ba t tery power is at a p remium , the tr end is toward lower valu es of RDS(on) an d

Vth.

DIODE FORWARD VOLTAGE

The diode forward voltage, VF, is the

guara nteed m aximu m forward drop of

the body-drain diode at a specified

value of sour ce cur rent . Figure 10

sh ows a t ypical I-V cha ra cteristics for

this diode at two temp eratu res. P-

cha nn el devices h ave a higher VF du e

to the higher conta ct resistan ce

between m etal an d p-s il icon

compared with n-type silicon.Maxim u m valu es of 1.6V for h igh

voltage d evices (>100 V) an d 1.0 V for

low voltage d evices (<100 V) are

common.

POWER DISSIPATION

The maximum allowable power

dissipat ion tha t will raise th e die

temperature to the maximu m

al lowable when th e case temperatu re

is h eld at 25 0C is importa nt . It is giveby Pd where:

T jmax = Maximu m allowable tem peratu re of the p-n ju nction in th e device (norm ally 150 0C or 175 0C) Rt h J C

= J un ction-to-cas e therma l imp edan ce of the device.

DYNAMIC CHARACTERISTICS

Sharp

Soft

ID

BVDSS

VDS

Figure 7. Power MOSFET BreakdownCharacteristics

N+

P-BASERSOURCE

RCH

RA

RJ

RD

RSUB

N+ SUBSTRATE

SOURCE

GATE

DRAIN

Figure 8. Origin of Internal Resistance in a Power MOSFET.

PdT j

R thJC=

-m a x 2 5(2)



When the MOSFET is us ed as a s witch, i ts bas ic fu nction is to control the d rain cu rrent by the gate

voltage. Figu re 11(a) sh ows the tran sfer cha ra cteristics an d Figure 11(b) is an equ ivalent circuit model

often u sed for the a na lysis of MOSFET switching perform an ce.

The switching perform an ce of a device is determ ined by th e t ime requ ired to estab lish voltage cha nges

across capacitances. RG is the d istr ibu ted res ista nce of the gate an d is a pproxima tely inversely

proportiona l to active area . LS an d LD are source an d drain lead indu ctances an d are a round a few tens o f

n H. Typica l values of inp u t (Cis s ), out pu t (Cos s ) an d reverse tra ns fer (Crs s ) capa citan ces given in the d ata

sh eets are u sed by circuit designers as a s tart ing point in determ ining circuit componen t values. The datash eet capacitan ces are defined in term s of the equ ivalent circuit capa citan ces as :

50V 100V 500VVoltage Rating:

Packaging

Metallization

Source

Channel

JFETRegion

ExpitaxialLayer

Substrate

REPI

RCH

Rwcml

Figure 9. Relative Contributions to RDS(on)

With Different Voltage Ratings.



C is s = CGS + CGD , CDS shor ted

Crs s = CGD

Cos s = CDS + CGD

Gate-to-drain cap acitance, CGD , is a

nonlinea r function of voltage an d is th e m ost

imp ortant p ara meter becau se i t provides afeedback loop between th e ou tpu t an d th e

inpu t of th e circuit. CGD is also called the

Miller capa citan ce becaus e it cau ses th e total

dynam ic inpu t capa citan ce to become greater

than the su m of the s ta t ic capacitances .

Figure 12 sh ows a typical switching t ime test

circu it . Also sh own are th e componen ts of

the r ise an d fall t imes with reference to th e

VGS an d VDS waveforms.

Turn-on delay, t d(on), is th e t ime ta ken tocha rge the inp u t capa citan ce of the device

before drain cur rent condu ction can st art .

Similarly, turn-off delay, t d(off), is th e t im e

taken to disch arge the ca pacitan ce after th e after is s witched off.

0.0 0.5 1.0 1.5 2.0 2.50.1

1

10

100

TJ

= 1500C

TJ

= 250C

VGS = 0V

VSD, Source-to-Drain Voltage (V)

I S D , R e v e r s e D r a i n C

u r r e n t ( A )

Figure 10. Typical Source-Drain (Body) Diode ForwardVoltage Characteristics.

ID

VGS

Slope = gfs

G R G

C GD

LD

D

D'

S'

C DS

LS

S

C GS

C I D

Body-drainDiode

(a) (b)

Figure 11. Power MOSFET (a) Transfer characteristics, (b) Equivalent Circuit Showing Components ThatHave Greatest Effect on Switching



GATE CHARGE

Although input capacitance

values a re u seful , they do not

provide accu rate resu lts when

compar ing the s witching

performa nces of two devices

from d ifferent m an u factu rers.

Effects of device size an dt r an scon d u c tan ce mak e su ch

compa risons more difficult. A

more us eful para meter from the

circuit design point of view is

the gate cha rge ra ther tha n

capacitance. Most

ma nu facturers include bo th

param eters on thei r data sheets .

Figure 13 sh ows a typical gate

cha rge waveform an d th e test

circuit. When th e gate is

connected to the su pply voltage,

VGS sta rts to increase u nti l itreaches Vth , at which point th e

drain cu rrent s tarts to flow an d

the CGS star ts to cha rge. During

the p eriod t 1 to t2, CGS

continu es to charge, the gate

voltage continu es to r ise an d

drain curren t r ises

pr oportion a lly. At time t2, CGS

is comp letely charged an d th e

drain curren t reaches the

predetermined curren t ID an d

sta ys cons tan t while the drainvoltage sta rts t o fall. With

reference to th e equ ivalent

circuit m odel of the MOSFET sh own in Figure 13, i t can be seen tha t with CGS fu lly char ged at t 2 , VGS

becomes consta nt a nd th e drive curren t sta rts to char ge the Miller capa citan ce, CDG . This continues

u nti l t ime t 3 .

RD

-

+VDD

VDS

VGS

RG

D.U.T.

-10V

Pulse Width < 1µµsDuty Factor < 0.1%

(a)

Figure 12. Switching Time Test (a) Circuit, (b) VGS and VDSWaveforms

td(on) tr td(off) tf

VGS

100%

90%

VDS

(b)



Cha rge time for th e Miller ca pa citan ce is

larger tha n th at for the gate to source

capacitance CGS du e to the rapidly cha nging

drain voltage between t 2 an d t3 (cu rren t = C

dv/ dt). Once both of th e capa citan ces CGS

an d CGD are fully charged, gate voltage (VGS )

sta rts increas ing again un ti l i t reach es the

su pply volta ge at time t 4 . The gat e cha rge

(QGS + QGD ) corresp ond ing to time t 3 is th e

bare m inimu m ch arge required to switch

th e device on. Good circuit design pra ctice

dictates th e u se of a higher gate voltage

than the ba re min imu m requi red fo r

switching an d th erefore the gate char ge

u sed in the calculat ions is Q G

corresponding to t 4.

The a dvanta ge of us ing gate ch arge is th at

the des igner ca n ea si ly calculate th e

am oun t of curr ent requ ired from th e drive

circuit to switch the device on in a desiredlength of time beca u se Q = CV an d I = C

dv/ dt , the Q = Time x curren t . For

exam ple, a device with a gate ch ar ge of

20nC can be tu rn ed on in 20µsec if 1m a is

su pplied to the gate or it can tu rn on in

20n sec if the gate cu rrent is increas ed to

1A. Thes e simp le calcu lations wou ld n ot

ha ve been possible with inp ut ca pacitan ce

values.

dv/dt CAPABILITY

Peak diode recovery is defined as the

ma ximu m rate of r ise of drain-sou rce

voltage allowed, i.e., dv/ dt cap ab ility. If th is

rate is exceeded th en th e voltage across th e

gate-source termina ls may become h igher

tha n the thr esh old voltage of the device,

forcing th e device into cu rrent condu ction

mode, and u nder certain condit ions a

catas trophic fai lu re may occur. There are two possible mecha nism s by which a dv/ dt indu ced turn -on

m ay take place. Figu re 14 sh ows the equivalent circu it m odel of a power MOSFET, includin g th e

para si t ic BJT. The first mecha nism of dv/ dt indu ced turn -on becomes a ct ive through th e feedback act ion

of the gate-drain capacitance, CGD. When a voltage ramp a ppears across th e drain an d source termina l

of the device a cur rent I1 flows th rough th e gate resistan ce, RG, by mea ns of the gate-drain capa citan ce,CGD . RG is the total gate r esistan ce in th e circuit an d th e voltage drop a cross i t is given by:

(3)

Wh en t he gat e volta ge VGS exceeds t h e th res h old voltage of th e device Vth , th e device is forced in to

condu ction. The dv/ dt capab ili ty for this mech an ism is thu s set by:

VDD

DID

D

G

S

CGS

CDG

SID

TEST CIRCUIT

(a)

OGS

OGD

GATEVOLTAGE

VG

VG(TH)

t0

t1

t2

t3

t4

t

DRAIN CURRENT

DRAINVOLTAGE

VDD

ID

WAVEFORM

(b)

Figure 13. Gate Charge Test (a) Circuit, (b) Resulting Gateand Drain Waveforms.

V I R R Cdv

dtGS G G GD= =1



(4)

It is clear th at low Vth

devices a re m ore prone to

dv/ d t tu rn -on . Thenegat ive temperatu re

coefficien t of Vth is of

special imp ortan ce in

app licat ions where h igh

temperatu re env ironments

are present . Also gate

circu it imp edan ce has to be

chooses car efu lly to avoid

this effect.

The second m echan ism for

the dv/ d t tu rn-on in

MOSFETs is th rough th e

para si t ic BJT as s hown inFigure 15. The capacitance

as sociated with th e

depletion region of th e body

diode extend ing into th e

drift region is den oted a s

CDB and a ppears between

the ba se of the BJ T an d th e drain of the MOSFET. This capa citan ce gives r ise to a curr ent I2 to flow

through the bas e res is tan ce RB when a voltage ram p appear s across th e drain-source terminals. With

an alogy to the first mech an ism , the dv/ dt capa bility of this m echan ism is:

(5)

If th e voltage tha t develops a cross RB is greater

than about 0 .7V, then the base-emit ter junction

is forward-bias ed an d th e par asi t ic BJ T is

tu rned on. Under the condit ions of high (dv/ dt)

an d large valu es of RB, the b rea kdown voltage of

th e MOSFET will be lim ited to th at of th e open -

ba se brea kdown voltage of th e BJT. If th e

app lied dra in voltage is greater th an the open -

base breakdown voltage, then the MOSFET will

enter avalanch e and m ay be destroyed if the

cur rent is not limited externa lly .

In crea sing (dv/ dt) cap ab ility th erefore requ ires

reducing the ba se res i s tance RB by increa sing

the b ody region d oping an d redu cing the

d is tan ce curren t I2 has to flow laterally before it

is collected by the sou rce met allization. As in

the f irst m ode, the BJT related dv/ dt capa bility

becomes worse a t h igher temperatures becaus e

RB increases an d VBE decreases with increasing

temperature .

dv

dt

V

R C

th

G GD

=

DRAIN

APPLIEDRAMP

VOLTAGE

NPNBIPOLAR

TRANSISTOR

CDB

RB

I 2

D

S

SOURCE

CGS

RG

G

CGD

I 1

Figure 14. Equivalent Circuit of Power MOSFET Showing Two PossibleMechanisms for dv/dt Induced Turn-on.

GATESOURCE

N+ A

LN+

RS

CDS

DRAIN

Figure 15. Physical Origin of the Parasitic BJTComponents That May Cause dv/dt Induced Turn-on

dv

dt

V

R C

BE

B DB=



R e f e r e n c e s :

"HEXFET Power MOSFET Designer 's Man u al - Application Notes an d Reliab ility Data," Int ern ationa l

Rectifier

"Modern Power Devices," B. J aya n t Baliga

"Physics of Semiconductor Devices," S. M. Sze

"Power FETs and Their Applications," Edwin S. Oxner

"Power MOSFETs - Theory an d Applications ," Du nca n A. Gra nt a nd J ohn Gower

Date post:	06-Apr-2018
Category:	Documents
Upload:	ivan-braga
View:	232 times
Download:	0 times

An-1084 Power MOSFET Basics

Documents