An 558: Implementing Dynamic Reconfiguration in Arria II GX … · 2021. 7. 19. · Figure 2....

© March 2009 Altera Corporation

© March 2009

AN 558: Implementing DynamicReconfiguration in Arria II GX Devices

AN-558-1.0

IntroductionArria® II GX transceivers allow you to dynamically reconfigure various channel and CMU settings without powering down any part of the device. This application note provides an introduction and examples about how to utilize this feature for various applications.

The following features are described:

■ Transmit and receive analog settings

■ Transmit data rate in the multiples of 1, 2, and 4

■ One channel at a time

■ Channel and clock multiplier unit (CMU) PLL

■ CMU PLL only

Finally, this application note walks you through the different design scenarios and provides the necessary information so you can successfully connect the ALTGX_RECONFIG megafunction to the ALTGX megafunction.

This application note contains the following sections:

■ “Conventions Used in this Application Note” on page 2

■ “Dynamic Reconfiguration Modes” on page 2

■ “Dynamic Reconfiguration Controller Architecture” on page 4

■ “Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration” on page 7

■ “Clock Requirements for the ALTGX Instance and ALTGX_RECONFIG Instance” on page 26

■ “Interfacing the ALTGX_RECONFIG Instance and the ALTGX Instance” on page 28

■ “Offset Cancellation Control for Receiver Channels” on page 37

■ “Functional Simulation of the Offset Cancellation Process” on page 41

■ “PMA Controls Reconfiguration” on page 41

■ “PMA Control Reconfiguration Examples” on page 48

■ “Error Indication in the ALTGX_RECONFIG MegaWizard Plug-In Manager” on page 54

■ “Combining Transceiver Channels with Dynamic Reconfiguration Enabled” on page 55

■ “Dynamic Reconfiguration Duration and FPGA-Fabric Resource Utilization” on page 56

AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices

Page 2 Conventions Used in this Application Note

■ “Dynamic Reconfiguration (ALTGX_RECONFIG Instance) Resource Utilization” on page 57

■ “Transceiver Channel Reconfiguration Modes” on page 58

■ “Document Revision History” on page 103

Conventions Used in this Application NoteThe following conventions are used throughout this document:

■ ALTGX instance—Represents the transceiver instance generated by the ALTGX MegaWizard Plug-In Manager. This term is used when the various inputs, outputs, and connections to the transceiver channels are explained.

■ ALTGX_RECONFIG instance—Represents the dynamic reconfiguration controller instance generated by the ALTGX_RECONFIG MegaWizard Plug-In Manager. This term is used when the various inputs, outputs, and connections to the controller are explained.

■ Dynamic reconfiguration controller—Represents the dynamic reconfiguration controller. This term is used when a concept related to the controller is explained.

■ Logical channel addressing—Used whenever the concept of logical channel addressing is explained. This term does not refer to the logical_channel_address port or the Use 'logical_channel_address' port option available in the ALTGX_RECONFIG MegaWizard Plug-In Manager.

■ PMA controls—Represents the Analog controls (VOD, pre-emphasis, and manual equalization) option as displayed in both the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Managers.

Dynamic Reconfiguration ModesThe different modes of dynamic reconfiguration are as follows:

■ Physical medium attachment (PMA) controls reconfiguration

■ Offset cancellation for receiver channels

■ Transceiver channel reconfiguration modes

These modes are described briefly in the following sections.

PMA Controls ReconfigurationYou can dynamically reconfigure the following PMA controls:

■ Pre-emphasis settings

■ Equalization settings

■ DC gain settings

■ Voltage output differential (VO D) settings

For more information, refer to “PMA Controls Reconfiguration” on page 41.

AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices © March 2009 Altera Corporation

Dynamic Reconfiguration Modes Page 3

Offset Cancellation The Arria II GX device provides an offset cancellation circuit per receiver channel to counter the offset variations due to process, voltage, and temperature. These variations create an offset in the analog circuit voltages, pushing them out of the expected range. In addition to reconfiguring the transceiver channel, the dynamic reconfiguration controller performs offset cancellation on all the receiver channels connected to it on power up.

The offset cancellation for the receiver channels option is automatically enabled in both the ALTGX and ALTGX_RECONFIG MegaWizard™ Plug-In Managers for Receiver and Transmitter and Receiver only configurations. It is not available for Transmitter only configurations. For Receiver and Transmitter and Receiver only configurations, you must connect the necessary interface signals between the ALTGX_RECONFIG and ALTGX (with receiver channels) instances. For more information, refer to “Offset Cancellation Control for Receiver Channels” on page 37.

1 For proper device operation, you must always connect the ALTGX_RECONFIG and ALTGX (with receiver channels) instances.

Transceiver Channel Reconfiguration ModesEach transceiver block has four transceiver channels. The transceiver channels have both the PMA and PCS blocks.

Transceiver ChannelsFor the transceiver channels, dynamic reconfiguration involves reconfiguration of the following:

■ Transceiver channel functional mode

■ Transceiver channel data rate switch

■ Transceiver channel functional mode and data rate switch

However, the following dynamic reconfiguration cannot be achieved for the transceiver channels in the Arria II GX device:

■ Mode switch to and from any ×4 and ×8 configurations

■ Not backward compatible with Arria GX devices

■ Testability features (Pseudo-Random Binary Sequence [PRBS] and Built-In Self Test [BIST])

Depending on how you want to reconfigure a transceiver channel, the transceiver channel reconfiguration is further classified into the following dynamic reconfiguration modes:

Data Rate Division in TX

For more information, refer to “Data Rate Division in TX Mode” on page 59.

© March 2009 Altera Corporation AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices

Page 4 Dynamic Reconfiguration Controller Architecture

Channel and TX PLL Select/Reconfig

The following are channel and TX PLL select/reconfig modes:

■ CMU PLL reconfiguration

■ Channel and CMU PLL reconfiguration

■ Channel Reconfiguration with TX PLL select

For more information, refer to “Channel and TX PLL select/reconfig Modes” on page 64.

Offset cancellation is enabled by default. All other dynamic reconfiguration modes are available for selection through the reconfig_mode_sel signal. Based on which part of the transceiver channel you want to reconfigure, you can select one or more of these dynamic reconfiguration modes.

The reconfig_mode_sel signal is available as an input to the dynamic reconfiguration controller only when you select multiple dynamic reconfiguration modes. Based on the value you set at the reconfig_mode_sel signal, the respective dynamic reconfiguration mode is enabled. The reconfig_mode_sel signal is 2 bits wide.

Dynamic Reconfiguration Controller ArchitectureThe dynamic reconfiguration controller is a soft IP that utilizes the FPGA-fabric resources. You can use only one controller per transceiver block.

1 The Quartus® II software automatically combines channels with similar settings into the same transceiver blocks. However, if you connect these channels to different dynamic reconfiguration controllers, the Quartus II software does not combine these channels but does allocate additional transceiver blocks. To avoid this you can connect these channels to the same controller and reconfigure these channels individually. For more information, refer to “Combining Transceiver Channels with Dynamic Reconfiguration Enabled” on page 55.

You cannot use the dynamic reconfiguration controller to control multiple Arria II GX devices or any off-chip interfaces. Figure 1 shows a conceptual view of the dynamic reconfiguration controller architecture.


Dynamic Reconfiguration Controller Architecture Page 5

The dynamic reconfiguration controller consists of the following control logic modules:

■ PMA controls reconfiguration control logic

■ Data rate division control logic to the TX local divider

■ Offset cancellation control logic for receiver channels

■ Channel reconfiguration with TX PLL select/reconfig control logic

■ CMU PLL reconfiguration control logic

■ Channel and CMU PLL reconfiguration control logic

■ Channel reconfiguration with TX PLL select control logic

For PMA controls reconfiguration, the dynamic reconfiguration control inputs to the controller are translated into address and data bus. The address and data bus are then converted into serial data and forwarded to the transceiver channel selected.

For the data rate division control logic to the TX local divider, the rate_switch_ctrl [1:0] input to the controller is translated into address and data bus within. The address and data bus are then converted into serial data and forwarded to the local divider in the transmitter channel.

Figure 1. Block Diagram of the Dynamic Reconfiguration Controller (Note 1)

Note to Figure 1:

(1) The PMA control ports consist of the VOD controls, pre-emphasis controls, DC gain controls, and manual equalization controls. For detailed descriptions of the inputs and outputs of the ALTGX_RECONFIG instances, refer to Table 1 on page 9 through Table 9 on page 25.

Offset Cancellationcontrol logic

addr

data

busy

error

read

(1)

CMU PLLReconfig

control logic

Channel andCMU PLL

Reconfigurationcontrol logic

Dynamic RateSwitch

rate_switch_ctrl[1:0]

reconfig_address_out

reconfig_address_en

channel_reconfig_done

Channel andCMU PLL

Reconfigurationcontrol logic

logical_tx_pll_sel

logical_tx_pll_sel_en

rate_switch_out

reconfig_clk

write_allreconfig_fromgxb[]

PMA controls reconfig inputs

reconfig_data[15:0]reset_reconfig_address

ALTGX_RECONFIG MegaWizard Plug-In Manager Instance

reconfig_togxb[3:0]

data valid

Parallel toSerial

Converter

AddressTranslation

PMA controlsreconfiguration

logic

rx_tx_duplex_sel[]

logical_channel_address[]

reconfig_mode_sel[2:0]


Page 6 Dynamic Reconfiguration Controller Architecture

For the CMU PLL reconfiguration, channel and CMU PLL reconfiguration, and channel reconfiguration with TX PLL select modes, the dynamic reconfiguration controller receives 16-bit words from a Memory Initialization File (.mif) that you generate and sends this information to the transceiver channel selected. The .mif generation is described in detail in “.mif Generation” on page 65.

Dynamic Reconfiguration Controller InterfaceThe dynamic reconfiguration controller interface consists of certain control input and output status signals. The dynamic reconfiguration controller interface (Figure 2) shows the dynamic reconfiguration interface list, which consists of all the inputs and outputs to the dynamic reconfiguration controller.

Figure 2. Dynamic Reconfiguration Controller Interface

Notes to Figure 2:(1) These ports assume that the dynamic reconfiguration controller is connected to a single channel in the design.(2) These are the optional PMA control input signals and the optional PMA control output status signals. You must select

at least one of these PMA control ports if you want to dynamically configure the PMA controls of a transceiver channel. For a detailed description of the inputs and outputs of the ALTGX_RECONFIG instance, refer to Table 1 on page 9 through Table 9 on page 25.

(3) The logical_channel_address port is available for selection only when the number of channels controlled by the dynamic reconfiguration controller is more than one. This is shown in this section to represent the complete port list.

rx_eqdcgain[2..0]

tx_preemp[3..0]

read

tx_vodctrl[]2..0] (1 )

rx_eqctrl[3..0]

busy

tx_vodctrl_out [2..0]

rx_eqctrl_out[3..0] ( 1 )

rx_eqdcgain_out[2..0]

tx_preemp_out[3..0]

rx_tx_duplex_sel [1:0]

logical_channel_address [6:0]

error

reconfig_data[15..0]

reset_reconfig_address

rate_switch_ctrl[1:0]

logical_tx_pll_sel


rate_switch_out [1:0]

DynamicReconfiguration

Controller

reconfig_clk

reconfig_fromgxb[543:0]

write_all

reconfig_mode_sel[]

(1 )

(1 )

(1 )

(1 )

(1 )

(3 )

(2 )

(2 )

reconfig_address_out[5:0]

reconfig_address_en

channel_config_done

( 1 )

( 1 )

( 1 )

data_valid

reconfig_togxb [3..0]


Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration Page 7

Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration

To support dynamic reconfiguration, the Arria II GX device provides a MegaWizard Plug-In Manager interface, ALTGX_RECONFIG, in addition to the ALTGX MegaWizard Plug-In Manager. This section describes the options available on the individual pages of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

1 The MegaWizard Plug-In Manager provides a warning if any of the settings you choose are illegal.

ALTGX_RECONFIG MegaWizard Plug-In ManagerThe Quartus II software provides the ALTGX_RECONFIG MegaWizard Plug-In Manager to instantiate the dynamic reconfiguration controller to dynamically reconfigure the PMA controls, to enable the Analog controls option in the Reconfiguration settings tab, and to enable at least one of the PMA control ports in the Analog controls tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Figure 3 shows the first page of the MegaWizard Plug-In Manager. To generate an ALTGX_RECONFIG custom megafunction variation, select Create a new custom megafunction variation. Click Next.

Figure 4 shows the second page of the MegaWizard Plug-In Manager. Select the following options, then click Next when you are done.

1. In the list of megafunctions on the left, click the + icon beside the I/O item. From the options presented, click ALTGX_RECONFIG megafunction.

2. From the pull-down menu beside Which device family will you be using?, select Arria II GX.

3. Choose your output file format (AHDL, VHDL, or Verilog HDL) from the radio buttons under Which type of output file do you want to create?.

4. In the box under What name do you want for the output file?, enter the file name or click the Browse button to search for it.

1 For the design to compile successfully, always enable the dynamic reconfiguration controller for all the ALTGX instances in the design.

Figure 3. MegaWizard Plug-In Manager (Page 1)


Page 8 Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic

ALTGX_RECONFIG Megafunction Default SettingsFigure 5 shows page 3 of the ALTGX_RECONFIG MegaWizard Plug-In Manager. From the pull-down menu, select the number of channels controlled by the dynamic reconfiguration controller. In the Quartus II software version 9.0, you can enable the Analog controls, Data rate division in TX, and Channel and TX PLL select/reconfig features of the dynamic reconfiguration controller.

Figure 4. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Page 2)



Table 1 describes the available options on the Reconfiguration settings tab (page 3) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation. Select the Match project/default option if you want to change the Currently selected device family options.

Make your selections on Page 3, then click Next.

Figure 5. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Reconfiguration Settings) (Page 3)

Table 1. MegaWizard Plug-In Manager Options (Page 3) (Part 1 of 2)

ALTGX_RECONFIG Default Setting (Page 1 of 2)

ALTX_RECONFIG Settings Description

What is the number of channels controlled by the reconfig controller?

Determine the highest logical channel address among all the ALTGX instances connected to the ALTGX_RECONFIG instance. Round it up to the next multiple of four and set that number in this option.

Depending on the number of channels set, the resource estimate changes because this is a soft implementation that uses fabric logic resources. The resource estimate is shown in the bottom left portion of Page 3 of the MegaWizard Plug-in Manager.

What are the features to be reconfigured by the reconfig controller?

Offset Cancellation for Receiver Channels (default).

When the device powers up, the dynamic reconfiguration controller performs offset cancellation on the receiver portion of all the transceiver channels controlled by it. For more information about the Offset Cancellation feature, refer to “Offset Cancellation Control for Receiver Channels” on page 37.



ALTGX_RECONFIG Default Ports

Port Name Input/Output Description

reconfig clk Input The frequency range of this clock depends on the following transceiver channel configuration modes:

■ Receiver only (37.5 MHz to 50 MHz)

■ Receiver and Transmitter (37.5 MHz to 50 MHz)

■ Transmitter only (2.5 MHz to 50 MHz)

By default, the Quartus II software assigns a global clock resource to this port.

reconfig_togxb Output This is an output port of the ALTGX_RECONFIG instance. You must connect the reconfig_togxb[3:0] input port of every ALTGX instance controlled by the dynamic reconfiguration controller to the reconfig_togxb[3:0] input port of the ALTGX_RECONFIG instance.

reconfig_fromgxb Input This is an input port in the ALTGX_RECONFIG instance. This is a transceiver block-based signal. Therefore, the width of this signal increases in steps of 17-bits per transceiver block.

Depending on this setting, the ALTGX_RECONFIG MegaWizard Plug-In Manager generates the appropriate signal width for the interface signal (reconfig_fromgxb) between the ALTGX_RECONFIG and ALTGX instances. It also gives the necessary bus width for all the selected physical media attachment signals.

busy Output This signal is used to indicate the busy status of the dynamic reconfiguration controller during two conditions:

■ Dynamic reconfiguration of PMA controls—This signal is high when the dynamic reconfiguration controller performs a read or write transaction.

■ Offset cancellation—After the device powers up, this signal remains low for the first reconfig_clk clock cycle. It then gets asserted and remains high when the dynamic reconfiguration controller performs offset cancellation on all the receiver channels connected to the ALTGX_RECONFIG instance.

The de-assertion of the busy signal indicates the successful completion of the offset cancellation process.




Figure 6 shows Error checks/Data rate switch (page 4) of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Table 2 describes the available options on the Error checks/Data rate switch tab (page 4) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation. Select the Match project/default option if you want to change the Currently selected device family options.


Figure 6. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Error Checks/Data Rate Switch) (Page 4)


ALTGX_RECONFIG Default Setting (Page 1 of 2)


Enable illegal mode checking When this option is selected, the ALTGX_RECONFIG MegaWizard Plug-In Manager provides the error output port. The dynamic reconfiguration controller checks for specific unsupported options within two reconfig_clk cycles, de-asserts the busy signal, and asserts the error output port for two reconfig_clk cycles. The dynamic reconfiguration controller does not execute the unsupported operation.

Enable self recovery When this option is selected, the ALTGX_RECONFIG MegaWizard Plug-In Manager provides the error output port. The dynamic reconfiguration controller quits an operation if it did not complete within the expected number of clock cycles. After recovering from the illegal operation, the dynamic reconfiguration controller de-asserts the busy signal and asserts the error output port for two reconfig_clk cycles.



ALTGX_RECONFIG Megafunction with Analog Controls EnabledFigure 7 shows the ALTGX_RECONFIG megafunction, Reconfiguration settings tab, with Analog controls enabled.

ALTGX_RECONFIG Default Ports


error Output Optional status signal to indicate that an unsupported operation is attempted. You can enable the error port by selecting the options in the Error checks/data rate switch tab. The dynamic reconfiguration controller de-asserts the busy signal and asserts the error signal for two reconfig_clk cycles when you attempt an unsupported operation.


Figure 7. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Reconfiguration Settings, Analog Controls Enabled) (Page 3)



Table 3 describes the available options on the Reconfiguration settings tab (page 3) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation with Analog Controls enabled.


Table 3. MegaWizard Plug-In Manager Options (Reconfiguration Settings, Analog Controls Enabled) (Page 3)

ALTGX_RECONFIG with Analog Controls Enabled (Page 1 of 3)


Analog controls Allows dynamic reconfiguration of PMA controls such as equalization, pre-emphasis, DC gain, and VOD. This option generates the Analog Controls page in the MegaWizard Plug-In Manager.

Table 4 on page 14 describes the analog setting control and status ports.

ALTGX_RECONFIG Ports with Analog Controls Enabled


write_all Input Assert this signal for one reconfig_clk clock cycle to initiate a write transaction from the ALTGX_RECONFIG instance to the ALTGX instance.

read Output Assert this signal for one reconfig_clk clock cycle to initiate a read transaction. The read port is available when you select Analog controls in the Reconfiguration settings tab and select at least one of the PMA control ports in the Analog controls tab.

data_valid Output Indicates the validity of the data read from the transceiver by the dynamic reconfiguration controller.

NOTE: This occurs ONLY if data_valid is high; the current data on the output read ports is the valid data.

This signal gets enabled when you enable at least one PMA control port used in read transactions; for example, tx_vodctrl_out.



Figure 8 shows the Analog Controls tab (page 4) of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Table 4 describes the available options on the Analog Controls tab (page 4) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation.

Make your selections on page 4, then click Next.

Figure 8. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Analog Controls Tab) (Page 4)

Table 4. MegaWizard Plug-In Manager Options (Analog Control, Page 4) (Part 1 of 4)

ALTGX_RECONFIG with Analog Controls Enabled (Page 2 of 3)


Use ‘logical_channel_address’ port This option is available for selection when the number of channels controlled by the ALTGX_RECONFIG instance is more than one. The logical_channel_address port is enabled by the ALTGX_RECONFIG MegaWizard Plug-In Manager when you enable this option. The dynamic reconfiguration controller reconfigures only the channel whose logical channel address is specified at the logical_channel_address port.

The width of this port is selected by the ALTGX_RECONFIG MegaWizard Plug-In Manager depending on the number of channels controlled by the dynamic reconfiguration controller. The maximum width of the logical_channel_address port is 9 bits.



Use the same control signal for all channels

This option is available for selection when the number of channels controlled by the ALTGX_RECONFIG instance is more than one. When you enable this option, the dynamic reconfiguration controller writes the same control signals to all the channels connected to it.

This option is not available for selection when you enable the previous Use ‘logical_channel_address’ port option.

Write Control These are optional signals. The signal widths are based on the setting you entered for the What is the number of channels controlled by the reconfig controller? option and whether you enable the Use ‘logical_channel_address’ port option. At least one of these PMA control ports must be enabled to configure and use the dynamic reconfiguration controller.

Read Control These are optional signals. The signal widths are based on the setting you entered for the What is the number of channels controlled by the reconfig controller? option and whether you enable the Use ‘logical_channel_address’ port option. The PMA controls are available for selection only if the corresponding write control is selected. Read and write transactions cannot be performed simultaneously.

ALTGX_RECONFIG Ports with Analog Controls Enabled



Input The logical_channel_address port is enabled by the ALTGX_RECONFIG MegaWizard Plug-In Manager when you enable the Use 'logical_channel_address' port option in the Analog controls tab. The width of the logical_channel_address port depends on the value you set in the What is the number of channels controlled by the reconfig controller? option in the Reconfiguration settings tab.

You can enable the logical_channel_address port only when the number of channels controlled by the dynamic reconfiguration controller is more than one.




tx_vodctrl Input This is an optional transmit buffer VOD control signal. It is 3 bits per transmitter channel. The number of settings varies based on the transmit buffer supply setting and the termination resistor setting on the TX Analog tab of the ALTGX MegaWizard Plug-In Manager.

The width of this signal is fixed to 3 bits if you enable either the Use 'logical_channel_address' port option or the Use same control signal for all the channels option in the Analog controls tab. Otherwise, the width of this signal is 3 bits per channel.

The following shows the VOD values corresponding to the tx_vodctrl settings for 100-Ω termination.

tx_vodctrl VOD (mV) for 1.4 V VCCH

000 N/A

001 400

010 600

011 N/A

100 800

101 900

110 1000

111 1200

For more information, refer to the “Programmable Output Differential Voltage” section of the Arria II GX Transceiver Architecture chapter in volume 2 of the Arria II GX Device Handbook.

tx_preemp Input This is an optional pre-emphasis write control for first post tap for the transmit buffer. Depending on what value you set at this input, the controller dynamically writes the value to the first post tap control register of the transmit buffer.

The width of this signal is fixed to 4 bits if you enable either the Use 'logical_channel_address' port option or the Use same control signal for all the channels option in the Analog controls tab. Otherwise, the width of this signal is 4 bits per channel.

For more information about the pre-emphasis feature, refer to the “Programmable Pre-Emphasis” section of the Arria II GX Transceiver Architecture chapter in volume 2 of the Arria II GX Device Handbook.

rx_eqctrl Input This is an optional write control to write an equalization control value for the receive side of the PMA. The width of this signal is fixed to 4 bits if you enable either the Use 'logical_channel_address' port option or the Use same control signal for all the channels option in the Analog controls tab. Otherwise, the width of this signal is 4 bits per channel.

For more information, refer to the “Programmable Equalization and DC Gain” section of the Arria II GX Transceiver Architecture chapter in volume 2 of the Arria II GX Device Handbook.



http://www.altera.com/literature/hb/arria-ii-gx/aiigx_52001.pdf






rx_egdcgain Input This is an optional equalizer DC gain write control. The width of this signal is fixed to 2 bits if you enable either the Use 'logical_channel_address' port option or the Use same control signal for all the channels option in the Analog controls tab. Otherwise, the width of this signal is 2 bits per channel.

The following values are the legal settings allowed for this signal:

00 => 0 dB

01 => 3 dB

10 => 6 dB

11 => N/A

For more information, refer to the “Programmable Equalization and DC Gain” section of the Arria II GX Transceiver Architecture chapter in volume 2 of the Arria II GX Device Handbook.

tx_vodctrl_out Output This is an optional transmit VOD read control signal. This signal reads out the value written into the VOD control register. The width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller.

tx_preemp_out Output This is an optional first post-tap, pre-emphasis read control signal. This signal reads out the value written by its input control signal. The width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller.

rx_eqctrl_out Output This is an optional read control signal to read the equalization setting of the ALTGX instance. The width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller.

rx_eqdcgain_out Output This is an optional equalizer DC gain read control signal. This signal reads out the settings of the ALTGX instance DC gain. The width of this output signal depends on the number of channels controlled by the dynamic reconfiguration controller.





Figure 9 shows the Error checks/Data rate switch page (page 5) of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Table 5 describes the available options on the Error checks/Data rate switch page (page 5) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation.


Figure 9. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Error checks/Data rate switch, Page 5)

Table 5. MegaWizard Plug-In Manager Options (Error checks/Data rate switch, Page 5) (Part 1 of 2)

ALTGX_RECONFIG Error checks/Data rate switch Page


Enable illegal mode checking When this option is selected, the ALTGX_RECONFIG MegaWizard Plug-In Manager provides the error output port. The dynamic reconfiguration controller checks for specific unsupported options within two reconfig_clk cycles, de-asserts the busy signal and asserts the error output port for two reconfig_clk cycles. The dynamic reconfiguration controller does not execute the unsupported operation.

Enable self recovery When this option is selected, the ALTGX_RECONFIG MegaWizard Plug-In Manager provides the error output port. The dynamic reconfiguration controller quits an operation if it did not complete within the expected number of clock cycles. After recovering from the illegal operation, the dynamic reconfiguration controller de-asserts the busy signal and asserts the error output port for two reconfig_clk cycles.



Use ‘rx_tx_duplex_sel’ port You can select among three transceiver channel configurations; for example, TX only, RX only, or Duplex mode for dynamic reconfiguration. If you do not enable this port, duplex mode is set by default. The settings are:

■ 00 - Duplex mode

■ 01 - RX only mode

■ 10 - TX only mode

■ 11 - unsupported value (do not use this value)

ALTGX_RECONFIG Ports Error Checks/Data Rate Switch Page


rx_tx_duplex_sel Input This is a 2-bit wide signal. It is available for selection in the Error checks/Data rate switch tab.

The advantage of using this optional port is that it allows you to reconfigure only the transmitter portion of a channel, even if the channel configuration is duplex.

For a setting of:

■ rx_tx_duplex_sel = 2'b00 => transmitter and receiver portion of the channel is reconfigured

■ rx_tx_duplex_sel = 2'b01 => receiver portion of the channel is reconfigured

■ rx_tx_duplex_sel = 2'b10 => transmitter portion of the channel is reconfigured

Table 5. MegaWizard Plug-In Manager Options (Error checks/Data rate switch, Page 5) (Part 2 of 2)



ALTGX_RECONFIG Megafunction with Data Rate Division in TX EnabledFigure 10 shows the ALTGX_RECONFIG megafunction, Reconfiguration settings (page 3), with Data rate division in TX enabled.

Table 6 describes the available options on the Reconfiguration settings page (page 3) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation.


Figure 10. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Reconfiguration Settings, Data rate division in TX Enabled) (Page 3)

Table 6. MegaWizard Plug-In Manager Options (Reconfiguration settings, Data Rate Division in TX Enabled) (Page 3) (Part 1 of 2)

ALTGX_RECONFIG with Data Rate Division in TX Enabled


Data rate division in TX This option also enables the write_all, read, and data_valid ports.



Figure 11 shows the Error checks/Data rate switch page (with Data rate division in TX enabled) (page 4) of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

ALTGX_RECONFIG Ports with Data Rate Division in TX Enabled


rate_switch_ctrl Input This input is the control signal to write the desired division factors on a per-channel transmitter basis. This port is only applicable when reconf_mode_sel is set to 011. The output value is listed below:

00 — Divide by 1

01 — Divide by 2

10 — Divide by 4

11 — Not supported (do not attempt to read or write with this value)

Table 6. MegaWizard Plug-In Manager Options (Reconfiguration settings, Data Rate Division in TX Enabled) (Page 3) (Part 2 of 2)

Figure 11. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Error Checks/Data Rate Switch, Data rate division in TX Enabled) (Page 4)



Table 7 describes the available options on the Error checks/Data rate switch page with Data Rate Division in TX enabled (page 4) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation.


Table 7. MegaWizard Plug-In Manager Options (Error Checks/Data Rate Switch, Data Rate Division in TX Enabled) (Page 4)

ALTGX_RECONFIG Error Checks/Data Rate Switch page with Data Rate Division in TX Enabled


Use 'rate_switch_out' port Port to read out the current data rate division values. This optional output status port reads out the current setting on the CMU local divider.

ALTGX_RECONFIG Ports with Error Checks/Data Rate Switch page with Data Rate Division in TX Enabled


rate_switch_out Output This signal reads out the value that has written in for the rate switch of specified transmitter outputs. This output port is only applicable when reconf_mode_sel is set to 011.

The output value is listed below:

00 — Divide by 1

01 — Divide by 2

10 — Divide by 4

11 — illegal value (do not use this value)



ALTGX_RECONFIG Megafunction with Channel and TX PLL Select/Reconfig EnabledFigure 11 shows the Reconfiguration settings page (with Channel and TX PLL select/reconfig enabled) (page 3) of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Table 7 describes the available options on the Reconfiguration settings page with Channel and Transmitter PLL select/reconfig enabled (page 3) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation.


Figure 12. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Reconfiguration Settings, Channel and TX PLL select/reconfig Enabled) (Page 3)

Table 8. MegaWizard Plug-In Manager Options (Reconfiguration settings, Channel and Transmitter PLL select/reconfig Enabled) (Page 3) (Part 1 of 2)

ALTGX_RECONFIG Reconfiguration Settings Page with Channel and Transmitter PLL Select/Reconfig Enabled


Channel and TX PLL select/reconfig This option also enables the write_all port. This option generates the Channel and TX PLL reconfiguration page in the MegaWizard Plug-In Manager.

For more information about this port, refer to the Table 3 on page 13.



After page 3, the Quartus II software creates additional pages for options that you choose. Refer to Figure 7 on page 12 for the Analog controls tab, Figure 8 on page 14 for the Data rate division in TX page, and Figure 9 on page 18 for the Error checks/Data rate switch page.

1 Whether or not you enable any of these features, the Error checks/Data rate switch page remains, but the option on this page is different. For more information, refer to Table 5 on page 18.

ALTGX_RECONFIG Ports Reconfiguration Settings Page with Channel and Transmitter PLL Select/Reconfig Enabled


reconfig_mode_sel Input Select the reconfiguration mode for the ALTGX_RECONFIG megafunction. The signal encoding is as follows:

000 — Reconfiguration for analog controls



011 — Dynamic Transmit data rate switch

*100 — CMU PLL Reconfiguration

*101 — Channel and CMU PLL reconfiguration

*110 — Channel reconfiguration with TXPLL selected


*The features corresponding to these values are described in “Channel and CMU PLL Reconfiguration Mode” on page 74.

Table 8. MegaWizard Plug-In Manager Options (Reconfiguration settings, Channel and Transmitter PLL select/reconfig Enabled) (Page 3) (Part 2 of 2)



Figure 13 shows the Channel and TX PLL reconfiguration page (page 4) of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Table 9 describes the available options on the Channel and TX PLL reconfiguration page (page 4) of the MegaWizard Plug-In Manager for your ALTGX_RECONFIG custom megafunction variation.

Figure 13. MegaWizard Plug-In Manager—ALTGX_RECONFIG (Channel and TX PLL reconfiguration Page) (Page 4)

Table 9. MegaWizard Plug-In Manager Options (Channel and TX PLL reconfiguration Page) (Page 4) (Part 1 of 2)

ALTGX_RECONFIG Channel and TX PLL reconfiguration Page


Use ‘reconfig_address_out’ The value on this optional port indicates the address associated with the words (reconfig instructions) in the .mif. Each dynamic configuration feature requires a maximum of 28 or 38 addresses.

For example, if the Channel Reconfiguration feature is selected, the dynamic reconfiguration controller automatically increments the address from 0 to 27. If the Channel and TX PLL Reconfiguration feature is selected, the address is incremented from 0 to 37.

Therefore, the width of the reconfig_address_out is set to either 5-bits or 6 bits wide, depending on the feature selected. The dynamic reconfiguration controller automatically increments the address at the end of each write cycle.

Use ‘reconfig_address_en’ When high, this optional output status signal indicates that the address to be used in the write cycle has changed. This signal gets asserted when the write transaction is completed (busy signal de-asserted).

Use ‘reset_reconfig_address’ When asserted, this optional control signal resets the current reconfiguration address to 0.


Page 26 Clock Requirements for the ALTGX Instance and ALTGX_RECONFIG

Clock Requirements for the ALTGX Instance and ALTGX_RECONFIG Instance

This section describes the dynamic reconfiguration clock requirements for both the ALTGX instance (transceiver instance) and the ALTGX_RECONFIG instance (dynamic reconfiguration controller instance).

Use ‘logical_tx_pll_sel’ This is an optional control signal. The functionality of the signal depends on the feature selected, as shown below:

■ TX PLL reconfiguration—The corresponding TX PLL is reconfigured based on the value on this signal.

■ Channel and TX PLL reconfiguration—The corresponding TX PLL is reconfigured based on the value on this signal. The transceiver channel listens to the TX PLL selected by this signal.

■ Channel reconfiguration with TX PLL select — The transceiver channel listens to the TX PLL selected by this signal.

Use ‘logical_tx_pll_sel_en’ This is an optional control signal. When this signal is enabled in the ALTGXB_RECONFIG MegaWizard Plug-In Manager, the value set on the logical_tx_pll_sel signal is valid only if the logical_tx_pll_sel_en is set to 1.

For more information, refer to “Logical TX PLL Selection” on page 71.

ALTGX_RECONFIG Ports Channel and TX PLL Reconfiguration Page


logical_tx_pll_sel Input This control signal allows you to select the CMU PLL that you wish to reconfigure. It also allows you to select the CMU PLL to which the channel is listening in Channel Reconfiguration with TX PLL Select mode.


logical_tx_Pll_sel_en Input This signal validates the logical_tx_pll_sel signal.


channel_reconfig_done Output This port indicates that the ALTGX_RECONFIG megafunction has finished writing all the words of a .mif. This is only applicable for channel reconfiguration mode.

reconfig_address_out Output This signal indicates the address out and that the address read out is the current address to be reconfigured by the ALTGX_RECONFIG megafunction during channel reconfiguration. This signal is 5 bits wide in channel reconfiguration mode and 6 bits wide in channel and CMU PLL reconfiguration mode.

reconfig_address_en Output This port indicates the current address to be reconfigured for the ALTGX_RECONFIG megafunction had already changed during channel reconfiguration.

Table 9. MegaWizard Plug-In Manager Options (Channel and TX PLL reconfiguration Page) (Page 4) (Part 2 of 2)


Clock Requirements for the ALTGX Instance and ALTGX_RECONFIG Instance Page 27

Clock Requirements for the ALTGX InstanceFor all the functional mode configurations except PCI Express (PIPE) configurations, you must connect the reconfig_clk input port of the ALTGX instance to the same clock that is connected to the reconfig_clk input port of the ALTGX_RECONFIG instance.

For the PCI Express (PIPE) configurations of the ALTGX instance, fixedclk must be used to clock the dynamic reconfiguration process instead of reconfig_clk. Table 10 shows the dynamic reconfiguration clock settings for the ALTGX instance for the reconfig_clk and fixedclk input ports.

Clock Requirements for the ALTGX_RECONFIG InstanceYou must connect the reconfig_clk input port of the ALTGX_RECONFIG instance to the same clock that is connected to the reconfig_clk input port of the ALTGX instance.

Table 11 shows the reconfig_clk settings for the ALTGX_RECONFIG instance for the Receiver only, Receiver and Transmitter, and Transmitter only configuration modes of the ALTGX instance. Table 11 also shows the reconfig_clk settings for the ALTGX_RECONFIG instance based on the ALTGX configurations.

1 Based on the ALTGX configurations (Receiver only, Transmitter only, and Receiver and Transmitter configurations) controlled by the ALTGX_RECONFIG instance, select the fastest reconfig_clk frequency value. This satisfies both the offset cancellation control for receiver channels and the dynamic reconfiguration of the transmitter and receiver channels.

Table 10. Dynamic Reconfiguration Clock Settings for the ALTGX Instance (Note 1)

Clock Input Frequency Range

reconfig_clk 37.5 MHz to 50 MHz

fixedclk (only for PCI Express [PIPE] configurations

125 Mhz

Note to Table 10:

(1) Altera recommends the reconfig_clk signal and fixedclk signal be driven on a global clock resource.

Table 11. Dynamic Reconfiguration Clock Settings for the ALTGX Instance (Note 1)

Clock Input Frequency Range

Receiver and Transmitter reconfiguration mode 37.5 MHz to 50 MHz

Receiver only reconfiguration mode 37.5 MHz to 50 MHz

Transmitter only reconfiguration mode 2.5 MHz to 50 MHz

Note to Table 11:

(1) Altera recommends the reconfig_clk signal be driven on a global clock resource.


Page 28 Interfacing the ALTGX_RECONFIG Instance and the ALTGX Instance

Interfacing the ALTGX_RECONFIG Instance and the ALTGX InstanceThis section describes the various dynamic reconfiguration settings available in the ALTGX_RECONFIG and ALTGX MegaWizard Plug-In Managers and how to set them. It also provides information about the interface signals and connections between the ALTGX_RECONFIG and ALTGX instances.

There are two ways to connect the ALTGX_RECONFIG instance to the ALTGX instance in your design:

■ Single dynamic reconfiguration controller

Use a single ALTGX_RECONFIG instance to control all the ALTGX instances in your design. Figure 14 shows a block diagram of a single ALTGX_RECONFIG instance controlling multiple ALTGX instances.

■ Multiple dynamic reconfiguration controllers

Your design can have multiple ALTGX_RECONFIG instances, where every ALTGX instance is controlled by it own ALTGX_RECONFIG instance. Figure 15 shows a block diagram of multiple ALTGX_RECONFIG instances each controlling an ALTGX instance.

Figure 14. Block Diagram of a Single Dynamic Reconfiguration Controller in a Design

Figure 15. Block Diagram of Multiple Dynamic Reconfiguration Controllers in a Design

Single Dynamic Reconfiguration Controller(ALTGX_RECONFIG Instance)

ALTGX_RECONFIG instance

reconfig_fromgxb[n:0]

reconfig_togxb[3:0]

ALTGX instance 1

ALTGX instance 2

Multiple Dynamic Reconfiguration Controllers(ALTGX_RECONFIG Instances 1 and 2)


reconfig_togxb[3:0]

ALTGX_RECONFIG instance 1

ALTGX_RECONFIG instance 2


reconfig_togxb[3:0]ALTGX instance 2

ALTGX instance 1


Interfacing the ALTGX_RECONFIG Instance and the ALTGX Instance Page 29

To enable dynamic reconfiguration of a transceiver channel, it is important to understand the following:

■ Logical Channel Addressing—The dynamic reconfiguration controller identifies a transceiver channel by using the logical channel address. The What is the starting channel number? option in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager enables you to set the logical channel address of all the channels within the ALTGX instance. This concept is explained in detail in “Logical Channel Addressing” on page 29.

■ Total number of channels controlled by the ALTGX_RECONFIG instance—Every dynamic reconfiguration controller in a design might be connected to either a single ALTGX instance or multiple ALTGX instances. Depending on the number of channels within each of these ALTGX instances, you must set the total number of channels controlled by the dynamic reconfiguration controller in the ALTGX_RECONFIG MegaWizard Plug-In Manager. This concept is explained in “Total Number of Channels Controlled by the ALTGX_RECONFIG Instance” on page 31. Also, as mentioned earlier, you can use only one controller per transceiver block.

■ Connecting reconfig_fromgxb/reconfig_togxb ports between the ALTGX and ALTGX_RECONFIG instances.

■ A single reconfig controller must be used to control all the channels in the quad.

Logical Channel AddressingThis section describes how to determine and set the logical channel addresses for the ALTGX megafunction and the total number of channels to control for the ALTGX_RECONFIG megafunction. This section uses five different case scenarios to illustrate the correct settings for the What is the starting channel number? option and the What is the number of channels controlled by the reconfig controller? option.



Figure 16 shows the What is the starting channel number? option in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager.

This value determines the logical channel address of all the transceiver channels in the ALTGX instance. You must always set the starting channel number in an ALTGX instance as a multiple of four because each transceiver block has four channels.

For a design that has multiple ALTGX instances controlled by a single ALTGX_RECONFIG instance, follow these rules for setting the What is the starting channels number? option:

■ Determine the highest logical channel address of the current transceiver instances connected to the same dynamic reconfiguration controller.

■ Round the highest logical channel address value to the next multiple of four.

■ Use this value to set the What is the number of channels controlled by the reconfig controller? option.

1 The previously mentioned rules apply for a ALTGX instance that is a receiver only, transmitter only, or receiver and transmitter configuration.

Figure 16. The What is the starting channel number? Option in the ALTGX MegaWizard Plug-In Manager



Total Number of Channels Controlled by the ALTGX_RECONFIG InstanceSimilarly, the dynamic reconfiguration controller requires information about the total number of channels connected to it. Based on this information, the reconfig_fromgxb and logical_channel_address input ports vary in width. Therefore, provide this information in the What is the number of channels controlled by the reconfig controller? option in the Reconfiguration settings tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

The maximum number of channels that you can set in this option is 256. Consider the scenario where one ALTGX_RECONFIG instance is controlling all the ALTGX instances in a design. Use the following rules for setting the What is the number of channels controlled by the controller? option:

■ Determine the highest logical channel address of all the transceiver instances connected to the same dynamic reconfiguration controller. For information about determining the logical channel address using the starting channel number, refer to “Logical Channel Addressing” on page 29.

■ Round the logical channel address value to the nearest multiple of four.

■ Use this value to set the What is the number of channels controlled by the reconfig controller? option.

1 The previously mentioned rules apply for setting the number of channels for a single ALTGX_RECONFIG instance that is controlling either a single or multiple ALTGX instances.

Connecting the reconfig_from_gxb/reconfig_to_gxb PortsThe dynamic reconfiguration interface has the reconfig_fromgxb and reconfig_togxb signals, which must be connected between the ALTGX_RECONFIG instance and the ALTGX instance to successfully complete the dynamic reconfiguration process:

■ reconfig_togxb[3:0]—This is an input port of the ALTGX instance and an output port of the ALTGX_RECONFIG instance. This port is always 4 bits wide regardless of the channels selected in the ALTGX and ALTGX_RECONFIG megafunction. You must connect the reconfig_togxb[3:0] input port of every ALTGX instance controlled by the dynamic reconfiguration controller to the reconfig_togxb[3:0] input port of the ALTGX_RECONFIG instance.

■ reconfig_fromgxb—This is an output port in the ALTGX instance and an input port in the ALTGX_RECONFIG instance. This is a transceiver block-based signal. Therefore, the width of this signal increases in steps of 17 bits per transceiver block.

In the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Manager, the width of this signal depends on the number of channels you select in the What is the number of channels? and What is the number of channels controlled by the reconfig controller? options in the respective MegaWizard Plug-In Manager.



The following are the available widths of the reconfig_fromgxb signal depending on the number of channels selected:

■ 1 ≤ Channels ≤ 4: output port reconfig_fromgxb = 17 bits




To connect the reconfig_fromgxb port between the ALTGX_RECONFIG instance and multiple ALTGX instances, follow these rules:

■ Take the reconfig_fromgxb[16:0] of ALTGX instance 1 and connect it to the reconfig_fromgxb[16:0] of the ALTGX_RECONFIG instance. Connect the reconfig_fromgxb[] port of the next ALTGX instance to the next available bits of the ALTGX_RECONFIG instance, and so on.

■ Similarly, connect the reconfig_fromgxb port of the ALTGX instance which has the highest What is the starting channel number? option to the MSB of the reconfig_fromgxb port of the ALTGX_RECONFIG instance.

The Quartus II Fitter produces an error if the Dynamic Reconfiguration option is enabled in the ALTGX instance, but the reconfig_fromgxb and reconfig_togxb ports are not connected to the ALTGX_RECONFIG instance.

Table 12 shows the example scenarios under which you must set the starting channel number differently.

Case 1aThe design contains the following instances:

■ ALTGX_RECONFIG instance

■ ALTGX instance 1 with one channel

■ ALTGX instance 2 with three channels

Table 12. Example Scenarios for Logical Channel Addressing in ALTGX Instances

Example Scenario Number of ALTGX InstancesNumber of ALTGX_RECONFIG

InstancesNumber of Channels per

Instance

Case 1a Two ALTGX instances:

■ ALTGX instance 1 (Transmitter and Receiver)

■ ALTGX instance 2 (Transmitter and Receiver)

One ALTGX_RECONFIG instance controlling both the ALTGX instances

Instance 1: 1 channel

Instance 2: 3 channels

Case 1b Instance 1: 5 channels

Instance 2: 3 channels

Case 2 One ALTGX instance (ALTGX instance 1) stamped five times.

One ALTGX_RECONFIG instance controlling all the five stamped ALTGX.v or ALTGX.vhd instances.

Instance 1: 1 channel



Figure 17 shows a block diagram of the ALTGX instances and ALTGX_RECONFIG instance and their respective settings in the design.

Logical Channel Addressing on the ALTGX Instance(s)Because there is no instance before ALTGX instance 1, the starting channel address for ALTGX instance 1 is assigned as 0 and the single channel of ALTGX instance 1 has a logical channel address of 0. Using the rules highlighted in this section, the starting channel address for ALTGX instance 2 is assigned as 4 because the highest logical channel address of ALTGX instance 1 is 0 and the next multiple of four is 4. Therefore, the three channels of ALTGX instance 2 have logical channel addresses of 4, 5, and 6, respectively.

Total Number of Channels Controlled by the ALTGX_RECONFIG InstanceThe highest logical channel of all the instances is 6; therefore, the total number of channels controlled by the ALTGX_RECONFIG instance is 8, as it is the next multiple of four.

Figure 17. Case 1a—Block Diagram of the ALTGX Instances and ALTGX_RECONFIG Instance

Note to Figure 17:

(1) reconfig_fromgxb[33:0] = {reconfig_fromgxb[16:0] and reconfig_fromgxb[16:0]}

reconfig_togxb[3:0]

(1)

ALTGX instance 1Single channel instance

Set the What is the startingchannel number? option = 0

Channel 0(logical channel address = 0)


ALTGX instance 2Three channels instance




reconfig_fromgxb [16:0]



Set the What is the number ofchannels controlled by thereconfig controller? option = 8

ALTGX_RECONFIGinstance



Connecting the reconfig_from_gxb/reconfig_to_gxb PortsALTGX instance 1 has one channel and ALTGX instance 2 has three channels; therefore, the reconfig_from_gxb port is 17 bits wide for both instances. The ALTGX_RECONFIG instance has 8 channels; therefore, the reconfig_from_gxb port is 34 bits wide.

Connect the reconfig_from_gxb ports as follows:

■ ALTGX_RECONFIG instance reconfig_from_gxb[16:0] = ALTGX instance 1 reconfig_from_gxb[16:0]

■ ALTGX_ RECONFIG instance reconfig_from_gxb[33:17] = ALTGX instance 2 reconfig_from_gxb[16:0]

Connect the reconfig_to _gxb ports as follows:

■ ALTGX_RECONFIG instance reconfig_to _gxb[3:0] = ALTGX instance 1 reconfig_to_gxb[3:0]

■ ALTGX_ RECONFIG instance reconfig_to_gxb[3:0] = ALTGX instance 2 reconfig_to_gxb[3:0]

Case 1bThe design contains the following instances:


■ ALTGX instance 1 with five channels




Figure 18 shows a block diagram of the ALTGX instances and ALTGX_RECONFIG instance in the design.

Logical Channel Addressing on the ALTGX Instance(s)Similar to Case 1a, there is no instance before ALTGX instance 1, the starting channel address for ALTGX instance 1 is assigned as 0, and the five channels of ALTGX instance 1 have a logical channel address of 0, 1, 2, 3, and 4, respectively. Because the highest logical channel address of ALTGX instance 1 is 4, which is a multiple of four, you must choose the next multiple of four, which is 8, to be the starting channel address for ALTGX instance 2. Therefore, the three channels of ALTGX instance 2 have logical channel addresses of 8, 9, and 10, respectively.

Figure 18. Case 1b—Block Diagram of the ALTGX Instances and ALTGX_RECONFIG Instance

Note to Figure 18:(1) Reconfig_fromgxb[50:0] = {reconfig_fromgxb[33:0] and reconfig_fromgxb[16:0]}

(1)


ALTGX instance 1Five channels instance








ALTGX instance 2Three channels instance





reconfig_togxb [3:0]



Set the What is the number ofchannels controlled by thereconfig controller? option = 12



Total Number of Channels Controlled by the ALTGX_RECONFIG InstanceThe highest logical channel of all the instances is 10 and the total numbers of channels controlled by the ALTGX_RECONFIG instance is 12, as it is the next multiple of four.

Connecting the reconfig_from_gxb/reconfig_to_gxb PortsALTGX instance 1 has five channels and ALTGX instance 2 has three channels; therefore, the reconfig_from_gxb port is 33 bits and 17 bits wide for both instances, respectively. The ALTGX_RECONFIG instance has 12 channels; therefore, the reconfig_from_gxb port is 51 bits wide.

Connect the reconfig_from_gxb ports as follows:

■ ALTGX_RECONFIG instance reconfig_from_gxb[33:0] = ALTGX instance 1 reconfig_from_gxb[33:0]

■ ALTGX_ RECONFIG instance reconfig_from_gxb[50:34] = ALTGX instance 2 reconfig_from_gxb[16:0]

Connect the reconfig_to _gxb ports as follows:

■ ALTGX_RECONFIG instance reconfig_to _gxb[3:0] = ALTGX instance 1 reconfig_to_gxb[3:0]

■ ALTGX_ RECONFIG instance reconfig_to_gxb[3:0] = ALTGX instance 2 reconfig_to_gxb[3:0]

Case 2The design contains the following instances:


■ ALTGX instance 1 with one channel but ALTGX.v or ALTGX.vhd is stamped five times in the design.

Logical Channel Addressing on the ALTGX Instance(s)Set the What is the starting channel number? option to 0. This implies that the ATLGX MegaWizard Plug In Manager sets the logical channel address of the single channel of ALTGX instance 1 = 0.

When you stamp the configured transceiver instance five times, the starting channel numbers of the other four instances (assume “instance2”, “instance3”, “instance4”, and “instance5”) are 4, 8, 12, and 16, respectively.

Specify the starting channel number of the other stamped instances using the defparam parameter (for Verilog) as shown:

■ defparam instance2: starting_channel_number = 4

■ defparam instance3: starting_channel_number = 8; and so on for the remaining stamped instances

To set the total number of channels controlled by the ALTGX_RECONFIG instance and connect the reconfig_from_gxb/reconfig_to_gxb ports, follow the rules outlined in this section.


Offset Cancellation Control for Receiver Channels Page 37

Offset Cancellation Control for Receiver ChannelsAs the silicon progresses toward smaller process nodes, the performance of circuits at these smaller nodes depends more on process variations. These process variations result in analog voltages being offset from required ranges. The Arria II GX device provides an offset cancellation circuit per receiver channel to counter the offset variations due to process, voltage, and temperature. The offset cancellation logic corrects these offsets. The receiver buffer and receiver clock data recovery (CDR) require offset cancellation.

Offset cancellation is automatically executed once every time the device is powered on. The control logic for offset cancellation is integrated into the dynamic reconfiguration controller. You must connect the ALTGX_RECONFIG instance to the ALTGX instances with receiver channels in your design. You must connect the reconfig_fromgxb, reconfig_togxb, and necessary clock signals to both the ALTGX_RECONFIG and ALTGX (with receiver channels) instances. For connection guidelines, refer to “Interfacing the ALTGX_RECONFIG Instance and the ALTGX Instance” on page 28.

1 For proper device operation, you must always connect the ALTGX_RECONFIG and ALTGX (with receiver channels) instances.

OperationEvery ALTGX instance for Receiver and Transmitter or Receiver only configurations requires that the offset cancellation for the receiver channels option is enabled in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager. This option is enabled by default for the previously described two configurations. It is disabled for the Transmitter only configuration.


Page 38 Offset Cancellation Control for Receiver Channels

Figure 19 shows the Offset cancellation for receiver channels option enabled by default in the ALTGX instance.

Because this option is enabled by default, the ALTGX instance must be connected to an ALTGX_RECONFIG instance (dynamic reconfiguration controller). The offset cancellation controls are also enabled by default in the Reconfiguration settings tab of the ALTGX_RECONFIG instance.

You must also set the What is the starting channel number? option in the What is the starting channel number? option for every ALTGX instance connected to the ALTGX_RECONFIG instance. For more information, refer to “Logical Channel Addressing” on page 29.

Figure 19. ALTGX MegaWizard Plug-In Manager—Offset Cancellation for the Receiver Channels Option Enabled


Offset Cancellation Control for Receiver Channels Page 39

Figure 20 shows only the Offset Cancellation for Receiver Channels option enabled by default in the ALTGX_RECONFIG MegaWizard Plug-In Manager.

When the device powers up, the dynamic reconfiguration controller initiates offset cancellation on the receiver channel by disconnecting the receiver input pins from the receiver data path. It also sets the receiver CDR into a fixed set of dividers to guarantee a voltage controlled oscillator (VCO) clock rate within the range necessary to provide proper offset cancellation. Subsequently, the offset cancellation process goes through different states, and culminates in offset cancellation of the receiver buffer and receiver CDR. After offset cancellation is complete, the users divider settings are restored.

The dynamic reconfiguration controller sends and receives data to the transceiver channel through the reconfig_togxb and reconfig_fromgxb signals. You must connect these signals between the ALTGX_RECONFIG instance and the ALTGX_instance. You must also set the What is the number of channels controlled by the reconfig controller? option in the Reconfiguration settings tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager. For details about how to set this option, refer to “Total Number of Channels Controlled by the ALTGX_RECONFIG Instance” on page 31.

The Use ‘logical_channel_address’ port option in the Analog controls tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager is not applicable for the receiver offset cancellation process.

Figure 20. ALTGX_RECONFIG MegaWizard Plug-In Manager—Offset Cancellation for the Receiver Channels Option


Page 40 Offset Cancellation Control for Receiver Channels

1 If the design does not require PMA controls reconfiguration and uses optimum logic element (LE) resources, you can connect all the ALTGX instances in the design to a single dynamic reconfiguration controller (ALTGX_RECONFIG instance).

1 The gxb_powerdown signal must not be asserted during the offset cancellation sequence.

1 Refer to “PMA Controls Reconfiguration” on page 2 to understand the impact on system power-up when you control all the transceiver channels using a single dynamic reconfiguration controller.

Consider the scenario where the design has ALTGX instances with channels of both Transmitter only and Receiver only configurations. You must include the Transmitter only channels also while setting the What is the starting channel number? option in the ALTGX instance and while setting the What is the number of channels controlled by the reconfig controller? option in the ALTGX_RECONFIG instance for receiver offset cancellation.

■ After the device powers up, the busy signal remains low for the very first reconfig_clk clock cycle.

■ The busy signal then gets asserted for the second reconfig_clk clock cycle, when the dynamic reconfiguration controller initiates the offset cancellation process.

■ The de-assertion of the busy signal indicates the successful completion of the offset cancellation process.

Figure 21 shows the dynamic reconfiguration signals transition during offset cancellation on receiver channels.

f Due to the offset cancellation process, the transceiver reset sequence has changed. For additional information, refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook.

Figure 21. Dynamic Reconfiguration Signals Transition during Offset Cancellation on the Receiver Channels

Note to Figure 21:

(1) After device power up, the busy signal remains low for the first reconfig_clk cycle.

busy ( 1 )

reconfig_clk



Functional Simulation of the Offset Cancellation Process Page 41

Functional Simulation of the Offset Cancellation ProcessThis section describes the points to be considered during the functional simulation of the dynamic reconfiguration process.

You must connect the ALTGX_RECONFIG instance to the ALTGX_instance/ALTGX instances in your design for functional simulation. The functional simulation uses a reduced timing model of the dynamic reconfiguration controller. Therefore, the duration of the dynamic reconfiguration process is 16 reconfig_clk clock cycles for functional simulation only. The gxb_powerdown signal must not be asserted during the offset cancellation sequence (for functional simulation and silicon).

PMA Controls ReconfigurationYou can reconfigure the following PMA controls that:

■ Pre-emphasis settings

■ Equalization settings

■ DC gain settings

■ Voltage output differential (VOD) settings

Dynamically Reconfiguring PMA ControlsThe ALTGX_RECONFIG MegaWizard Plug-In Manager has the PMA control ports available in the Analog controls tab (Figure 8 on page 14). Depending on which of the PMA controls you want to reconfigure, you can select the appropriate PMA control ports (for example: tx_vodctrl to write new VOD settings or tx_vodctrl_out to read the existing VO D settings).

You can dynamically reconfigure the PMA controls of a transceiver channel using the following methods:

■ Using the logical_channel_address to reconfigure a specific transceiver channel

■ Using the same control signals for all transceiver channels

■ Using different control signals for a specific transceiver channel

These methods are explained in detail in this section. For each method, you can additionally use the rx_tx_duplex_sel port. The width of this port is fixed to 2 bits.

You can enable this port by selecting the Use 'rx_tx_duplex_sel' port to enable RX only, TX only or duplex reconfiguration option in the Error checks/Data rate switch tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

This option is available only when you select the Analog controls option in the Reconfiguration settings tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager. Table 13 shows the allowed values for this port.


Page 42 PMA Controls Reconfiguration

Method 1: Using logical_channel_address to Reconfigure Specific Transceiver Channels

Using this method, you can dynamically reconfigure the PMA controls of a transceiver channel by using the logical_channel_address port without affecting the remaining active channels. You can enable the logical_channel_address_port port by selecting the Use ‘logical_channel_address’ port option in the Analog controls tab, as shown in Figure 8 on page 14. This method is applicable only for a design where the dynamic reconfiguration controller controls more than one channel.

You can additionally reconfigure either the receiver portion, transmitter portion, or both the receiver and transmitter portions of the transceiver channel by setting the corresponding value on the rx_tx_duplex_sel input port.

The following section describes how to connect the PMA controls when using Method 1.

Connecting the PMA Control Ports When using Method 1, the selected PMA control ports remain fixed in width, irrespective of the number of channels controlled by the ALTGX_RECONFIG instance:

■ tx_vodctrl and tx_vodctrl_out are fixed to 3 bits

■ tx_preemp and tx_preemp_out are fixed to 5 bits

■ rx_eqdcgain and rx_eqdcgain_out are fixed to 3 bits

■ rx_eqctrl and rx_eqctrl_out are fixed to 4 bits

Write TransactionSet the selected PMA control ports to the desired settings (for example: tx_vodctrl = 3'b000). Set the input port logical_channel_address to the logical channel address of the transceiver channel whose PMA controls you want to reconfigure. Set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are written to the transceiver channel. Ensure that the busy signal is low before you start a write transaction. Assert the write_all signal for one reconfig_clk clock cycle. This initiates the write transaction.

The busy output status signal is asserted high to indicate that the dynamic reconfiguration controller is busy writing the PMA control values. When the write transaction has complete, the busy signal goes low.

Table 13. Setting the rx_tx_duplex_sel Input Port of the ALTGX_RECONFIG Instance (Note 1)

rx_tx_duplex_sel Reconfiguration Mode

00 Receiver and Transmitter

01 Receiver Only

10 Transmitter Only

11 Unsupported Value

Note to Table 13:

(1) For more information about the rx_tx_duplex_sel port, refer to Table 5 on page 18.


PMA Controls Reconfiguration Page 43

Figure 22 shows the write transaction waveform for Method 1.

Read TransactionConsider the scenario where you want to read the existing VOD values from the transmit VOD control registers of the transmitter portion of a specific channel controlled by the ALTGX_RECONFIG instance. The read transaction in this scenario is explained in the following:

■ Set the input port logical_channel_address to the logical channel address of the transceiver channel whose PMA controls you want to read (for example, tx_vodctrl_out).

■ Set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are read from the transceiver channel.

■ Ensure that the busy signal is low before you start a read transaction.

■ Assert the read signal for one reconfig_clk clock cycle. This initiates the read transaction.

The busy output status signal is asserted high to indicate that the dynamic reconfiguration controller is busy reading the PMA control values. When the read transaction has completed, the busy signal goes low. The data_valid signal gets asserted, indicating that the data available at the read control signal is valid.

Figure 22. Write Transaction Waveform—Use ‘logical_channel_address’ port Option Enabled

Notes to Figure 22:(1) Consider that you want to write to only the transmitter portion of the channel.(2) This waveform assumes that the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the

logical_channel_address port is 2 bits wide.

(2) 2'b00 2'b01

busy

(1) 2'b00 2'b10

3'b000 3'b100

reconfig_clk

write_all



tx_vodctrl [2:0]



Figure 23 shows the read transaction waveform for Method 1.

1 Simultaneous write and read transactions are not allowed.

Method 2: Using the Same Control Signals to Control All Transceiver ChannelsThis method does not require the logical_channel_address port to dynamically reconfigure the PMA controls of the transceiver channels. With this method, the PMA controls of all the transceiver channels connected to the ALTGX_RECONFIG instance are reconfigured.

The Use the same control signal for all the channels option is available in the Analog controls tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager, as shown in Figure 8 on page 14. If this option is enabled, the width of the PMA control ports are fixed as follows:

PMA Control Ports Used in a Write Transaction■ tx_vodctrl is fixed to 3 bits

■ tx_preemp is fixed to 5 bits

■ rx_eqdcgain is fixed to 3 bits

■ rx_eqctrl is fixed to 4 bits

Figure 23. Read Transaction Waveform—Use ‘logical_channel_address port’ Option Enabled

Notes to Figure 23:(1) Consider that you want to read from only the transmitter portion of the channel.(2) This waveform assumes that the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the

logical_channel_address port is 2 bits wide.

read

(2) 2'b00 2'b01

3'b000 3'bXXX 3'b001

busy

(1) 2'b00 2'b10

reconfig_clk



data_valid

tx_vodctrl_out [2:0]



PMA Control Ports Used in a Read Transaction■ tx_vodctrl_out is 3 bits per channel

■ tx_preemp_out is 5 bits per channel

■ rx_eqdcgain_out is 3 bits per channel

■ rx_eqctrl_out is to 4 bits per channel

For example, if the number of channels controlled by the dynamic reconfiguration controller is two, tx_vodctrl_out is 6 bits wide.

Write TransactionThe value you set at the selected PMA control ports gets written to all the transceiver channels connected to the ALTGX_RECONFIG instance.

Consider that you have enabled tx_vodctrl in the ALTGX_RECONFIG MegaWizard Plug-In Manager to reconfigure the VOD of the transceiver channels.

The following are involved in the write transaction to reconfigure the VOD, as shown in Figure 24:

■ Before you initiate a write transaction, set the selected PMA control ports to the desired settings (for example, tx_vodctrl = 3'b000).

■ Set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are written to the transceiver channel.

■ Ensure that the busy signal is low before you start a write transaction.

■ Assert the write_all signal for one reconfig_clk clock cycle. This initiates the write transaction.

■ The busy output status signal is asserted high to indicate that the dynamic reconfiguration controller is busy writing the PMA control values. When the write transaction has completed, the busy signal goes low.

Figure 24. Write Transaction Waveform—Use the same control signal for all the channels Option Enabled

Note to Figure 24:(1) Consider that you want to write to only the transmitter portion of the channel.

busy

(1) 2'b00 2'b10

3'b000 3'b011

reconfig_clk

write_all


tx_vodctrl [2:0]



Read TransactionIf you want to read the existing values from a specific channel connected to the ALTGX_RECONFIG instance, observe the corresponding byte positions of the PMA control output port after the read transaction is completed.

For example, if the number of channels controlled by the ALTGX_RECONFIG is two, the tx_vodctrl_out is 6 bits wide. The tx_vodctrl_out[2:0] corresponds to channel 1, and similarly, tx_vodctrl_out[5:3] corresponds to channel 2.

The following describe the read transaction to the VOD values of the second channel, as shown in Figure 25:

■ Before you initiate a read transaction, set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are read from the transceiver channel.

■ Ensure that the busy signal is low before you start a read transaction.

■ Assert the read signal for one reconfig_clk clock cycle. This initiates the read transaction.

■ The busy output status signal is asserted high to indicate that the dynamic reconfiguration controller is busy reading the PMA control settings.

■ When the read transaction has completed, the busy signal goes low. The data_valid signal gets asserted, indicating that the data available at the read control signal is valid. To read the current VOD values in channel 2, observe the values in tx_vodctrl_out[5:3].

Figure 25 assumes that the transmit VOD settings written in channels 1 and 2 prior to the read transaction are 3'b001 and 3'b010, respectively.


Figure 25. Read Transaction Waveform—Use the same control signal for all the channels Option Enabled

Note to Figure 25:(1) Consider that you want to read from only the transmitter portion of all the channels.

read

busy

6'b000000 6'bXXXXXX 6'b010001

2'b00 2'b10(1)

reconfig_clk

data_valid


tx_vodctrl_out [2:0]



Method 3: Using Different Control Signals to Control all Transceiver ChannelsWhen the Use the same control signal for all the channels option is disabled, the PMA control ports for write transaction are separate for each channel.

PMA Control Ports Used in a Write Transaction■ tx_vodctrl is 3 bits per channel

■ tx_preemp are 5 bits per channel

■ rx_eqdcgain is 3 bits per channel

■ rx_eqctrl is to 4 bits per channel

For example, if you have two channels, the tx_vodctrl is 6 bits wide (tx_vodctrl [2:0] corresponds to channel 1 and tx_vodctrl [5:3] corresponds to channel 2).

PMA Control Ports Used in a Read TransactionThe width of the PMA control ports for a read transaction are always separate for each channel (the same as “Connecting the PMA Control Ports” on page 42).

Write TransactionBecause the PMA controls of all channels are written, if you want to reconfigure a specific channel connected to the ALTGX_RECONFIG instance, set the new value at the corresponding PMA control port of the channel under consideration and retain the previously stored values in the other active channels using a read transaction prior to this write transaction.

For example, assuming that the number of channels controlled by the ALTGX_RECONFIG is two, the tx_vodctrl in this case is 6 bits wide. The tx_vodctrl[2:0] corresponds to channel 1, and similarly, tx_vodctrl[5:3] corresponds to channel 2.

■ If you want to dynamically reconfigure the PMA controls of only channel 2 with a new value, first perform a read transaction to retrieve the existing PMA control values from tx_vodctrl_out[5:0]. Use the tx_vodctrl_out[2:0] value for tx_vodctrl[2:0] to write in channel 1. By doing so, channel 1 is overwritten with the same value.

■ Perform a write transaction. This ensures that the new values are written only to channel 2, while channel 1 remains unchanged.



Figure 26 shows a write transaction waveform with the Use the same control signal for all the channels option disabled.


Read TransactionThe read transaction is explained in “Read Transaction” on page 43.

PMA Control Reconfiguration ExamplesThe following design examples illustrate the various possible topologies of the dynamic reconfiguration controller with ALTGX instances. The first two design examples specifically describe a single controller controlling multiple instances of an ALTGX megafunction and a single controller controlling one instance of an ALTGX megafunction. Design example three describes the HDL construct requirements if you are stamping the ALTGX instances. Each ALTGX instance can have more than one transceiver channel. The dynamic reconfiguration of PMA controls is enabled for all the design examples.

Example 1: One Reconfiguration Controller Connected to Multiple ALTGX InstancesConsider a design as described in “Case 1b” on page 34:


■ ALTGX instance 1 with five channels


Assume the following for this example:

■ ALTGX instance 1 and ALTGX instance 2 cannot be physically packed into the same transceiver block.

Figure 26. Write Transaction Waveform—Use the same control signal for all the channels Option Disabled

Notes to Figure 26:(1) Consider that you want to write to only the transmitter portion of the channel.(2) The waveform assumes that the number of channels controlled by the dynamic reconfiguration controller (ALTGX_RECONFIG instance) is two

and that the tx_vodctrl control port is enabled.

busy

(2) 6'b000000 6'b000011

2'b00 2'b10(1)

reconfig_clk

write_all


tx_vodctrl [5:0]



■ One dynamic reconfiguration controller controls both the ALTGX instances.

■ You want to dynamically reconfigure the transmit VOD PMA control (tx_vodctrl) of the first channel of ALTGX instance 1 and receiver equalization PMA control (rx_eqctrl) of the second channel of the ALTGX instance 2.

■ You are using logical channel addressing feature in ALTGX megafunction.

Figure 27 shows the ALTGX_RECONFIG instance connected to both ALTGX instance 1 and ALTGX instance 2.

The following are the typical steps that help set up the dynamic reconfiguration process.

Setting the ALTGX Instances

1. Refer to “Case 1b” on page 34 to set up the logical channel addressing for both ALTGX instances.

2. Enable the Analog controls (VOD, pre-emphasis, and manual equalization) option in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager.

Figure 27. Example 1 for PMA Controls Reconfiguration

read

write busy



ALTGX instance 1(no. of channels is 5)




data_valid







rx_eqctrl [3:0]

tx_vodctrl [2:0]

reconfig_clk

Set the What is the number ofchannels controlled by the

reconfig controller? option = 12



Setting the ALTGX_RECONFIG Instance

1. Refer to “Case 1b” on page 34 to set up the logical channel control for the ALTGX_RECONFIG instance.

2. Select the rx_tx_duplex_sel [1:0] port in the Error checks/Data rate switch tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

3. Select the tx_vodctrl and rx_eqctrl controls. tx_vodctrl is 3 bits wide and rx_eqctrl is 4 bits wide.

ALTGX Instances and ALTGX_RECONFIG Instance Connections

Refer to steps shown in “Connecting the reconfig_from_gxb/reconfig_to_gxb Ports” on page 36 to connect the ALTGX instances to the ALTGX_RECONFIG instance.

Figure 28 shows the write transaction waveform for Example 1.

Example 2: Two ALTGX_RECONFIG Instances Connected to Two ALTGX InstancesThis design example has two instances of distinct configurations: ALTGX instance 1 with five transceiver channels and ALTGX instance 2 with three channels.

This configuration requires separate dynamic reconfiguration controllers for the two instances. This scenario covers the case of multiple dynamic reconfiguration controllers controlling multiple instances of the ALTGX.

Figure 28. Write Transaction Waveform for Example 1

(2) 4'b0000 4'b0000

busy

(1) 2'b00 2'b10

3'b000 3'b100

4'b0000 4'b1000

2'b01

4'b1001

reconfig_clk

write_all



tx_vodctrl [2:0]

rx_eqctrl [3:0]

(receiver portion)

(Channel 1 of ALTGX instance 2)

(transmitter portion)




Figure 29 shows the ALTGX_RECONFIG instance 1 connected to the ALTGX instance 1 and ALTGX_RECONFIG instance 2 connected to the ALTGX instance 2.

Assume that you want to reconfigure the transmit VOD PMA control of the second channel of ALTGX instance 1 and the receive equalization PMA control of the third channel of ALTGX instance 2. The following are the typical steps to set up the configuration:

Setting the ALTGX Instances

1. Refer to “Case 1b” on page 34 to set up the logical channel addressing for both ALTGX instances.


Setting the ALTGX_RECONFIG Instance

1. Refer to “Case 1b” on page 34 to set up the logical channel control for the ALTGX_RECONFIG instance.

2. Select the rx_tx_duplex_sel [1:0] port in the Error checks/Data rate switch tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

3. Select the tx_vodctrl and rx_eqctrl controls. tx_vodctrl is 3 bits wide and rx_eqctrl is 4 bits wide.

Figure 29. Example 2 for PMA Controls Reconfiguration






reconfig_fromgxb [16:0]busy [1]

data_valid [1]


Set the What is the number ofchannels conrolled by the

controller? option = 4

ALTGX_RECONFIGinstance 2

rx_tx_duplex_sel_1 [1:0]


logical_channel_address_1 [1:0]

rx_eqctrl [3:0]

write [1]

read [1]

reconfig_clk

Set the What is the number ofchannels conrolled by the

controller? option = 8


data_valid [0]

busy [0]

ALTGX_RECONFIGinstance 1




tx_vodctrl [3:0]

write_0

read_0

reconfig_clk



ALTGX Instances and ALTGX_RECONFIG Instances Connections

Refer to steps shown in “Connecting the reconfig_from_gxb/reconfig_to_gxb Ports” on page 36 to connect the ALTGX instances to ALTGX_RECONFIG instance.

Figure 30 shows the write transaction waveform for “Example 2: Two ALTGX_RECONFIG Instances Connected to Two ALTGX Instances” on page 50.

Example 3: One ALTGX_RECONFIG Instance Connected to an ALTGX Instance Stamped Five Times This design example consists of five channels of transceivers. This configuration has one dynamic reconfiguration controller to control five channels. This scenario covers the case stamping five instantiations of one channel ALTGX instance configuration.

ALTGX Instance with One Transceiver Channel

1. Set the What is the number of channels? option in the General tab of the ALTGX MegaWizard Plug-In Manager to 1.

Figure 30. Write Transaction Waveform for Example 2

(2) 3'b000 3'b001

(1) 2'b00 2'b10

3'b000 3'b100

4'b0000 4'b1000

(2) 2'b00 2'b10

(1) 2'b00 2'b01

reconfig_clk

write [0]

write [1]





busy [0]

busy [1]

tx_vodctrl [2:0]

rx_eqctrl [3:0]

(transmitt portion for ALTGX instance 1)

(receiver portion for ALTGX instance 2)






3. The reconfig_fromgxb output signal is transceiver block based so the number of bits for this instance is 17. This is because the number of channels is one and it can logically fit into a single transceiver block. The reconfig_togxb input signal is a fixed bus (four bits).

4. Set the What is the starting channel number? option in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager to 0. For more information, refer to “Logical Channel Addressing” on page 29.

5. Click Finish.

6. Assume that the instantiation name is “instance1”.

Instantiating Five Transceiver Channels Using the Same ALTGX Instance

When you stamp instance 1 five times, the What is the starting channel number? options of the other four stamped instances (assume instance2, instance3, instance4, instance5, and instance6) are 4, 8, 12, and 16, respectively. For more information, refer to “Logical Channel Addressing” on page 29.

Dynamic Reconfiguration Controller Instance (ALTGX_RECONFIG Instance)

1. Launch the ALTGX_RECONFIG MegaWizard Plug-In Manager.

2. Set the What is the number of channels controlled by the reconfig controller? option in the Reconfiguration settings tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager to 20. This enables five sets of MegaWizard Plug-In Manager signals. (reconfig_fromgxb[84:0]). Connect each of the stamped ALTGX instance to one set of MegaWizard Plug-In Manager signals.

3. Select the necessary write and read controls to write in and read out from the VOD, pre-emphasis, equalization, and DC gain options. For example, if you select the VOD setting: the tx_vodctrl signal is 60 bits wide (3 bits per channel). tx_vodctrl [2:0] corresponds to the single channel of the first stamped instance. The bits tx_vodctrl [11:3] are not used because they correspond to the unused channels in the first stamped instance with logical channel addresses 1 to 3. Similarly, tx_vodctrl [14:12] corresponds to the single channel of the second stamped instance, and so on.

ALTGX Instances and ALTGX_RECONFIG Instance Connections

1. Connect the reconfig_fromgxb signal from each ALTGX instance to the same signal in the ALTGX_RECONFIG instance. You must connect it in such that a way that the reconfig_fromgxb output port of the first ALTGX instance (ALTGX instance with the What is the starting channel number? option of 0) is connected to the LSB of the reconfig_fromgxb input port of the ALTGX_RECONFIG instance, and so on.

2. Connect the reconfig_togxb signal from the ALTGX_RECONFIG instance to the same signal in each of the ALTGX instances.


Page 54 Error Indication in the ALTGX_RECONFIG MegaWizard Plug-In Manager

Dynamically Reconfiguring the tx_vodctrl of Instance 1 Using Method 2

1. Set the tx_vodctrl port to the desired setting. For example, if you want to write a VOD value of 2, set the tx_vodctrl [2:0] port to 3'b010.

2. For more information, refer to “Method 1: Using logical_channel_address to Reconfigure Specific Transceiver Channels” on page 42.

1 When you perform a write transaction using “Method 2: Using the Same Control Signals to Control All Transceiver Channels” on page 44, the values on the PMA control ports are written on all transceiver channels connected to the dynamic reconfiguration controller. Therefore, ensure that you also have the desired values on tx_vodctrl [59:3]. If you want to make sure that the VOD settings of the remaining channels are not affected, you can optionally perform a read transaction, and obtain the existing values and write back the same values.

Error Indication in the ALTGX_RECONFIG MegaWizard Plug-In ManagerThe ALTGX_RECONFIG MegaWizard Plug-In Manager provides an error status signal when you select the Enable illegal mode checking option or the Enable self recovery option in the Error checks/data rate switch tab. The conditions under which the error signal is asserted are:

■ Enable illegal mode checking option—When you select this option, the dynamic reconfiguration controller checks whether an attempted operation falls under one of the conditions listed below. The dynamic reconfiguration controller detects these conditions within two reconfig_clk cycles, de-asserts the busy signal, and asserts the error signal for two reconfig_clk cycles.

■ PMA controls, read operation—None of the output ports (rx_eqctrl_out, rx_eqdcgain_out, tx_vodctrl_out, and tx_preemp_out) are selected in the ALTGX_RECONFIG instance.

and

The read signal is asserted

■ PMA controls, write operation—None of the input ports (rx_eqctrl, rx_eqdcgain, tx_vodctrl, and tx_preemp) are selected in the ALTGX_RECONFIG instance.

and

The write_all signal is asserted.

■ Enable self recovery option—When you select this option, the controller automatically recovers if the operation did not complete within the expected time. The error signal is driven high whenever the controller performs a self recovery.


Combining Transceiver Channels with Dynamic Reconfiguration Enabled Page 55

Combining Transceiver Channels with Dynamic Reconfiguration Enabled

Packing the transceiver channels into the same physical transceiver block is called "combining". You can combine the transceiver channels in a design into the same physical transceiver block by assigning the tx_dataout and rx_datain pins of the channels to the same transceiver block. By default, the software automatically packs the transceiver channels in the same physical transceiver block based on certain requirements which are described the following sections.

The Quartus II software also allows you to combine multiple channels into the same physical transceiver block based on the same requirements described in the following sections.

RequirementsWhen dynamic reconfiguration is enabled, the Quartus II software has certain requirements for combining multiple transceiver channels in the same physical transceiver block:

■ All the channels that you want to combine into the same transceiver block need to have the same options enabled in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager. When you enable the Analog controls (VOD, pre-emphasis, and manual equalization) option in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager for a channel, you need to enable the same option for all the other channels to be combined.

■ All the channels must be controlled by the same ALTGX_RECONFIG (dynamic reconfiguration controller) instance. The transceiver channels connected to multiple ALTGX_RECONFIG instances cannot be combined into the same physical transceiver block, even if they are configured to the same functional mode and data rate.

Combining a Transmitter Only Instance and Receiver Only Instance.Consider that you want to combine one Receiver only instance and another Transmitter only instance in the same transceiver block:

■ The Receiver only instance must be controlled by an ALTGX_RECONFIG instance for offset cancellation control.

■ Because you want to combine the Receiver only instance with another Transmitter only instance into the same transceiver block, you must control the Transmitter only instance using the same ALTGX_RECONFIG instance.

■ Therefore, you must enable the same option in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager for both the Transmitter only and Receiver only instances.

■ There are constraints with the independent Transmitter only and independent Receiver only configurations. Both transmitter and receiver have to go through a reset sequence, even if the transmitter or receiver is reconfigured.


Page 56 Dynamic Reconfiguration Duration and FPGA-Fabric Resource

Dynamic Reconfiguration Duration and FPGA-Fabric Resource Utilization

This section describes the time taken for dynamic reconfiguration transactions and FPGA-fabric resources used by the dynamic reconfiguration controller when used in different modes of reconfiguration.

Dynamic Reconfiguration DurationDynamic reconfiguration duration is the number of cycles for which the busy signal is asserted when the dynamic reconfiguration controller performs write transactions, read transactions, or offset cancellation of receiver channels.

PMA Controls Reconfiguration DurationThe following section gives an estimate of the number of reconfig_clk clock cycles for which the busy signal is asserted during the PMA controls reconfiguration using “Method 1: Using logical_channel_address to Reconfigure Specific Transceiver Channels” on page 42 and “Method 2: Using the Same Control Signals to Control All Transceiver Channels” on page 44.

PMA Controls Reconfiguration Duration When Using Method 1The logical_channel_address port is used in this method. The write transaction and read transaction duration is as follows:

Write Transaction Duration

For writing values to the following PMA controls, the busy signal is asserted for 260 reconfig_clk clock cycles for each of these controls:

■ tx_preemp (pre-emphasis control)

■ tx_vodctrl (voltage output differential)

■ rx_eqctrl (equalizer control)

■ rx_eqdcgain (equalizer DC gain)

Read Transaction Duration

For reading the existing values of the following PMA controls, the busy signal is asserted for 130 reconfig_clk clock cycles for each of these controls. The data_valid signal is then asserted when the busy signal goes low.

■ tx_preemp_out (pre-emphasis control)

■ tx_vodctrl_out (voltage output differential)

■ rx_eqctrl_out (equalizer control)

■ rx_eqdcgain_out (equalizer DC gain)


Dynamic Reconfiguration (ALTGX_RECONFIG Instance) Resource Utilization Page 57

PMA Controls Reconfiguration Duration When Using Method 2The logical_channel_address port is NOT used in this method. The write transaction duration and read transaction duration is as follows:

Write Transaction Duration

For writing values to the following PMA controls, the busy signal is asserted for 260 reconfig_clk clock cycles per channel for each of these controls.

■ tx_preemp (pre-emphasis control)

■ tx_vodctrl (voltage output differential)

■ rx_eqctrl (equalizer control)

■ rx_eqdcgain (equalizer DC gain)

Read Transaction Duration

For reading the existing values of the following PMA controls, the busy signal is asserted for 130 reconfig_clk clock cycles per channel for each of these controls. The data_valid signal is then asserted when the busy signal goes low.

■ tx_preemp_out (pre-emphasis control)

■ tx_vodctrl_out (voltage output differential)

■ rx_eqctrl_out (equalizer control)

■ rx_eqdcgain_out (equalizer DC gain)

Offset Cancellation Duration

When the device powers up, the busy signal remains low for the first reconfig_clk clock cycle. After the device powers up, it takes 70 reconfig_clk clock cycles for the dynamic reconfiguration controller to identify the receiver channels.

When it identifies the receiver channels, the dynamic reconfiguration controller takes another 2600 reconfig_clk clock cycles to perform the offset cancellation process. In other words, the busy signal goes low after 2670 (70 + 2600) reconfig_clk clock cycles per receiver channel.

1 If the design does not require PMA controls reconfiguration, each ALTGX instance in the design can have its own dynamic reconfiguration controller (ALTGX_RECONFIG instance). This minimizes the offset cancellation duration.

Dynamic Reconfiguration (ALTGX_RECONFIG Instance) Resource Utilization

You can observe the resources utilized during dynamic reconfiguration in the ALTGX_RECONFIG MegaWizard Plug-In Manager itself. The following sections give an estimate of the logic element resources utilized during dynamic reconfiguration.

You can obtain the resource utilization for all other PMA controls from the ALTGX_RECONFIG MegaWizard Plug-In Manager.


Page 58 Transceiver Channel Reconfiguration Modes

For example, the number of LEs used by one dynamic reconfiguration controller is 39 with only tx_vodctrl selected. Similarly, the number of registers is 125.

Figure 31 shows the resource utilization in the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Transceiver Channel Reconfiguration ModesThis section describes the following dynamic reconfiguration modes in detail:

■ Data Rate Division in TX

■ Channel and TX PLL select/reconfig

■ CMU PLL reconfiguration

■ Channel and CMU PLL reconfiguration

■ Channel reconfiguration with TX PLL select

1 You can enable the above dynamic reconfiguration modes together by selecting the Channel and Transmitter PLL Reconfiguration option in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager (as shown in Figure 16 on page 30). You do not have the option to individually enable any of the above dynamic reconfiguration modes.

Figure 31. ALTGX_RECONFIG MegaWizard Plug-In Manager—Resource Utilization


Transceiver Channel Reconfiguration Modes Page 59

Figure 32 shows the Channel and Transmitter PLL Reconfiguration option in the ALTGX MegaWizard Plug-In Manager.

Data Rate Division in TX ModeYou can use the Date Rate Division in TX mode to modify the data rate of the transmitter channel in multiples of 1, 2, and 4. This dynamic reconfiguration mode is available ONLY for the transmit side and not for the receive side.

Blocks Reconfigured in the Data Rate Division in TX ModeThe only block that gets reconfigured by this mode is the TX local divider block of a transmitter channel. You can set the TX local divider to a divide by value of /1, / 2, or /4, as shown in Figure 33.

Figure 32. ALTGX MegaWizard Plug-In Manager— Channel and Transmitter PLL Reconfiguration Option

Figure 33. Local Divider of a Transmitter Channel

CMU0 High-SpeedClock Output

CMU1 High-SpeedClock Output

CMU0 Clock Divider Block

/N (1, 2, 4)/S

(4, 5, 8, 10)coreclkout to FPGA Fabric

(for Bonded Modes)

High-Speed Serial Clock (for Bonded Modes)

Low-Speed Parallel Clockfor Transmitter Channel PCS

(for Bonded Modes)

/2



You must be aware of the device operating range before you enable and use this feature. There are no legal checks that are imposed by the Quartus II software because it is an on-the-fly control feature. You also need to ensure that a specific functional mode supports the data rate range before dividing the clock when using this rate switch option.

ALTGX_RECONFIG MegaWizard Plug-In Manager Setup The settings available for the Data Rate Division in TX mode are:

1. Set the What is the number of channels controlled by the reconfig controller? option in the Reconfiguration settings tab. For more information, refer to the “Total Number of Channels Controlled by the ALTGX_RECONFIG Instance” on page 31.

2. Specify the logical channel address of the transmitter channel at the logical_channel_address input port.

3. Select the Data Rate Division in TX option in the Reconfiguration settings tab, as shown in Figure 10 on page 20.

The rate_switch_ctrl [1:0] input port is available when you enable the Data Rate Division in TX option. The value you set at the rate_switch_ctrl [1:0] signal determines the TX local divider settings, as shown in Table 14.

If you want to read the existing local divider settings of the transmitter channel, select the Use 'rate_switch_out' port option to read out the current data rate division option in the Error checks/Data rate switch tab, as shown in Figure 11 on page 21.

The decoding for rate_switch_out [1:0] output signal is the same as the rate_switch_ctrl [1:0] input signal.

1 The dynamic rate switch has no effect on the dividers on the receive side of the transceiver channel. It can be used only for the transmitter.

1 The Data Rate Division in TX mode does not require a .mif.

For more information about read and write transactions, refer to “Data Rate Division in TX Mode” on page 59.

Table 14. TX Local Divider Settings based on the rate_switch_ctrl[1:0] Port

rate_switch_ctrl[1:0] Local Divider Settings

00 Receiver and Transmitter

01 Receiver Only

10 Transmitter Only

11 Unsupported Value



ALTGX MegaWizard Plug-In Manager SetupEnable the following settings in the ALTGX MegaWizard Plug-In Manager:

1. Select the Channel and Transmitter PLL Reconfiguration option in the Reconfig tab (shown in Figure 32 on page 59) to enable the ALTGX_RECONFIG instance to modify the TX channel local divider values dynamically.

2. Set the What is the starting channel number? option in the Reconfig tab. For more information, refer to “Logical Channel Addressing” on page 29.

1 The alternate reference clock is not required because a single clock source is used. The /1, /2, or /4 data rates can be derived from the single input reference clock.

Data Rate Division in TX: OperationThe following sections describe the steps involved in a write and read transaction for Data Rate Division in TX mode.

Data Rate Division in TX: Write Transaction

1. Set the reconfig_mode_sel [2:0] signal to 011 to activate this mode.

2. Set the rate_switch_ctrl [1:0] signal to the corresponding TX local divider setting.

3. Set the logical_channel_address port to the logical channel address of the transmitter channel whose local divider settings you want to reconfigure.

4. Ensure that the busy signal is low.

5. Initiate a write transaction by asserting the write_all signal for one reconfig_clk cycle.



Figure 34 shows a write transaction waveform in this mode.

Data Rate Division in TX: Read Transaction


2. Select the rate_switch_out [1:0] to read out the existing TX local divider settings.

3. Set the logical_channel_address port to the logical channel address of the transmitter channel whose local divider settings, you want to read.


5. Assert the read signal for one reconfig_clk cycle.

Figure 34. Data Rate Division in TX: Write Transaction

Notes to Figure 34:(1) The waveform assumes that you want to reconfigure the local divider settings of the transmitter channel to Divide by 4. Therefore, the value set

at rate_switch_ctrl [1:0] is 2'b10.(2) The waveform assumes that the value set in the What is the number of channels controlled by the reconfig controller? option of the

ALTGX_RECONFIG MegaWizard Plug-In Manager is 4. Therefore, the logical_channel_address input is 2 bits wide. (3) The waveform also assumes that you want to reconfigure the local divider settings of the transmitter channel whose logical channel address is

2'b01.

busy

2'bXX 2'b01

2'bXX 2'b10 2'bXX

2'bXX

3'b0113'bXXXreconfig_mode_sel [2:0]

reconfig_clk

rate_switch_ctrl [1:0] (1)

logical_channel_address (2), (3)

write_all



Figure 35 shows a read transaction waveform in this mode.

1 Do not perform a read transaction in Date Rate Division in TX mode if rate_switch_out [1:0] is not selected in the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Data Rate Division in TX Mode: Design ExampleThis design example explains the steps to dynamically divide the transmit data rate of a transceiver channel by 4, 2, or 1 without requiring .mif generation.

1 Use the rate_switch_ctrl [1:0] signal only for dividing the data rate of the transmit side. To divide the data rate for both transmit and receive sides, a .mif based approach is required.

Consider the following for this example:

■ ALTGX instance 1: Two transceiver channels configured in Basic functional mode with 8B/10B enabled and running at 2.5 Gbps data rate. You can reconfigure the mode dynamically among these three data rates: 2.5 Gbps, 1.25 Gbps, and 675 Mbps.

■ ALTGX_RECONFIG instance 1: A single dynamic reconfiguration controller connected to the ALTGX instance 1.

Figure 35. Data Rate Division in TX: Read Transaction

Notes to Figure 35:(1) The waveform assumes that the existing local divider settings of the transmitter channel are Divide by 2. Hence, the value read out at

rate_switch_out [1:0] is 2'b01.(2) The waveform assumes that the value set in the What is the number of channels controlled by the reconfig controller? option of the

ALTGX_RECONFIG MegaWizard Plug-In Manager is 4. Therefore, the logical_channel_address input is 2 bits wide. (3) The waveform assumes that you want to read the existing local divider settings of the transmitter channel whose logical channel address is 2'b01.

read

busy

2'bXX 2'b01

2'bXX 2'b01

2'bXX

3'b0113'bXXXreconfig_mode_sel [2:0]

reconfig_clk

logical_channel_addres (1), (2)

rate_switch_out [1:0] (3)

data_valid

Invalid output



ALTGX Instance 1 Settings

■ Create a Basic functional mode by setting the operation mode to Receiver and Transmitter configuration.

■ Select single-width mode.

■ You can set the channel width to 8 or 16. Therefore, if the transceiver runs at 675 Mbps with a 16-bit FPGA fabric-Transceiver interface, the FPGA fabric clock frequency in this case will be 33.75 MHz (675/20 = 33.75).

■ Set the input frequency to 67.5 MHz.

■ Select the Channel and Transmitter PLL Reconfiguration option in the Reconfig tab. This is required to enable the ALTGX_RECONFIG instance to modify the channel local divider values dynamically. The alternate reference clock is not required because one clock source is used. Also, all the data rates can be derived from the 67.5 MHz clock.

■ Click Finish to complete the ALTGX MegaWizard Plug-In Manager instantiation.

ALTGX_RECONFIG Instance 1 Settings

1. Select the Data Rate Division in TX option in the Reconfiguration Settings tab. This creates the rate_switch_ctrl [1:0] input signal. You can optionally enable the rate_switch_out [1:0] output signal by selecting the Use rate_switch_out port to read out the current data rate division option in the Error checks/Data rate switch tab. Table 14 on page 60 shows the values for each of the rate_switch_ctrl [1:0] settings.

2. Click Finish to complete the ALTGX_RECONFIG MegaWizard Plug-In Manager instantiation.

Create the Top Level Design

1. Create the ALTGX_RECONFIG instance control logic, reset control logic, and the FPGA fabric logic to handle the data path.

f For information on transceiver resets, refer to the “Reset Recommendations" section of the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook.

2. Connect the reconfig_fromgxb [16:0] and reconfig_togxb [3:0] signals between the ALTGX instance 1 and ALTGX_RECONFIG instance 1.

Channel and TX PLL select/reconfig ModesThe dynamic reconfiguration modes grouped under the Channel and TX PLL select/reconfig option require a .mif to be generated. The following section describes this is in detail.




.mif Generation When you reconfigure the functional mode and/or the data rate of a transceiver channel, the dynamic reconfiguration controller requires that you provide a 16-bit word (reconfig_data [15:0]) on every write transaction, using the write_all signal. This 16-bit word is part of a .mif, that is generated by the Quartus II software when you compile an ALTGX instance.

1 The dynamic reconfiguration controller ignores a new 16-bit word if the previously initiated write transaction is not complete. As explained previously in this document, an ongoing or active write transaction is signified by the busy signal. You can only input a new word of 16-bits when the busy signal is de-asserted.

Design FlowThe Quartus II software provides a design flow called user memory initialization file flow. This design flow involves writing specific contents of the .mif for a channel or CMU PLL or channel and CMU PLL based on the dynamic reconfiguration mode you select.

The Quartus II software generates the .mifs when you provide the appropriate project settings and then compile an ALTGX instance. For more information about these project settings, refer to “.mif Generation”.

Each .mif can have the settings for:

■ Receiver and transmitter portions of a transceiver channel

■ Transmitter portion of a transceiver channel

■ Receiver portion of a transceiver channel

These settings are all legal register settings of the transceiver channel. The ALTGX_RECONFIG instance reads the value in the .mif using the reconfig_data [15:0] port for every write transaction.

The size of the .mif is fixed to thirty eight 16-bit words.

The Quartus II software creates the .mif under the <Project_DIR>/reconfig_mif folder. The file name is based on the ALTGX instance name and the logical channel address of the channel undergoing dynamic reconfiguration; for example, basic_gxb_5.mif. (<instance name>_<logical_channel_num>.mif).

You can change the .mif name. One design can have multiple .mifs (there is no limit) and you can use one .mif to reconfigure multiple channels. These .mifs can be stored in on-chip or off-chip memory.

Quartus II settings for .mif generationThe .mif is not generated by default in a Quartus II compilation. This section describes the Quartus II software settings you must enable to generate a .mif file. The three steps to enable .mif generation are shown below:

1. On the Assignments menu, select Settings (Figure 36).



2. Select Fitter settings, then click More Settings (Figure 37).

Figure 36. Step 1 to Enable .mif Generation

Figure 37. Step 2 to Enable .mif Generation



3. On the More Fitter Settings page in the Option box, set one of the following options to On based on the dynamic reconfiguration mode enabled:

a. If you enable Channel Reconfiguration with TX PLL Select mode, set the Generate Arria II GX GXB reconfig MIF option to On (Figure 38).

b. If you enable Channel and CMU PLL Reconfiguration or CMU PLL reconfiguration modes, set the Generate Stratix IV GX/Arria II GX GXB reconfig MIF with PLL option to On (Figure 38).

The .mif is generated in the Assembler stage of the compilation process. However, for any change in the design or the above settings, the Quartus II software runs through the fitter stage before starting the assembler stage.

CMU PLL Reconfiguration Mode You can use this mode to reconfigure the data rate of a transceiver channel. Use this mode to reconfigure only the CMU PLL without affecting the remaining blocks of the transceiver channel. When you reconfigure the CMU PLL of a transceiver block to run at a different data rate, all the transceiver channels listening to this CMU PLL also get reconfigured to the new data rate. This reconfiguration mode is a .mif-based approach.

1 The logical_channel_address port is not applicable in CMU PLL Reconfiguration mode, even though it is available as an input.

Figure 38. Step 3a to Enable .mif Generation



Blocks Reconfigured in the CMU PLL Reconfiguration Mode

Each transceiver block has two CMU PLLs: CMU PLL 0 and CMU PLL 1.You can reconfigure each of these CMU PLLs to a different data rate in dynamic reconfiguration mode. Figure 39 shows a conceptual view of both the CMU PLLs in a transceiver block.

ALTGX MegaWizard Plug-In Manager Setup

When you intend to reconfigure the CMU PLL to another data rate, enable .mif generation and set up the ALTGX MegaWizard Plug-In Manager as listed below. The dynamic reconfiguration controller reconfigures the CMU PLL with the new information stored in the .mif.

1. Select the Channel and Transmitter PLL reconfiguration option in the Reconfig tab of the ATLGX and ALTGX_RECONFIG MegaWizard Plug-In Manager.

2. Provide the new data rate at which you want the CMU PLL to run at in the General tab.

3. Provide the logical reference index value in the What is the main PLL logical reference index? option in the Reconfig Clks tab.

Figure 39. CMU PLLs in a Transceiver Block

TX CHANNEL

refclk1

clockmux

clockmux

refclk0

Clock Multiplier Unit

CMU PLL 0

CMU PLL 1

LogicalTX PLLselect

LOCALDIVIDER

full duplex transceiver channel

digital + analog logic

RX CHANNEL

TX PLL digital + analog logicclockmux

Blocks that can be reconfigured in CMU PLL Reconfiguraiton mode.



Logical Reference Index of the CMU PLL

Figure 40 shows that transceiver channel 1 listens to CMU PLL 1 of the transceiver block. Similarly, transceiver channel 2 listens to CMU PLL 2 of the transceiver block.

You can direct the dynamic reconfiguration controller to dynamically reconfigure CMU PLL 0 by specifying its logical reference index. The logical reference index is the identity of the CMU PLL 0. Similarly, you can direct the dynamic reconfiguration controller to dynamically reconfigure CMU PLL 1 instead by providing the logical reference index of CMU PLL 1.

This value is stored as the reference index value, along with the other transceiver channel settings in the generated .mif.

Provide the number of input reference clocks available for the CMU PLL in the How many input clocks? option in the Reconfig Clks tab. The maximum number of input reference clocks allowed is 10.

Figure 40. Logical Reference Index of CMU PLLs in a Transceiver Block


clockmux

clockmux

3.125 Gbps

CMU PLL 0

2.5 Gbps

CMU PLL 1

refclk0

refclk1

156.25 MHz

125 MHz

full duplex transceiver channel 1

TX CHANNEL 1

LogicalTX PLLselect

LOCALDIVIDER

3.125 Gbps


3.125 Gbps


3.125 Gbps

RX PLL

clockmux

full duplex transceiver channel 2

RX CHANNEL 1

TX CHANNEL 2

LogicalTX PLLselect

LOCALDIVIDER

2.5 Gbps


RX CHANNEL 2

clockmux

2.5 Gbps

RX PLL

2.5 Gbps




Provide the identification of the input reference clock used by the CMU PLL in the What is the selected input clock source for the Transmitter PLL and Receiver PLL? option in the Reconfig Clks tab.

1 You can reuse the .mif generated for one CMU PLL to reconfigure the other CMU PLL in the same or in other transceiver blocks.

ALTGX_RECONFIG MegaWizard Plug-In Manager Setup

The settings available for the CMU PLL Reconfiguration mode are:

1. In the Reconfiguration settings tab, set the What is the number of channels controlled by the reconfig controller? option. For more information, refer to the “Total Number of Channels Controlled by the ALTGX_RECONFIG Instance” on page 31.

2. In the Reconfiguration settings tab, select the Channel and TX PLL select/reconfig option, as shown in Figure 12 on page 23.

The ALTGX_RECONFIG MegaWizard Plug-In Manager enables the channel_reconfig_done output signal, when you enable the Channel and TX PLL select/reconfig option. The dynamic reconfiguration controller asserts this signal to indicate that the 38 words of the .mif have been written into the transceiver.

The following options are not required, but are available for selection in the Channel and TX PLL Reconfiguration tab:

■ reconfig_address_out [5:0]—This output signal provides the address value that you can use to read the appropriate word from the .mif. Use the value at this port in combination with the reconfig_address_en signal to decide when to write the next word.

■ reset_reconfig_address—Use this signal to reset the reconfig_address_out value to 0.

■ reconfig_address_en—The ALTGX_RECONFIG instance asserts this output signal to indicate the change in value on the reconfig_address_out port. This signal only gets asserted after the dynamic reconfiguration controller completes writing a 16-bit word of the .mif.

■ logical_tx_pll_sel—You can reuse the .mif created for one CMU PLL on another CMU PLL using the optional logical_tx_pll_sel port in the ALTGX_RECONFIG MegaWizard Plug-In Manager. If the logical_tx_pll_sel port is enabled, the dynamic reconfiguration controller uses the value on this port irrespective of the reference index value stored in the .mif. By using this port, you specify the identity of the CMU PLL that you intend to reconfigure.

■ logical_tx_pll_sel_en—If you want to use the logical_tx_pll_sel only under some conditions and use the reference index value stored in the .mif; otherwise, enable the logical_tx_pll_sel_en port. If this port is enabled, the dynamic reconfiguration controller uses the value on the logical_tx_pll_sel port ONLY if the logical_tx_pll_sel_en port is set to 1 (Figure 43).

1 The values at logical_tx_pll_sel and logical_tx_pll_sel_en need to be held at a constant logic level until reconfiguration is completed.



Logical TX PLL Selection

Figure 41 explains how the dynamic reconfiguration controller selects between the reference index stored in the .mif and the reference index specified at the logical_tx_pll_sel port.

Table 15 shows the selected logical_tx_pll value under all the combinations of these two signals.

When you configure a transceiver channel in the ALTGX MegaWizard Plug-In Manager, Altera recommends that you keep track of the transmitter PLL that drives the channel.

1 The logical_tx_pll_sel port does not modify any transceiver setting on the RX side.

Figure 42 shows the required signal transitions to reconfigure the CMU PLL with a logical_tx_pll value of 1. Keep the logical_tx_pll_sel and logical_tx_pll_sel_en signals at a constant logic level until the dynamic reconfiguration controller asserts the channel_reconfig_done signal.

Figure 41. Using logical_tx_pll_sel and logical_tx_pll_sel_en Ports

0

1

reference indexvalue stored in

the .mif

logical_tx_pll_sel


selected logical tx pll value


Table 15. Various Combinations of logical_tx_pll_sell and logical_tx_pll_sel_en Ports

logical_tx_pll_sel logical_tx_pll_sel_enlogical_tx_pll value selected by the

ALTGX_RECONFIG Instance

Enabled Enabled and value is 1 Value on the logical_tx_pll_sel port

Enabled Enabled and value is 0 Reference index value stored in the .mif

Enabled Disabled Value on the logical_tx_pll_sel port

Disabled Disabled Reference index value stored in the .mif



CMU PLL Reconfiguration Operation



3. Initiate a write transaction by asserting the write_all signal for one reconfig_clk cycle, to write the first 16-bit word of the .mif. Similarly, initiate a write transaction to write all the 38 words of the .mif. You can use the reconfig_address_out_en port to determine when to initiate the next write transaction.

4. The dynamic reconfiguration controller asserts the busy signal for every write transaction initiated by you. The busy signal remains asserted until the complete 16-bit word has been written.

The dynamic reconfiguration controller automatically increments the values on the reconfig_address_out port from word 0 through 37. The words 28 through 37 contain information to reconfigure the CMU PLL. During reconfiguration, the dynamic reconfiguration controller powers down the CMU PLL until new values are written.

The dynamic reconfiguration controller asserts the channel_reconfig_done signal to indicate that the CMU PLL reconfiguration is complete.

Figure 42. Signal Transitions to Reconfigure a Transmitter PLL with a Reference Index Value of 1

100

Dynamic reconfigurationcontroller does not register thelogical_tx_pll_sel value for this

write because the logical_tx_pll_sel_en is low

reconfig_mode_sel

channel_reconfig_done

write_all

logical_tx_pll_sel




Example

Consider the following scenario:

■ The design has four Transmitter only ALTGX instances in the same transceiver block.

■ All the four instances are configured in Basic functional mode and have a 2.5 Gbps data rate.

■ All the four channels can listen to CMU PLL 0.

■ The input reference clock used by CMU PLL 0 is 100 MHz.

■ You want to reconfigure all the four channels identically to 2 Gbps together.

Figure 43 depicts this example scenario before and after dynamic reconfiguration.

■ You can achieve the CMU PLL reconfiguration by reconfiguring the CMU PLL 0 once to run for 2 Gbps. This, in turn, changes the transmit data rate of all the four channels listening to this CMU PLL 0.

Figure 43. CMU PLL Reconfiguration Example

refclk0

refclk1

clock multiplier unit

clockmux

clockmux

CMU PLL 0

CMU PLL 1

Blocks that can be reconfigured in Channel and CMU PLLReconfiguration mode

full duplex transciever channel

TX CHANNEL

RX CHANNEL

LogicalTX PLLselect

LOCALDIVIDER


digital + analog logicRX PLLclockmux

Table 16. CMU PLL Reconfiguration Example (Part 1 of 2)

ALTGX Instances ALTGX_RECONFIG Instance

ALTGX Setting Four TX Only Instances ALTGX_RECONFIG Setting ALTGX_RECONFIG Instance

What is the effective data rate? option

2000 Gbps Channel and TX PLL select/reconfig option

Enabled

Enable Channel and Transmitter PLL Reconfiguration option

Enabled Use reconfig_address_out option

Enabled



After generating the .mif, follow the steps listed in the CMU PLL Reconfiguration Operation section to write all the 38 words.

TX PLL Powerdown

During the CMU PLL Reconfiguration mode, the dynamic reconfiguration controller automatically powers down the selected CMU PLL until it completes reconfiguring the selected CMU PLL. The ALTGX_RECONFIG instance does not provide any external ports to control the CMU PLL power down. When you reconfigure the CMU PLL, the pll_locked signal goes low. Therefore, after reconfiguring the transceiver, wait for the pll_locked signal from the ALTGX instance before continuing normal operation.

1 The dynamic reconfiguration controller powers down ONLY the selected CMU PLL. The other CMU PLL is not affected.

Channel and CMU PLL Reconfiguration ModeYou can reconfigure a transceiver channel to a different functional mode and data rate by using this dynamic reconfiguration mode.

What is the main transmitter PLL reference index? option

1

Use reconfig_address_out option Enabled

How many input clocks? option

2

What is the selected input clock source for the Transmitter PLL and Receiver PLL? option

1

What is clock 0 in-put frequency? option

125 MHz

What is clock 1 in-put frequency? option

100 MHz

Table 16. CMU PLL Reconfiguration Example (Part 2 of 2)

ALTGX Instances ALTGX_RECONFIG Instance

ALTGX Setting Four TX Only Instances ALTGX_RECONFIG Setting ALTGX_RECONFIG Instance



Blocks Reconfigured in the Channel and CMU PLL Reconfiguration Mode

Figure 44 shows the various functional blocks that can be dynamically reconfigured using this feature.

Because the CMU PLL is also reconfigured when you use this feature, all the channels that are listening to the CMU PLL are affected.

ALTGX MegaWizard Setup

You can use this mode to reconfigure both the functional mode and the data rate of a transceiver channel. If you want to enable this feature:

1. In both the ATLGX and ALTGX_RECONFIG MegaWizard Plug-In Managers, select the Channel and TX CMU PLL select/reconfig option.

2. In the ALTGX_RECONFIG MegaWizard Plug-In Manager, select the Channel and TX CMU PLL reconfiguration option.

3. In the ALTGX_RECONFIG MegaWizard Plug-In Manager, select the Selecting Logical Reference Index option.

4. In the ALTGX_RECONFIG MegaWizard Plug-In Manager, select the .mif File Generation option.

ALTGX_RECONFIG MegaWizard Setup

The following describes the Channel and CMU PLL reconfiguration operation.

Channel and CMU PLL Reconfiguration Operation

1. Set the reconfig_mode_sel to 101.

2. Initiate a write transaction by asserting the write_all signal for one reconfig_clk clock cycle to write the .mif contents. During reconfiguration, the dynamic reconfiguration controller powers down the selected logical CMU PLL until the new values are updated.

Figure 44. Channel and CMU PLL Reconfiguration in a Transceiver Block

/1

pll_inclk_rx_cruclk[1]

156.25 MHz

125 MHzpll_inclk_rx_cruclk[0]


3.125 Gbps

LOGICALTXPLL0

2.5 Gbps

LOGICALTXPLL1

clockMUX

clockMUX

Full Duplex Transceiver Channel

TX CHANNEL

RX CHANNEL

3.125 Gbps

digital + analog logicLOCAL

DIVIDER

LogicalTX PLLSelect

clockMUX

3.125 Gbps

RX PLL

3.125 Gbps




f For more information regarding the power down feature, refer to the Arria II GX Transceiver Architecture chapter in volume 2 of the Arria II GX Device Handbook.

To illustrate the functional blocks that are reconfigured, the following example is used. This same example is used for the three reconfiguration features.

Example

Consider that you have an ALTGX instance with the following configuration:

■ The full-duplex channel with the main CMU PLL configured to 3.125 Gbps data using a 156.25 MHz reference clock.

■ The alternate CMU PLL is configured to 2.5 Gbps using a 125 MHz reference clock.

■ Assume that the logical tx pll value is set to 0 for the main CMU PLL. (For more information about this setting, refer to the “ALTGX MegaWizard Setup” on page 75.

Consider that you intend to switch to the following two modes:

Mode1:

■ Full-duplex channel with the main CMU PLL configured to 3.125 Gbps data using a 156.25 MHz reference clock.

■ Assume that the logical tx pll is set to 0 for the main CMU PLL and rate matcher is not enabled in the ALTGX MegaWizard Plug-In Manager.


Mode2:

■ Full-duplex channel with the main CMU PLL configured to 2.5 Gbps data using a 156.25 MHz reference clock.

■ Assume that the logical tx pll is set to 0 for the main CMU PLL.

■ Rate matcher is enabled in the ALTGXB MegaWizard Plug-In Manager.


Consider that the .mif is generated for mode1 and mode2. (For more information, refer to “.mif Generation” on page 65. The intent of this example is to show how the functional blocks are reconfigured based on the feature used).





Figure 45 shows the functional blocks that are reconfigured after the dynamic reconfiguration controller writes the mode2 .mif.

1 On the receive side; the rate matcher gets enabled after reconfiguration because the mode2 .mif contains settings to enable the rate matcher block.

Channel Reconfiguration with TX PLL Select ModeUse this mode to dynamically reconfigure the functional mode of one transceiver channel at a time. Also use this mode to dynamically reconfigure the data rate of a transceiver channel. Every transceiver block has two TX CMU PLLs. If you want to reconfigure the data rate of a transceiver channel listening to TX CMU PLL 0, you can use this mode to reconfigure the transceiver channel to listen to TX CMU PLL 1 instead. As a result, the transceiver channel now runs at the data rate at which the TX CMU PLL 1 is configured at. Complete the following steps, if you want to enable this feature.

1. Select the Channel and TX CMU PLL select/reconfig option in both the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Managers.

2. Select the Channel Reconfiguration with TX CMU PLL select option in the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Main PLL and Alternate PLL To reconfigure the CMU PLL during run time, you need the flexibility to select one of the two CMU PLLs (Figure 46).

Consider that the transceiver channel is listening to CMU PLL 0 and that you want to reconfigure CMU PLL 0 (Figure 46).

Figure 45. Reconfigured Functional Blocks after the Channel and TX PLL Reconfiguration

/1

pll_inclk_rx_cruclk[1]156.25 MHz

pll_inclk_rx_cruclk[0]125 MHz


clockMUX

clockMUX

2.5 Gbps

LOGICALTXPLL0

2.5 Gbps

LOGICALTXPLL1

Reconfigured functional blocks after MIF write Rate Matcher Enabled

RX CHANNEL

2.5 Gbps

RX PLL

clockMUX

2.5 Gbps


2.5 Gbps


Full Duplex Transceiver Channel

TX CHANNEL

LogicalTX PLLSelect

LOCALDIVIDER



You can select the CMU PLL 0 by specifying its identity in the ALTGX MegaWizard Plug-In Manager. This identification is referred to as the logical tx pll value.

This value provides a logical identification to CMU PLL 0 and associates it with a transceiver channel, without requiring the knowledge of its physical location.

In the ALTGX MegaWizard Plug-In Manager, the transmitter PLL configuration set in the General tab is called the main PLL. When you provide the main PLL with a logical tx pll value, for example 1, the alternate PLL automatically takes the complement value 0. The logical tx pll value for the main PLL is stored along with the other transceiver channel information in the generated .mif.

1 You can reuse the .mif generated for one CMU PLL to reconfigure the other CMU PLL in the same or in other transceiver blocks.

Provide the logical tx pll value for the main PLL in the What is the main PLL logical reference index? option in the Reconfig Clks tab.

CMU PLL Reconfiguration mode is also useful when used in combination with the dynamic reconfiguration mode, Channel Reconfiguration with CMU PLL select.

Consider that you have one transceiver channel listening to one CMU PLL of the transceiver block.You want to reconfigure the transceiver channel to a different data rate.

Figure 46. Main PLL and Alternate PLL

TX CHANNEL

Active Connections


1

0

Unused Connections

refclk0

refclk1

156.25 MHz

125 MHz

clockmux

clockmux

3.125 Gbps

CMU PLL 0

2.5 Gbps

CMU PLL 1

Main PLLlogical_tx_pll value = 1 (provided bythe user in the ALTGX MegaWizard

Plug-In Manager


RX CHANNEL

LogicalTX PLLselect

LOCALDIVIDER

3.125 Gbps


clock mux

3.125 Gbps


3.125 Gbps

RX PLL

Alternate PLLlogical_tx_pll value = 0

(automatically set by the ALTGXMegaWizard Plug-In Manager)



You can first use the CMU PLL Reconfiguration mode (set the reconfig_mode_sel to 100) and reconfigure the second unused CMU PLL of the transceiver block to the desired data rate. For more information, refer to “CMU PLL Reconfiguration Mode” on page 67.

You can then use the Channel Reconfiguration with CMU PLL select mode (set the reconfig_mode_sel to 110) and reconfigure the transceiver channel to listen to the second reconfigured CMU PLL. For more information, refer to “Channel and CMU PLL Reconfiguration Operation” on page 75.

1 The main PLL corresponds to the CMU PLL configuration set in the General tab of the ALTGX MegaWizard Plug-In Manager and the alternate PLL corresponds to the CMU PLL configuration set in the Reconfig Alt PLL tab.

Channel Reconfiguration with CMU PLL Select ModeThis section describes the channel reconfiguration with CMU PLL select mode. A transceiver channel reconfiguration can be a data rate reconfiguration using two CMU PLLs and local clock dividers, a functional mode reconfiguration, or both. To reconfigure a channel successfully, select the appropriate options in the ALTGX MegaWizard Plug-In Manager.

This mode allows you to reconfigure a transceiver channel by writing a new set of legal register bits into the channel by the ALTGX_RECONFIG instance.

1 Channel reconfiguration only affects the channel involved in the reconfiguration without affecting the remaining transceiver channels controlled by the dynamic reconfiguration controller.

Channel reconfiguration with CMU PLL select mode can be further classified into two categories:

Data Rate Reconfiguration

■ You can reconfigure the data rate of a transceiver channel by switching between the two CMU PLLs present in a transceiver block and reconfiguring the Receiver PLLs. The two CMU PLLs can be set to different base rates. You can choose one of the CMU PLLs based on the data rate at which you want the channel to run.

■ Every transmitter channel has one local clock divider. Similarly, every receiver channel has one local clock divider. You can reconfigure the data rate of a transceiver channel by reconfiguring these local clock dividers to /1, /2, or /4. When you reconfigure these local clock dividers, ensure that the functional mode of the transceiver channel supports the reconfigured data rate.

Functional Mode Reconfiguration

You can reconfigure the existing functional mode of the transceiver channel to a totally different functional mode using this feature. The various ways by which you can reconfigure the existing functional mode are as follows:

■ You can switch from one functional mode to another functional mode

■ You can switch from one functional mode to a Basic functional mode

■ You can switch from one Basic functional mode to another Basic functional mode



There is no limit to the number of functional modes you can reconfigure the transceiver channel to, provided the various clocks involved support the transition. For more information about core clocks, refer to “Core Clocking Setup” on page 81.

1 In addition to the above mentioned categories, you can choose to reconfigure the data rate and functional mode of a transceiver channel

1 For the following sections, assume that the transceiver channel has the Receiver and Transmitter configuration in the ALTGX MegaWizard Plug-In Manager, unless specified as Transmitter only or Receiver only configurations.

Blocks Reconfigured by the Channel Reconfiguration with CMU PLL Select Mode

The various blocks that get reconfigured by this dynamic reconfiguration mode are the PCS and PMA blocks of a transmitter channel, local divider settings of the transmitter and receiver channel, and multiplexer selecting the CMU PLL.

Figure 47 shows the blocks that get reconfigured by this mode.

Channel Reconfiguration Supported Modes

Channel reconfiguration is applicable to the following configurations of a physical transceiver channel:

■ Receiver and Transmitter configuration

■ Transmitter only configuration

■ Receiver only configuration

■ Independent Transmitter and Independent Receiver combined into the same physical channel.

Figure 47. Reconfigured Blocks During Channel Reconfiguration with CMU PLL Select Mode

RX PLL

refclk0

refclk1


CMU PLL 0

CMU PLL 1clock mux

clock mux


TX CHANNEL

RX CHANNEL

LogicalTX PLLselect

LOCALDIVIDER


digital + analog logicclockmux

Blocks that can be reconfigured in Channel and CMU PLLReconfiguration mode



In the Transmitter only configuration, there is only one transmitter in a physical transceiver channel. The .mif for the Transmitter only file has the bits of the unused receiver, but these bits are disabled. The Receiver only configuration is the same as the Transmitter only configuration except it pertains to the receiver.

1 Channel reconfiguration from a Transmitter only mode to an Receiver only mode and vice versa is not allowed.

The Quartus II software allows combining Independent Transmitter only configuration with another Independent Receiver only configuration in one physical channel. To place an Independent Transmitter configuration and an Independent Receiver configuration in one physical channel, use the following steps:

1. Perform the pin assignments accordingly.

There are constraints with the independent Transmitter only and independent Receiver only configurations. Both transmitter and receiver have to go through a reset sequence, even if the transmitter or receiver is reconfigured.

ALTGX MegaWizard Setup

You must setup the following two system design aspects in the ALTGX MegaWizard instance:

■ Transceiver and core clocking

■ FPGA fabric-Transceiver channel interface selection

Transceiver and core clocking and FPGA fabric-Transceiver channel interface selection are described in detail in the following sections.

Core Clocking SetupThis section describes the steps involved in setting up the transceiver core clocks. The transceiver core clocks are the write and read clocks of the Transmit Phase Compensation FIFO and the Receive Phase Compensation FIFO, respectively.

Core clocking is classified as follows:

■ Transmitter core clocking

■ Receiver core clocking

Transmitter Core Clocking This section describes the various options available for you to select the write clock of the Transmit Phase Compensation FIFO. The clock you select is used to write the parallel data from the FPGA fabric into the Transmit Phase Compensation FIFO.

You can use one of the following clocks to write into the Transmit Phase Compensation FIFO:

■ tx_coreclk—You can use a clock of the same frequency as the tx_clkout, from the FPGA fabric to provide the write clock to the Transmit Phase Compensation FIFO. If you use tx_coreclk, it overrides the tx_clkout options in the ALTGX MegaWizard Plug-In Manager.



■ tx_clkout—The Quartus II software automatically routes the tx_clkout to the FPGA fabric and back into the Transmit Phase Compensation FIFO. There are two options available within the tx_clkout option itself, in the Reconfig 2 tab of the ALTGX MegaWizard Plug-In Manager. Figure 48 shows the two different tx_clkout options in the ALTGX MegaWizard Plug-In Manager.

Option 1: Sharing a Single Transmitter Clock between TransmittersEnable this option if you want the tx_clkout of the first channel (channel 0) of the transceiver block to provide the write clock to the transmitter phase compensation FIFOs of the remaining channels in the transceiver block. This option is typically enabled when all the channels of a transceiver block are of the same functional mode and data rate, and are reconfigured to another functional mode.

Consider the following example scenario:

■ Four transceiver channels configured at 3 Gbps and in the same functional mode

■ Channel Reconfiguration mode is enabled in the ALTGX_RECONFIG MegaWizard Plug-In Manager.

■ You want to reconfigure all the four transceiver channels to 1.5 Gbps and vice versa.

Option 1 is applicable in this scenario as it saves clock resources.

Figure 48. The tx_clkout options in the ALTGX MegaWizard Plug-In Manager



Figure 49 shows the sharing of channel 0’s tx_clkout between all of the four regular channels of a transceiver block.

Option 2: Use Respective Channel Transmitter Core ClocksEnable this option if you want the individual transmitter channel tx_clkout signals to provide the write clock to their respective Transmit Phase Compensation FIFOs. This option is typically enabled when each transceiver channel is reconfigured to a different functional mode using channel reconfiguration.


■ Four transceiver channels configured at 3 Gbps and totally different functional modes.


■ You want to reconfigure each of the four transceiver channels to different data rates and different functional modes.

Option 2 is applicable in this scenario as the design requires all the four transceiver channels to be reconfigured to different data rates and functional modes.

Figure 50 shows how each transmitter channel’s tx_clkout signal provides clock to the transmit phase compensation FIFOs of the respective transceiver channels.

Therefore, you can reconfigure each channel to a different functional mode using the dynamic reconfiguration mode: channel reconfiguration.

Figure 49. Option 1 for Transmitter Core Clocking (Channel Reconfiguration Mode)

TX1 (3 Gbps)

RX1

TX0 (3 Gbps)

RX2

TX2 (3 Gbps)

RX3

TX3 (3 Gbps)

RX4

CMU PLL 1

CMU PLL 0



Receiver Core ClockingThis section describes the various options available for you to select the read clock of the Receive Phase Compensation FIFO. The clock you select is used to read the parallel data from the Receiver Phase Compensation FIFO into the FPGA fabric.

You can use one of the following clocks to read from the Receive Phase Compensation FIFO:

■ rx_coreclk—You can use a clock of the same frequency as the rx_clkout from the FPGA fabric to provide the read clock to the Receive Phase Compensation FIFO. If you use rx_coreclk, it overrides the rx_clkout options in the ALTGX MegaWizard Plug-In Manager.

■ rx_clkout—The Quartus II software automatically routes the rx_clkout to the FPGA fabric and back into the Receive Phase Compensation FIFO. There are three options available within the rx_clkout option itself, in the Reconfig 2 tab of the ALTGX MegaWizard Plug-In Manager.

Figure 50. Option 2 for Transmitter Core Clocking (Channel Reconfiguration Mode)

TX1 (3 Gbps)

RX1

TX0 (3 Gbps)

RX2

TX2 (3 Gbps)

RX3

RX4

TX3 (3 Gbps)

CMU PLL 1

CMU PLL 0



Figure 51 shows the three different rx_clkout options in the ALTGX MegaWizard Plug-In Manager.

Option 1: Sharing a Single Transmitter Core Clock between ReceiversEnable this option if you want the tx_clkout of the first channel (channel 0) of the transceiver block to provide the read clock to the Receive Phase Compensation FIFOs of the remaining receiver channels in the transceiver block. This option is typically enabled when all the channels of a transceiver block are in Basic or Protocol functional mode, with rate matching, and are reconfigured to another Basic or Protocol functional mode with rate matching.


■ Four transceiver channels configured to Basic 2 Gbps functional mode with rate matching.


■ You want to reconfigure all the four transceiver channels to 3.125 Gbps functional mode with rate matching.

Option 1 is applicable in this scenario.

Figure 51. The rx_clkout Options in the ALTGX MegaWizard Plug-In Manager



Figure 52 shows the sharing of channel 0’s tx_clkout between all of the four regular channels of a transceiver block.

Option 2: Use Respective Channel Transmitter Core ClocksEnable this option if you want the individual transmitter channel’s tx_clkout signal to provide the read clock to its respective Receive Phase Compensation FIFO. This option is typically enabled when all the transceiver channels have rate matching enabled with different data rates and are reconfigured to another Basic or Protocol functional mode with rate matching.


■ TX1/RX1: Basic 1 Gbps functional mode with rate matching to Basic 2 Gbps functional mode with rate matching

■ TX3/RX3: Basic 2 Gbps functional mode with rate matching to Basic 1 Gbps functional mode with rate matching

■ TX0/RX0: Basic 3.125 Gbps functional mode with rate matching to 1 Gbps functional mode with rate matching and vice versa

■ Channel Reconfiguration mode is enabled in the ALTGX_RECONFIG MegaWizard Plug-In Manager

Option 2 is applicable in this scenario as the design requires all the four transceiver channels to be reconfigured to another Basic or Protocol functional mode with rate matching and different data rates.

Figure 53 shows how each transmitter channel’s tx_clkout signal provides the read clock to the receive phase compensation FIFOs of the respective receiver channels.

Therefore, you can reconfigure each channel to another Basic or Protocol functional mode with rate matching enabled and a different data rate.

Figure 52. Option 1 for Receiver Core Clocking (Channel Reconfiguration Mode)

CMUPLL0

TX1

RX1

TX0

RX0

TX2

RX2

TX3

RX3

(All 4 channels configured to Basic 2Gwith RM and set up to switch to Basic

3.125 with RM)

CMUPLL1



Option 3: Use Respective Channel Receiver Core ClocksEnable this option if you want the individual channel’s rx_clkout signal to provide the read clock to its respective Receive Phase Compensation FIFO. This option is typically enabled when the channel is reconfigured from a Basic or Protocol functional mode with or without rate matching to another Basic or Protocol functional mode with or without rate matching.


■ TX1/RX1: GIGE functional mode to SONET/SDH OC48 functional mode.

■ TX2/RX2: Basic 2.5 Gbps functional mode with rate matching disabled to Basic 1.244 Gbps functional mode with rate matching disabled.


Option 3 is applicable in this scenario.


Transceiver Block

TX1

RX1

TX0

TX2

TX3

RX0

RX2

RX3



Figure 54 shows how each transmitter channel’s rx_clkout signal provides the read clock to the Receive Phase Compensation FIFOs of the respective receiver channels.

FPGA Fabric-Transceiver Channel Interface SelectionThis section describes the ALTGX MegaWizard settings related to FPGA fabric-Transceiver channel interface data width when you select and activate channel reconfiguration mode. You need to set up the FPGA fabric-Transceiver channel interface data width when channel reconfiguration involves the following:

■ Functional mode reconfiguration involving changes in the FPGA fabric-Transceiver channel data width

■ Functional mode reconfiguration involving enabling and disabling the static PCS blocks of the transceiver channel

You can set up the FPGA fabric-Transceiver channel interface data by enabling one or both of the following settings in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager:

Channel InterfaceEnable this option if the reconfiguration of the transceiver channel involves the following changes:

■ The static PCS blocks of the transceiver channel are enabled or disabled.

■ The reconfigured data rate requires the second CMU PLL of the transceiver block to be set up. In this case, you must also enable the Use alternate reference clock option in the Reconfig tab of the ALTGX MegaWizard Plug-In Manager. For more information, refer to “The Use alternate reference clock Option” on page 89.

■ The FPGA fabric-Transceiver channel interface data width is constant for the new reconfiguration and no additional control or status signals are required.


TX1

RX1

TX0

RX0

TX2

RX2

TX3

RX3

Transceiver Block



Figure 55 shows the Channel Interface option in the ALTGX MegaWizard Plug-In Manager.

The Use alternate reference clock OptionThe following sections describe the Use alternate reference clock option.

Enable this option if the reconfiguration of the transceiver channel involves the following changes:

■ The reconfigured channel has a changed FPGA fabric-Transceiver channel interface data width

■ The reconfigured channel has changed input control signals and output status signals

There are new input signals available when you enable this option:

■ tx_datainfull—The width of this input signal depends on the number of channels you set up in the ALTGX MegaWizard Plug-In Manager. It is 44 bits wide per channel. This signal is available only for Transmitter only and Receiver and Transmitter configurations. This port replaces the existing tx_datain port.

■ rx_dataoutfull—The width of this output signal depends on the number of channels you set up in the ALTGX MegaWizard Plug-In Manager. It is 64 bits wide per channel. This signal is available only for Receiver only and Receiver and Transmitter configurations. This port replaces the existing rx_dataout port.

Figure 55. The Channel Interface option in the ALTGX MegaWizard Plug-In Manager



1 In addition to these two new ports, the Reconfig 2 tab is available for you to select the necessary control and status signals for the reconfigured channel.

The following signals are not available when you enable this option for the FPGA fabric-Receiver interface:

■ rx_dataout

■ rx_syncstatus

■ rx_patterndetect

■ rx_a1a2sizeout

■ rx_ctrldetect

■ rx_errdetect

■ rx_disperr

The following signals are not available when you enable this option for the FPGA fabric-Transmitter interface:

■ tx_datain

■ tx_ctrlenable

■ tx_forcedisp

■ tx_dispval

The Quartus II software has legal checks for the connectivity of tx_datainfull and rx_dataoutfull and the various control and status signals you enable in the Reconfig 2 tab (Table 17).

For example, the Quartus II software allows you to select and connect the pipestatus and powerdn signals. It assumes that you are planning to switch to and from the PCI Express (PIPE) functional mode.

Table 17. tx_datainfull[43:0] FPGA fabric-Transceiver Channel Interface Signal Descriptions (Part 1 of 3)

FPGA Fabric-Transceiver Channel Interface Description

Transmit Signal Description (Based on Arria II GX Supported FPGA Fabric-Transceiver Channel Interface Widths)

8-bit FPGA fabric-Transceiver Channel Interface

tx_datainfull[7:0]: 8-bit data (tx_datain)

The following signals are used only in 8B/10B modes:

tx_datainfull[8]: Control bit (tx_ctrlenable)

tx_datainfull[9]: Force disparity enable for tx_datainfull[7:0] (non PIPE mode).

Transmitter force disparity Compliance (PIPE) (tx_forcedisp) in all modes except PIPE.

For PIPE mode, (tx_forcedispcompliance) is used.

tx_datainfull[10]: Forced disparity value for tx_datainfull[7:0] (tx_dispval)

10-bit FPGA fabric-Transceiver Channel Interface

tx_datainfull[9:0]: 10 bit data (tx_datain)



16-bit FPGA fabric-Transceiver Channel interface with PCS-PMA set to 16/20 bits

Two 8-bit Data (tx_datain)

tx_datainfull[7:0] - tx_datain (LSByte) and tx_datainfull[18:11] - tx_datain (MSByte)


Two Control Bits (tx_ctrlenable)

tx_datainfull[8] - tx_ctrlenable (LSB) and

tx_datainfull[19] - tx_ctrlenable (MSB)

Force Disparity Enable

tx_datainfull[9] - tx_forcedisp (LSB) and

tx_datainfull[20] - tx_forcedisp (MSB)

Force Disparity Value

tx_datainfull[10] - tx_dispval (LSB) and

tx_datainfull[21] - tx_dispval (MSB)



tx_datainfull[7:0] - tx_datain (LSByte) and

tx_datainfull[29:22] - tx_datain (MSByte)


Two Control Bits (tx_ctrlenable)


tx_datainfull[30] - tx_ctrlenable (MSB)

Force Disparity Enable

For non-PIPE:

tx_datainfull[9] - tx_forcedisp (LSB) and

tx_datainfull[31] - tx_forcedisp (MSB)

For PIPE:

tx_datainfull[9] - tx_forcedispcompliance (LSB) and

tx_datainfull[31] - tx_forcedispcompliance (MSB)

Force Disparity Value

tx_datainfull[10] - tx_dispval (LSB) and

tx_datainfull[32] - tx_dispval (MSB)

20-bit FPGA fabric-Transceiver Channel interface with PCS-PMA set to 20 bits














Four 8-bit Data (tx_datain)

tx_datainfull[7:0]- tx_datain (LSByte) and

tx_datainfull[18:11]




Four Control Bits (tx_ctrlenable)


tx_datainfull[19]

tx_datainfull[30]

tx_datainfull[41]- tx_ctrlenable (MSB)

Force Disparity Enable (tx_forcedisp)

tx_datainfull[9]- tx_forcedisp (LSB) and

tx_datainfull[20]

tx_datainfull[31]

tx_datainfull[42]- tx_forcedisp (MSB)

Force Disparity Value (tx_dispval)

tx_datainfull[10]- tx_dispval (LSB) and

tx_datainfull[21]

tx_datainfull[32]

tx_datainfull[43]- tx_dispval (MSB)


Four 10-bit Data (tx_datain)




tx_datainfull[42:33]- tx_datain (MSByte)






Table 18. rx_dataoutfull[63:0] FPGA fabric-Transceiver Channel Interface Signal Descriptions



8-bit FPGA fabric-Transceiver Channel interface

The following signals are used in 8-bit 8B/10B modes:

rx_dataoutfull[7:0]: 8-bit decoded data (rx_dataout)

rx_dataoutfull[8]: Control bit (rx_ctrldetect)

rx_dataoutfull[9]: Code violation status signal. It indicates error detected in rx_dataoutfull[7:0], which is replaced by invalid code-group (invalid or running disp.error) in GIGE mode.

In PCI Express, when code violation occurs, the EDB character is placed on the erroneous data byte (= K30.7) (rx_errdetect)

rx_dataoutfull[10]: rx_syncstatus

rx_dataoutfull[11]: Disparity error status signal. It indicates disparity error detected in rx_dataoutfull[7:0] (rx_disperr)

rx_dataoutfull[12]: Pattern detect status signal (rx_patterndetect)

rx_dataoutfull[13]: Reserved


rx_dataoutfull[14:13]: PIPE/PCI-E mode:

2'b00: data OK

2'b01: 1 SKP deletion

2'b10: elastic buffer underflow if data is 0xFE, else 1 SKP insertion

2b11: elastic buffer overflow (rx_pipestatus)


The following signals are used in 8-bit SONET/SDH mode:

rx_dataoutfull[7:0]: 8-bit un-encoded data (rx_dataout)

rx_dataoutfull[8]: rx_a1a2sizeout



rx_dataoutfull[12]: rx_patterndetect

10-bit FPGA fabric-Transceiver Channel interface

rx_dataoutfull[9:0]: 10-bit un-encoded data (rx_dataout)



rx_dataoutfull[12]: rx_patterndetect







Two 8-bit unencoded Data (rx_dataout)

rx_dataoutfull[7:0] - rx_dataout (LSByte) and

rx_dataoutfull[23:16]- rx_dataout (MSByte)

The following signals are used in 16-bit 8B/10B modes:

Two Control Bits

rx_dataoutfull[8] - rx_ctrldetect (LSB) and

rx_dataoutfull[24]- rx_ctrldetect (MSB)

Two Receiver Error Detect Bits

rx_dataoutfull[9] - rx_errdetect (LSB) and

rx_dataoutfull[25]- rx_errdetect (MSB)

Two Receiver Sync Status Bits

rx_dataoutfull [10] - rx_syncstatus (LSB) and

rx_dataoutfull[42] - rx_syncstatus (MSB)

Two Receiver Disparity Error Bits

rx_dataoutfull [11] - rx_disperr (LSB) and

rx_dataoutfull[43] - rx_disperr (MSB)

Two Receiver Pattern Detect Bits

rx_dataoutfull[12] - rx_patterndetect (LSB) and

rx_dataoutfull[44]- rx_patterndetect (MSB)

rx_dataoutfull[13] and rx_dataoutfull[45]: Reserved


Two 2-bit PIPE Status Bits

rx_dataoutfull[14:13] - rx_pipestatus (LSB) and rx_dataoutfull[46:45] - rx_pipestatus (MSB)

PIPE/PCI-E mode:

2'b00: data OK


2'b10: elastic buffer underflow if data is hexFE, else 1 SKP insertion

2'b11: elastic buffer overflow








Two 8-bit Data


rx_dataoutfull[39:32] - rx_dataout (MSByte)

The following signals are used in 16-bit 8B/10B mode:

Two Control Bits

rx_dataoutfull[8] - rx_ctrldetect (LSB) and

rx_dataoutfull[40] - rx_ctrldetect (MSB)

Two Receiver Error Detect Bits

rx_dataoutfull[9] - rx_errdetect (LSB) and

rx_dataoutfull[41]- rx_errdetect (MSB)


rx_dataoutfull[10] - rx_syncstatus (LSB) and

rx_dataoutfull[42]- rx_syncstatus (MSB)

Two Receiver Disparity Error Bits

rx_dataoutfull[11] - rx_disperr (LSB) and




rx_dataoutfull[44] - rx_patterndetect (MSB)



Two 2-bit PIPE Status Bits

rx_dataoutfull[14:13] - rx_pipestatus (LSB) and rx_dataoutfull[46:45]- rx_pipestatus (MSB)

PIPE/PCI-E mode:

2'b00: data OK


2'b10: elastic buffer underflow if data is hexFE, else 1 SKP insertion

2'b11: elastic buffer overflow (rx_pipestatus)







16-bit FPGA fabric-Transceiver Channel interface with PCS-PMA set to 8/10 bits (continued)

The following signals are used in 16-bit SONET/SDH mode:

Two 8-bit Data



Two Receiver Alignment Pattern Length Bits

rx_dataoutfull[8] - rx_a1a2sizeout (LSB) and

rx_dataoutfull[40]- rx_a1a2sizeout (MSB)








Two 10-bit Data (rx_dataout)














Two 10-bit Data


















32-bit mode

Four 8-bit un-encoded Data (rx_dataout)

rx_dataoutfull[7:0]- rx_dataout (LSByte)

rx_dataoutfull[23:16]



The following signals are used in 32-bit 8B/10B mode:

Four Control Data Bits (rx_dataout)

rx_dataoutfull[8] - rx_ctrldetect (LSB)

rx_dataoutfull[24]

rx_dataoutfull[40]

rx_dataoutfull[56] - rx_ctrldetect (MSB)

Four Receiver Error Detect Bits

rx_dataoutfull[9]- rx_errdetect (LSB)

rx_dataoutfull[25]

rx_dataoutfull[41]

rx_dataoutfull[57] - rx_errdetect (MSB)

Four Receiver Pattern Detect Bits

rx_dataoutfull[10]- rx_syncstatus (LSB) and

rx_dataoutfull[26]

rx_dataoutfull[42]

rx_dataoutfull[58] rx_syncstatus (MSB)

Four Receiver Disparity Error Bits

rx_dataoutfull[11]- rx_disperr (LSB)

rx_dataoutfull[27]

rx_dataoutfull[43]



rx_dataoutfull[12]- rx_patterndetect (LSB)

rx_dataoutfull[28]

rx_dataoutfull[44]







32-bit mode (continued)

rx_dataoutfull[13], rx_dataoutfull[29], rx_dataoutfull[45] and rx_dataoutfull[61]: Reserved

rx_dataoutfull[14], rx_dataoutfull[30], rx_dataoutfull[46], and rx_dataoutfull[62]: Reserved

rx_dataoutfull[15], rx_dataoutfull[31], rx_dataoutfull[47], and rx_dataoutfull[63]: Reserved

The following signals are used in 32-bit SONET/SDH scrambled backplane mode:

Four Control Data Bits (rx_dataout)





rx_dataoutfull[8], rx_dataoutfull[24], rx_dataoutfull[40], and rx_dataoutfull[56]: four Reserved

Four Receiver Sync Status Bits

rx_dataoutfull[10]- rx_syncstatus (LSB)

rx_dataoutfull[26]

rx_dataoutfull[42]




rx_dataoutfull[28]

rx_dataoutfull[44]


40-bit mode

Four 10-bit Control Data Bits (rx_dataout)





Four Receiver Sync Status Bits

rx_dataoutfull[10]- rx_syncstatus (LSB)

rx_dataoutfull[26]

rx_dataoutfull[42]




rx_dataoutfull[28]

rx_dataoutfull[44]







ALTGX_RECONFIG MegaWizard SetupYou must set up the ALTGX_RECONFIG MegaWizard Plug-In Manager for Channel Reconfiguration mode. Select the Channel Reconfiguration option in the Reconfiguration settings tab of the ALTGX_RECONFIG MegaWizard Plug-In Manager.

Figure 12 on page 23 shows this option in the ALTGX_RECONFIG MegaWizard.

Set the What is the number of channels controlled by the reconfig controller? option and select the optional signals in the channel reconfiguration section. For more information, refer to “Total Number of Channels Controlled by the ALTGX_RECONFIG Instance” on page 31.

Connect the ALTGX and ALTGX_RECONFIG instances.

Control and Status Signals for Channel Reconfiguration

The various control input signals involved in the Channel Reconfiguration mode are as follows:

■ logical_channel_address [8:0]—Use this control signal to select the specific channel you want to dynamically reconfigure using this mode. Based on the value you set at this port, the dynamic reconfiguration controller writes the .mif contents to the transceiver channel you specify. This signal gets enabled when the number of channels controlled by the dynamic reconfiguration controller is more than one. Because the channel reconfiguration is done on a per-channel basis, you have to use this signal and provide the necessary logical channel address to write the .mif words so that a successful channel reconfiguration is achieved for that channel.

■ reset_reconfig_address—Use this optional control signal to reset the reconfig_address_out value to 0. This reset control signal is only applicable in channel reconfiguration.

■ reconfig_mode_sel[2:0]—Refer to Table 8 on page 23.

■ write_all—Refer to Table 3 on page 13.

The following are status signals:

■ reconfig_address_en—This is an optional output signal. The ALTGX_RECONFIG instance asserts this signal to indicate the change in value on the reconfig_address_out port. This signal only gets asserted after the dynamic reconfiguration controller completes writing the 16-bit data.

■ reconfig_address_out [4:0]—This is an optional output signal. It provides the address value that you can use to read the appropriate word from the .mif. Use the value in this port in combination with the reconfig_address_en signal to decide when to initiate a new write transaction.

■ channel_reconfig_done—This signal is available when you select the Channel Reconfiguration option in the dynamic reconfiguration controller. This port indicates that the ALTGX_RECONFIG instance has finished writing all the words of a .mif in a sequence. This signal is very useful for user logic to implement reset recommendations during and after dynamic reconfiguration.



f For information on transceiver resets, refer to the “Reset Recommendations" section of the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook.

■ error—Refer to “Error Indication in the ALTGX_RECONFIG MegaWizard Plug-In Manager” on page 54.

■ busy—Refer to Table 1 on page 9.

Write Transactions and How the Controller Uses .mif Files In channel reconfiguration mode, only a write transaction can occur—no read transactions are allowed.

■ Set the reconfig_mode_sel[2:0] control signal to 001 to use the channel reconfiguration feature. When you use this feature, the dynamic reconfiguration controller requires that you provide a 16-bit word (reconfig_data[15:0]) on every write transaction using the write_all signal. This 16-bit word is part of a .mif, that is generated by the Quartus II software when an ALTGX instance is compiled.

■ Set the rx_tx_duplex_sel port to enable the transmitter or receiver or the receiver and transmitter portion for reconfiguration.

■ Set the logical_channel_address port to specify the logical channel address of the transceiver channel.

■ Ensure the busy signal is low and assert the write_all signal for one reconfig_clk clock cycle.

Requirements to Reuse the .mif FilesWhen you use the global clock line to provide input reference clocks, be aware of the following restrictions and implications:

■ The hardware allows two global clock inputs for the two TX PLLs in a transceiver block.

■ In a receiver-only channel configuration, the RX PLL of each channel in a transceiver block can be clocked by an independent global clock line. But, if you connect different clock input pins to the RX PLL in each channel, you cannot reuse the .mifs between these two channels.

Input Reference Clock Requirements for Reusing .mif FIlesThe .mif contains information about the input clock multiplexer and the functional blocks that you selected during the ALTGXB MegaWizard Plug-In Manager instantiation. The Quartus II software generates a .mif for each channel. You can use this .mif in any of the other channels in the device if you satisfy the following two requirements for the input reference clocks:



■ The order of the clock inputs must be consistent. For instance, assume that a .mif is generated for a transceiver channel in bank 13 and the clock source is connected to the pll_inclk_rx_cruclk[0] port. When the generated .mif is used in a channel in other transceiver blocks (for example, bank 14), the same clock source needs to be connected to the pll_inclk_rx_cruclk[0] port. Figure 56 and Figure 57 show the incorrect and correct order of input reference clocks, respectively.

■ In Figure 56, the clocking is incorrect to reuse the .mif because the input reference clock is not connected to the corresponding pll_inclk_rx_cruclk[] ports in the two instances.

Figure 56. Incorrect Input Reference Clock Connection to Reuse the .mif

Figure 57. Correct Input Reference Clock Connection to Reuse the .mif

156.25 MHzclock source

Stratix II GX Device

bank 13ALT2GXBInstance 1


156.25 MHz pll_inclk_rx_cruclk[0]

IQ Lines or Global Clock Network




clock source

125 MHz

156.25 MHzclock source




156.25 MHz pll_inclk_rx_cruclk[0]





clock source

125 MHz



If you connect the input reference clock ports of the ALTGXB instances through different input pins, you cannot reuse the .mif generated between these two instances, even if you provide the same clock frequency on these two pins. For example, in Figure 58, the clock source provides 156.25 MHz clock to instance1 and instance2 through two different pins. In this case, if you generate a .mif for instance1, you cannot reuse it in instance2.

When you try to reconfigure using the .mif for instance1 in a transceiver block (for example, bank 13) on instance2 in another transceiver block (for example, bank 14), the reconfig controller remaps the clock input multiplexer information in the .mif (generated for instance1) to correspond to instance2. During this translation process, it assumes that the same clock input is connected to the pll_inclk_rx_cruclk[] port. Therefore, the reconfig controller selects the clock multiplexer value for the IQ line or global clock network that connects to the clock input of instance1.

If you want to reuse the .mif, connect the clock source to only one clock pin in the device. In your design, connect the clock input port of your transceiver instances to that clock pin. The Quartus II software automatically routes the clock input to all the transceiver blocks through IQ lines or global clock routing resources, depending on whether you selected a dedicated refclk pin or a clock I/O pin. Figure 58 shows the incorrect clocking scheme. Figure 59 shows the correct clocking scheme.

Figure 58. Incorrect Clocking Scheme to Reuse the .mif

clock source


ALT2GXBInstance 1bank 13


refclk0

156.25 MHzpll_inclk_rx_

cruclk[0]

pll_inclk_rx_cruclk[0]156.25 MHz

refclk0

two different clock pins


Document Revision History

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Document Revision HistoryTable 19 shows the revision history for this application note.

Figure 59. Correct Clocking Scheme to Reuse the .mif

clock source




refclk0

156.25 MHzpll_inclk_rx_

cruclk[0]



Table 19. Document Revision History

Date and Document Version Changes Made Summary of Changes

March 2009, v1.0 Initial release. —

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