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AN 779: Intel FPGA JESD204B IPCore and ADI AD9691 HardwareCheckout Report
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Contents
1 Intel® FPGA JESD204B IP Core and AD9691 Hardware Checkout Report......................... 31.1 Hardware Requirements ......................................................................................... 31.2 Hardware Setup .................................................................................................... 41.3 Hardware Checkout Methodology ............................................................................. 5
1.3.1 Receiver Data Link Layer ............................................................................ 51.3.2 Receiver Transport Layer .............................................................................71.3.3 Descrambling ............................................................................................ 81.3.4 Deterministic Latency (Subclass 1) ...............................................................9
1.4 JESD204B IP Core and ADC Configurations ..............................................................101.5 Test Results ........................................................................................................ 111.6 Test Result Comments .......................................................................................... 181.7 Document Revision History for AN 779: Intel FPGA JESD204B IP Core and AD9691
Hardware Checkout Report................................................................................. 18
Contents
AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report2
1 Intel® FPGA JESD204B IP Core and AD9691 HardwareCheckout Report
The Intel® FPGA JESD204B IP core is a high-speed point-to-point serial interfaceintellectual property (IP).
The JESD204B IP Core has been hardware-tested with a number of selectedJESD204B-compliant ADC (analog-to-digital converter) devices.
This report highlights the interoperability of the JESD204B IP Core with the AD9691converter evaluation module (EVM) from Analog Devices Inc. (ADI). The followingsections describe the hardware checkout methodology and test results.
1.1 Hardware Requirements
The hardware checkout test requires the following hardware and software tools:
• Intel Intel Arria® 10 GX FPGA Development Kit
• ADI AD9691 EVM
• USB cable
• SMA cable
• Clock source card capable of generating device clock frequencies
AN-779 | 2017.12.18
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2008Registered
1.2 Hardware Setup
Figure 1. Intel Arria 10 GX FPGA Development Kit Hardware SetupAn Intel Arria 10 GX FPGA Development Kit is used with the ADI AD9691 daughter card module installed to thedevelopment board’s FMC connector.
• The AD9691 EVM derives power from 4.5V power adaptor.
• The FPGA and ADC device clock is supplied by external clock source card through SMA connectors onAD9691 EVM.
• Both FPGA and ADC device clock must be sourced from the same clock source card with two differentfrequencies, one for FPGA and one for ADC.
For subclass 1, FPGA generates SYSREF for the JESD204B IP as well as the AD9691 device.
The following system-level diagram shows how the different modules connect in thisdesign.
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Figure 2. System Diagram
Note: The IOPLL input reference clock is sourcing from device clock through the global clock network. Sourcingreference clock from a cascaded PLL output, global clock or core clock network might introduce additional jitterto the IOPLL and transceiver PLL output. Refer to this KDB Answer for a workaround you should apply to the IPcore in your design.
ADC
ADC
sysref_out (15.36 MHz @ K=32)
312.5 MHzFPGA Ref clock
625 MHz ADC clock
AD96914-wire
SMA3-wire
rx_dev_sync_n
device_clk
Intel Arria 10 GX FPGA Development Kit AD9691 Evaluation BoardFMC B
rx_serial_data[7:0] (12.5 Gbps)
sclk, ss_n[0], miso, mosi
mgmt_clk
100 MHz
jesd204b_ed_top.sv
jesd204b_ed.sv
Design Example
JESD204B IP Core
(Duplex)L=2, M=2, F=2
Avalon-MMInterface
signals
global_rst_n
link_clk (312.5 MHz) Avalon MM
Slave Translator
Platform Designer System
JTAG to AvalonMaster Bridge
PIO
Signal Tap L0 – L7
Sysrefgenerator
ConversionCircuit
SPISlave
CLK & SYNC
SMA
sysref
sync_n
In this setup, where LMF=222, the data rate of transceiver lanes is 12.5 Gbps. Anexternal clock source card provides 312.5 MHz clock to the FPGA and 625 MHzsampling clock to AD9691 device. The Sysref is generated by the FPGA.
1.3 Hardware Checkout Methodology
The following section describes the test objectives, procedure, and the passingcriteria. The test covers the following areas:
• Receiver data link layer
• Receiver transport layer
• Descrambling
• Deterministic latency (Subclass 1)
1.3.1 Receiver Data Link Layer
This test area covers the test cases for code group synchronization (CGS) and initialframe and lane synchronization.
On link start up, the receiver issues a synchronization request and the transmittertransmits /K/ (K28.5) characters. The Signal Tap Logic Analyzer tool monitors thereceiver data link layer operation.
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1.3.1.1 Code Group Synchronization (CGS)
Table 1. CGS Test CasesL in the following table indicates the number of lanes.
Test Case Objective Description Passing Criteria
CGS.1 Check whethersync request is de-asserted aftercorrect receptionof foursuccessive /K/characters.
The following signals in<ip_variant_name>_inst_phy.v aretapped:• jesd204_rx_pcs_data[(L*32)-1:0]• jesd204_rx_pcs_data_valid[L-1:0]• jesd204_rx_pcs_kchar_data[(L*4)-1:
0] (1)The following signals in<ip_variant_name>.v are tapped:• rx_dev_sync_n• jesd204_rx_intThe rxlink_clk is used as the Signal Tapsampling clock.Each lane is represented by 32-bit databus in jesd204_rx_pcs_data signal. The32-bit data bus for is divided into 4octets.
• /K/ character or K28.5 (0xBC) isobserved at each octet of thejesd204_rx_pcs_data bus.
• The jesd204_rx_pcs_data_validsignal is asserted to indicate datafrom the PCS is valid.
• The jesd204_rx_pcs_kchar_datasignal is asserted whenever controlcharacters like /K/, /R/, /Q/ or /A/characters are observed.
• The rx_dev_sync_n signal is de-asserted after correct reception of atleast four successive /K/ characters.
• The jesd204_rx_int signal isdeasserted if there is no error.
CGS.2 Check full CGS atthe receiver aftercorrect receptionof another four8B/10B characters.
The following signals in<ip_variant_name>_inst_phy.v aretapped:• jesd204_rx_pcs_errdetect[(L*4)-1:0]• jesd204_rx_pcs_disperr[(L*4)-1:0]
(1)The following signal in<ip_variant_name>.v are tapped:• jesd204_rx_intThe rxlink_clk is used as the Signal Tapsampling clock.
The jesd204_rx_pcs_errdetect,jesd204_rx_pcs_disperr andjesd204_rx_int signals should not beasserted during CGS phase.
1.3.1.2 Initial Frame and Lane Synchronization
Table 2. Initial Frame and Lane Synchronization Test CasesL in the following table indicates the number of lanes.
Test Case Objective Description Passing Criteria
ILA.1 Check whether theinitial framesynchronizationstate machineenters FS_DATAstate uponreceiving non /K/characters.
The following signals in<ip_variant_name>_inst_phy.v aretapped:• jesd204_rx_pcs_data[(L*32)-1:0]• jesd204_rx_pcs_data_valid[L-1:0]• jesd204_rx_pcs_kchar_data[(L*4)-1:
0] (2)The following signals in<ip_variant_name>.v are tapped:• rx_dev_sync_n• jesd204_rx_intThe rxlink_clk is used as the Signal Tapsampling clock.
• /R/ character or K28.0 (0x1C) isobserved after /K/ character at thejesd204_rx_pcs_data bus.
• The jesd204_rx_pcs_data_validsignal must be asserted to indicatethat data from the PCS is valid.
• The rx_dev_sync_n andjesd204_rx_int signals aredeasserted.
• Each multiframe in ILAS phase endswith /A/ character or K28.3 (0x7C).
• The jesd204_rx_pcs_kchar_datasignal is asserted whenever controlcharacters like /K/, /R/, /Q/ or /A/characters are observed.
continued...
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Test Case Objective Description Passing Criteria
Each lane is represented by 32-bit databus in jesd204_rx_pcs_data. The 32-bitdata bus for is divided into 4 octets.
ILA.2 Check theJESD204Bconfigurationparameters fromADC in secondmultiframe.
The following signals in<ip_variant_name>_inst_phy.v aretapped:• jesd204_rx_pcs_data[(L*32)-1:0]• jesd204_rx_pcs_data_valid[L-1:0]
(2)The following signal in<ip_variant_name>.v is tapped:• jesd204_rx_intThe rxlink_clk is used as the Signal Tapsampling clock.The system console accesses thefollowing registers:• ilas_octet0• ilas_octet1• ilas_octet2• ilas_octet3The content of 14 configuration octets insecond multiframe is stored in these 32-bit registers - ilas_octet0, ilas_octet1,ilas_octet2 and ilas_octet3.
• /R/ character is followed by /Q/character or K28.4 (0x9C) at thebeginning of second multiframe.
• The Jesd204_rx_int is deasserted ifthere is no error.
• Octets 0-13 read from theseregisters match with the JESD204Bparameters in each test setup.
ILA.3 Check the lanealignment
The following signals in<ip_variant_name>_inst_phy.v aretapped:• jesd204_rx_pcs_data[(L*32)-1:0]• jesd204_rx_pcs_data_valid[L-1:0]
(2)The following signals in<ip_variant_name>.v are tapped:• rx_somf[3:0]• dev_lane_aligned• jesd204_rx_intThe rxlink_clk is used as the Signal Tapsampling clock.
• The dev_lane_aligned is assertedupon the last /A/ character of theILAS is received, which is followed bythe first data octet.
• The rx_somf marks the start ofmultiframe in user data phase.
• The jesd204_rx_int is deasserted ifthere is no error.
1.3.2 Receiver Transport Layer
To check the data integrity of the payload data stream through the RX JESD204B IPCore and transport layer, the ADC is configured to output PRBS-9 and Ramp test datapattern. The ADC is also set to operate with the same configuration as set in theJESD204B IP Core. The PRBS checker/Ramp checker in the FPGA fabric checks dataintegrity for one minute.
This figure shows the conceptual test setup for data integrity checking.
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Figure 3. Data Integrity Check Using PRBS/Ramp CheckerThe Signal Tap Logic Analyzer tool monitors the operation of the RX transport layer.
PRBS/RampGenerator
ADC
FPGA
RXJESD204B IP Core
PHY and Link Layer
TXPHY and Link Layer
TXTransport Layer
RXTransport Layer
PRBS/RampGenerator
Table 3. Transport Layer Test Cases
TestCase
Objective Description Passing Criteria
TL.1 Check the transportlayer mapping usingRamp test pattern.
The following signals in altera_jesd204_transport_rx_top.sv aretapped:• jesd204_rx_data_validThe following signals in jesd204b_ed.sv are tapped:• data_error• jesd204_rx_intThe rxframe_clk is used as the Signal Tap sampling clock.The data_error signal indicates a pass or fail for the PRBSchecker.
• Thejesd204_rx_data_valid signal isasserted.
• The data_errorandjesd204_rx_intsignals aredeasserted.
TL.2 Check the transportlayer mapping usingPRBS-9 testpattern.
The following signals in altera_jesd204_transport_rx_top.sv aretapped:• jesd204_rx_data_validThe following signals in jesd204b_ed.sv are tapped:• data_error• jesd204_rx_intThe rxframe_clk is used as the Signal Tap sampling clock.The data_error signal indicates a pass or fail for the PRBSchecker.
• Thejesd204_rx_data_valid signal isasserted.
• The data_errorandjesd204_rx_intsignals aredeasserted.
1.3.3 Descrambling
The PRBS/Ramp checker at the RX transport layer checks the data integrity ofdescrambler. The Signal Tap Logic Analyzer tool monitors the operation of the RXtransport layer.
Table 4. Descrambler Test Cases
Test Case Objective Description Passing Criteria
SCR.1 Check thefunctionality of thedescrambler usingPRBS-9 test pattern.
Enable scrambler at the ADC anddescrambler at the RX JESD204B IP Core.The signals that are tapped in this test caseare similar to test case TL.1
• The jesd204_rx_data_validsignal is asserted.
• The data_error andjesd204_rx_int signals aredeasserted.
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1.3.4 Deterministic Latency (Subclass 1)
The figure below shows the block diagram of deterministic latency test setup. ASYSREF generator provides a periodic SYSREF pulse for both the AD9691 andJESD204B IP Core. The SYSREF generator is running in link clock domain and theperiod of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulserestarts the LMF counter and realigns it to the LMFC boundary.
The deterministic latency measurement block checks deterministic latency. This isdone by measuring the number of link clock counts between the start of de-assertionof SYNC to the first user data output (assertion of rx_valid). Figure 5 on page 9shows the deterministic latency measurement timing diagram.
Figure 4. Deterministic Latency Test Setup Block Diagram
ADC
ADC
sysref_out (15.36 MHz @ K=32)
312.5 MHzFPGA Ref clock
625 MHz ADC clock
AD96914-wire
SMA3-wire
rx_dev_sync_n
device_clk
Intel Arria 10 GX FPGA Development Kit AD9691 Evaluation BoardFMC B
rx_serial_data[7:0] (12.5 Gbps)
sclk, ss_n[0], miso, mosi
mgmt_clk
100 MHz
jesd204b_ed_top.sv
jesd204b_ed.sv
Design Example
JESD204B IP Core
(Duplex)L=2, M=2, F=2
Avalon-MMInterface
signals
global_rst_n
link_clk (312.5 MHz)
Avalon MM Slave
Translator
Platform DesignerSystem
JTAG to AvalonMaster Bridge
PIO
SignalTap II
L0 – L7
Sysrefgenerator
ConversionCircuit
SPISlave
CLK & SYNC
SMA
sysref
sync_n
DeterministicLatency
Management
Figure 5. Deterministic Latency Measurement Timing Diagram
With the setup above, four test cases were defined to prove deterministic latency. Bydefault, the JESD204B IP Core does single SYSREF detection. The SYSREF N-shotmode is enabled on the AD9691 for this deterministic measurement.
Table 5. Deterministic Latency Test Cases
Test Case Objective Description Passing Criteria
DL.1 Check the FPGASYSREF singledetection.
Check that the FPGA detects the first risingedge of SYSREF pulse.Read the status of sysref_singledet (bit[2])identifier in syncn_sysref_ctrl register ataddress 0x54.
The value of sysref_singledetidentifier should be zero.
DL.2 Check the SYSREFcapture.
Check that FPGA and ADC capture SYSREFcorrectly and restart the LMF counter. BothFPGA and ADC are also repetitively reset.
If the SYSREF is capturedcorrectly and the LMF counterrestarts, for every reset, the
continued...
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Test Case Objective Description Passing Criteria
Read the value of rbd_count (bit[10:3])identifier in rx_status0 register at address0x80.
rbd_count value should onlydrift a little due to wordalignment.
DL.3 Check the latencyfrom start of SYNC~deassertion to firstuser data output.
Check that the latency is fixed for every FPGAand ADC reset and power cycle.Record the number of link clocks count fromthe start of SYNC~ deassertion to the first userdata output, which is the assertion ofjesd204_rx_link_valid signal.
Consistent latency from thestart of SYNC~ deassertion tothe assertion ofjesd204_rx_link_valid signal.
DL.4 Check the datalatency during userdata phase.
Check that the data latency is fixed during userdata phase.Observe the ramp pattern from the Signal TapLogic Analyzer.
The ramp pattern should be inperfect shape with nodistortion.
1.4 JESD204B IP Core and ADC Configurations
The JESD204B IP Core parameters (L, M and F) in this hardware checkout are nativelysupported by the AD9691 device's quick configuration register at address 0x570. Thetransceiver data rate, sampling clock frequency, and other JESD204B parameterscomply with the AD9691 operating conditions.
The hardware checkout testing implements the JESD204B IP Core with the followingparameter configuration.
Table 6. Parameter ConfigurationGlobal settings for all configuration:
• N = 14
• N' = 16
• CS = 0
• CF = 0
• FPGA Device Clock = 312.5 MHz (The device clock is used to clock the transceiver.)
• FPGA Management Clock = 100 MHz
• Character Replacement = Enabled
• Data Pattern = PRBS-9, Ramp(1)
LMF HD S ADC SamplingClock (MHz)
FPGA FrameClock (MHz)(2)
FPGA Link Clock(MHz)(2)
Lane Rate(Gbps)
DDCenabled
112 0 1 625 312.5 312.5 12.5 No
211 1 1 1250 312.5 312.5 12.5 No
212 0 2 1250 312.5 312.5 12.5 No
411 1 2 1250 156.25 156.25 6.25 No
412 0 4 1250 156.25 156.25 6.25 No
811 1 4 1250 78.125 78.125 3.125 No
continued...
(1) Ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, DL.3 andDL.4 only.
(2) The frame clock and link clock is derived from the device clock using an internal PLL.
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LMF HD S ADC SamplingClock (MHz)
FPGA FrameClock (MHz)(2)
FPGA Link Clock(MHz)(2)
Lane Rate(Gbps)
DDCenabled
812 0 8 1250 78.125 78.125 3.125 No
124 0 1 312.5 312.5 312.5 12.5 No
222 0 1 625 312.5 312.5 12.5 No
421 1 1 1250 312.5 312.5 12.5 No
422 0 2 1250 312.5 312.5 12.5 No
821 1 2 1250 156.25 156.25 6.25 No
822 0 4 1250 156.25 156.25 6.25 No
148 0 1 312.5 156.25 312.5 12.5 Yes
244 0 1 625 312.5 312.5 12.5 Yes
442 0 1 1250 312.5 312.5 12.5 Yes
841 1 1 1250 156.25 156.25 6.25 Yes
842 0 2 1250 156.25 156.25 6.25 Yes
288 0 1 312.5 156.25 312.5 12.5 Yes
484 0 1 625 312.5 312.5 12.5 Yes
882 0 1 1250 312.5 312.5 12.5 Yes
1.5 Test Results
The following table contains the possible results and their definition.
Table 7. Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of thesituation is included, such as due to time limitations only a portion of the testing was performed.
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation ofthe situation is included.
The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3,TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock,link clock and SYSREF frequencies.
(2) The frame clock and link clock is derived from the device clock using an internal PLL.
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Table 8. Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1
Test L M F Subclass SCR K Datarate
(Gbps)
ADC SamplingClock (MHz)
LinkClock(MHz)
Result
1 1 1 2 1 0 16 12.5 625 312.5 PASS
2 1 1 2 1 1 16 12.5 625 312.5 PASS
3 1 1 2 1 0 32 12.5 625 312.5 PASS
4 1 1 2 1 1 32 12.5 625 312.5 PASS
5 2 1 1 1 0 20 12.5 1250 312.5 PASS
6 2 1 1 1 1 20 12.5 1250 312.5 PASS
7 2 1 1 1 0 32 12.5 1250 312.5 PASS
8 2 1 1 1 1 32 12.5 1250 312.5 PASS
9 2 1 2 1 0 16 12.5 1250 312.5 PASS
10 2 1 2 1 1 16 12.5 1250 312.5 PASS
11 2 1 2 1 0 32 12.5 1250 312.5 PASS
12 2 1 2 1 1 32 12.5 1250 312.5 PASS
13 4 1 1 1 0 20 6.25 1250 156.25 PASS
14 4 1 1 1 1 20 6.25 1250 156.25 PASS
15 4 1 1 1 0 32 6.25 1250 156.25 PASS
16 4 1 1 1 1 32 6.25 1250 156.25 PASS
17 4 1 2 1 0 16 6.25 1250 156.25 PASS
18 4 1 2 1 1 16 6.25 1250 156.25 PASS
19 4 1 2 1 0 32 6.25 1250 156.25 PASS
20 4 1 2 1 1 32 6.25 1250 156.25 PASS
21 8 1 1 1 0 20 3.125 1250 78.125 PASS
22 8 1 1 1 1 20 3.125 1250 78.125 PASS
23 8 1 1 1 0 32 3.125 1250 78.125 PASS
24 8 1 1 1 1 32 3.125 1250 78.125 PASS
25 8 1 2 1 0 16 3.125 1250 78.125 PASS
26 8 1 2 1 1 16 3.125 1250 78.125 PASS
27 8 1 2 1 0 32 3.125 1250 78.125 PASS
28 8 1 2 1 1 32 3.125 1250 78.125 PASS
29 1 2 4 1 0 16 12.5 312.5 312.5 PASS
30 1 2 4 1 1 16 12.5 312.5 312.5 PASS
31 1 2 4 1 0 32 12.5 312.5 312.5 PASS
32 1 2 4 1 1 32 12.5 312.5 312.5 PASS
33 2 2 2 1 0 16 12.5 625 312.5 PASS
34 2 2 2 1 1 16 12.5 625 312.5 PASS
continued...
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Test L M F Subclass SCR K Datarate
(Gbps)
ADC SamplingClock (MHz)
LinkClock(MHz)
Result
35 2 2 2 1 0 32 12.5 625 312.5 PASS
36 2 2 2 1 1 32 12.5 625 312.5 PASS
37 4 2 1 1 0 20 12.5 1250 312.5 PASS
38 4 2 1 1 1 20 12.5 1250 312.5 PASS
39 4 2 1 1 0 32 12.5 1250 312.5 PASS
40 4 2 1 1 1 32 12.5 1250 312.5 PASS
41 4 2 2 1 0 16 12.5 1250 312.5 PASS
42 4 2 2 1 1 16 12.5 1250 312.5 PASS
43 4 2 2 1 0 32 12.5 1250 312.5 PASS
44 4 2 2 1 1 32 12.5 1250 312.5 PASS
45 8 2 1 1 0 20 6.25 1250 156.25 PASS
46 8 2 1 1 1 20 6.25 1250 156.25 PASS
47 8 2 1 1 0 32 6.25 1250 156.25 PASS
48 8 2 1 1 1 32 6.25 1250 156.25 PASS
49 8 2 2 1 0 16 6.25 1250 156.25 PASS
50 8 2 2 1 1 16 6.25 1250 156.25 PASS
51 8 2 2 1 0 32 6.25 1250 156.25 PASS
52 8 2 2 1 1 32 6.25 1250 156.25 PASS
53 1 4 8 1 0 16 12.5 312.5 312.5 PASS
54 1 4 8 1 1 16 12.5 312.5 312.5 PASS
55 1 4 8 1 0 32 12.5 312.5 312.5 PASS
56 1 4 8 1 1 32 12.5 312.5 312.5 PASS
57 2 4 4 1 0 16 12.5 625 312.5 PASS
58 2 4 4 1 1 16 12.5 625 312.5 PASS
59 2 4 4 1 0 32 12.5 625 312.5 PASS
60 2 4 4 1 1 32 12.5 625 312.5 PASS
61 4 4 2 1 0 16 12.5 1250 312.5 PASS
62 4 4 2 1 1 16 12.5 1250 312.5 PASS
63 4 4 2 1 0 32 12.5 1250 312.5 PASS
64 4 4 2 1 1 32 12.5 1250 312.5 PASS
65 8 4 1 1 0 20 6.25 1250 156.25 PASS
66 8 4 1 1 1 20 6.25 1250 156.25 PASS
67 8 4 1 1 0 32 6.25 1250 156.25 PASS
68 8 4 1 1 1 32 6.25 1250 156.25 PASS
69 8 4 2 1 0 16 6.25 1250 156.25 PASS
continued...
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Test L M F Subclass SCR K Datarate
(Gbps)
ADC SamplingClock (MHz)
LinkClock(MHz)
Result
70 8 4 2 1 1 16 6.25 1250 156.25 PASS
71 8 4 2 1 0 32 6.25 1250 156.25 PASS
72 8 4 2 1 1 32 6.25 1250 156.25 PASS
73 2 8 8 1 0 16 12.5 312.5 312.5 PASS withcomments
74 2 8 8 1 1 16 12.5 312.5 312.5 PASS withcomments
75 2 8 8 1 0 32 12.5 312.5 312.5 PASS withcomments
76 2 8 8 1 1 32 12.5 312.5 312.5 PASS withcomments
77 4 8 4 1 0 16 12.5 625 312.5 PASS withcomments
78 4 8 4 1 1 16 12.5 625 312.5 PASS withcomments
79 4 8 4 1 0 32 12.5 625 312.5 PASS withcomments
80 4 8 4 1 1 32 12.5 625 312.5 PASS withcomments
81 8 8 2 1 0 16 12.5 1250 312.5 PASS withcomments
82 8 8 2 1 1 16 12.5 1250 312.5 PASS withcomments
83 8 8 2 1 0 32 12.5 1250 312.5 PASS withcomments
84 8 8 2 1 1 32 12.5 1250 312.5 PASS withcomments
The following table shows the results for test cases DL.1, DL.2, DL.3 and DL.4 withdifferent values of L, M, F, K, subclass, data rate, sampling clock, link clock andSYSREF frequencies.
Table 9. Results for Deterministic Latency Test
Test L M F Subclass K Datarate
(Gbps)
SamplingClock(MHz)
LinkClock(MHz)
Result Latency(LinkClock
Cycles)
DL.1 1 1 2 1 16/32 12.5 625 312.5 PASS For K=16DL= 75For K=32DL= 115
DL.2 1 1 2 1 16/32 12.5 625 312.5 PASS
DL.3 1 1 2 1 16/32 12.5 625 312.5 PASS
DL.4 1 1 2 1 16/32 12.5 625 312.5 PASS
DL.1 2 1 1 1 20/32 12.5 1250 312.5 PASS For K=20DL= 53For K=32DL= 67
DL.2 2 1 1 1 20/32 12.5 1250 312.5 PASS
DL.3 2 1 1 1 20/32 12.5 1250 312.5 PASS
continued...
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Test L M F Subclass K Datarate
(Gbps)
SamplingClock(MHz)
LinkClock(MHz)
Result Latency(LinkClock
Cycles)
DL.4 2 1 1 1 20/32 12.5 1250 312.5 PASS
DL.1 2 1 2 1 16/32 12.5 1250 312.5 PASS For K=16DL=67For K=32DL=99
DL.2 2 1 2 1 16/32 12.5 1250 312.5 PASS
DL.3 2 1 2 1 16/32 12.5 1250 312.5 PASS
DL.4 2 1 2 1 16/32 12.5 1250 312.5 PASS
DL.1 4 1 1 1 20/32 6.25 1250 156.25 PASS For K=20DL=53For K=32DL=67
DL.2 4 1 1 1 20/32 6.25 1250 156.25 PASS
DL.3 4 1 1 1 20/32 6.25 1250 156.25 PASS
DL.4 4 1 1 1 20/32 6.25 1250 156.25 PASS
DL.1 4 1 2 1 16/32 6.25 1250 156.25 PASS For K=16DL=67For K=32DL=99
DL.2 4 1 2 1 16/32 6.25 1250 156.25 PASS
DL.3 4 1 2 1 16/32 6.25 1250 156.25 PASS
DL.4 4 1 2 1 16/32 6.25 1250 156.25 PASS
DL.1 8 1 1 1 20/32 3.125 1250 78.125 PASS For K=20DL=53For K=32DL=67
DL.2 8 1 1 1 20/32 3.125 1250 78.125 PASS
DL.3 8 1 1 1 20/32 3.125 1250 78.125 PASS
DL.4 8 1 1 1 20/32 3.125 1250 78.125 PASS
DL.1 8 1 2 1 16/32 3.125 1250 78.125 PASS For K=16DL=67For K=32DL=115
DL.2 8 1 2 1 16/32 3.125 1250 78.125 PASS
DL.3 8 1 2 1 16/32 3.125 1250 78.125 PASS
DL.4 8 1 2 1 16/32 3.125 1250 78.125 PASS
DL.1 1 2 4 1 16/32 12.5 312.5 312.5 PASS For K=16DL=99For K=32DL=195
DL.2 1 2 4 1 16/32 12.5 312.5 312.5 PASS
DL.3 1 2 4 1 16/32 12.5 312.5 312.5 PASS
DL.4 1 2 4 1 16/32 12.5 312.5 312.5 PASS
DL.1 2 2 2 1 16/32 12.5 625 312.5 PASS For K=16DL=67For K=32DL=115
DL.2 2 2 2 1 16/32 12.5 625 312.5 PASS
DL.3 2 2 2 1 16/32 12.5 625 312.5 PASS
DL.4 2 2 2 1 16/32 12.5 625 312.5 PASS
DL.1 4 2 1 1 20/32 12.5 1250 312.5 PASS For K=20DL=56For K=32DL=67
DL.2 4 2 1 1 20/32 12.5 1250 312.5 PASS
DL.3 4 2 1 1 20/32 12.5 1250 312.5 PASS
DL.4 4 2 1 1 20/32 12.5 1250 312.5 PASS
DL.1 4 2 2 1 16/32 12.5 1250 312.5 PASS For K=16DL=67
continued...
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Test L M F Subclass K Datarate
(Gbps)
SamplingClock(MHz)
LinkClock(MHz)
Result Latency(LinkClock
Cycles)
DL.2 For K=32DL=99
4 2 2 1 16/32 12.5 1250 312.5 PASS
DL.3 4 2 2 1 16/32 12.5 1250 312.5 PASS
DL.4 4 2 2 1 16/32 12.5 1250 312.5 PASS
DL.1 8 2 1 1 20/32 6.25 1250 156.25 PASS For K=20DL=52For K=32DL=67
DL.2 8 2 1 1 20/32 6.25 1250 156.25 PASS
DL.3 8 2 1 1 20/32 6.25 1250 156.25 PASS
DL.4 8 2 1 1 20/32 6.25 1250 156.25 PASS
DL.1 8 2 2 1 16/32 6.25 1250 156.25 PASS For K=16DL=67For K=32DL=99
DL.2 8 2 2 1 16/32 6.25 1250 156.25 PASS
DL.3 8 2 2 1 16/32 6.25 1250 156.25 PASS
DL.4 8 2 2 1 16/32 6.25 1250 156.25 PASS
DL.1 1 4 8 1 16/32 12.5 312.5 312.5 PASS For K=16DL=195For K=32DL=67
DL.2 1 4 8 1 16/32 12.5 312.5 312.5 PASS
DL.3 1 4 8 1 16/32 12.5 312.5 312.5 PASS
DL.4 1 4 8 1 16/32 12.5 312.5 312.5 PASS
DL.1 2 4 4 1 16/32 12.5 625 312.5 PASS For K=16DL=115For K=32DL=195
DL.2 2 4 4 1 16/32 12.5 625 312.5 PASS
DL.3 2 4 4 1 16/32 12.5 625 312.5 PASS
DL.4 2 4 4 1 16/32 12.5 625 312.5 PASS
DL.1 4 4 2 1 16/32 12.5 1250 312.5 PASS For K=16DL=67For K=32DL=99
DL.2 4 4 2 1 16/32 12.5 1250 312.5 PASS
DL.3 4 4 2 1 16/32 12.5 1250 312.5 PASS
DL.4 4 4 2 1 16/32 12.5 1250 312.5 PASS
DL.1 8 4 1 1 20/32 6.25 1250 156.25 PASS For K=20DL=51For K=32DL=67
DL.2 8 4 1 1 20/32 6.25 1250 156.25 PASS
DL.3 8 4 1 1 20/32 6.25 1250 156.25 PASS
DL.4 8 4 1 1 20/32 6.25 1250 156.25 PASS
DL.1 8 4 2 1 16/32 6.25 1250 156.25 PASS For K=16DL=67For K=32DL=99
DL.2 8 4 2 1 16/32 6.25 1250 156.25 PASS
DL.3 8 4 2 1 16/32 6.25 1250 156.25 PASS
DL.4 8 4 2 1 16/32 6.25 1250 156.25 PASS
DL.1 2 8 8 1 16/32 12.5 312.5 312.5 PASS For K=16DL=195For K=32DL=67
DL.2 2 8 8 1 16/32 12.5 312.5 312.5 PASS
DL.3 2 8 8 1 16/32 12.5 312.5 312.5 PASS
continued...
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Test L M F Subclass K Datarate
(Gbps)
SamplingClock(MHz)
LinkClock(MHz)
Result Latency(LinkClock
Cycles)
DL.4 2 8 8 1 16/32 12.5 312.5 312.5 PASS withcomments
DL.1 4 8 4 1 16/32 12.5 625 312.5 PASS For K=16DL=115For K=32DL=195
DL.2 4 8 4 1 16/32 12.5 625 312.5 PASS
DL.3 4 8 4 1 16/32 12.5 625 312.5 PASS
DL.4 4 8 4 1 16/32 12.5 625 312.5 PASS withcomments
DL.1 8 8 2 1 16/32 12.5 1250 312.5 PASS For K=16DL=67For K=32DL=99
DL.2 8 8 2 1 16/32 12.5 1250 312.5 PASS
DL.3 8 8 2 1 16/32 12.5 1250 312.5 PASS
DL.4 8 8 2 1 16/32 12.5 1250 312.5 PASS withcomments
The following figure shows the Signal Tap waveform of the clock count from thedeassertion of SYNC~ to the assertion of the jesd204_rx_link_valid signal, the firstoutput of the ramp test pattern (DL.3 test case). The clock count measures the firstuser data output latency.
Figure 6. Deterministic Latency Measurement Ramp Test Pattern Diagram
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1.6 Test Result Comments
In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILAphase, and until user data phase. No data integrity issue is observed by the PRBS andRamp checker.
In deterministic measurement test case DL.3, the link clock count in the FPGAdepends on the board layout and the LMFC offset value set in the ADC register. Thelink clock count can vary by only one link clock when the FPGA and ADC are reset orpower cycled. The link clock variation in the deterministic latency measurement iscaused by word alignment, where the control characters fall into the next cycle of datasometime after realignment. This makes the duration of ILAS phase longer by one linkclock sometimes after reset or power cycle.
For modes with 8 converters (M=8), the result is updated with ‘PASS with comments’because the test cases TL.1, TL.2 and DL.4 are validated only for first 7 convertersdue to known limitation of ADC. The ADC does not output RAMP/PRBS test-pattern forthe 8th converter and this is documented in the ADC’s datasheet in TEST MODESsection on page 54.
For a few modes, in order to avoid lane de-skew error or achieve deterministic latency,RBD offset and LMFC offset registers had to be programmed. The modes and thecorresponding values used are tabled below.
Table 10. Mode (LMF)csr_lmfc_offsetcsr_rbd_offset
Mode (LMF) csr_lmfc_offset csr_rbd_offset
211-K20 2 0
421-K20 0 2
821-K20 0 1
411-K20 2 0
841-K20 0 2
1.7 Document Revision History for AN 779: Intel FPGA JESD204B IPCore and AD9691 Hardware Checkout Report
Date Version Changes
December 2017 2017.12.18 • Renamed the document as AN 779: Intel FPGA JESD204B IP Coreand AD9691 Hardware Checkout Report.
• Added a note to clarify that the IOPLL input reference clock issourcing from device clock through global clock network in theHardware Setup topic.
• Updated for latest branding standards.
May 2017 2017.05.08 Rebranded as Intel.
October 2016 2016.10.31 Initial release.
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