AN 883: Intel Arria 10 DisplayPort TX-only Design

AN 883: Intel Arria 10 DisplayPortTX-only Design

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Contents

1. Intel® Arria® 10 DisplayPort TX-only Design...................................................................31.1. Design Components............................................................................................... 41.2. Clocking Scheme................................................................................................... 51.3. Top Level Interface Signals..................................................................................... 61.4. Quick Start Guide ................................................................................................. 6

1.4.1. Hardware and Software Requirements.......................................................... 71.4.2. Compiling and Testing the Design ............................................................... 71.4.3. Running the Hardware................................................................................81.4.4. Design Debug Features.............................................................................10

1.5. Creating the TX-only Design with Bitec FMC Daughter Card....................................... 111.5.1. Generating the Design.............................................................................. 121.5.2. Removing Irrelevant Blocks....................................................................... 131.5.3. Instantiating Video and Image Processing (VIP) Intel FPGA IPs...................... 141.5.4. Generated Clocks.....................................................................................171.5.5. Making a Direct Connection to the TX Transceiver Block................................ 171.5.6. Modifying the Software............................................................................. 19

1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design.........22

Contents

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1. Intel® Arria® 10 DisplayPort TX-only DesignThe Intel® Arria® 10 DisplayPort TX-only design demonstrates how the DisplayPortsource (TX) transmits 4Kp60 video output generated by the Test Pattern Generator IIIntel FPGA IP.

This design uses the Bitec FMC daughter card to transmit the video output.

Figure 1. Intel Arria 10 DisplayPort TX-only Design Block DiagramComputer

OC RAM Nios II Processor

Test PatternGenerator II Avalon-ST

Video

Avalon-MMInterconnect

Clocked Video Output II

Video with Sync Signals

TX AUX Transaction Monitoring

TX AUX Debug Stream

DisplayPort TX DisplayPort TX Management Bridge

Avalon-MM InterconnectSource

Management

Debug FIFO

TX Reconfiguration

TX Sub-system (Platform Designer)

SYSIDTimer

JTAG UART

TX ReconfigurationManagement

Transceiver NativePHY

100 MHzReference Clock

Bitec FMC Daughter Card

Intel FPGA IP componentsoutside Platform Designer system

Intel FPGA IP componentsinside dp_core Platform Designer system

Intel FPGA IP componentsinside DisplayPort TX Platform Designer system

Custom logic component

Transceiver PHYRest Controller

TX PLL

TX PHY Top

Video PLL

16 MHz

160 MHz

148.5 MHz

Locked

Top

Reset Button

Core System (Platform Designer)

Reset Generator

Related Information

• Intel Design StoreProvides the design files.

• DisplayPort Intel Arria 10 FPGA IP Design Example User GuideProvides more information about the Intel Arria 10 design examples.

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1.1. Design Components

The DisplayPort Intel FPGA IP core design example requires these components.

Table 1. Core System Components

Module Description

Core System (Platform Designer) The core system consists of the Nios II processor and its necessary components,DisplayPort TX core sub-system and the Video and Image Processing (VIP) FPGAIPs.This system provides the infrastructure to interconnect the Nios II processor withthe DisplayPort Intel FPGA IP core (TX instance) through Avalon Memory Mapped(Avalon-MM) interface within a single Platform Designer system to ease thesoftware build flow.This system consists of:• CPU Sub-System• TX Sub-System• VIP FPGA IPs

TX Sub-System (Platform Designer) The TX sub-system consists of:• Clock Source—The clock source to the DisplayPort TX core. This sub-system

has two clock sources integrated: 100 MHz and 16 MHz.• Reset Bridge—The bridge that connects the external signal to the sub-system.

This bridge synchronizes to the respective clock source before it is used.• DisplayPort TX Core—DisplayPort Source IP core, VESA DisplayPort Standard

version 1.4.• Debug FIFO—This FIFO captures all DisplayPort TX auxiliary cycles, and prints

out in the Nios II Debug terminal. This component is only used when theTX_AUX_DEBUG parameter is turned on.

• PIO—The parallel IO that triggers the DPTX register update in software(tx_utils.c).

• Avalon-MM Pipeline Bridge—This Avalon-MM bridge interconnects the Avalon-MM interface between components within the TX sub-system to the Nios IIprocessor in the Core sub-system.

Table 2. DisplayPort TX PHY Top Components

Module Description

TX PHY Top The TX PHY top level consists of the components related to the transmitter PHYlayer.• Transceiver Native PHY(TX)—The transceiver block that receives 20-bit or

40-bit parallel data from the DisplayPort Intel FPGA IP core and serializes thedata before transmitting it. This block supports up to 8.1 Gbps (HBR3) datarate with 4 channels.Note: You must set the TX channel bonding mode to PMA and PCS

bonding and the PCS TX Channel bonding master parameter to 0(default is auto).

• Transceiver PHY Reset Controller—The TX Reconfiguration Managementmodule triggers the reset input of this controller to generate thecorresponding analog and digital reset signals to the Transceiver Native PHYblock according to the reset sequencing.

• TX Reconfiguration Management—This block reconfigures and recalibrates theTransceiver Native PHY and TX PLL blocks to transmit serial data in therequired data rates (RBR, HBR, HBR2, and HBR3).

• TX PLL—The transmitter PLL block provides a fast serial fast clock to theTransceiver Native PHY block. For the DisplayPort Intel FPGA IP core designexample, Intel uses transmitter fractional PLL (FPLL).

Note: 8.1 Gbps is available only in the Intel Quartus® Prime Pro Editionsoftware.

1. Intel® Arria® 10 DisplayPort TX-only Design

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Table 3. Top-Level Common Blocks

Module Description

IOPLL IOPLL generates three common source clocks:• 160 MHz—Used as main clock for Clocked Video Output II and Test Pattern

Generator II FPGA IPs.• 16 MHz—Used as DisplayPort TX auxiliary clock.• 148.5 MHz—Used as video clock for DisplayPort Intel FPGA source and

Clocked Video Output II FPGA IP

1.2. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel FPGA IP coredesign example.

Table 4. Clocking Scheme Signals

Clock Signal Name in Design Description

TX PLL Refclock tx_pll_refclk 135 MHz TX PLL reference clock, that is divisible by thetransceiver for all DisplayPort data rates (1.62 Gbps, 2.7Gbps, and 5.4 Gbps).Note: The reference clock source of the TX PLL refclock is

located at the HSSI refclk pin.

TX Transceiver Clockout gxb_tx_clkout TX clock recovered from the transceiver, and the frequencyvaries depending on the data rate and symbols per clock.

Data Rate Symbols perClock

Frequency(MHz)

RBR (1.62 Gbps) 2 (dual) 81

4 (quad) 40.5

HBR (2.7 Gbps) 2 (dual) 135

4 (quad) 62.5

HBR2 (5.4 Gbps) 2 (dual) 270

4 (quad) 135

HBR3 (8.1 Gbps) 4 (quad) 202.5

Management Clock tx_rcfg_mgmt_clk A free running 100 MHz clock for both Avalon-MM interfacesfor reconfiguration and PHY reset controller for transceiverreset sequence.

Component RequiredFrequency

(MHz)

Avalon-MM reconfiguration 100 – 125

Transceiver PHY reset controller 1 – 500

16 MHz Clock clk_16 16 MHz clock used to encode and decode auxiliary channel inthe DisplayPort Intel FPGA source and sink IP cores.

Calibration Clock dp_tx_clk_cal A 50 MHz calibration clock input that must be synchronous tothe Transceiver Reconfiguration module's clock. This clock isused in the DisplayPort Intel FPGA IP core's reconfigurationlogic.

continued...


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Clock Signal Name in Design Description

TX Video Clock tx_vid_clk Video clock frequency generated from IOPLL. A correct outputclock frequency needs to be generated according to videoformat.Used when DisplayPort source's TX_SUPPORT_IM_ENABLE =0.

CVO Video Clock tx_vid_clk Fixed video clock generated by the video PLL (148.5 MHz) tothe DisplayPort Intel FPGA source.

VIP Clock vip_clk 160 MHz clock generated by the video PLL.

1.3. Top Level Interface Signals

The tables list the signals for the TX-only design example.

Table 5. Top-Level Signals

Signal Direction Width Description

On-board Oscillator Signal

refclk1_p Input 1 100 MHz clock source used as IOPLL reference clock andAvalon-MM management clock

User Push Button

cpu_resetn Input 1 Global reset

DisplayPort FMC Daughter Card Pins on FMC Port A

fmca_gbtclk_m2c_p Input 1 135 MHz dedicated transceiver reference clock from FMCport A

fmca_dp_c2m_p Output N DisplayPort TX serial dataNote: N = TX maximum lane count

fmca_la_rx_n_9 Input 1 DisplayPort TX HPD• 1 = HPD asserted• 0 = HPD deasserted

fmca_la_tx_p_12 Input 1 DisplayPort TX Aux In

fmca_la_rx_p_10 Output 1 DisplayPort TX Aux Out

fmca_la_rx_n_10 Output 1 DisplayPort TX Aux OE

fmca_la_tx_n_12 Output 1 FMC card TX CAD

1.4. Quick Start Guide

The reference design features a hardware design that supports compilation andhardware testing.


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1.4.1. Hardware and Software Requirements

To test the design, ensure that you have the appropriate hardware and software.

Hardware

• Intel Arria 10 GX FPGA Development Kit (10AX115S2F45I1SG)

• Bitec FMC daughter card revision 5.0 or later

• DisplayPort sink (monitor)

• DisplayPort cables

Software

• Intel Quartus Prime Pro Edition 18.1 (for hardware testing)

1.4.2. Compiling and Testing the Design

You can download the DisplayPort TX-only design file (A10_DP_TX_FMC_PRO.par)from the Intel Design Store. To compile and run a demonstration test on the hardwareexample design, follow these steps.

The .par file contains includes pre-compiled .sof and .elf files that you can run totest the design.

1. To extract the files in the .par file, refer to the Installation Package instruction inthe Intel Design Store design download page.

2. Extract and unzip the Additional_Files.zip file from theA10_DP_TX_FMC_PRO.par file, and move the Script and Software folder tothe main project directory.

3. Launch the Intel Quartus Prime Pro Edition software and open <projectdirectory>/quartus/top.qpf.

Note: Bitec DisplayPort FMC daughter card revision 10 has schematic changescompared to revisions 8 and earlier. Revision 8 has lane reversal andpolarity inversion at TX. To support all revisions, the design example toplevel RTL file at <project directory>/rtl/top.v file include a localparameter for you to select the FMC revision.

localparam BITEC_DP_CARD_REV = 0;

// 0 = Bitec FMC DP card rev.4 - 8,

// 1 = rev.9 or later

4. Open Nios II Command Shell and navigate to the Script folder.

5. Run the build_sw_sh script in the Nios II terminal to build the software.

6. In the Intel Quartus Prime Pro Edition software, click Processing ➤ StartCompilation.

7. After successful compilation, the Intel Quartus Prime Pro Edition softwaregenerates a .sof file in your specified directory.


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Related Information

Intel Design StoreProvides the design files.

1.4.2.1. Regenerating ELF File

By default, the ELF file is generated when you generate the dynamic design example.

Note: In some cases, you need to regenerate the ELF file if you modify the software file ormodify and regenerate the dp_core.qsys file. Regenerating the dp_core.qsys fileupdates the .sopcinfo file, which requires you to regenerate the ELF file.

1. Go to <project directory>/software and edit the code if necessary.

2. Go to <project directory>/script and execute the following build script:

source build_sw.sh

• On Windows, search and open Nios II Command Shell. In the Nios IICommand Shell, go to <project directory>/script and execute sourcebuild_sw.sh.

• On Linux, launch the Platform Designer, and open Tools ➤ Nios II CommandShell. In the Nios II Command Shell, go to <project directory>/scriptand execute source build_sw.sh.

3. Make sure an .elf file is generated in <project directory>/software/dp_demo.

4. Download the generated .elf file into the FPGA without recompiling the .sof fileby running the following script:

nios2-download <project directory>/software/dp_demo/*.elf

5. Push the reset button on the FPGA board for the new software to take effect.

1.4.3. Running the Hardware

Set up the hardware before you run the design on the Intel Arria 10 development kit.


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https://fpgacloud.intel.com/devstore/platform/18.1.0/Pro/intel-arria-10-displayport-tx-only-design/


Figure 2. Arria 10 Development Kit Hardware SetupDisplayPort TXto sink device

Bitec FMCdaughter card

USB tocomputer

Power supply

Reset button

1. Install the Bitec FMC daughter card at the FMC port A on the Intel Arria 10development kit.

2. Connect the DisplayPort TX connector on the Bitec FMC daughter card to a videoanalyzer or DisplayPort sink device such as a monitor.

3. Ensure all MSEL switches on the development board are in default position.

4. Power up and connect the development board to your PC using a micro USB cable.

5. Download the .sof file into the FPGA device using Intel Quartus PrimeProgrammer.

6. Push the Reset button on the Intel Arria 10 development kit.

7. The DisplayPort sink device displays the video.


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Figure 3. DisplayPort TX-only Design Output Video

Note: The hardware setup below uses ASUS MG28UQ monitor with Bitec FMC daughter card revision 8 connected toIntel Arria 10 FPGA development kit. The monitor runs 4Kp60 color bar video generated by the Video andImage Processing Intel FPGA IPs.

1.4.4. Design Debug Features

This design also offers debugging features that are useful for debugging link up and novideo output issues.

1.4.4.1. Main Stream Attribute (MSA) Information

This debug feature enables you to check the MSA information.

This feature is a part of the DisplayPort TX-only design example. To display the (MSAof the DisplayPort TX core, type ‘S’ on the keyboard while in the Nios II terminal. TheTX stream MSA values will appear on the Nios II terminal.


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Figure 4. MSA Values on Nios II Terminal

Other Nios II Commands:

• h - help

• s - MSA Status

• c- Read Sink DPCD CRC

• v - Print versions

1.4.4.2. Auxiliary Channel Traffic Monitor

This debug feature enables you to check the auxiliary channel transaction.

This feature is also a part of the DisplayPort TX-only design example. To display theauxiliary channel transaction on the Nios II terminal, set the BITEC_AUX_DEBUG flagin the config.h file in the project folder to 1.

#define BITEC_AUX_DEBUG 1 // Set to 1 to enable AUX CH traffic monitoring

Rebuild the Nios II software and download the ELF image into the FPGA.

1.5. Creating the TX-only Design with Bitec FMC Daughter Card

You can create the DisplayPort TX-only design by making certain software andhardware modifications to the already provided DisplayPort SST parallel loopback withPCR design example. The steps below align with Intel Quartus Prime Pro Edition 18.1software release. For newer Quartus release, additional steps to create TX-only designmay be needed.


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1.5.1. Generating the Design

Before you make the modifications, first you need to generate the DisplayPort SSTParallel Loopback design example in the Intel Quartus Prime Pro Edition.

1. Instantiate the DisplayPort Intel FPGA IP and specify the parameters.

Table 6. Example of IP Parameters Value to Generate a 4kp60 Output Video

Parameters Value Description

Maximum video output color depth (Source) 10 bpc This design supports GPU and monitors up to amaximum of 10 bit-per-color depth.

Maximum link rate 5.4 Gbps The bandwidth requirement for 4Kp60 and 10bpc video stream through serial link:• Active video resolution = 3840 × 2160

pixels/frame• Total resolution (including reduced blanking)

= 4000 × 2222 pixels/frame• Refresh rate = 60 Hz or 60 frames per

second• Bits per pixel = 10 bpc × 3 colors = 30 bits

per pixel• Total bandwidth = (4000 × 2222) pixel/

frame × 60 frame/s × 30 bits/pixel =15.9984 Gbits/s

With 8b/10b encoding scheme, the actualbandwidth required = 15.9984 × 10/8 =19.998 Gbps. With 4 lanes at 5.4 Gbps, theaggregated bandwidth of 21.6 Gbps is sufficientto support the 4K video stream at 60 Hzrefresh rate.

Maximum lane count 4

Symbol output mode (Source) Quad Symbol mode affects the transceiver parallelbus width and the DisplayPort IP core clockfrequency. The DisplayPort IP core synchronizeswith the transceiver parallel clock. The parallelclock frequency is link rate/transceiver parallelbus width.Frequency for HBR2 (5.4 Gbps) is 5400/20 or270 MHz for dual (20 bits) and 5400/40 or 135MHz for quad (40 bits) mode.

Symbol input mode (Sink)

Pixel input mode (Source) Quad Pixel mode affects the video clock frequencyand video port width of the IP core.For 4Kp60 video stream, the bandwidthrequirement is 4000 × 2222 × 60 pixel/s =533280000 pixels/s. Because of the highbandwidth requirement, the design requiresdual or quad pixel mode for timing closure.• Single (1 pixel/clock) 533.28 MHz• Dual (2 pixels/clock) 266.64 MHz• Quad (4 pixels/clock) 133.32 MHz

Pixel output mode (Sink)

Support analog reconfiguration On Enable analog reconfiguration interface. Usedto reconfigure vod and pre-emphasis value.

Enable AUX debug stream On Enable AUX source traffic output to Avalon-STport

DisplayPort SST Parallel Loopback With PCR On Enable Pixel Clock Recovery in the design.


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Note: The table above is an example of IP setting. However, Intel recommendsyou to generate a base example design with required IP setting (BPC,symbol per clock, pixel per clock, number of channels, link rate) and thenproceed with the design modification. Changing the IP settings at the laterstage can cause design conflict if not done properly.

2. Click Generate Example Design with Intel Arria 10 GX FPGA Development kit asa target board.

1.5.2. Removing Irrelevant Blocks

Modify the generated design example by removing the irrelevant blocks from the top-level design and from the dp_core.qsys file.

Remove the RX sub-system, RX PHY top. Pixel Clock Recovery (PCR), and TransceiverArbiter components (in gray), as shown in the diagram below. These blocks are notneeded for the TX-only design.

Figure 5. Components Required for the DisplayPort TX-only Design

TX only component

Component to be removed

Parallel Data

Avalon-MM

Control/Sataus

Serial Data

Top

Core System (Platform Designer)

RX Sub-system (Platform Designer) TX Sub-system (Platform Designer)

PIO

DebugFIFO

DisplayPort TX

Avalon-MMInterconnect

PIO

CPU Sub-systemDebugFIFO

EDIDRAM

Transceiver PHY ResetController

Transceiver PHY ResetController

RX Reconfiguration

Management

TX Reconfiguration

Management

Transceiver Native PHY

Pixel Clock Recovery

(PCR)

Transceiver Arbiter

Video Pattern

GeneratorIOPLL

RX PHY Top

Video Data Video Data

Audio Data

TX PHY Top

TX PLL

DisplayPort RX

Avalon-MM Interconnect

Transceiver Native PHY

1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.vFile

Below are detailed steps to remove the irrelevant blocks in top level file:

1. Module a10_dp_demo IO port modification:-


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• Remove Transceiver Data RX inputs - fmca_dp_m2c signals

• Remove other RX signals (RX_HPD, RX Cable Detect, RX Power Detect and RXAUX Signals)

• Remove Paratech Retimer signals (Bitec FMC Card Rev.8 or below)

2. DisplayPort Core Qsys system dp_core instantiation modifications;

• Remove I2C Avalon Interface to Paratech/Megachip Retimer

• Remove the DisplayPort Sink Sub-system

3. Remove rx_phy_top module instantiation.

4. Remove bitec_clkrec module instantiation

• This module is only available if you generated DisplayPort design example withPCR

5. Remove Transceiver Reconfiguration Arbiter module instantiation.

6. Remove I2C master interface

1.5.2.2. Removing Irrelevant Block in Platform Designer

Below are detailed steps to remove the irrelevant blocks in Platform Designer

1. From Quartus Project Navigator, double click to open dp_core system.

2. Remove dp_rx sub-system.

3. Remove i2c_master.

4. Remove unused RX components - dp_rx_clk_16 bridge and dp_rx_reset_bridge.

Note: Before generating HDL, save the changes in Platform Designer, Sync SystemInfo and Validate System Integrity to ensure no errors were introduced.

1.5.3. Instantiating Video and Image Processing (VIP) Intel FPGA IPs

After removing irrelevant blocks in the design, instantiate the relevant Video andImage Processing FPGA IPs.

1. Instantiate the Clocked Video Output (CVO) II and Test Pattern Generator (TPG) IIIntel FPGA IPs in the Platform Designer and specify the parameters. The tablebelow is an example of parameter value that generates a 4kp60 video.

Note: The Test Pattern Generator (TPG) II Intel FPGA IP generates video streamthat displays color bars video pattern. The Clocked Video Output II IntelFPGA IP converts the Avalon-ST video format received from the TPG II IntelFPGA IP to standard clocked video format.

Note: Certain sink devices may not be able to accept below video resolution andsettings. Contact sink device manufacturer for more information.

Table 7. Clocked Video Output (CVO) II and Test Pattern Generator (TPG) IIParameter Settings

FPGA IP Parameters Value

Clocked Video Output II Image width / Active pixels 3840

Image height / Active lines 2160

continued...


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FPGA IP Parameters Value

Note: The CVO II parameter setting isspecific for 4K video resolution.For other video resolution, refer

to VESA monitor timingstandard specifications.

Bits per pixel per color plane 10

Number of color planes 3

Number of pixels in parallel 4

Separate syncs only - Frame/ Field 1Horizontal sync

32

Separate syncs only - Frame/ Field 1Horizontal front porch

48

Separate syncs only - Frame/ Field 1Horizontal back porch

80

Separate syncs only - Frame/ Field 1Vertical sync

5

Separate syncs only - Frame/ Field 1Vertical front porch

3

Separate syncs only - Frame/ Field 1Vertical back porch

54

Pixel FIFO size 3840

FIFO level at which to start output 3839

Use control port 4

Test Pattern Generator II Bits per color sample 10

Number of pixels in parallel 4

Color planes transmitted in parallel Yes

Output format 4:4:4

Maximum frame width 3840

Maximum frame height 2160

Default Interlacing Progressive output

Number of test patterns 1

Pattern Color bars

Subsampling & Colorspace RGB

2. Add Clock Bridge (160MHz clock input to TPG II and CVO II) for VIP and exportout the input port.

3. Add Reset Bridge (active low reset with none synchronous edges) for VIP andexport out the input port.

4. Connect the CVO II and TPG II Intel FPGA IP instances in the Platform Designer.


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Figure 6. Connecting the CVO II and TPG II in the Platform Designer

Main Clock

Main Reset

Test Pattern Generator II

Dout

Main Clock

Main Reset

Clocked Video

Clocked Video Output II

Din

VIP Clock Bridge

VIP Reset Bridge

Note: The CVO II and TPG II Intel FPGA IPs share the reset input from the resetgenerator output. Ensure the Clocked Video Port of CVO II FPGA IP signalsare exported out from Platform Designer.

5. Save the changes, run Sync System Info & Validate System Integrity. Afterthat, proceed to Generate HDL.

Note: By adding TPG II, CVO II, Clock and Reset Bridge in the system, design toplevel instantiations of dp_core modules needs to be updated. Refer to theInstantiation Template in Platform Designer and update your top levelinstantiation accordingly.

Note: Ensure the TPG II, CVO II, Clock and Reset Bridge are listed in the QuartusProject Navigator. If it is not available, manually add the IPs in the QuartusSettings > Files.

6. At the top level design file, connect the signals in the DisplayPort TX sub-systemas shown below.

Figure 7. Video PLL with Tx_vid_clk output

video_pll_i

outclk_2(148.5 MHz)

Clocked Video Output II DisplayPort TX Sub-system

Vid_clk Tx_vid_clk

Vid_v_syncVid_h_sync

Vid_dataVid_datavalid

Tx_vid_v_syncTx_vid_h_sync

Tx_vid_dataTx_vid_de

Note: The CVO II and TPG II Intel FPGA IPs share the reset input from the resetgenerator output (reset_n), through VIP Reset Bridge.


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1.5.4. Generated Clocks

Apart from the default clocking scheme in the generated design example, you need togenerate an additional output clock from the video PLL. To do that, double click onvideo_pll_a10.ip on Quartus Project Navigator to open IP Parameter Editor.

Table 8. DisplayPort TX-only Design Generated Clocks

Clocks Signal Name Description

outclk_0 (default) vip_clk 160 MHz output clock that acts as the main clock for CVO IIand TPG II FPGA IP instances through VIP Clock Bridge.

outclk_1 (default) clk_16 16 MHz output clock for DisplayPort Source 1 Mbps AUXchannel interface.

outclk_2 (user-generated) tx_vid_clk 148.5 MHz output clock for DisplayPort TX and CVO II videoclocks.Note: The 148.5 MHz clock frequency supports the native

4K or UHD resolution video output. Other videoformats may run at different clock frequency.

After you make the changes, click Save and Generate HDL.

1.5.5. Making a Direct Connection to the TX Transceiver Block

The existing dynamic DisplayPort parallel SST loopback with PCR design example usesthe Transceiver Arbiter to share between an RX and TX transceiver within the samechannel. As the TX-only design only requires the TX transceiver, you need to removethe Transceiver Arbiter and make a direct connection to the TX transceiver.

1. Before you make the connection, in the Platform Designer turn on the ShareReconfiguration Interface parameter in the Transceiver Native PHY block toallow for single Avalon-MM slave interface for dynamic reconfiguration of allchannels.

2. Update the transceiver signal width as shown below in the design top-level andthe tx_phy_top.v files.

Table 9. TX Transceiver Signals

Signal Direction Width (Bit)

gxb_tx_rcfg_write Input 1

gxb_tx_rcfg_read Input 1

gxb_tx_rcfg_address Input 12

gxb_tx_rcfg_writedata Input 32

gxb_tx_rcfg_readdata Input 32

gxb_tx_rcfg_waitrequest Input 1

3. Make a direct connection from the Bitec Reconfig block to the TX transceiver blockin the tx_phy_top.v file as shown in the diagram below.


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Figure 8. Bitec Reconfig and TX Transceiver Block Connection

tx_phy_top

TX Transceiver Reconfig Interface

TX Transceiver Interface

tx_rcfg_write

tx_rcfg_read

tx_rcfg_address

tx_rcfg_writedata

tx_rcfg_readdata

tx_rcfg_waitrequest

tx_rcfg_cal_busy

gxb_tx_rcfg_write

gxb_tx_rcfg_read

gxb_tx_rcfg_address

gxb_tx_rcfg_writedata

gxb_rx_rcfg_readdata

gxb_rx_rcfg_waitrequest

gxb_rx_rcfg_cal_busy

4. Remove the following Transceiver Reconfig Group assignments from the IntelQuartus Prime Settings File (qsf).

• - set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -tofmca_dp_c2m_p[0] -entity a10_dp_demo





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1.5.6. Modifying the Software

After removing the irrelevant blocks and reconnecting the remaining blocks with thenewly instantiated FPGA IPs, modify the software.

1. First, modify the software's config.h file. Navigate to the design example folderand change the values of the following parameter settings in the file.

Table 10. Config.h Parameter Settings

Parameter Value Description

BITEC_AUX_DEBUG 0 Set to 1 to enable AUX channel trafficmonitoring.

BITEC_STATUS_DEBUG 1 Set to 1 to enable MSA and link statusmonitoring.

DP_SUPPORT_RX 0 Set to 1 if the DisplayPort supports RX.

BITEC_RX_GPUMODE 0 Set to 1 to enable Sink GPU mode.

BITEC_RX_CAPAB_MST 0 Set to 1 to enable MST support.

BITEC_RX_FAST_LT_SUPPORT 0 Set to 1 to enable Fast Link Training support.

BITEC_RX_LQA_SUPPORT 0 Set to 1 to enable Link Quality Analysissupport.

BITEC_EDID_800X600_AUDIO 0 Set to 1 to use an EDID with maximumresolution 800 x 600

BITEC_DP_0_AV_RX_CONTROL_BITEC_CFG_RX_SUPPORT_MST

0 Set to 1 to enable MST support

DP_SUPPORT_TX 1 Set to 1 if DisplayPort supports TX

BITEC_TX_CAPAB_MST 0 Set to 1 to enable MST support

TX_VIDEO_IM_ENABLE 0 Set to 1 to enable TX Video IM interface

DP_SUPPORT_EDID_PASSTHRU 0 Set to 1 to enable EDID passthrough from sinkto source.

BITEC_DP_CARD_REV 0 • Set to 0 = Bitec FMC DisplayPort daughtercard revision 4 – 8 (without ParadetechRetimer)

• Set to 1 = Bitec FMC DisplayPort daughtercard revision 9 or later (with ParadetechRetimer)

MST_RX_STREAMS 0 RX MST number of streams

MST_TX_STREAMS 0 TX MST number of streams


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Note: You must select a correct Bitec FMC DisplayPort daughtercard revision. Makethe selection in the Config.h and design top level file.

2. Since DisplayPort TX-only design does not require a retimer at RX, remove belowcode in the software/dp_demo/Main.c.

#if (BITEC_DP_CARD_REV == 1) // Bitec Daughter Card Rev 10 // Init the PS8460 I2C interface intel_fpga_i2c_init(I2C_MASTER_BASE, 100000000);

// Set the PS8460 P4 registers // Set the PS8460 equaliser as required by your design intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x09, 0x02); intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0B, 0xC4); // Enable EQ from I2C register,squelch enabled intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0C, 0x55); // HBR RBR EQ intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0D, 0x85); // HBR2 EQ intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0E, 0x05); // HBR3 EQ intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x9A, 0x88); // L1_VOD L1_PRE L0_VOD L0_PRE intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x9B, 0x88); // L3_VOD L3_PRE L2_VOD L2_PRE intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0xA4, 0x08); // Full Jitter cleaning mode#endif

#if (BITEC_DP_CARD_REV == 2) // Bitec Daughter Card Rev 11 unsigned int data;

// Init the MCDP6000 on the Bitec Sink main link input // (on the Bitec daughter board) // Set the MCDP6000 as required by your design intel_fpga_i2c_init(I2C_MASTER_BASE, 100000000);

data = 0x0001704E; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0504, (unsigned char *)&data, 4); data = 0x00000601; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x01D8, (unsigned char *)&data, 4); data = 0x00005011; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0660, (unsigned char *)&data, 4); data = 0x00000001; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x067C, (unsigned char *)&data, 4); data = 0x55801E14; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0A00, (unsigned char *)&data, 4); // MC solution #2 data = 0x0000001F; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0350, (unsigned char *)&data, 4); // MC solution #3

#endif

3. In the Intel Quartus Prime Pro Edition software, the bitec_dptx_init()function is only called when DP_SUPPORT_EDID_PASSTHRU is enabled inConfig.h. Since DP_SUPPORT_EDID_PASSTHRU is not needed for this design, DPTX will never get initialized. To avoid this, bring out the bitec_dptx_init()function from the #if DP_SUPPORT_EDID_PASSTHRU directive so that the functioncan run. For example:

// Init Bitec DP system library#if DP_SUPPORT_TX btc_dptx_syslib_add_tx(0, DP_TX_DP_SOURCE_BASE, DP_TX_DP_SOURCE_IRQ_INTERRUPT_CONTROLLER_ID,


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DP_TX_DP_SOURCE_IRQ); btc_dptx_syslib_init(); bitec_dptx_init(); #endif

4. Remove the bitec_dp_dump_sink_msa() andbitec_dp_dump_sink_config() from the Main.c.

5. Next, for debugging purposes, modify the debug.c file located in the software/dp_demo folder. Open the debug.c file and remove the voidbitec_dp_dump_sink_msa() and void bitec_dp_dump_sink_config()functions.

Note: Any modifications you make in the debug.c and Main.c, the script will beoverwritten each time you rebuild the software. To prevent this, place acopy of the modified Main.c and debug.c file in the main software folderbefore you rebuild your software.

6. In a Nios II Command Shell, cd into the script directory and ‘source build_sw.sh’to update software. The updated dp_demo.elf file is located in the software/dp_demo directory.

Note: • After you make any change to the software (ie: config.h or any othersoftware file), you must run build_sw.sh script from a nios2-terminalto ensure the software (dp_demo.elf) file is accurate.

• The IP components in the Platform Designer are utilized in thegeneration of the BSP (Board Support Package). For this reason, it isalso imperative to regenerate software if you make any changes orupdates within the Platform Designer dp_core system as well.

• If design has already been compiled and a10_dp_demo.sof imagepreviously generated, load dp_demo.elf from a nios2 command shelland run ‘nios2-download dp_demo.elf’ in the Nios terminal. Use pushbutton reset on the Intel Arria 10 GX development kit for softwarechanges to take effect.


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1.6. Document Revision History for AN 883: Intel Arria 10DisplayPort TX-only Design

DocumentVersion

Changes

2021.07.03 • Edited the Description for TX Video Clock in Table: Clocking Scheme Signals.• Added the steps to extract the files in the .par file in Compiling and Testing the Design.• Added the software version 18.1 for Intel Quartus Prime Pro Edition in Creating the TX-only Design

with Bitec FMC Daughter Card.• Added a note and renamed Table: Example of IP Parameters Value to Generate a 4kp60 Output

Video.• Added subtopic Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File and

Removing Irrelevant Block in Platform Designer in section Removing Irrelevant Blocks.• Edited the Instantiating Video and Image Processing (VIP) Intel FPGA IPs.

— Changed the Value from 8 to 10 for Bits per pixel per color plane in Table: Clocked Video Output(CVO) II and Test Pattern Generator (TPG) IIParameter Settings.

— Edited Figure: Connecting CVO II Intel FPGA IP to the DisplayPort TX Sub-system.— Added Figure: Video PLL with tx_vid_clk output.

• Added a new column Signal Name in the Table: DisplayPort TX-only Design Generated Clocks.• Changed Figure: Bitec Reconfig and TX Transceiver Block Connection.• Added the instructions in Modifying the Software.

2019.02.20 Initial release.


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Date post:	26-Dec-2021
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AN 883: Intel Arria 10 DisplayPort TX-only Design

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