UCL- June 2001 1
LABORATOIRE DE MICROELECTRONIQUEBATIMENT MAXWELL B-1348 LOUVAIN-LA-NEUVE BELGIQUE
An Approach to the Design of
Analog Fuzzy Logic Controllers in CMOS Technologies:
Implementation, Test and Application
Carlos Dualibe
UCL- June 2001 2
FUZZY LOGIC: Formalism for codifying Human Reasoning within a Numerical Framework.
FUZZY SYSTEM: Model-Free Universal Approximator. Structured Knowledge Base (“if-then” rules)
Usefulness: To solve problems that are either difficult to tackle mathematically or where its use provides improved performances and/or simpler implementations.
Engineering Applications : -Process and Environmental Control(examples) -Robotics and Automation -Automotive Industrial Applications -Signal and Image Processing
-Power Electronics-…………
UCL- June 2001 3
10 100 1000
ns
s
ms
s
ElectronicSystems
Micro-mechanicalSystems
MechanicalSystems
ExpertSystems
Complexity (fuzzy rules)
Syst
em r
espo
nse
tim
e
10 100 1000
ns
s
ms
s
Complexity (fuzzy rules)
Syst
em r
espo
nse
tim
eDedicated ASICs
Fuzzy Coprocessors
General Purpose Processorswith fuzzy support
32-bit microcontrollers
16-bit microcontrollers
8-bit microcontrollers
a) b)
Hardware Implementation Choices for Fuzzy Controllers
Allocation of the applications in the space [Complexity ; Time Response]
Allocation of hardware solutions in the space [Complexity ; Time Response]
Intended Target Applications: Signal and Image Processing, Power Electronics
UCL- June 2001 4
Why Analog?
Main Goals of this Work•Comprehensive study of the Analogue Fuzzy Operators
•Design and Test of Programmable Architectures for Analogue Fuzzy Controllers
Secondary Goal: •To undertake preliminary studies of an embedded Fuzzy Logic application
in the field of Signal Processing.
•Fuzzy Processing is analog in ‘nature’.•Usual applications demand reduced accuracy.•Low Power and/or High Speed•Reduced Complexity: Small area – No need of A/D and D/A
to interface Sensors and Actuators•Ideal for Embedded Subsystems.
UCL- June 2001 5
FuzzificationInterface
DecisionMaking Unit
DefuzzificationInterface
Inputs Outputs
Fuzzy Controller Architecture and Fuzzy Algorithms
Suits optimal for Hardware Implementation !
R1:Building Blocks:
•Membership Functions
•T-Norms ; T-CoNorms
•Consequents
•Defuzzifiers
R2:
Fuzzy Controller
x* y*
x y
w2
x y
w1
(x*)A2μ
(y*)B2μ
(y*)B1μ
(x*)A1μ
IN PU T S
z
z
C
C
C 2
C 2
*C2 *C1
z
Z dz μ(z) Z dz μ(z) z
*z
z*
z1= a1 x* + b1 y* + c1
z2= a2 x* + b2 y* + c2
w2 w1z2 w2 z1 w1 *z
A ntecedent part of the rules Consequent part of the rules
T-N orm = M in M A M D A NI TA K A G I-SU G EN O
(z)zμ
UCL- June 2001 6
I1 I2
DA1 DA2
Mc1 Mc2
V
M1 M2
IoVin Vk
Md1 Md2
Md4Md3
Md5
Md6
Ip Vin- Vin+
Vdd
Vout
Vs
Vds
V k V in [V ]
I [A ]
Io
Io2
I2 I1
2
gmαtg
VsVTp - Vdd(W/L) 2
(W/L)
(W/L) 2
(W/L)VinVinVds
Md1
Md5
Md2
Md5-
Vds2-M1L
WμCox gm
Vds
Circuit : M1, M2Triode Non-Symmetric Diff. Amp. DA1,DA2
(W/L)Md1 > (W/L)Md2
Transfer Curve: Slopegm CrossoverVk
Membership Functions Circuits: -Trapezoidal Shapes Based on Triode Transconductors
TYPE –I: Differential Regulated Cascode Triode Transconductor
UCL- June 2001 7
Transfer Curve: Slopegm KneeV2=Vk + n Vds/2
Vds
Circuit : M1TriodeM2 Saturated
Membership Functions Circuits (2):
TYPE –II: Single Regulated Cascode Triode Transconductor
Vin [V]
I1 [A]
Io
I1
V1 V2 V3 V4IogmM1
I1
I2
DA
Mc1
VM1 M2
Vk
Vdd
Vin Io
a) b)
gmM1 << gmM2
tg = gmM1
n = Subthreshold slope factorM2: Large size transistor aimed for setting a conduction threshold
UCL- June 2001 8
Iout1
Io
Io2
Vk1 Vk2 Vin Vk1 Vk2 Vin
Iout2
Io
3Io2
2Io
gm22
gm12
gm22
gm12
a) b)
gm1 gm2
Vk1 Vk2Io IoVin
Iout1 Iout2
Complementary FMF (CFMF) Direct FMF
Membership Functions (3) : Four Independent Parameters 2 slopes (gm1, gm2); 2 Crossover (Vk1 , Vk2)
UCL- June 2001 9
Analogue Programming: Electrically Tunable Slopes by setting Vds
Discrete Programming: large slope range is optimally allowed by a set of (W/L)s:
Small Slopes can be set by using small Vds rather than very long channel Transistors
Increased Current Consumption (Differential Amplifiers at the Regulation loop)
More sensible to Mismatch (Triode transistors Vds)
min
maxminmax
gmgm
W/LW/L
2
mingm
maxgm
minW/LmaxW/L
Triode Saturated
Membership Functions Circuits (4): Comparison against saturated transconductor
i+ i-
Iovi+ vi-
UCL- June 2001 10
Vin
Vk1Vk2Vk3Vk4
Io
I1I2I3I4I5
Vs1Vs2Vs3Vs4
VddVddVdd
Membership Functions Circuits (6): Full Programmable Compact Fuzzy Partition
(Based on [1])
[1] Willamosky B. et al, ANNIE’96
SlopesVs1,…Vs4 - Crossover points Vk1<Vk2…<Vk4
SPICE simulation for a 7-label
Circuit: Io= 10A, Vdd=5V
Reduced number of transconductors
Reduced Current Consumption
Cumulative mirroring errors and delay due to cascading
UCL- June 2001 11
T-Norm
or
T-CoNorm
T-Norm and T-CoNorm circuits: General Requirements
In1
InN
Out
• Multiple inputs (N)
• O(N) Complexity: Size and consumption proportional to N
• Parallel Processing: No cascade tree of binary operators
• Inputs Transparency: Same load at each input - Same input/output delay
Circuits: - Improved Lazzaro’s WTA-MAXIMUM
- Mixed-Mode O(N) MAXIMUM
- O(N2) LTA-MINIMUM
- O(N) LTA-MINIMUM
UCL- June 2001 12
T-Norm and T-CoNorm (1): Lazzaro’s WTA-MAXIMUM
M1
Imax
Mc
Mo
Vdd
Vbias
I1IN
M1
Imax
Vdd
I1IN
Mo
a) b)
M2
M1
M2 M2M2
M1
Mc Mc
•N current-controlled voltage-sources ( M1, M2 ) ‘fighting’ in parallel
• Propagation error Early effect in M2 ( Mo)
• Discrimination error: Early effect in M2 - inversion degree of M1
• Mismatch error: VT and of M2, Mo
Concept Improved Version
Systematic Errors: ~1.6%
UCL- June 2001 13
Ids
Vgs
M1 MOST
Vt
0 Emax
M1
Imax
EE
I1=5A I2=pulse 3A to 7A - 100ns
T-Norm and T-CoNorm (2): Lazzaro’s WTA-MAXIMUM
Delay & Undershot Improvement!
E
UCL- June 2001 14
T-Norm and T-CoNorm (3): Mixed-Mode MAXIMUM
I1
M1A
C
M2
Mpc
IN
M1A M2
Mnc
Iout=MAX(I1....IN)
Id Id
MnMn
MpMp
Ms
V-V+ Vout
IQ Ip
Vdd
MAX_1
12
N
Mpc_1
MAX_k
12
N
Mpc_k
CFMF
M1 RULE_1
RULE_k
WIRE
Ii
Imax_1
Imax_k
Distribution of Input Signals
achievable in voltage-mode !!
•Set of N Source Followers ‘fighting’ in parallel
•Propagation error: Voff = offset of A
•Discrimination error: Ao = DC gain of A
•Mismatch errors: due to Voff mainly
Systematic Errors: ~2.3%
UCL- June 2001 15
T-Norm and T-CoNorm (4): New O(N2) LTA-MINIMUM [2]
[2] Dualibe, Jespers, Verleysen,
IEEE ISCAS’2001
I1 I2
Imin
Mp1
Mp4
Vdd
Mn1 Mc
1:1
1:1 1:1
1:1
I1 I2
Imin
Mp4
Vdd
Mn1 Mc
1:1
1:1
1:1
Vo1 Vo2
V1 V2 V3
a) b)
V4
Vout
Mn2 Mn2
Mp5Mp6
Mp3Mp2
Mp5
Mp2
Mp6
Mp3
2-Input LTA & MINIMUM 2-Input MINIMUM
• Parallel comparison between input currents -Vdd limits the number of inputs
•Propagation error: Due to the Early Effect in transistors Mp
•Discrimination error : with the impedance of internal nodes (i.e.: V2)
•Mismatch errors: Associated with mirrors Mn and Mp
Systematic Errors: ~3%
UCL- June 2001 16
T-Norm and T-CoNorm (5): New O(N) LTA-MINIMUM [3]
[3] Donckers, Dualibe, Verleysen,
IEEE ISCAS’2000
Ii Iop
Ion
Imin
VoiIoi
Cell-i Common Cell
Nc
M1
M2
M3
M4
Mn
Mp
Vdd Ii Iop
Ion
Imin
Ioi
Cell-i Common Cell
Nc
M1
M2M3
M4
Mn
Mpc
Vdd
NbM5
M6
V5V4
V1V2
a) b) c)
Ii
Mpi
Concept Improved Version with current feedback Ii Mirror
• N current-controlled voltage sources (Cells-i) ‘fighting’ in parallel
• Current feedback improves accuracy of the MINIMUM (~ enhanced Wilson mirror)
•Systematic error (~0.4%)
•Mismatch error: due to VT and of M5, M6
UCL- June 2001 17
Defuzzifiers : Closed Loop Defuzzifiers
G1
I1
mGm
Im
Gi = f (Ii); for i = 1....m
Gi
Gi αiVo
m
FMF T-Norm
Io = Ii = constant
I1
Im
Iout= i Ii
Feedback control node
a) b)
Ii
Ii αi IoIi αiIout
singleton
I1
mIm
singleton
Voltage mode Current mode• Complexity increases with the
number of rules
• May need frequency compensation
due to feedback: speed
• FMF or T-Norms’ gain must be controlled
•May need frequency compensation
due to feedback: speed
UCL- June 2001 18
Defuzzifiers(2): Open Loop Defuzzifiers
m
I1
Im
D I V
i I i
I i
V o
Io u t = i I iN
I1 N Im N
R 1 R mI1 Im
Io = I iN = C o n stan t
m Im N I1 N
m
cu rre n t m irro r (s ing le to n )
s in g le to n
IiN = I i H (I1 ,I2 ..I i. .Im )
a ) b )
Ii
Ii αi Vo
Pseudo-Normalizer Divider
•Complexity may increase with the number of rules (i.e.:R1….Rm)
•Only one extra mirror per rule to compute denominator
UCL- June 2001 19
Defuzzifiers(3): Open Loop Defuzzifier with Divider
‘Common Weighting’ strategy for digitally programmable singletons.
T-Norms
D/A
DIV.
Defuzzifier
C1n-1 C1o
I1
(n+1) Curr. Mirrors Im
Ii
Vo
Ii αi
(n+1) Curr. Mirrors
Cmn-1 Cmo
: 1 : 1 : 1 : 11
Ii
to DIV (i) to D/A
i
2 : 1 4 : 1 2n : 1
Vddm
D/Ato DIV (ii)
n-mirrors
• ‘n’ mirrors per singleton
•Silicon surface and input capacitance of each singleton result much smaller than in the ‘local weighting’ approach (i.e.: (2n/n) times reduced)
•Only one D/A- Can be optimized to get desired accuracy
•Simplicity
UCL- June 2001 20
NnNd
Defuzzifiers(4): Novel Two-Quadrant Analog Divider [4]
M1 M2 M3
M4
M5
M6
M7M8
M9
INID
Vdd
Vb1 Vbo Vout
I1 I2 I3
1 : 1 : k
• M1= M2=M3triode
Input Nodes Nd and Nn become resistive!
Thus: Vout-Vbo= (Vb1-Vbo) (IN/ k ID)
•Current/input voltage/output IDEAL!
•Systematic errors: - Mainly due to mobility reduction in triode transistors M1, M2, M3. - Gain error and offset can be neglected if cascoded PMOS mirrors are used (M7, M8, M9).
•Mismatch errors: -For small current ID, strongly influence of mismatch of VT between transistors M4,M5,M6.
[4] Dualibe, Verleysen, Jespers, IEE Electronics Letters, 1998.
UCL- June 2001 21
a) b)
(Vou
t-V
bo)
[V
]
IN [A] ID [A]
rela
tive
erro
r
ID=10A
IN=8A
Defuzzifiers(5): Two-Quadrant Analog Divider-Measurement
(Vout-Vbo) vs. IN:
0< IN <10A; 10A< ID <30A
Relative errors vs. ID:
2 A < IN < 8A; 10A< ID <30A
Non-Linearity: 1% ~ 100% swingoutput maximum
deviation maximumNL
(+) Measured
(-) Calculated
UCL- June 2001 22
Defuzzifiers(6): Comparison Against other DividersWiegerink R., Kluwer A. P., 1993
Huertas et al, Trans. Fuzzy Systems, 1996
Current-to-voltage converter Divider
Id-Ic
Ib-Ia v2)(v1
β
β'V2V1Vo
• Need extra I-to-V converter•Differential currents inputs•NL = ~1% (only divider)
2IB
IxIyIout2Iout1Iout
• Inputs must be supplied at different nodes at least twiceAdditional mirroring errors•NL = ~1%
UCL- June 2001 23
Defuzzifiers(7): Electrically Programmable Singletons
M1 M2 M3
M4M5
M7M8
M9
Iout
Iin
Vdd
Vb1 Vbo
1 : 1 : 1
1:B
M10
M11
M6
Vb2
a) b)
Iin Vbo)-(Vb1
Vbo)-(Vb2 B Iout
New Electrically Tunable Linear Current-Mirror
Spice Simulation: 1V<Vb2<1.5V
M 1 M 2
Iin Iout
V c1 V c2 V ref2V c2
Iin VTn)(Vref1
VTn)(Vref2
β
β Iout
M1
M2
V ref1 V c1
Other Approach:
Sasaki et al, 3th Int. Conf. On Industrial Fuzzy Control and Intelligent Systems
1993
UCL- June 2001 24
Estimation of the global accuracy of the Controller
VinCFMF T-Norm
Iout Iout1
Consequent + D/A
Mirror 1:1
DividerVout
fo f1
f2
f3
f4
IN
ID
σ a σ a σ a σ a σ a σ a σ 2FMFFMF
2IoIo
2Norm-TNorm-T
2mirrormirror
2D/AconsD/Acons
2divdiv
2Vout
a) b)
Unrealistic! Divider
Singletons +D/A
Mirror
Only One Fired Rule: 2% < Vout/Vout <3%
Vout %
UCL- June 2001 25
Estimation of the global accuracy of the Controller(2)
a) b)
Vout for: 0.1< 1 < 0.9
2=0.9
%: (+) Divider
(o) CFMF+T-Norm+Io
Two Fired Rules in a complementary way: 2.5% < Vout/Vout <3.5%w
u
S M B
S
Z
F
25
UCL- June 2001 26
• Standard CMOS Technologies Mixed Signal : Analogue Processing + Digital Programming
• Current-Mode vs. Voltage-Mode: Current Mode Voltage Mode
Analog Computation:…………. + -
Signal Routing…….:…………..- +
Chip external Interface:……….. - +
MIXED MODE
• Building Blocks Interface: Avoid the use of extra V-to-I or I-to-V convertersImproves Delays and Accuracy.
• Modularity: Share operators (i.e: Membership Functions Circuits, Common weighting)
•Transistors Sizing: Large size Good MatchingPoor Integration Density (dedicated controllers)
Small size Poor MatchingGood Integration Density (programm. controllers)
Programmability can help to relax sizing requirements for a given accuracy!
Programmable Fuzzy Architectures: General Guidelines
UCL- June 2001 27
A 9-Rule 2-Input 1-Output Programmable Fuzzy Controller [6]
CFMF21 CFMF22 CFMF23
CFMF11 CFMF12 CFMF13
Digital bus for CFMFsprogramming
Vin1
Vin2
MAX
MAX (n+1) Curr. mirrors (1:1)
(n+1) Curr. mirrors (1:1)
Cn-1 Co
D/A
DIVVo
1
9
Digital bus for singletonsprogramming
Rules-Evaluation
Ii i * Ii
+_
+_
2
Fuzzifiers & Rules Set Defuzzifier
2
singleton
I1
I9
Io
Io
•Zero-Order Controller-Fixed Number of Rules (Grid Partition)•Complementary MF Labels (Type II – Three per input)• T-Norm: Complemented Lazzaro’s MAXIMUM•Defuzzifier: ‘Common weighting’•Discrete Programming of Antecedents and Consequents •Intended for embedded applications
[6] Dualibe, Jespers, Verleysen, IEEE ISCAS’2000
UCL- June 2001 28
Iout
DA1
Mc1
VM1 M2
IoVin Vk
Is Is 2Is
s2 s3
Vs1Ms1
Vdd
Vdd
Vdd
Vs1
Vdd
MR1
p4
16Ip
Vk
R
MR2
MR3
p3p2p1p0
Ip 2Ip 4IpIp 8Ip
s1s0
Is
M1_0 M1_1 M1_2
S2 S3
Vin
Mp1
Mp2
9-Rule Fuzzy Controller (1): Membership Function Programming
Linear Resistor
•Local setting of analog parameters
•s0…..s3Slopes (2x4-bit)
•p0….p4Knees (2x5-bit)
•Measured CFMF Type-II:
•Io=10A ; Vdd=5V
•Input Range: 1.5V<Vin<4.5V
Half CFMF Type-II
UCL- June 2001 29
9-Rule Fuzzy Controller (2):Test Result
RMSE _max Mean()
27mV (2.7%)
62mV (6.2 %)
35mV (3.5%)
TARGET MEASURED
Relative Error Surface Relative Error Distribution
Settling time (90%):
S.Signal: ~190ns
L.Signal: ~450ns
UCL- June 2001 30
9-Rule Fuzzy Controller (3):Comparison
[KeSc93] [MaFr96] [GuPe96] [BaHu98] [VaVi99] [DuVe00]
Complexity 9rules@2input
@1output
9rules@2input
@2output
13rules@3input
@1output
9rules@2input
@1output
16rules@2input
@1output
9rules@2input
@1output
Technology 3 Bi-CMOS 0.7 CMOS 2.4 CMOS 2.4 CMOS 1 CMOS 2.4 CMOS
Power
Consumption no data 44mW@5V 550mW@10V 20mW@5V 8.6mW@5V 13.4mW@5V
Input to Output
Delay no data 550ns 160ns 2000ns 471ns 450ns
Precision no data RMSE: 3.33% no data no data MAX: 4% MAX: 6.2%
Interface
(inputs@outputs)
currents@
currents
voltages@
voltages
voltages@
voltages
voltages@
voltages
voltages@
currents
voltages@
voltages
Area 13.75mm2 1.9mm2 16.2mm2 1mm2 1.6mm2 4.5mm2
Programmability
MF Knees:
MF Slopes:
Consequents:
fixed
fixed
fixed
on chip (6b)
fixed
on chip (6b)
off chip
on chip (4b)
off chip
on chip (6b)
on chip (2b)
on chip (4b)
off chip
fixed
on chip (4b)
on chip (5b)
on chip (4b)
on chip (5b)
UCL- June 2001 31
Application Example: Fuzzy Control of a DC/DC “Buck” Converter[9]
Vin
QL
IL
CVout
PW M
D
Dp
Di
E
IL
Vout
Vreft
0
RL
dt E(t)DiE(t))Dp(IL(t),D(t) PWM “duty cycle”:
Dp, Di: Highly Nonlinear functions Small Steady-State Error and Fast Settling Time for RL Changes
([9] Franchi E. et al., IEEE JSSC, June 1998)
UCL- June 2001 32
Application Example(2): Fuzzy Control of a DC/DC “Buck” Converter[10]
DP: 2 Inputs-1 Output 4 Rules
DI: 1 Input-1 Output 4 Rules
Optimal Control Surfaces
([10] Rashid M., Power Electronics-Circuits, Devices and Applications, Prentice Hall, 1993)
UCL- June 2001 33
AntecedentParameters RAM
ConsequentParameters RAM
Configuration RAM
CFMFs Banks Switch Matrix
CFMF-1 CFMF-2
CFMF-3
T-Norms Singletons Columns
MAX-1
MAX-2
MAX-M
Vin1 Vin2 VinN
INPUTS
D/A1 D/A2 D/AQ
Div1 Div2 DivQ
V01 Vo2 VoQ
Zero-Order OUTPUTS
First-Order OUTPUT
QCFMF-F
N Q
A General-Purpose Programmable and Reconfigurable Fuzzy Controller
N 5; Q 3; M 27; F 16
•CFMF type-II
•Programmable MAXIMUM mixed mode O(N)
•SWITCH MATRIX: ‘smartly’ wired
UCL- June 2001 34
D/A_0 D/A_1 D/A_2
Div_0 Div_1 Div_2
Vbo
Vb1
Vin1 Vin2
a0i a1i a2i M-Rules
Vout0 Vout1 Vout2 Vout
Rule-i
Singletons Column - 0 Singletons Column - 1 Singletons Column - 2
sw1 sw2
General-Purpose Controller (2): First-Order Output Configuration
Mi1
INID
V1Vbo
Vout
Vdd
V2VQMi2MiQ
1:1
1:1
1:1Q:1
Q:1
Q:1
INID
Vdd
Vb1 Vbo Vout
Divider
Novel High-Input Impedance Voltage Mode Adder:
1...Mifor Vin2; a2i Vin1 a1i a0i Ci
Vin2Ii
Ii a2iVin1
Ii
Ii a1i
Ii
Ii a0i
Ii
Ii CiVout M
1
M
1M
1
M
1M
1
M
1M
1
M
1
Consequent Rule-i
DefuzzifiedValue
Q
1iVbo)(Vi
IDIN Vbo)(Vout
UCL- June 2001 35
General-Purpose Controller (3): Zero-Order Test Result
Surface RMSE _max Mean()
a) 80mV (4%) 180mV (9 %) 64mV (3.2%)
b) 94mV (4.7%) 240mV (12 %) 75mV (3.75%)
Settling time (90%):
S.Signal: 570ns
L.Signal: 1100ns
Rules Map Measured Surface Relative Errors
a)
b)
UCL- June 2001 36
General-Purpose Controller (4): 4-rules First-Order Controller Test Result
a) b)Measured CFMF Measured Surface
a) b) c)
ANFIS Fitting: A comparison
•1st-Order; 4-rules
•28 parameters
•RMSE: 0.8%
•Zero-Order; 4-rules
•20 parameters
•RMSE: 2%
•Zero-Order; 9-rules
•33 parameters
•RMSE: 1.4%
UCL- June 2001 37
3 4 5 6
7
8 9
10 11 12 13
13 1
2
COMPARISON
[FaMa94] [FrMa98] Our Approach
Technology 0.8 CMOS 0.7 CMOS 2.4 CMOS
Processing Mode Sampled Time Continuous Time Continuous Time
Complexity
Mamdani:
32rules@8input
@4output (max)
Zero-Order Sugeno:
15rules@3input
@1output (max)
Zero and First-Order Sugeno:
27rules@5input
@3output (max)
Power supply Vdd=5V Vdd=5V Vdd=5V
Power
Consumption no data 44mW (2.93mW/rule) 63mW (2.33mW/rule)
Input to Output
Delay ~2S ~600ns ~1.1s
Accuracy no data RMSE < 3% RMSE < 4.7%
Interface
(inputs@outputs)
digital@
digital
voltages@
voltages
voltages@
voltages
Input Range 8-bits 2V 3V
Output Range 6-bits 2V 2V
Area 70mm2 33mm2 (2.2mm2/rule) 39.5mm2 (1.4mm2/rule)
Programmability
MF Crossover:
MF Slopes:
Consequents:
on chip(8b)
on chip(5b)
on chip (6b)
on chip (6b)
fixed
on chip (6b)
on chip (5b)
on chip (4b)
on chip (5b)
Total storing capacity needed
~3200 bits 16000 bits 909 bits
UCL- June 2001 38
-Same L (keep same Early)
-W W/2 ===>50% Area Reduction
!t!Improvemen Mismatch 50%LW
2VToA
21
2LW
1 4
2VToA
L*W
2*VToA
2VToσ
General Purpose Controller (6):Further Improvements
•Scaling to Modern Technologies: Cox Early AVTo
CMOS 2.4 50 A/V 10V/ 24mV
CMOS 0.8 100 A/V 10V/ 12mV A) Analog Circuits:
2VTo - Vgs LW Cox)(u
2n1Id
Same Vdd, VToSame Current
2 2
Silicon Area
Mismatch
B) Digital Circuits: theoretical scaling factor: (1/9). Let us assume (1/4.5).
Total Area Reduction: 39.5mm2 == 13.6mm2
UCL- June 2001 39
Time-Domain Signal Analysis Using Fuzzy Logic and its Application to Self-Adaptive Channel Equalization
t
S(t) y~S(t)
x~t
Signal 2D-Figure
Features Extraction
Reference Pattern
Fuzzy Decision Making
Assertions
Fuzzy Inference System
General Setup
Built-in ‘Oscilloscope’: inferred Assertions could be used for adaptation, detection, testing, etc.
UCL- June 2001 40
Continuous-Time Self-Adaptive Equalization based on the Eye-Pattern [8]: System Architecture
Adaptive Equalizing System Control Surface related to the Eye Pattern
• On-Chip Real-Time Scope: SIGNAL 2D-FIGURE (EYE PATTERN)
•Controller’s Decision Making : “Keep ACTUAL EYE within AREA TOLERANCE”
•Controller’s Output: EQUALIZER’S ZEROS PLACEMENT
A) B)E(s) = (s-z) (s+z)
[8] Dualibe, Jespers, Verleysen, IEEE ISCAS’2001
UCL- June 2001 41
Fuzzy Logic Controller : Rule Base and Input Partition
Vt
NB N Z P PB
NB
N Z
PPB
Vs
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
Area ToleranceBoosting must Increase Boosting must Decrease
•RULE BASE: 25-Rules controlling Equalizer Amplitude Boosting (5-labels per input)
•Area Tolerance: immunity to NOISE, RINGING, PULSE SHAPE, ETC
UCL- June 2001 42
Architecture of the Fuzzy Controller
•Zero-Order Sugeno :25 rules•Fuzzifiers: 5-Labels per input.•T-Norms: 2-input MINIMUM (O(N2) )•Defuzzifier: Averaged Weighted Sum•Discrete Programming of singletons (5-bits)
MIN MIN MIN MIN
Vs
Vt D/A
Div.
NB N Z P PB
NB N Z P PB
Fuzzy Partition Circuits
T-Norms Defuzzifier
(n+1) Curr. Mirrors (1:1)
Cn-1 Co
I1
(n+1) Curr. Mirrors (1:1)
Cn-1 Co
25 I25
Ii Ii αi
Vo
UCL- June 2001 43
5-Labels Fuzzy Partition Circuit
INB
Io
Vk1
IN
Vk2
IZ
Vk3
IP
Vk4
IPB
Vin
Ma
Mb
Mc
Vdd
•Chained differential pairs: low consuming, small area and compactness
•Vk1<Vk2<…..<Vk4 fix the crossover points
•Fixed slopes at mask level by transistors Ma size
SPICE simulation for Io=10A
Vin
UCL- June 2001 44
Fuzzy Controller Test Results
Measured
Target
Fuzzy Logic Controller
Technology: CMOS-2.4
Complexity: 25-Rules; 2-inputs; 1-output
Power Supply: 5V
Power Consumption:
4.4mW
Area: Analog: 2.9 mm2
Digital: 1.1 mm2
RMSE: 4.5%
Input/Output Delay (90% Steady State):
S. Signal: 380ns
L. Signal: 900ns
UCL- June 2001 45
•Use Tree Partition for the input space to minimize rules set ONLY 11 Rules
•Input Vs Compact 5-Label Fuzzy partition circuit
•Input Vt Six individual Membership Functions
R1 R2 R3
R4
R5 R6 R7
R8
R9 R10 R11
Vs
Vt
Fuzzy Controller: Improvement
UCL- June 2001 46
Amplitude-Boosting Gm-C Filter
Vin
Vout
C1C2gm1
gm2
gm5
gm4gm3
•gm1=gm3=gm5=gmmaxfix
•gm2=gm4tunable up to gmmax
Symmetric Zeros at:
gmmax
gm4Kz with ;
C1C2
gmmax Kz z2z1,
Bi-Quad Filter: A)
Phase
Amplitude
Theoretical Frequency Response
UCL- June 2001 47
New Full Electrically Tunable Triode Transconductor [9]
Transconductance:
Vbo)-(Vb1
Iz Bk
2
1gm
•Linear tuningIz
•Phase error < 2°M1 M2 M3
M5
M8M9
Iz
Vb1 Vbo
Vin+
M11
Iout+M6
M10
M12
M14
M16
Iout-M13
M15
Vin-
M4
M7
M1 M2M3
M4
M5
M6
M7M8
M9
INID
Vb1 VboVout
Vdd Vdd
I+I-
1:BB:1
a) b)
k : 1 : 1 : k 1 : 1 : k
Transconductor: Divider:
Vin+
Iout+
Io
Vin-
Iout-
Io
IL
Io
Io
Iogm
Vout+Vout-
Vout- Vout+VCM
Vdd Vdd
VCMcnt
Vbiasal
+
+
Mal1
Mal2
Mal3
Mal4
Me1 Me2 Me3 Me4
Me5
Me6
Me7
Me8
a) b)
-
-
CMFB with adaptive Bias Io [10] Improved common-mode voltage stability upon tuning.
CMFB
[9] Dualibe, Jespers Verleysen
IEEE ISCAS’2001 [10] DeLima, Dualibe, IEEE ISCAS’2000
UCL- June 2001 48
Equalizing Filter Test Results
BiQuad Gm-C filterTechnology: CMOS-2.4
Power Supply: 5.5V
Power Consumption:
22.6mW (nominal)
(Iz=25 A )
Area: 5.3mm2
Max. Boost : 30dB (@7Mhz.)
Tuning range: 15A< Iz < 35A
Measured AC Response
UCL- June 2001 49
Cable Equalization (simulations)
a) b)
Signals for L=360mFs = 5Mb/s
Kz evolution forL=120, 240, 360m
Eye Pattern: before and after the equalizer
Cable: CAT5 UTP
A1) A2) B1) B2)
UCL- June 2001 50
Adaptation Performance for Noisy Channels
a) b)
Noise: Mean=0 -Variance=0.03
Our Approach Widrow [85]
Kz Evolution during adaptation
UCL- June 2001 51
Self-Adaptive Equalization: Conclusions
Fuzzy Logic Controller
Equalizing Filter
•Robust Adaptive Equalization: Area Tolerance filters out noise, ringing, etc.
•Fuzzy Logic Allows easily the Analog Implementation of highly non-linear control functions.
•Time-Domain Signal Analysis using Fuzzy Reasoning = On-Chip ‘Oscilloscope’ Applications beyond Channel Equalization topic: ………detection, on-chip analog testing, etc
UCL- June 2001 52
•Systematic Approach for Analogue Non-Linear Synthesis.
•Very Easy to Understand!
•Available Optimization and Design Tools (i.e.: ANFIS).
•Invariant Network Structure independent on the function to synthesize (i.e: “if-then rules”).
•Possibility of programmable devices built by standard blocks (Fuzzifiers, Inference Operators and Defuzzifiers).
Fuzzy Logic must take a place in the Toolbox of Analogue Designers for the synthesis of non-linear circuits!!
CONCLUSIONS: Fuzzy Logic & Non-Linear Analogue Design
