An HDL-Based System Design Methodologies for Multistandard RF SoCsPresenter:Jajal Jatin141160742003OutlineIntroductionDesign MethodologiesAutomated Parameter Extraction (APX)Bluetooth Low-Energy Radio (BLE)Understanding the ReceiverComparisonConclusionReference

22OverviewRadio Frequency (RF)

Multistandard Radio Frequency SoC

Application

Advantage

33Design Approaches4Fig.1 Comparison of Design Approach [1]System Design With APX[1]APX5Fig. 2 APX Characterization chart [1]HDL Model of BLEHDL-based design I=V/RIN VCMLaplaceInput StageBehaviour StageOutput StageFig. 3 The generic analog model [1]6Blocks of the Chip

Low Noise Amplifier (LNA)

ComplexDownconversionMixer7Fig. 4 Analog Model implementation of the LNA [1]Fig. 5 Analog Model implementation of the Mixer [1]

Complex Bandpass Filter

Delta Sigma ADC8Fig. 6 Analog Model implementation of the Polyphase filter [1]Fig. 7 Analog Model implementation of the Delta sigma ADC loop [1]HDL Verification VS SoC MeasurementsHDL VerificationMeasuredLNAVoltage Gain Matcing (S11) NF20.7-23.27 dB3 dB20.4-29 dB3.25 dBBaseband FilterVoltage Gain

Image Rej.28.54 dB

30 dB28 dB

26 dBFront-end(LNA+Mixer+Fiilter)IIP3-26.1 dBm-28 dBmADCSNR6056.8ReceiverSensitivity NF Max. Input Co-Ch. Intrf.-73 dBm10 dBm-10 dBm-67 dBm-73 dBm11.5 dBm-6 dBm-67 dBmPLLPhase Noise(100 kHz)Phase Noise (1 MHz)-112 dBc/Hz

-133 dBc/Hz-109 dBc/Hz

-132 dBc/HzSoCPower-Analog Power-Digital--21.6 mW6.1 mW9Fig. 8 SoC HDL and Measurement Performance Comparison[1]910Fig. 9 Simulation times comparison[1]ConclusionAutomatic Parameter Extraction (APX) method enables a fully automatic modelling of the RF and Analog blocks of an SoC and combines the model with digital sections to get full system verification also it assisted HDL verification saves up to 1900x times for top level verification compared to the transistor level verification.

1112

Fig. 10 Chip photo of the Bluetooth Low Energy SoC[1]ReferenceAytac Atac, Zhimiao Chen, Lei Liao, Yifan Wang,Marotin Schleyer, Ye Zhang, Ralf Wunderlich, Stefan Heinen, An HDL-Based Sytstem Design Methodology for Multistandard RF SoCs, Design Automation Conference (DAC),51st ACM/EDAC/IEEE 2014.

1314