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UNITED STATES DEPARTMENT OF INTERIOR GEOLOGICAL SURVEY AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER FOR USE ON THE SCSI BUS WITH THE UNIX OPERATING SYSTEM Peter L. Ward U. S. Geological Survey 345 Middlefield Road Menlo Park, CA 94025 Reese Cutler Cutler Digital Design 2215 Sun Mor Ave. Mountain View, CA 94040 November 3, 1987 Open-File Report 87-624 This report is preliminary and has not been reviewed for conformity with U.S. Geological Survey editorial standards. Any use of trade names is for descriptive purposes only and does not imply endorse- ment by the USGS. REPRODUCED FROM BEST AVAILABLE COPY
Transcript
Page 1: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

UNITED STATES DEPARTMENT OF INTERIOR GEOLOGICAL SURVEY

AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER

FOR USE ON THE SCSI BUS

WITH THE UNIX OPERATING SYSTEM

Peter L. Ward

U. S. Geological Survey345 Middlefield Road

Menlo Park, CA 94025

Reese Cutler

Cutler Digital Design2215 Sun Mor Ave.

Mountain View, CA 94040

November 3, 1987

Open-File Report 87-624

This report is preliminary and has not been reviewed for conformity with U.S. Geological Survey editorial standards. Any use of trade names is for descriptive purposes only and does not imply endorse­ ment by the USGS.

REPRODUCED FROM BEST AVAILABLE COPY

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INTRODUCTION

We received a small amount of money to install a seismographic network in Katmai National Park, Alaska, in order to study the relationship of earthquakes in the region to the volcanoes. This net­ work included 16 seismic channels in the first year and might be expanded over several years to 64 or more channels. The existing options for recording these data are limited and expensive. Using indivi­ dual drum recorders or digital event recorders becomes cumbersome and expensive for more than a few stations. Film recorders are difficult to maintain and are no longer commercially available. Most mag­ netic tape recorders are best suited for networks of less than 7 channels or more than 64. None of these systems allow online detection and location of earthquakes. Digital computer systems have proven to be the more desirable method to monitor and record data from such networks but have typically cost between $50k and $100k. Given that the cost of computers has been rapidly declining while their pro­ cessing power has been escalating, we decided to try to develop a much lower cost computing system. Our design ideas were heavily influenced by the time available. Funding for this network was received in late April, 1987, and the system was installed in Alaska in early September, 1987. This document describes briefly our design concepts and the specific design.

DESIGN PRINCIPLESA major factor in the design of computer systems is the cost of the software both in terms of time

and programmers' salary. Nearly all of the software that we need to detect, process online, and interac­ tively reprocess earthquake data exists and is running on a variety of minicomputers throughout the world. Much of this software has been written on systems with virtual memory capability and it would be difficult to trim these programs to fit computers with a severely limited address space. Thus our first fundamental decision was that the system must have virtual memory capability (address space of at least 16 megabytes) and should have a processing capability of at least 1 MIPS (Million Instructions Per Second).

The next decision was that the processor must have true multi-user and multi-tasking capability so that many programs could be run simultaneously without our software having to distribute system resources. In this way the large pool of existing software could be implemented rapidly and the configuration of software could be changed easily depending on need.

The third basic decision was to use the UNIX operating system (UNIX is a trademark of Bell Laboratories). All of the software needed was already running under UNIX. UNIX has become the industry standard portable, multi-user, multi-tasking operating system. Nearly all manufacturers of mini­ computers now sell and support UNIX for their hardware. IBM and Apple have announced their intent to sell and support UNIX on the new generation of personalsumicrocomputers being introduced this year. Thus by chosing UNIX, not only can existing software be

readily ported to our system, but our system can then be readily ported to hundreds of models of com­ puters being developed by dozens of manufacturers. The choice of UNIX put some constraints on design of the analog-to-digital converter as discussed below.

These decisions ruled out use of IBM PC, XT, and AT compatible and Apple II and Macintosh I personal computers. We reconsidered this result carefully because, after all, these computers are inex­ pensive, widely available, and easily maintainable worldwide. These machines do not have sufficient power for large seismic networks and programming to fit their addressing and processing limitations would negate any apparent cost savings. Furthermore these systems are soon to be replaced by new models that will meet the above criteria and that would make such special programming obsolete. While there are good arguments for ultimately using such mass-produced computers, we decided that the most expeditious way to proceed in 1987 was to do the development on the best machine available, but to use industry standards so that we could readily port our system to whichever hardware was best in the future.

The next decision involved how to interface the analog-to-digital converter (A/D) to the com­ puter. The standard approach for large microcomputers and minicomputers is via a bus such as VME bus or Multibus. Processors using such high-performance buses, however, are typically expensive. The most powerful and least expensive processors typically use the Small Computer Systems Interface or

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SCSI bus to connect to peripherals. SCSI is rapidly becoming an industry standard as increasing numbers of disk drive and tape drive manufacturers are producing systems to connect directly to this bus. Several manufacturers provide chips that do all of the low level interface to this bus so that inter­ facing a new device is relatively easy. SCSI will be available for many of the new generation personal computers announced this year. We decided that if we could make our A/D look like a read-only disk on the SCSI bus, then it could be readily interfaced to a wide variety of processors.

UNIX is not a realtime operating system. In other words it can not guarantee to service any specific process on a set schedule within fractions of a second. In fact most multiuser, multi-tasking operating systems are not as realtime oriented as single task processors. High performance A/D systems get around this problem by using buffering. Thus we concluded that if the A/D could buffer data for as much as a few seconds, it should be able to work properly even in a heavily laden UNIX environment. Within UNIX it is possible to lock a given process in core and to give it the highest priority, so that it will be serviced regularly.

Our design goal was to build a system capable of digitizing data from 128 seismic components at a rate of 100 samples-per-second each. We wanted to use as many off-the-shelf components as possible to reduce development time and to minimize cost

OVERALL DESIGNWe researched all computer systems available that would meet the above criteria and would cost

under $20k including disk and tape subsystems. We concluded that the most mature and powerful (1.5 MIPS) processor available in mid 1987 for the lowest price was the SUN Microsystems Model 3/50 Workstation. This system with a floating-point processor, 4 megabytes of memory, 142 megabytes of disk storage, and 60 megabytes of cartridge tape storage was available for about $10k.

We were unable to find a buffering A/D interfaced to the SCSI bus and were thus forced to build our own. A/D chips, however, can be bought off the shelf, so that what we had to build was only an A/D controller. SCSI controllers are also available off the shelf, but we were unable to get one within a reasonable time period and thus had to build our own. The overall design of the A/D unit is shown in Figure 1.

The dynamic range of the seismic telemetry system is less than 60db, so that a 12 bit A/D is more than adequate. This leaves 4 bits of each 16 bit word unused. We decided to use these extra bits to record time information. The Kinemetrics/True Time GOES Satellite Synchronized Clock (Model 468-DC) provides absolute time accurate to a millisecond and has an option for parallel output of the time information in BCD format. Thus by using each set of 4 bits for one BCD digit, the complete time of year from day of year thru millisecond can be encoded in 12 samples. The clock also puts out 4 error bits. Table 1 shows the information encoded in each sweep of 16 channels of seismic information. The clock data are latched into registers at the beginning of each sweep and then added 4 bits at a time to the A/D data stream. By placing the time information in the least significant bits, i.e. in the noise, the data can be processed without removing the time information.

The A/D is a Burr-Brown SDM854 Hybrid Data Acquisition System that contains not only an A/D, but a sample and hold amplifier, 16 channel multiplexer, clock, delay timer, and multiplexer address latch. Each channel of this internal multiplexer can then receive data from an external multi­ plexer (Burr-Brown MPC16S CMOS Analog Multiplexer) giving input from up to 256 channels. For ease of design and buffering, the number of channels in our system is selectable in units of 16, the number of multiplexers active. Similarly the sample rate is adjustable only to 50, 100, or 200 samples per second.

The output of the A/D and clock goes into a FIFO (Integrated Device Technology Model IDT7202) to provide some flexibility in the processor's response to the data stream. At high throughputs near 25.6K samples per second, the processor might otherwise miss some samples.

Our initial idea was to use a large FIFO as the whole data buffer and use Programmable Array Logic (PAL) to control the A/D and SCSI bus. The cost of 600K bytes of FIFO, however, is

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prohibitive. Furthermore the SCSI interface chip is designed to talk to a processor. Several people who had designed SCSI interfaces advised us that debugging a PAL-based SCSI system would be very difficult. Thus we decided to use a processor for buffering and control. The most inexpensive and well proven processor readily available to us was an Intel 8088 in the form of an IBM-XT clone. A fully configured XT was available for development with a cross assembler and a prom burner. Thus we could write and compile the program in a standard working environment, burn a prom, and insert it into the A/D. This established the physical configuration of the A/D as an XT clone case, power supply, and motherboard containing processor and memory. We then used standard XT full-length plugin prototype boards to hold the custom wire-wrap circuitry. All of these components were readily available over the counter. In addition a serial RS-232 port board was purchased to provide printer output during debug­ ging of the SCSI interface.

The wiring diagrams are shown in Appendix A. There are three types of boards. Board 1 is the digital board (JDR Microdevices wirewrap prototype card model IBM-PR2) containing I/O interface logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card model IBM-PR 1) containing time source input, A/D converter, a DC-DC con­ verter for power regulation, buffers, and decoding circuitry. Board 3 (also model IBM-PR1) contains multiplexers for 128 channels. Board 4 (not built) is a copy of Board 3 for 128 more channels.

The software that runs the processor as a standalone program is loaded in a 2K ROM and is listed in Appendix B. It uses an 8K byte segment of processor memory (RAM) for program variables and the remaining 632K bytes for buffer space.

A binary digital counter operates 8 LEDs that display the numbers of buffers waiting to be read over the SCSI bus. A buffer is 4096 bytes. This display shows immediately how well the interface to UNIX is working and whether the A/D is functioning properly.

The SCSI bus is very powerful and has numerous options, but it is not documented for beginners. The bus is defined in a standard distributed by the American National Standards Institute, New York, and described in a document called "Small Computer System Interface (ANSI X3.131-1986)". Delivery from ANSI takes months, but the document can also be bought overnight at higher cost from Global Engineering Documents in Santa Ana, California (800-854-7179). The standard is so broad that a sub­ set of the standard is being developed in a document called "Common Command Set of the SCSI(X3T9.2/85-52 Rev 43)". Interface chips are made by Western Digital (WD33C93), NCR Microelectronics (NCR 53C80), and now other vendors. The vendors provide design manuals and sam­ ple software. We used the WD33C93 on the recommendation of several designers who thought it had fewer bugs since it was developed later and because it had higher level commands. The greatest prob­ lem in the development of this A/D system was to clearly understand the SCSI bus and bus language. Now that we have done it, it seems easy, but the documentation available is exceedingly terse and assumes a prior knowledge. There is no question, however, that if we did it again, we would choose SCSI. After all, we did figure it out in only a few weeks!

SUN SOFTWARESUN Microsystems Consulting Group sells a generic SCSI bus driver called CONSULT-SIP. The source code is provided with a manual entitled "Software Interface Description to SCSI Intelligent Peri­ pherals". This code works under SUN release 3.2 of UNIX but does not work under release 3.4. We spent considerable time discovering this fact and ended up reinstalling 3.2 and using it for this work. SUN will be correcting the problems, caused by a major rewrite of the SCSI system drivers after release 3.2. This software provides the appropriate interfaces for the C Language subroutine calls open, close, read, write, and several options under ioctl (the IO control subroutine) that we used to identify the A/D, to reset the A/D, and to report errors. We designed the A/D interface to provide what this software expected. Porting this device to another machine will require a similar appropriate driver. A real benefit of the SCSI bus is that such a generic driver can be used. Writing a new SCSI bus driver would be a major undertaking.

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PERFORMANCEThe noise on the analog channels was about 5 mv peak-to-peak with reference to a plus and minus 5 volt maximum input causing jitter in the second data bit Since the seismic signals input to the multi­ plexers had noise greater than this, no effort was made to reduce this noise.

The A/D was run for days into a program that read the header information, checking that the time between samples was always between 9 and 11 milliseconds, checking that the multiplexer numbers were sequential, and checking that the distinct numbers were always in their proper place. The only errors found were traced to poor reception by the Satellite Clock due to a misaligned antenna and automatic seeking between the two satellites. Over a period of hours the time between samples did not change 8 specific times and then suddenly changed 80 milliseconds as the internal clock in the receiver was resynchronized to the satellite. Reorientation of the antenna and setting the receiver to use only one satellite corrected this problem. No loss of data by the A/D was ever detected.

Throughput of data proved to be no problem for up to 256 channels at 100 samples per second or 25.6K samples per second. The Burr-Brown Hybrid Data Acquisition System is rated at 27K sps. The FIFO and processor had no problem maintaining this rate because DMA channels were used and the processor was dedicated to data collection and transmission. This rate would not be attainable using the MSDOS operating system. The bandwidth of the SCSI bus is up to 4 megabytes per second with DMA input and output. The SUN 3/50 was able to receive the data and write it to disk at 25.6K sps. For test­ ing purposes we installed a do loop in the main program on the SUN doing integer multiplies and discovered that 4 such multiplies per sample could be done without losing data. There was some indica­ tion that data may have been lost by the disk at specific moments, perhaps during switching of disk tracks. This problem was not regular, however, and we did not have time to investigate it fully. In cases where the highest throughputs are required, it may be wise to use a higher cost SUN model including a VME bus so that data is input on the SCSI and output to disk on the VME bus. Throughput was influenced by system load. If the A/D reading program was run at standard priority (nice=0) and a large amount of other disk or tape I/O or computing was going on simultaneously, the number of buffers in the A/D would increase and decrease, sometimes causing buffer overflow. If the A/D program was run at highest priority (nice= -10) this was rarely a problem and never a problem for less than 200 channels (20K sps). When buffer overflow occurs, the A/D sends an error message and continues to col­ lect data so that the buffer always contains the most recent data. The possibility of overflow can be further decreased by a program called plock that is available from SUN Consulting to lock a process in core. We did not buy or test the effect of this on throughput, because we never expected to use more than 128 channels.

A standard long-term short-term detection program was used to select and save earthquake data (Herriot, J. W., unpublished data). We could run 224 channels of data through this program without los­ ing data and using all of the system bandwidth. We tested the program extensively with data from 32 stations near Parkfield, California. Running the complete detection algorithm on all 32 stations and sav­ ing suspected events on disk used less than 10 percent of the computer resources. While this task was running in background, we could use the rest of the computer resources for editing, compiling, and other computing. We also modified this program so that the data was not only scanned with suspected earthquakes saved to disk files, but also written continuously to magnetic tape. This allows us to collect continuous data from the network when desired

The only task that would backup buffers in the A/D was extensive use of the cartridge streamer tape drive. This tape drive hogs the SCSI bus even while rewinding, a problem that should be corrected by a better controller. A major feature of the SCSI bus is that when a device is asked to do something that will take a long time, the device can disconnect from the bus and then reconnect once the data are available. We use this feature in reading the A/D. The SUN requests one buffer (4096 bytes). If the A/D does not have one ready, it disconnects and then reconnects when the buffer is ready. The tape controller should do this but does not. Thus it is possible to lose some data from the A/D when writing a very long cartridge tape. There may be ways to mitigate this problem, but in our case we concluded that the problem was likely to occur so rarely, that we would not spend more time on it.

A program is listed in Appendix 3 that allows the A/D data to be displayed as it is collected and also allows display of the events detected along with the response of the detector algorithm. This

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program provides for auto-scaling of the traces and shows the trace offset and scale. This program was written quickly and has not been refined.

ACKNOWLEDGEMENTSMany people were involved in discussions that led to the development of this system. In particular Bill Jolitz of Symmetric Computer Systems suggested several key ideas. Jim Ellis and Gray Jensen of the U.S.G.S. helped extensively in evaluating options. Jim Herriot provided the detection program and assisted in implementing it. John VanSchaack, Wes Hall, Anselmo Rodrigues and Dick Fry provided major assistance in connecting the prototype system to incoming seismic signals from Parkfield. Rex Alien provided many useful comments and reviewed this document

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Multiplexers (16x16 256 input channels)

Page 8: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

Table 1: BCD codes added to the least-significant 4 bits of each data word. These 16 codes are added to each sweep of 16 channels.

Distinct number (1$)

Multiplexer number

Days (100s)

Days (10s)

Days (Is)

Hours(IOs)

Hours(ls)

Minuies(lOs)

Minutesils)

Seconds(10s)

Seconds(1s)

Mi 11isecondsUOOs)

hi 1 i iseconds(.10s)

Milliseconds (1s)

Error bits

Distinct number

7

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Page 25: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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Page 26: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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Page 27: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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Page 28: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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Page 29: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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Page 30: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

CUTLER DIGITAL DESIGN2215 SUN MOR ATE.

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Page 31: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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Page 32: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

<EDD CUTLER DIGITAL DESIGN2213 SUN MOR AVE.

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Page 33: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

Appe

ndix

2

A/D ENGINE DRIVING SOFTWARE - FIRST IMPLEMENTATION

INPUT FILENAME

: TEST.ASM

OUTPUT FILENAME

: TEST.OBJ

910 11 12 13 14 15 16 17 18 1920 21 22 23 24 25 26 27 28 29

30 31 32

333435 36 37 38 39 40 41 42 43 44 45 46 47 48 49

50

0000:0000

LIST

ON

MACLIST OFF

0000

:

0000

:[01]

0000 12A5

CUTLER DIGITAL DESIGN

2215 SUN

MOUNTAINMOR AVENUE

VIEW, CALIFORNIA 94040

(415

) 964-1481

DEFINITIONS

RATED IS THE SYSTEM CLOCK DIVIDER USED TO PRODUCE 1 KHZ

%ATEO:

EQU

4773

THE BUFFER POWER DETERMINES HOW LARGE OR SMALL A BUFFER IS USED FOR TRANSFERS

FROM THE A/D

BYTE CO

UNT)

,0000 OOOC

BUFPWR: VAR

IFTRUE

BUFPWR: VAR

[00]

[01]

ENDIF

IFTRUE

BUFPWR: VAR

[00]

0000

:

0000

:

[01]

ENDIF

0000 1000

BUFSIZE: EQU

0000 0004

SHIFTCNT: EQU

IFZ

RESERVD: EQU

[01]

0000

[00]

0000

0000

0000

0000

0000

0000

0000

0000

ELSE

0000 0001

RESERVD: EQU

ENDIF

0000 OFFF

XFERCNT: EQU

0000 OOOF

XFERHI:

EQU

0000 OOFF

XFERLO:

EQU

0000 009F

MAXBUF:

EQU

0000 0000

ZERO

: EQU

0000 FFFF

MINUSONE: EQU

0000 0001

0000 0007

ONE:

EQU

SEVEN:

EQU

TO MEMORY.

THE BUFFERS WILL BE A POWER OF TWO IN SIZE (A

CTUA

LAND THE POWER SHOULD BE BETWEEN 8 AND 16

12 BUFPWR. LT.

88 BUFPWR. GT.

16

16 2**BUFPWR

BUFPWR- 8

STACKT . MOD . BUFSIZB

STACKT/BUFSIZE

(STACKT /BUFSIZE) +1

BUFSIZE-1

XFERCNT/100H

XFERCNT. MOD. 100H

(AOO

OH/ (BUFSIZE/IOH) )

-RESERVD

OOH

FFFFH

01H

07H

Page 34: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

at6d

.(idd

e

51525354

5556

575859 60 61 62 63 64 65 66

67 68 69 70

71

72 73

74757677 78 79

80

818283

84

85 86

87 8889 90 91 92 93 94 95 96 97 98 99

100

101

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000 0001

0000 0002

0000 0004

0000 0008

0000 0010

0000 0020

0000 0040

0000 0080

0000 0000

0000 0001

0000 0002

0000 0003

0000 0004

0000 0005

0000 0006

0000 0007

0000 0008

0000 0009

0000 OOOA

0000 OOOB

0000 OOOC

0000 OOOD

0000 OOOE

0000 OOOF

0000 0002

BITO:

BIT1:

BIT2:

BIT3:

BIT4:

BITS:

BIT6:

BIT7:

DMAOO:

DMA01:

DMA02:

DMA03:

DMA04:

DMA05:

DMA06:

DMA07:

DMA08:

DMA09:

DMAOA:

DMAOB:

DMAOC:

DMAOD:

DMAOE:

DMAOF:

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

AMASKBIT: EQU

1H2H4H

8H

10H

2 OH

40H

8 OH

OOH

DMAOO+1

DMAOO+2

DMAOO+3

DMAOO+4

DMAOO+5

DMAOO+6

DMAOO+7

DMAOO+8

DMAOO +9

DMAOO+10

DMAOO+11

DMAOO+1 2

DMAOO-H3

DMAOO+1 4

DMAOO+15

02H

0000

: 0000 0000

0000

: 0000 0040

0000

: 0000 0080

0000

: 0000 OOCO

0000

: 0000 0000

*

DMA MODE BYTE

BITS: 7654

0 0

0 1

1 0

1 1

0 10 1

)EMANDMD: EQU

SINGLEMD: EQU

BLOCKMD :

EQU

CASCADMD: EQU

HDDINC :

EQU

DEFINITION:

3210

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

OOH

4 OH

8 OH

COH OOH

DEMAND mode

single mode

BLOCK mode

CASCADE mode

addr

ess

increment

addr

ess

decr

emen

tno

auto in

itAUTO INIT

verify transfer

writ

e to memory

read from memory

ille

gal

channel

0ch

anne

l 1

channel 2

channel 3

Page 35: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

3

TEST PROGRAM FOR A/D ENGINE

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

[01]

too]

[01]

0000

[00]

[01]

[00]

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000 0020

0000 0010

0000 0000

0000 0000

0000 0004

0000 0008

0000 0000

0000 0001

0000 0002

0000 0003

0000 0000

0000 0004

0000 0058

0000 0041

0000 0042

0000 0043

0000 0083

0000 0081

0000 0082

0000 0001

0000 0002

: 0000 0081

0000 0020

0000 0021

0000 0040

0000 0041

0000 0042

0000 0043

0000 0060

0000 0061

0000 0062

0000 0063

0000 OOAO

ADDDEC:

AUTOIN:

NOAOTOIN

VERIFY:

TOMEM:

FROMEM:

CEO:

CH1:

CH2:

CH3:

SETON:

SETOFF :

CHOMODE:

CH1MODE:

CH2MODE:

CH3MODE:

DMASEG1:

DMASEG2 :

DMASEG3 :

IMP:

OUTP

:

ODTS

EG:

OUTSEG :

OUTS

EG:

INTREGO :

INTREG1 :

TIMO:

TIM1

:TIM2:

TIMC

ON:

SPARA:

SPARE:

SPARC:

SP ARGON

NMIR

EG:

EQU

EQU

: EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

IFTRUE

EQU

ENDIF

IFTRUE

EQU

ENDIF

IFTRUE

EQU

ENDIF

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

20H

10H

OOH OOH

4H8H OOH

01H

02H

03H

OH 4H

SINGLEMDAI

SINGLEMDAJ

SINGLEMDAJ

SINGLEMDAJ

83H

81H

82H

CH1

CH2

OUTP.EQ.CH1

DMASEG1

OUTP.EQ.CH2

DMASEG2

OUTP.EQ.CH3

DMASEG3

20H

INTREGO-fl

40H

41H

42H

43H

60H

61H

62H

63H

OAOH

;A/D INPUT USES DMA CHANNEL ONE

;SCSI OUTPUT USES DMA CHANNEL TWO

Page 36: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

4

TEST PROGRAM FOR A/D ENGINE

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

1 179

\J-80

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0300

IOBA

SE:

EQD

0300

PARA:

EQU

0301

PARS:

EQU

0302

PARC:

EQU

0303

PARCON: EQU

0304

CLKO:

EQU

0305

CLK1

: EQU

0306

CLK2

: EQU

0307

CLKCON: EQU

0308

FIFO:

EQD

OUTPUT

0080

SETPARMODE :

0000

BITWIDC:

0000

ABAS 1C:

0020

ASTROBE:

0040

ABIDIR:

0010

AINPUT:

0000

AOUTPUT :

0008

CUPIN:

0000

CUPO

UT:

0000

BBASIC:

0004

BSTROBE:

0002

BINPUT:

0000

BOUTPUT:

0001

CDOWNIN:

0000

CDOWNOUT:

300H

IOBASE

IOBASE -H

IOBASE+2

IOBASE+3

IOBASE+4

IOBASE+5

IOBASE+6

IOBASE+7

IOBASE+8

76543210

1 000 01 10 111 01 00 1 1 0

1 0EQU

EQU

EQU

EQU

EQU

BQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

EQU

0000

0000

0000

0000

0000 030C

0000 030D

0000 0001

0000 0000

; SCSI DEFINITIONS

SCSIO:

EQU

30CH

SCSI1:

EQU

SCSIO-fl

MJV:

MN

V:EQU

EQU

01H

OOH

TO PARALLEL CONTROL BYTE

SET PARALLEL MODE

BIT CHANGE FOR PORT C

PORT A AND UPPER C MODE ZERO (BASIC I/

O)

PORT A AND UPPER C MODE ONE (STROBED I/O)

PORT A AND UPPER C MODE TWO (B

IDIR

I/O)

PORT A AND UPPER C MODE TWO (B

IDIR

I/O)

PORT A - INPUT

PORT A - OUTPUT

PORT C(UPPER) - INPUT

PORT C(UPPER) - OUTPUT

PORT B AND LOWER C MODE ZERO (B

ASIC

I/O)

PORT B AND LOWER C MODE ONE (STROBED I/

O)

PORT B -

INPUT

PORT B - OUTPUT

PORT C(LOWER) - INPUT

PORT C(LOWER) - OUTPUT

BIT7

ZERO

ZERO

BITS

BIT6

BIT4

ZERO

BIT3

ZERO

ZERO

BIT2

BIT1

ZERO

BITO

ZERO

;SOFTWARE MAJOR VERSION

;SOFTWARE MINOR VERSION

Page 37: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

TEST PROGRAM FOR A/D ENGINE

Appendix 2

PAGE 5

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000 0040

0000 0000

0000 0004

0000 OOFF

0000 0002

0000 0080

0000 0000

0000 0004

0000 0005

0000 0000

0000 0001

0000 0004

0000 0005

0000 OOOB

0000 OOOC

0000 0014

0000 0015

0000 0016

0000 0000

0000 0001

0000 0004

0000 0003

0000 0008

0000 OOOA

0000 0012

0000 001A

BUFSZ :

EQU

GOOD

: EQU

RELEASE: EQU

BAD

EQD

CHKSTAT EQU

INTBIT EQU

NOSENSE EQU

HARDERR EQU

BADCOMM EQU

RESET

EQU

ABORT

EQU

DISCON

EQU

RESEL

EQU

RESELSEN EQU

WAITSEL EQU

SENDSTAT EQU

SENDDATA EQU

SENDMESS EQU

TESTRDT EQU

REZERO EQU

SCSIDISCON EQU

REQSENSE EQU

RECEIVE EQU

SEND

EQU

INQUIRY EQU

SENDDIAG EQU

64 004H

OFFH

02H

80H

OOH

04H

05H

OOH

01H

04H

05H

OBH

OCH

14H

15H

16H

OOH

01H

04H

03H

08H

OAH

12H

1AH

BUFFER SIZE FOR MESSAGES

COMMAND COMPLETE MESSAGE BYTE

DISCONNECTING MESSAGE BYTE

COMMAND COMPLETE WITH ERROR STATUS BYTE

CHECK STATUS VALUE

SENSEKEY VALUE FOR NO PROBLEM

SENSEKEY VALUE FOR BUFFER OVERFLOW

SENSEKEY VALUE FOR BAD COMMAND

WW33C93 COMMANDS:

RESET

ABORT

DISCONNECT

RESELECT

RESELECT AND SEND

WAIT FOR SELECT

SEND STATUS

SEND DATA

SEND MESSAGE

SCSI COMMANDS ISSUED BY INITIATOR

TEST UNIT READY

REZERO UNIT

DISCONNECT

REQUEST SENSE

RECEIVE

SEND

INQUIRY

SEND DIAGNOSTIC

PAGE

Page 38: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

Appendix 2

TEST PROGRAM FOR A/D ENGINE

PAGE 6

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000 0000

0000 0001

0000 0002

0000 0003

0000 0004

0000 0005

0000 0006

0000 0007

0000 0008

0000 OOOF

0000 0010

0000 0011

0000 0012

0000 0013

0000 0014

0000 0015

0000 0016

0000 0017

0000 0018

0000 0019

OWNID

EQU

CONTROL EQU

TIMEOUT EQU

CDB1

EQU

CDB2

EQU

CDB3

EQU

CDB4

EQU

CDB5

EQU

CDB6

EQU

TARLUN EQU

COMPHASE EQU

SYNCHTR EQU

TRANSHI EQU

TRANSMID EQU

TRANSLO EQU

DESTID

EQU

SOURCID EQU

SCSISTAT EQU

COMMAND EQU

DATAREG EQU

OOH

01H

02H

03H

04H

05H

06H

07H

08H

OFH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

FEOO

0000

0000

0000

0000

0000

0000 0000

0000 FEOO

0000 0000

0000 0000

0000 0000

0000 0000

PUR:

EQU

PURHI:

EQU

PURLO:

EQU

IPUR:

EQU

IPURHI: EQU

IPURLO: EQU

PAGE

FEOO:OOOOH

FEOOH

OOOOH

0000:OOOOH

OOOOH

OOOOH

WD33C93 REGISTERS

OWN ID REGISTER

CONTROL REGISTER

TIMEOUT REGISTER

COMMAND DATA BYTE 1

COMMAND DATA BYTE 2

COMMAND DATA BYTE 3

COMMAND DATA BYTE 4

COMMAND DATA BYTE 5

COMMAND DATA BYTE 6

TARGET LOGICAL UNIT NUMBER

COMMAND PHASE

SYNCHRONOUS TRANSFER

HIGH BYTE OF TRANSFER COUNT

MIDDLE BYTE OF TRANSFER COUNT

LOW BYTE OF TRANSFER COUNT

DESTINATION ID REGISTER

SOURCE ID REGISTER

SCSI STATUS REGISTER

COMMAND REGISTER

DATA REGISTER

Page 39: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

atod

.cod

ePAGE 7

TEST PROGRAM FOR A/D ENGINE

MACRO DEFINITIONS

269

SUBTITLE MACRO DEFINITIONS

270

271

; usage OUTPUT

OUTPUT-PORT

, VALUE

272

OUTPUT: .MACRO ARG1,ARG2

273

MOV

DX,ARG1

274

MOV

AL,ARG2

275

OUT

DX,AL

276

.MACEND

277

278

; USAGE

INPUT

INPUT-PORT

279

INPUT:

.MACRO ARG1

280

MOV

DX,ARG1

281

IN

AL,DX

282

.MACEND

283

284

; USAGE

INTON

285

INTON:

.MACRO

286

STI

287

.MACEND

288

INTOFF: .MACRO

289

CLI

290

.MACEND

291

292

SETREGIS: .MACRO

ARG1,ARG2

293

MOV

AL,ARG1

294

MOV

AH,ARG2

295

CALL

SETREG

296

.MACEND

297

298

GETREGIS: .MACRO

ARG1

299

MOV

AL,ARG1

300

CALL

READREG

301

.MACEND

302

303

COMMANDSCSI:

.MACRO ARG1

304

MOV

AL, COMMAND

305

MOV

AH,ARG1

306

MOV

LASTCOMM,AH

307

CALL

SETREG

308

CALL

WAITFINT

309

MOV

AL,SCSISTAT

310

CALL

READREG

311

MOV

LASTSTAT,AL

312

MOV

AH,ARG1

313

MOV

AL,10H

314

CALL

SHOWSCSI

/DIAGNOSTIC

315

MOV

AL, LASTSTAT

316

.MACEND

317

318

; END OF MACRO DEFINITIONS

319

Page 40: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

atod

.cod

ePAGE 8

TEST PROGRAM FOR A/D ENGINE

MACRO DEFINITIONS

320

321

322

PAGE

Page 41: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

9

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

323

324

325

326

327

328

329

330

331

332

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

£

352

o 353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

0000:

FEOO:

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

:0000

:0000

:0000

:0001

:0004

:0006

:0008

:OOO

A:O

OOD

:0010

:001

3

:0016

:0019

:001

B

:001D

:001F

:002

1:0

023

:002

5:0

027

:0029

:002

B:0

02D

:002

F:0

030

:0032

:003

3FEOO: 0035

FEOO

FEOO:0

037

:003

8

FEOO:003A

B8 8E 8E 8E BDBBBF

BE

BC

BOE6

BOE6BOE6

BOE6

E6

BOE6 50

E6 50 BOE6 50 E6

BO

00

D8

DOCO 00 00 00 00 00 00 AO 99 63 FO 61 04 08 OD

FF 01 01 00 00 00 54

00 00 00 00 00 08

START:

SUBTITLE INITIALIZE COMPUTER

.CODE

.ORG

PUR

; BEGIN OF PROGRAM

SET UP SEGMENT POINTERS

IKTOFF

MOV

AX,IPURHI

MOV

DS,AX

MOV

SS,AX

MOV

ES,AX

MOV

BP,ZERO

MOV

BX,ZERO

MOV

DI,ZERO

MOV

SI,ZERO

MOV

SP,OFFSET STACKT

DISABLE NON MASKABLE INTERRUPT

MOV

AL,ZERO

OUT

NMIREG,AL

SET UP SYSTEM PARALLEL PORT

MOV

AL,SETPARMODB*ABASIC'

OUT

SPARCON,AL

MOV

AL,OFOH

OUT

SPARB,AL

SET UP REFRESH AND DMA OPERATION

MOV

AL,04H

OUT

DMA08,AL

OUT

MOV

OUT

PUSH

OUT

DMAOD,AL

AL,OFFH

DMA01,AL

AX

DMA01,AL

PUSH

AX

MOV

AL,OOH

OUT

DMAOO,AL

PUSH

AX

OUT

DMAOO,AL

SET TIMER 1 MODE

MOV

AL,54H

DISABLE INTERRUPTS

LOAD SEGMENT REGISTERS

ZERO INDEX AND OFFSET REGISTERS

LOAD STACK POINTER

DISABLE NMI

AINPUTACUPINABBASICABOUTPUTACDOWNIN

SETUP OUTPUT PORT B

DISABLE DMA CHIP

MASTER CLEAR DMA

SET COUNT FOR 64K

(THIS COMMAND IS TO GIVED DMA TIME)

(THIS COMMAND IS TO GIVED DMA TIME)

SET UP ADDRESS OOOOH

(THIS COMMAND IS TO GIVED DMA TIME)

TIMER1, LSB, MODE 2

Page 42: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

atod

.c6d

ePAGE 10

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

418

423

424

425

426

427

428

429

430

431

432

433

434

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

:003C

:003

E:0040

:0042

:0044

:0046

:004

7

:004

9:004B

:004D

:004

F:0051

:0053

:0055

:0057

:005

9:005B

:005D

:005

F:0061

:0063

:0065

:006

7

:0069

:006C

:0072

E6

BOE6

BOE6 50 E6

BOE6

BOE6BOE6BOE6

BOE6

BOE6BOE6

BOE6

BC

43 58 OB 00 08 OA 12 41 41 OB 42 OB 43 OB 13 20 08 21 09

21 FF 21 00 08

OUT

TIMCON,AL

;SET DMA MODE

MOV

AL,CHOMODE

OUT

DMAOB,AL

;ENABLE DMA

MOV

AL,OOH

OUT

DMA08,AL

PUSH

AX

OUT

DMAOA,AL

;SET TIMER COUNT

MOV

AL,12H

OUT

TIM1,AL

;SET OTHER DMA CHANNEL MODES

MOV

AL,CH1MODE

OUT

DMAOB,AL

MOV

AL,CH2MODE

OUT

DMAOB,AL

MOV

AL,CH3MODE

OUT

DMAOB,AL

; INITIALIZE INTERRUPT CONTROLLER

MOV

AL,13H

OUT

INTREGO,AL

MOV

AL,8

OUT

INTREG1,AL

MOV

AL,9

OUT

INTREG1,AL

MOV

AL,OFFH

OUT

INTREG1,AL

; INITIALIZE INTERRUPT VECTORS

; INITIALIZE THE STACK

MOV

SP,OFFSET STACKT

; INITIALIZE PROTOTYPE PARALLEL PORT

DMA MODE: CHO,INC,SING,READ,AUTO

(THIS COMMAND IS TO GIVED DMA TIME)

REMOVE CHANNEL 0 MASK

18 CLOCK CYCLES 15.12 MICROS

DMA1:

SIN,INC,NOAUTO,VBRI

DMA2:

SIN,

INC,NOAUTO, VERI

DMA3: SIN,INC,NOAUTO,VERX

MASK ALL INTS OFF

LOAD STACK POINTER

OUTPUT

PARCON,SETPARMODEAABASICAAINPUTACUPOUTABBASICABOUTPUTACDOWNOUT

OUTPUT

PARC,COH

OUTPUT 11000000 TO PARALEL PORT C

1 FIFO RESET

1 SWEEP DISABLE

0 CLOCK 1 DISABLE

0 CLOCK 0 DISABLE

0 0 0 0

INPUT

PARA

Page 43: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E 11

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

435

436

437

438

439

440

441

442

443

447

448

449

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

"2 4

66T 467

468

469

470

471

472

473

478

492

493

494

495

496

497

498

499

513

514

515

519

520

521

X

FIFO HAS DATA

X

SWEEP IS ON

X

DATA RATE B2

000

RATE - 200HZ

X

DATA RATE Bl

001

RATE - 50 HZ

X

DATA RATE BO

OTHER

RATE - 100HZ

X

SCSI UNIT B2

X

SCSI UNIT Bl

X

SCSI UNIT BO

FEOO:0078

FEOO:007C

FEOO:007D

FEOO:007F

FEOO :0082

FEOO:0083

FEOO: 0085

FEOO:0087

FEOO: 0089

FEOO:008B

FEOO: 0090

FEOO: 0093

FEOO: 0098

FEOO:009B

FEOO:OOAO

FEOO:OOA3

FEOO:OOA3

FEOO : OOA6

FEOO:OOA6

FEOO:OOA9

FEOO:OOA9

FEOO : OOAE

FEOO : OOB3

FEOO:OOB8

FEOO:OOC1

FEOO:OOE1

FEOO:OOE3

FEOO:OOE5

FEOO:OOEA

FEOO:OOEA

FEOO:OOED

FEOOrOOED

FEOO:OOFO

FEOO: 0110

FEOO: 0113

FEOO: 0118

FEOO:011A

50

24

A2 5824 74 24 74

C6E9C6E9C6E9

E8

BC

C6C6C6

07 5D 38 OC

30 10 06

10 06 08 06

00 EF 00 06 06 06

04 5A 04

OA

00 5A 04

05

00 5A 04

14

00 05 08 51 04 00

49 04

00

ID 04 00

INPUT

PUSH

AND

MOV

POP

AND

JZ

AND

JZ

MOV

JMP

SET200

MOV

JMP

SET50

MOV

JMP

STX

CALL

RESETITMOV

SCSICODEMOV

MOV

MOV

PARA

AX

AL, SEVEN

MASK OUT HIGH BITS

DEVID,AL

AX

AL,38H

SET200

AL,30H

SET50

BYTE PTR RATE1,10

STX

BYTE PTR RATE1,5

STX

BYTE PTR RATE1,20

STX

SERRESET

; RESET SERIAL PORT

SP, OFFSET STACKT

LOAD STACK POINTER

BYTE PTR SENSEKEY,NOSENSE

; RESET SENSE KEY

BYTE PTR ABNORMAL, ZERO

; RESET ABNORMAL FLAG

BYTE PTR ERRTYPE,ZERO

SETREGIS

OHNID,DEVID

COMMANDSCSI

RESET

3C 74 C6

E8

E8

00 05 06 82 3B

ID 04

FF

02 04

CMP

JE

MOV

SCSIL1

CALL

SCSILOOPCALL

AL, ZERO

SCSIL1

BYTE PTR ERRTYPE,OFFH

RESATOD

SROWBUFFER

;SET DISPLAY TO SHOW BUFFER

(COMMANDSCSI WAITSEL

A2

1C04

MOV

ERRCLASS,AL

GETREGIS

SOURCID

;FIND OUT WHO IS THE

24 A2

07 4B

04AND

MOV

AL, SEVEN

; STRIP OFF NON ID Bl

ROSTID,AL

;AND SAVE

Page 44: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

12

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

522

526

527

528

532

533

534

535

536

537

538

539

540

541

542

546

547

548

549

550

551

552

553

554

555

556

557

558

^T 559

^5S 562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

FEOOrOllD

FEOO:0122

FEOO:0125

FEOO:012A

FEOO:012D

FEOO:012F

FEOO:0131

FEOO:0134

FEOO:0137

FEOO:0139

FEOO:013B

FEOO:013E

FEOO:013E

FEOO:0143

FEOO:0146

FEOO:0148

FEOO:014A

FEOO:014D

FEOO:014F

FEOO:0151

FEOO:0154

FEOO:0156

FEOO:0158

FEOO:015B

FEOO:015D

FEOO:015F

FEOO:0162

FEOO:0164

FEOO:0166

FEOO:0169

FEOO:016B

FEOO:016D

FEOO:0170

FEOO:0170

FEOO:0173

FEOO:0173

A2 4E 04

A2 ID 04

3C 36

74 03

E9 38 02

AO 1C 04

3C 13

74 03

E9 2E 02

A2 47 04

3C 01

75 03

E9 F6 01

3C 00

75 03

E9 06 02

3C 03

75 03

E9 7C 01

3C 08

75 03

E9 77 00

3C 12

75 03

E9 12 00

3C 1A

75 06

E9 00 00

E9 00 00

C6 06 51

GETREGIS

TARLUN

MOV

IDENTIFY, AL

GETREGIS

COMPHASE

MOV

CMP

JE

JMP

SCSIL2 MOV

CMP

JE

JMP

SCSIL3

ERRTYPB,AL

AL,036B

SCSIL2

SCSIRSAV

AL,ERRCLASS

AL,013H

SCSIL3

SCSIRSAV

GETREGIS

CDB1

MOV

COMM,AL

;SAVE COMMAND

MOV

CALL

CALL

MOV

CALL

CALL

AL,'C'

PUTCB

SPACE

AL,COMM

PRBYTE

CRLF

MOV

AL,COMM

branch according to command received

CMP

AL,REZERO

JNE

SCSIL4

JMP

SCSIREZ

SCSIL4

CMP

AL,TESTRDY

JNE

SCSIL5

JMP

SCSITRDY

SCSIL5

CMP

AL,REQSENSE

JNE

SCSIL6

JMP

SCSIREQS

SCSIL6

CMP

AL, RECEIVE

JNE

SCSIL7

JMP

SCSISEND

SCSIL7

CMP

AL,INQUIRY

JNE

SCSIL8

JMP

SCSINQ

SCSIL8

CMP

AL,SENDDIAG

JNE

SCSIDFLT

JMP

SCSISNDI

SCSISNDIJMP

SCSIDFLT

SCSIDFLT

NON STANDARD COMMAND RECEIVED

MOV

BYTE PTR SENSEKEY,BADCOMM

;ILLEGAL REQUEST

Page 45: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E 13

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

582

583

584

FEOO:0178

E9 D3 01

JMP

PAGE

SCSIQEND

Page 46: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E 14

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

585

586

587

588

592

593

598

603

608

613

618

623

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

640

641

642

643

644

645

646

647

648

649

650

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

:017

B

:017

B:0180

:018

3:0

18A

:019

1:0198

:019F

:01A6

:01AD

:01AF

:01B

2:0

1B4

:01B7

:01B

9

:01B

C:0

1BE

:01C1

:01C3

:01C

6:0

1C9

:01CC

:01C

E

:01D1

:01D3

:01D

6

A2 BOE8

BOE8

BOE8

BOE8

BOE8

AO E8

BOE8

BOE8

E9

4F

AD

F2 00 ED 00 E8 00 E3 03 DE 52 D8 01 D3 00 CE 81

04 03 03 03 03 03 04 03 03 03 01

SCSINQ

INQUIRY COMMAND RECEIVED

GETREGIS CDB5

MOV

LENGTH, AL

SETREGIS TRANSLO,08H

SETREGIS TRANSMID,OOH

SETREGIS TRANSHI,OOH

SETREGIS SYNCHTR,OH

SETREGIS CONTROL,0OH

;GET LENGTH

;STORE IT

;NOT DM

A, OR DBA

SETREGIS COMMAND,SENDDATA

MOV

CALL

MOV

CALL

MOV

CALL

MOV

CALL

MOV

CALL

MOV

CALL

MOV

CALL

MOV

CALL

AL,OADH

PUTDATA

AL,0

PUTDATA

AL,OH

PUTDATA

AL,0

PUTDATA

AL,03H

PUTDATA

AL,BUFCNT

PUTDATA

AL,MJV

PUTDATA

AL,MNV

PUTDATA

; FIRST BYTE

; SECOND BYTE

; THIRD BYTE

; FOURTH BYTE

; FIFTH BYTE

; SIXTH BYTE

; SEVENTH BYTE

;EIGTH BYTE

JMP

PAGE

SCSIEND

Page 47: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

App

endi

x 2

PAG

E 15

651

652

653

654

655

656

660

661

665

666

667

668

669

670

671

672

673

674

675

676

677

678

679

680

681

682

683

684

685

686

687

688

689

690

691

692

693

698

699

700

701

702

703

704

705

706

707

708

709

710

724

FEOO:01D9

FEOO:01D9

FEOO:01DE

FEOO:01E1

FEOO:01E6

FEOO:01E9

FEOO:01EC

FEOO:01EF

FEOO:01F1

FEOO:01F3

FEOO:01F6

FEOO:01F9

FEOO:0202

FEOO:0202

FEOO:0205

FEOO:0208

FEOO:020A

FEOO:020D

FEOO:0210

FEOO:0210

A2 45 04

A2 44 04

Al 52 04

3D 00 00

75 44

BO 04

E8 81 03

E8 D9 03

Al 52 04

3D 00 00

75 06

E8 BA 01

E9 F2 FF

SC

SIS

EN

D: MOV

CALL

MOV

CALL

AL,"S"

PUTCH

AL,"E«

PUTCH

GETREGIS

CDB4

MOV

SCLNHI,AL

GETREGIS

CDB5

;SET LENGTH

MOV

SCSENDA MOV

CMP

JNE

CALL

JMP

SCLNLO,AL

AX,BUFCNT

AX,ZERO

SCSISEND1

CHKATOD

SCSENDA

SEND DISCONNECT MESSAGE TO INITIATOR

MOV

CALL

AL,"I

1

PUTCH

MOV

AL,RELEASE

CALL

XMITMESSAGE

DISCONNECT FROM BUS

MOV

CALL

AL,"2"

PUTCH

CALL

DISCONNECT

DISCONNECT FROM SCSI

MOV

CALL

AL,"3"

PUTCH

SETREGIS DESTID,HOSTID

SCSISEND2 MOV

CMP

JNE

CALL

JMP

SCSISEND3 MOV

CALL

AX,BUFCNT

AX, ZERO

SCSISEND3

CHKATOD

SCSISEND2

AL,"4"

PUTCH

SETREGIS

COMMANDSCSI

SOURCID,040H

RESEL

;ENABLE SELECTION AND RESEL

Page 48: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

ator

i.cod

ePAGE 16

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

741

742

743

744

745

746

747

748

753

758

763

768

773

774

775

776

779

784

789

790

795

800

805

806

807

808

813

814

819

820

821

822

823

824

825

FEOO:0230

BO 80

FEOO:0232

E8 42 03

FEOO:0235

FEOO:0235 Al 52 04

FEOO:0238

48

FEOO:0239 A3 52 04

FEOO:023C Al 56 04

FEOO:023F E8 22 02

FEOO:0242

88 26 43 04

FEOO:0246 A2 42 04

FEOO:0249

C6 06 41 04 00

FEOO:024E

E8 IB 02

FEOO:0251

FEOO:025A

FEOO:0263

FEOO:026A

FEOO:0271

FEOO:0278

FEOO:0279

FEOO:027F

FEOO:0285

FEOO:028B

FEOO:0292

FEOO:0299 Al 44 04

FEOO:029C

48

FEOO:029D

50

FEOO:029E

FEOO:02A4

58

FEOO:02A5

FEOO:02AB

MOV

CALL

AL,"5"

PUTCH

SEND IDENTIFY MESSAGE

MOV

AL,BIT7

CALL

XMITMESSAGE

; ;MOV

CALL

AL, "6"

PUTCH

SCSISENDl MOV

DEC

MOV

AX,BUFCNT

AXBUFCNT,AX

MOV

AX,OUTPTR

CALL

FIX

MOV

SCADHI,AH

MOV

SCADMID,AL

MOV

BYTE PTR SCADLO,ZERO

CALL

UPDOUT

;UPDATE BUFFER COUNT

SET

ADDRESS

;UP DATE POINTER TO NEXT BUFFER TO BE

OUTPUT

SETREGIS

SETREGIS

SETREGIS

SETREGIS

SETREGIS

SETREGIS

SET UP DMA

INTOFF

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

MOV

DEC

PUSH

OUTPUT

POP

OUTPUT

INPUT

PUSH

INPUT

CALL

POP

CALL

OUTPUT

TRANSLO,SCLNLO

TRANSMID,SCLNHI

TRANSHI,ZERO

CONTROL,BIT7ABIT3 ;TURN ON DMA ACCESS FOR SCSI CONTR.

SYNCHTR,OOH

SYNCHTR,045H

DMAOA, SETOFFAOUTP

;MASK OUTPUT CHANNEL

DMAOB,SINGLEMDAADDINCANOAUTOINAFROMEMAOUTP

;SET DMA CHANNEL MODE

;CLEAR BYTE FLIPFLOP

;SEND LOW ADDRESS

;SEND HIGH ADDRESS

;GET LENGTH

;DECREMENT THE COUNT

DMAOC,OOH

DMAO4,SCADLO

DMA04,SCADMID

AX,SCLNLO

AXAXDMA05,AL

AXDMA05,AH

DMA05

AXDMA05

PRBYTE

AXPRBYTE

OUTSEG,SCADHI

;AND SAVE

;SPECIFY LOW COUNT

:SEND HIGH COUNT

;PRINT COUNT -

1;SEND 64K SEGMENT NIBBLE

Page 49: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

17

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

830

831

836

839

840

845

846

847

848

849

850

851

852

853

854

855

856

857

858

859

860

861

862

863

864

865

866

867

868

869

870

FEOO:02B2

FEOO:02B8

FEOO:02B9

FEOO-.02CO

88 26 48 04

FEOO:02C4

E8 23 02

FEOO:02C7

FEOO:02C7

E8 FF 02

872

873

874

875

876

877

878

879

880

881

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

02CA

02CC

02CE

02D1

02D4

8A

BO

E8

AO

E9

EO

40

36

46

77

04

04

00

;GET AUX STAT REG

ENABLE DMA

OUTPUT

DMAOA,SETONAOUTP

;REMOVE MASK

INTON

SEND THE COMMAND, TO START THE TRANSFER

SETREGIS

COMMAND,SENDDATA

MOV

LASTCOMM,AH

WAIT FOR PROCESS DONE

CALL

WAITFINT

MOV

AL,SCADHI

CALL

PRBYTE

MOV

AL,SCADMID

CALL

PRBYTE

MOV

AL,SCADLO

CALL

PRBYTE

CALL

CRLF

CALL

SHOWDATA

FINISH OPERATION IF NOT DONE

CALL

AUXSTAT

AND

AL,BIT5ABIT4

JE

SS1

SETREGIS COMMAND,ABORT

MOV

AL,'A'

CALL

PUTCH

MOV

AL,'B'

CALL

PUTCH

CALL

SHOWAUX

CALL

WAITFREE

SS1 READ SCSI STATUS

CALL

GETSTAT

GETREGIS

SCSISTAT

MOV

LASTSTAT,AL

SHOW STATUS BEFORE ISSUING COMMAND

MOV

AH,AL

MOV

AL,040H

CALL

SHOWSCSI

MOV

AL,LASTSTAT

JMP

PAGE

SCSIQEND

Page 50: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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ePAGE 18

882

883

884

885

886

891

896

901

902

903

904

905

906

911

916

921

922

923

924

925

926

927

928

929

930

931

932

933

934

935

936

937

938

939

940

941

942

943

944

945

946

947

948

949

950

951

952

953

954

955

956

FEOO.-02D7

FEOO:02D7

C6 06 4F 04

OA

FEOO:02DC

FEOO:02DC

FEOO:02E5

FEOO : 02EC

FEOO

.-02F3

FEOO:02FA

FEOO: 0301

FEOO: 0308

BO 70

FEOO:030A E8 97 02

FEOO:030D

BO 00

FEOO:030F

E8 92 02

FEOO: 0312

AO 51

04

FEOO: 0315

E8 8C 02

FEOO: 0318

C6 06 51 04

00

FEOO:031D

BO 00

FEOO:031F

E8 82

02

FEOO: 0322

BO 00

FEOO: 0324

E8 7D 02

FEOO :03

27

BO 00

FEOO: 0329

E8 78 02

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

SCSIREQS

MOV

REQUEST SENSE

BYTE PTR LENGTH,0AH

SEND BACK ONLY 8 BYTES

REQ5

SETREGIS TRANSLO,LENGTH

SETREGIS TRANSMID,OOH

SETREGIS TRANSHI,OOH

MOV

AL,LENGTH

CALL

PRBYTE

CALL

CRLF

SETREGIS SYNCHTR,OOH

;ASYNCH

SETREGIS CONTROL,0OH

;NOT DMA, OR DBA

SETREGIS COMMAND,SENDDATA

MOV

CALL

MOV

CALL

CALL

MOV

CALL

MOV

CALL

CALL

MOV

CALL

MOV

CALL

CALL

MOV

MOV

CALL

MOV

CALL

CALL

MOV

CALL

MOV

CALL

CALL

MOV

CALL

MOV

CALL

AL,070H

PUTDATA

AL,070H

PRBYTE

SPACE

AL,0

PUTDATA

AL,0

PRBYTE

SPACE

AL, SENSBKEY

PUTDATA

AL,SENSEKEY

PRBYTE

SPACE

; FIRST BYTE

; SECOND BYTE

; THIRD BYTE

BYTE PTR SENSEKEY,NOSENSE

AL,0

PUTDATA

AL,0

PRBYTE

SPACE

AL,OH

PUTDATA

AL,OH

PRBYTE

SPACE

AL,0

PUTDATA

AL,0

PRBYTE

; FOURTH BYTE

; FIFTH BYTE

; SIXTH BYTE

Page 51: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

Appendix 2

957

958

959

960

961

962

963

964

965

966

967

968

969

970

971

972

973

974

975

976

977

978

979

980

981

982

983

984

985

986

987

FEOO:032C

FEOO:032E

FEOO:0331

FEOO:0333

FEOO:0336

FEOO:0336

FEOO:0338

FEOO:033B

FEOO:033D

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

BO 00

E8 73

02

BO 02

E8 6E

02

BO AS

E8 69

02

BO 5A

E8 64 02

FEOO:0340

E9 17 00

CALL

REQX

PAGE 19

SPACE

MOV

CALL

MOV

CALL

CALL

MOV

CALL

CALL

MOV

CALL

MOV

CALL

CALL

MOV

CALL

MOV

CALL

CALL

CALL

JMP

AL,OH

PUTDATA

AL,OH

PRBYTE

SPACE

AL,2

PUTDATA

PRBYTE

AL, OA5H

PUTDATA

AL,2H

PRBYTE

SPACE

AL,05AH

PUTDATA

AL,2H

PRBYTE

SPACE

CRLF

SCSIEND

;SEVENTH BYTE

;EIGHTH BYTE

;NINTH BYTE

;TENTH BYTE

PAGE

Page 52: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

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x 2

PAG

E 20

988

989

990

991

992

993

994

995

996

997

998

999

1000

1001

1002

1003

1004

1005

1006

1007

1008

1009

1010

1011

1012

1013

1014

1015

1016

1017

1018

1019

1020

1021

1022

1023

FEOO :03

43

FEOO:0343

FEOO:0346

FEOO:034B

FEOO:034E

FEOO:034E

FEOO:0351

FEOO:0353

FEOO:0355

FEOO:0357

FEOO:035A

FEOO:035A

FEOO : 035A

FEOO : 035A

FEOO:035C

FEOO:035C

FEOO:035F

FEOO: 0361

FEOO: 0363

FEOO: 0366

FEOO: 03 69

FEOO:036C

FEOO: 03

6C

E8 29 00

C6 06 51

04 00

E9 OC 00

AO 51

04

3C 00

74 05

BO 02

E9 02 00

BO 00

E8 EB 01

BO OE

BO 00

E8 11 02

E8 69

02

E9 81 FD

E9 04 FE

TEST PROGRAM FOR A/D ENGINE

INITIALIZE COMPUTER

SCSIREZMOV

CALL

CALL

MOV

JMP

AL,1

FREEZE

REZERO UNIT

RESATOD

BYTE PTR SENSEKEY,NOSENSE

SCSITRDY

; RESET SENSE KEY

SCSI

OJEN

D MOV

CMP

JE

; SEND REQUEST

MOV

JMP

SCSITRDY

SCSIEND:

SCSIEND1:

; SEND STATUS

«MOV

SCSIEND2: CALL

MOV

CALL

AL, SENSEKEY

AL,NOSENSE

SCSIEND1

TO CHECK STATUS

AL,CHKSTAT

SCSIEND2

TEST UNIT READY

GOOD

AL,GOOD

XMITSTATUS

AL,OEH

DISPAUX

SEND END MESSAGE

«= 0

MOV

AL,GOOD

CALL

XMITMESSAGE

DISCONNECT

CALL

DISCONNECT

JMP

SCSILOOP

;SET END MESSAGE TO ZERO

SCSIRSAVJMP

PAGE

SCSIDFLT

Page 53: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

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PAG

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21

TEST PROGRAM FOR A/D ENGINE

SUBROUTINES

1024

1025

1026

1027

1028

1029

1030

1031

1035

1036

1037

1038

1043

1044

1045

1049

1050

1051

1052

1053

1054

1055

1056

1057

1058

1059

1060

1061

1062

1063

1064

1065

1066

1071

1076

1081

1086

1091

1096

1101

1106

1111

1112

1113

FEOO:036F

FEOO:036F

E8 ID 00

FEOO:0372

FEOO:0376

24 80

FEOO:0378

74 F8

FEOO:037A

FEOO:0380

FEOO:0384

24 40

FEOO:0386

75 F8

FEOO:0388

E8 04

00

FEOO:038B

E8 59 00

FEOO:038E

C3

FEOO:038F

FEOO:0395

FEOO:039B

FEOO : 03A1

FEOO:03A7

FEOO:03AD

FEOO:03B4

FEOO:03BA

FEOO:03CO

FEOO:03C6

C3

SUBTITLE SUBROUTINES

RESATOD:

; SET UP A/D CLOCK RATE

CALL

SETCLK

WAIT UNTIL SOME DATA IS THERE

TO:

INPUT

PARA

AND

AL,80H

JE

TO

; TURN OFF CLOCK

OUTPUT

PARC,OOH

; WAIT UNTIL SAMPLE IS

DONE

Tl:

INPUT

PARA

AND

AL,4OH

JNE

Tl

READ ALL DATA FROM FIFO

T2:

INPUT

FIFO

INPUT

PARA

AND

AL,80H

JE

T2

RESET CLOCK AGAIN

CALL

SBTCLK

START A-TO-D DMA OPERATION

CALL

INITATOD

RET

SETCLK: OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

RET

PAGE

PARC,COH

CLKC

ON, 36H

CLKC

ON, 76H

CLKO,RATED.MOD.256

CLKO,RATEO/256

CLK1,RATE1

CLK1,OOH

PARC,FOB

PARC,30H

Page 54: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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.ctic

iePAGE 22

TEST PROGRAM FOR A/D ENGINE

SUBROUTINES

1114

1115

1119

1120

1121

1122

1123

1124

1125

1126

1127

1128

1129

1130

1131

1132

1133

1134

1135

1136

1137

1138

1139

1140

1141

1142

1143

1144

1145

FEOO

FEOO

FEOO

FEOO

FEOO

:03C

7:0

3C7

:03CB

:03C

D

:03CF

24 74 E8

02 03 2E

00

FEOO:03D2

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

:03D2

:03D

5:0

3D8

:03DA

:03DC

:03D

F:03E2

:03E

5:0

3E6

:03E7

:03E7

:03ED

:03FO

:03F3

:03F

9:03FF

BA

AO 3C 74 AO B9

Al EE

C3

C7

E8 E8C7

C7 C3

01 5C 00 06

5B 03 52 06 66 OD06

06

03 04 04 00 04 54 04 00 00

00 00 56 04 00 00

52 04

00

00

CHKATOD :INPUT

AND

JZ

CALL

CALL

CHKATODX: MOV

MOV

CMP

JEMOV

JMP

CHKATOD1: MOV

ADD

MOV

CHKATOD2: OUT

RET

INITATOD: MOV

CALL

CALL

MOV

MOV

RET

PAGE

DMA08

AL, OFFSET AMASKBIT

CHKATODX

NEXTATOD

INCFLAG

DX,PARB

AL,SSF

AL, ZERO

CHKATOD1

AL,FLAG

CHKATOD2

AX,BUFCNT

AX,256-MAXBUF

AL,INPTR

DX,AL

WORD PTR INPTR,ZERO

IFIX

NEXTATOD

WORD PTR OUTPTR,

WORD PTR BUFCNT,ZERO

ZERO

READ DMA STATUS REGISTER

CLEAR INPUT POINTER

FIX UP NEXT DMA POINTERS

INVOKE AND ATOD/DMA CYCLE

CLEAR OUTPUT POINTER

CLEAR BUFFER COUNT

Page 55: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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PAG

E

23

TE

ST

PRO

GR

AM

FO

R A

/D

EN

GIN

E

SUB

RO

UT

INE

S

1146

1147

1150

1151

1152

1153

1158

1163

1164

1169

1174

1179

1184

1189

1194

1199

1202

1203

1204

1205

1206

1207

1208

1209

1210

1211

1212

1213

1214

V.JN

1215

^1216

1217

1218

1219

1220

1221

1222

1223

1224

1225

1226

1227

1228

1229

1230

1231

1232

1233

1234

1235

1236

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:0

400

0400

0401

0402

0403

0404

040A

0410

0416

041C

0423

0429

042F

0436

043C

043D

0440

0443

0444

0445

0446

0447

044A

044B

044E

0450

0453

0456

0459

045C

045F

0463

0464

0464

50 52 51 E8 E8 595A

58 C3

Al 40 3D 75 B8

A3

Al E8

A2 88 C3 05

07 39 54 9F 03 00 54 54 08 5826 01

00 00 04 00 00 04 04 00 04 59 04

00

[01]

FEOO:

FEOO

:0467

0469

Bl D3

04 EO

[00]

FEOO

:046B

C3

NEXTATOD:

; UPDIN

; UPDIN:

UPDINX:

IFIX

:

FIX

; ;

INTOFF

PUSH

PUSH

PUSH

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INTON

CALL

CALL

POP

POP

POP

RET

AXDX cx DMAOA, SETOFFAIN

PMASK INPUT CHANNEL

DMAOB , SINGLEMDAADDINCANOAUTOINATOMEMAINP

;DMAOC, OOH

DMA02,OOH

DMA02,HIADD

DMA03,XFERLO

DMA03,XFERHI

DMASEG1,HINIB

DMAOA, SETONAIN

P

UPDIN

UPDBC

CXDX

AX

- UPDATES THE INPUT POINTER

MOV

INC

CMP

JNE

MOV

MOV

MOV

CALL

MOV

MOV

RET

MOV

RET

WHEN NECESSARY

AX,INPTR

AX

AX, OFFSET MAXBUF

UPDINX

AX, OH

INPTR,AX

AX,INPTR

FIX

HIADD,AL

HINIB,AH

AX,0040H

SET A-D DMA MODE

CLEAR BYTE FLIPFLOP

SEND LOW ADDRESS

SEND HIGH ADDRESS

SPECIFY LOW COUNT

SEND HIGH COUNT

SEND 64K SEGMENT NIBBLE

REMOVE MASK

UPDATE INPUT POINTER

UPDATE BUFFER COUNT

INPTR, WRAPPING IT AROUND

; DUMMY POINTER

ADD

AX,OFFSET RESERVD

IFTRUE

SHIFTCNT.GT.0

MOV

CL,SHIFTCNT

SHL

AX,CL

ENDIF

RET

PAGE

Page 56: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

TEST PROGRAM FOR A/D ENGINE

SUBROUTINES

1237

1238

1239

1240

1241

1242

1243

1244

1245

1246

1247

1248

1249

1250

1251

1252

1253

1254

1255

FEOO

FEOO

FEOO

FEOO

FEOO

:046

C:0

46F

:0470

:047

3:0475

FEOO: 0478

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

FEOO

:047

B

:047

C:0

47F

:0480

:048

3:0

485

:0488

:0489

:048

C:0

491

Al 40 3D 75 B8

A3 C3

Al 40 3D 74 A3 C3

E8C6

C3

56 9F 03 00

56 52 9F 04 52

EO 06

04 00 00 04 04 00 04 FF 51

04 04

UPDOUT MOV

INC

CMP

JNE

MOV

UPDOUTX MOV

RET

UPDB

C:

MOV

INC

CMP

JE

MOV

RET

UPDBCX: CALL

MOV

RET

PAGE

App

endi

x 2

at6d

.cod

e1PAGE 24

AX,OUTPTR

AX

AX,OFFSET MAXBUF

UPDOUTX

AX, OH

OUTPTR,AX

AX,BUFCNT

AX

AX,OFFSET MAXBUF

UPDBCX

BUFCNT,AX

UPDOUT

BYTE PTR SENSEKEY,HARDERR

Page 57: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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PAG

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TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

1256

1257

1258

1259

1260

1261

1262

1263

1264

1265

1266

1267

1268

1269

1270

1271

1272

1273

1274

1275

1276

1277

1278

1279

1280

1281

1282

1283

1284

1285

'1286

1287

1288

1289

1290

1291

1292

1293

1294

1295

1296

1297

1298

1299

1300

1301

1302

1303

1304

1305

1306

FEOO:0492

FEOO:0492

FEOO:0494

FEOO:0495

FEOO:0495

FEOO:0496

FEOO:0499

FEOO:049C

FEOO:049D

FEOO:049E

FEOO:049E

FEOO:04A1

FEOO:04A2

FEOO:04A3

FEOO:04A3

FEOO:04A5

FEOO:04A7

FEOO:04AA

FEOO:04AB

FEOO:04AE

FEOO:04BO

FEOO:04B1

FEOO:04B2

FEOO:04B5

FEOO:04B6

FEOO:04B9

FEOO

:04B

BFEOO:04BC

FEOO:04BF

FEOO:04C2

E2 FE

C3FEOO

: 0000 0020

51 B9 20

00

E8 F6 FF

59 C3 BA OC 03

EC

C3 3C 17

74 OB

BA OC 03

EEBA OD 03

EB 00

EC

C3

BA OC 03

EEBA OD 03

EB 00

EC

B9 07 00

E8 DO FF

C3

SUBTITLE SCSI SUBROUTINES

DELAY

DELAY1

LOOP

RET

PAUSECONST EQU

DELAYP

PUSH

MOV

CALL

POP

RET

ASSUMES DELAY COUNT IS IN CX

DELAY1

2 OH

CXCX,PAUSECONST

DELAY

CX

AUXSTAT RETURNS THE VALUE OF THE AUXILIARY STATUS IN AL

AUXSTATMOV

IN

RET

DX,SCSIO

AL,DX

READREG READS A SCSI REGISTER

THE REGISTER DESIGNATOR MUST BE STORED IN AL

USAGE:

MOV

AL,REGISTER_DESIGNATOR

CALL

READREG

THE VALUE FROM THE REGISTER IS LEFT IK AL

READREG

RREG1

CMP

JE

MOV

OUT

MOV

JMP

IN

RET

MOV

OUT

MOV

JMP

IN

MOV

CALL

RET

AL, SCSISTAT

RREG1

DX,SCSIO

DX,AL

DX,SCSI1

SHORT $-1-2

AL,DX

DX,SCSIO

DX,AL

DX,SCSI1

SHORT $-1-2

AL,DX

CX, SEVEN

DELAY

WAIT FOR SLOW I/O

WAIT FOR SLOW I/O

Page 58: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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ePAGE 26

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

1307

PAGE

Page 59: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

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PAG

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TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

1308

1309

1310

1311

1312

1313

1314

1315

1316

1317

1318

1319

1320

1321

1322

1323

1324

1325

1326

1327

1328

1329

1330

1331

1332

1333

1334

1335

.1.3

3 o

1337

1338

1339

1340

1341

1342

1343

1344

1345

1346

1347

1348

1349

1350

1351

1352

1353

1354

1355

1356

1357

1358

FEOO:04C3

FEOO:04C3

FEOO:04C6

FEOO:04C7

FEOO:04CA

FEOO-.04CC

FEOO:04CE

FEOO:04CF

FEOO:04DO

FEOO

.-04

DOFEOO:04D1

FEOO:04D2

FEOO:04D3

FEOO:04D4

FEOO:04D7

FEOO:04D7

FEOO:04DA

FEOO:04DC

FEOO:04DB

FEOO:04E1

FEOO:04E5

FEOO:04E7

FEOO-.04EA

FEOO:04EA

FEOO:04EB

FEOO:04EC

FEOO:04ED

BA OC 03

EE

BA OD 03

8A C4

EB 00

EE

C3 FEOO

: 0000 80

00

51 52

50 53 B9 00 80

E8 C4 FF

24 80

75 20

E8 5D

00

81 F9 00 80

75 FO

E9 14

00

51 52 50 53

SETREG READS A SCSI REGISTER

THE REGISTER DESIGNATOR MUST BE STORED IN AL

THE REGISTER VALUE MUST BE STORED IN AH

USAGE:

MOV

AL,REGISTER_DESIGNATOR

MOV

AH, VALUE

CALL

SETREG

SETREG

MOV

OUT

MOV

MOV

JMP

OUT

RET

DX, SCSIO

DX,AL

DX, SCSI1

AL,AH

SHORT $+2

DX,AL

THIS IS A WAIT FOR SLOW I/OPORTS

AS SPECIFIED IN THE WD33C92 STARTER KIT

WAITFINT POLLS THE AUXILIARY STATUS REGISTER FOR AN INTERRUPT

CONDITION.

IT ALSO INVOKES CHKATOD

WAITTIMB EQU

WAITFINTA PUSH

PUSH

PUSH

PUSH

MOV

CALL

MOV

CALL

CALL

MOV

WAITFINTB CALL

AND

ONE

MOV

CALL

CMP

ONE

MOV

CALL

CALL

JMP

WAITFINTPUSH

PUSH

PUSH

PUSH

MOV

8000H

cx DX

AXBX

AL, 'W'

PUTCH

AL, 'A'

PUTCH

CRLF

CX,WAITTIME

AUXSTAT

AL, INTBIT

WAITX

AL, "A"

POLLING

CX,WAITTIME

WAITFINTB

AL, "?

"

PUTCH

CRLF

WAITX

CXDX

AXBX

AL, 'W'

Page 60: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

App

endi

x 2

PAG

E

28

1359

1360

1361

1362

1363

1364

1365

1366

1367

1368

1369

1370

1371

1372

1373

1374

1375

1376

1377

1378

1379

1380

1381

1382

1383

1384

1385

<SsfN,

1386

^1387

^ 1388

1389

1390

1391

1392

1393

1394

1395

1396

1397

1398

1399

1400

1401

1402

1403

1404

1405

1406

1407

1408

1409

FEOO:04EE

FEOO:04F1

FEOO:04F1

FEOO:04F4

FEOO:04F6

FEOO:04F8

FEOO:04FB

FEOO:04FE

FEOO:04FE

FEOO:04FF

FEOO:0500

FEOO:0501

FEOO:0502

FEOO:0503

FEOO:0503

FEOO:0504

FEOO:0505

FEOO:0506

FEOO:0507

FEOOrOSOA

FEOO:050A

FEOO:050D

FEOO:050F

FEOO:0511

FEOO:0514

FEOO:0517

FEOO:0517

FEOO:051A

FEOO:051D

FEOO:0521

FEOO:0524

FEOO:0525

FEOO:0525

FEOO:052A

FEOO:052B

FEOO:052B

FEOO:0530

FEOO:0531

FEOO:0531

B9 00

E8 AA

24 80

75 06

E8 43

E9 F3

SB

585A

59

C3 5152

5053

B9 00

E8 91

24 30

74 ED

E8 2A

E9 F3

A2 SB

E8 81

OA 06

A2 SB

C3

C6 06

C3

C6 06

C3

E8 AC

80

FF 00

FF 80

FF 00

FF 04FFSB 04

04

5C 04 FF

5C 04 00

01

CALL

MOV

CALL

CALL

MOV

WAITFINT1 CALL

AND

ONE

MOV

CALL

JMP

WAITX

POP

POP

POP

POP

RET

WAITFREEPUSH

PUSH

PUSH

PUSH

MOV

CALL

MOV

CALL

CALL

MOV

WAITFREE1 CALL

AND

JEMOV

CALL

JMP

DISPAUX:MOV

CALL

ORMOV

RET

SHOWFLAG: MOV

RET

SHOWBUFFER:

MOV

RET

SHOWAUX:CALL

POTCH

AL, 'I'

PUTCH

CRLF

CX,WAITTIME

AUXSTAT

AL, INTBIT

WAITX

AL, "I"

POLLING

WAITFINT1

BX

AXDX

CX

CX

DX

AX

BX

AL, 'W

PUTCH

AL, 'F'

PUTCH

CRLF

CX,WAITTIME

AUXSTAT

AL,BIT5ABIT4

;<WAITX

AL, "F"

POLLING

WAITFREE1

FLAG,AL

AUXSTAT

AL,FLAG

FLAG.AL

BYTE PTR SSF, OFFH

BYTE PTR SSF, ZERO

SPACE

;CH

EC

K F

OR

BSY

O

R

CIP

Page 61: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

29

1410

FEOO:0534

1411

FEOO:0537

1412

FEOO:053A

1413

FEOO:053D

1414

FEOO:053E

1415

1416 FEOO:053E

1417

FEOO:0541

1418

FEOO:0544

1419

1420

1421

1422

1423

1424

1425

1426

1427

1428

1429

1430

1431

1432

1433

1434

1435

1436

'1437

1438

1439

1440

1441

FEOO:0546

1442

FEOO:0549

1443

1444

FEOO:0549

1445

1446

E8 67 FF

E8 AC 01

E8 98

01

C3

E8 86 FE

E8 51 FF

E2 03

B9 00 80

C3

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

POLLING:

CALL

CALL

CALL

RET

PUSH

CALL

CALL

LOOP

POP

PUSH

CALL

CALL

AUXSTAT

PRBYTE

CRLF

AX

CHKATOD

DELAYP

POLLINGX

AX

AXPUTCH

SPACE

;PAUSECONST DETERMINES THE LENGTH OF THIS DELAY

DISABLE DMA OPERATION ON OUTP

OUTPUT

DMAOA,SETOFFAOUTP

CLEAR FLIP FLOP

OUTPUT

DMAOC,OOH

READ LOW COUNT AND PUSH ONTO STACK

INPUT

DMA05

PUSH

AX

READ HI BYTE AND PRINT

INPUT

DMA05

CALL

PRBYTE

POP LOW BYTE AND PRINT

POP

AX

CALL

PRBYTE

ENABLE DMA OPERATION ON OUTP

OUTPUT

DMAOA,SETONAOUTP

SHOWDATA

SHOWAUX

CX,WAITTIME

CALL

CALL

MOV

POLLINGX: POP

RET

PAGE

AX

Page 62: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

30

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

1447

1448

1449

1450

1451

1455

1460

1465

1466

1467

1468

1469

1470

1471

1472

1473

1474

1475

1476

1477

1478

1479

1480

1481

1482

1483

1484

1485

1486

1487

1491

1496

1501

1502

1503

1504

1505

1506

1507

1508

1509

1510

1511

1512

1513

1514

1515

1516

1517

1518

1519

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO

:FE

OO:

FEOO:

FEOO:

FEOO:

FEOO

:FEOO:

FEOO:

FEOO:

FEOO

:FEOO:

FEOO

:FE

OO:

FEOO

:FE

OO:

FEOO

:FE

OO:

FEOO

:FEOO:

FEOO:

FEOO:

FEOO:

054A

05 4A

054D

0552

0559

0560

0563

0566

0569

05 6C

0570

0573

0576

0577

0577

057A

057F

0586

058D

0590

0593

0596

0599

:059D

:05A

O:05A3

:05A4

A2

AOE8

E8E8 8A

AO E8 C3

A2

AOE8

E8E8 8A

AOE8 C3

4C 4C

3E 81 5D 26 4C 91 4D 4D 11 54 30 26 4D 64

04 04 00 FF 00 46 04

04 01 04 04 00 FF 00 46 04

04 01

; XMITSTATUS EXPECTS STATUS IN REGISTER AL

XMITSTATUS:

MOV

XSTATUS,AL

;SKVE STATUS

GETREGIS

SCSISTAT

;CLEAR ANY INTERRUPTS BY READING STAT

SETREGIS

CONTROL,OOH

;TURN OFF DM

A, DBA

SETREGIS

COMMAND,SENDSTATABIT7

;ISSUE THE SEND_STAT COMMAND, SNG BYT

MOV

AL,XSTATUS

CALL

PUTDATA

;SEND XSTATUS TO DATA REGISTER WHEN RDY

;XMIT1

CALL

AND

JE

AUXSTAT

AL,01H

XMIT1

SETREGIS

DATAREG, XSTATUS

CALL

CALL

MOV

CALL

CALL

MOV

MOV

CALL

RET

HAITFINT

GETSTAT

AL,'S'

PUTCH

SPACE

AH, LASTSTAT

AL, XSTATUS

SHOWSCSI

;GET AUX STAT

;LOOK AT DBA BIT

;LOOP

UNTIL READY

; WRITE STATUS BYTE

; XMITMESSAGE EXPECTS MESSAGE IN REGISTER AL

XMITMESSAGE:

MOV

XMESSAGE,AL

;SAVE MESSAGE

GETREGIS

SCSISTAT

;CLEAR ANY INTERRUPTS BY READING STAT

SETREGIS

CONTROL,OOH

;TURN OFF DMA, DBA

SETREGIS

COMMAND,SENDMESSABIT7

;ISSUE THE SEND_MESS COMMAND, SNG BYT

MOV

AL,XMESSAGE

CALL

PUTDATA

;GET AUX STAT

;LOOK AT DBA BIT

;LOOP

UNTIL READY

DATAREG,XMESSAGE

; WRITE STATUS BYTE

XMIT2

CALL

AND

JE

SETR

ECCALL

CALL

MOV

CALL

CALL

MOV

MOV

CALL

RET

AUXSTAT

AL,01H

XMIT2

5IS

DA'

WAITFINT

GETSTAT

AL, 'M'

PUTCH

SPACE

AH, LASTSTAT

AL, XMESSAGE

SHOWSCSI

PUTDATA:

Page 63: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

App

endi

x 2

atod

.c6d

ePA

GE

31

1520

1521

1522

1523

1524

1525

1526

1527

1528

1529

1530

1531

1532

1533

1534

1535

1536

1537

1538

1539

1540

1541

1546

1547

1548

1549

1550

1554

1555

1556

1557

1558

1563

1568

1569

1570

1571

1572

1573

1574

1575

1576

1577

1578

1579

1580

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO

:FE

OO:

FEOO

:

FEOO:

FEOO

:FE

OO:

FEOO

:FEOO:

FEOO:

FEOO

:FEOO:

FEOO:

FEOO:

FEOO:

FEOO

:

05A4

05A7

05AA

05AA

05AD

05AF

05B1

05B4

05B6

05B9

05BC

05BC

05C5

05C8

05C9

05CE

05D1

05D2

05D2

05D9

05EO

FEOO:05E3

FEOO: :

05E6

A2B9

E8 24 75

E8 8B

3D

E9

E8C3

A2C3

E8

E8 C3

50 00

Fl 01 OB 8A

Cl 00 EE

CD 46 20

E3

04 80 FE

FF 80 FF

FE 04 FF

FF

MO

V

MO

VD

ATA

TEM

P, A

L

CX

,WA

ITT

IME

PUT

DA

TA

1CALL

AUXSTAT

AND

AL,01H

ONE

PUTDATAX

MOV

AL,'P'

CALL

POLLING

MOV

AX,CX

CMP

AX,WAITTIME

ONE

PUTDATA1

SETREGIS

COMMAND,ABORT

JMP

RESETIT

SETREGIS

COMMAND,DISCON

COMMANDSCSI

ABORT

COMMANDSCSI

DISCON

MOV

AL,7

CALL

FREEZE

GET AUXI STAT

LOOK AT DBA BIT

JMP

PUTDATA1

PUTDATAXSETREGIS

DATAREG,DATATEMP

CALL

DELAYP

RET

GETSTAT GETREGIS

SCSISTAT

MOV

LASTSTAT,AL

RET

DISCONNECT SETREGIS

SETREGIS

CALL

CALL

CALL

MOV

CALL

CALL

CALL

MOV

MOV

CALL

RET

PAGE

CONTROL,OOH

COMMAND,DISCON

WAITFREE

WAITFINT

GETSTAT

AL,'D'

PUTCH

CRLF

SPACE

AH,LASTSTAT

AL,OEEH

SHOWSCSI

Page 64: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E 32

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

1581

1582

1583

1584

1585

1590

1595

1600

1605

1610

1611

1612

1615

1620

1625

1626

1631

1636

1641

1642

1643

1644

1649

1650

1655

1660

^1661

^1666

1669

1670

1671

1672

1673

1674

1679

1680

1681

1682

1683

1687

1688

1689

1690

1691

1692

1693

1694

1695

1696

1697

1698

FEOO:05E7

FEOO:05E7

FEOO:05FO

FEOO:05F9

FEOO:0600

FEOO:0607

FEOO-.0610

FEOO-.0611

FEOO:0617

FEOO:061D

FEOO-.0623

FEOO:062A

FEOO:0631

Al 44 04

FEOO:0634

48

FEOO:0635

50

FEOO:0636

FEOO:063C

58

FEOO:063D

FEOO:0643

FEOO:064A

FEOO-.0650

FEOO:0651

FEOO:065A

88 26 48 04

FEOO:065E

E8 89 FE

FEOO:0661

FEOO.-0666 A2 46 04

FEOO:0669

8A EO

FEOO:066B

BO 40

FEOO:066D

E8 97

00

FEOO:0670 AO 46 04

FEOO:0673

C3

FEOO:0674

FEOO:0674

E8 27 FE

FEOO:0677

A2 00 04

; MODE TO BE FOUND IN SCMODB

; ADDRESS TO BE FOUND IN SCADBT,SCADMID,SCADLO

; LENGTH TO BE LIMITED TO 64K, FOUND IN SCLNHI,SCLNLO

WRITSCSISETREGIS

TRANSLO,SCLNLO

SETREGIS

TRANSMID,SCLNHI

SETREGIS

TRANSHI,ZERO

SETREGIS

CONTROL,BIT7

SETREGIS

DESTID,HOSTID

SET UP DMA

INTOFF

OUTPUT

OUTPUT

DMAOA,SETOFFAOUTP

;MASK OUTPUT CHANNEL

DMAOB,SINGLEMDAADDINCANOAUTOINAFROMEMAOUTP

;SET DMA CHANNEL MODE

DMAOC,OOH

DMAO4,SCADLO

DMAO4,SCADMID

AX,SCLNLO

AX

AXDMA05,AL

AX

DMA05,AH

DMASEG1,SCADHI

DMAOA,SETONAOUTP

OUTPUT

OUTPUT

OUTPUT

MOV

DEC

PUSH

OUTPUT

POP

OUTPUT

OUTPUT

ENABLE DMA

OUTPUT

INTON

SHOW STATUS BEFORE ISSUING COMMAND

MOV

AH,SCMODE

MOV

AL,30H

CALL

SHOWSCSI

SEND THE COMMAND, TO START THE TRANSFER

SETREGIS

COMMAND,SCMODE

MOV

LASTCOMM,AH

WAIT FOR PROCESS DONE

CALL

WAITFINT

READ SCSI STATUS

GETREGIS

SCSISTAT

MOV

LASTSTAT,AL

SHOW STATUS BEFORE ISSUING COMMAND

AH,AL

AL,040H

SHOWSCSI

AL,LASTSTAT

;CLEAR BYTE FLIPFLOP

;SEND LOW ADDRESS

;SEND HIGH ADDRESS

;GET LENGTH

;DECREMENT THE COUNT

;AND SAVE

;SPECIFY LOW COUNT

;SEND HIGH COUNT

;SEND 64K SEGMENT NIBBLE

;REMOVE MASK

MOV

MOV

CALL

MOV

RET

GET THE SCSI REGISTERS INTO THE DATA ARRAY CDAT

GETSCSIREG

CALL

AUXSTAT

;GET AUX STATUS BEFORE STATUS

MOV

CDATA,AL

Page 65: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

at6d

.C()d

ePA

GE

33

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

1699

1700

1701

1702

1703

1704

1705

1709

1710

1711

1712

1713

1714

1715

1716

1717

1718

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

FEOO:

067A

067D

0680

0683

0684

0685

0686

068B

068C

068E

068F

0690

0691

0692

0694

B9 1A

BB 01

BA 00

52 51 53 SB 88 07

43 595A 42 E2 EF

C3

00 04 00

MOV

MOV

MOV

GSREG1: PUSH

PUSH

PUSH

GETREGIS DL

POP

BX

MOV

[BX]

INC

BX

POP

CX

POP

DX

INC

DX

LOOP

GSREG1

RET

PAGE

CX,26

BX,OFFSET CDATA+1

DX,ZERO

DXCX

BX

AL

Page 66: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

34

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

1719

1720

1721

1722

1723

1724

1725

1726

1727

1728

1729

1730

1731

1732

1733

1734

1739

1744

1745

1750

1755

1760

1761

1766

1767

(T-1

772

XT* 17

73

\774

1775

1776

1777

1778

1782

1783

1784

1785

1790

1791

1792

1793

1794

1795

1796

1797

1798

1799

1800

1801

1802

1803

1804

; DIAGNOSTIC SUBROUTINES

FEOO

0000 03F8

SERBASE EQU

3F8H

FEOO

0000 03F8

TX

EQU

SERBASE

FEOO

0000 03F8

RX

EQU

SERBASE

FEOO

0000 03F8

DLLSB

EQU

SERBASE

FEOO

0000 03F9

DLMSB

EQU

SERBASE+1

FEOO

0000 03F9

IEREG

EQU

SERBASE+1

FEOO

0000 03FA

IIREG

EQU

SERBASE+2

FEOO

0000 03FB

LCREG

EQU

SERBASE+3

FEOO

0000 03FC

MCREG

EQU

SERBASE+4

FEOO

0000 03FD

LSREG

EQU

SERBASE+5

FEOO

0000 03FE

MSREG

EQU

SERBASE+6

FEOO: 0695

SERRBSET

; DISABLE INTERRUPTS

FEOO: 0695

FEOO:069B

FEOO:06A1

FEOO-.06A7

FEOO:06AD

OUTPUT

OUTPUT

; SET BAUD RATE

OUTPUT

OUTPUT

OUTPUT

LCRE

G, 03H

IEREG, OOH

LCRE

G, 83H

DLLS

B, OCR

DLMS

B, OOH

; SET TO READ OR WRITE DATA

FEOO:06B3

OUTPUT

LCRE

G, 03H

; SET MODEM CONTROL TO DTR,RTS

FEOO:06B9

FEOO:06BF

FEOO:06CO

FEOO :0 SCO

FEOO:06C1

FEOO:06C2

FEOO:06C5

FEOO:06C9

FEOO:06CB

FEOO:06CD

FEOO:06CE

FEOO.-06D4

FEOO:06D5

FEOO

-.06

D5FEOO:06D7

FEOO:06DA

FEOO:06DC

FEOO:06DF

FEOO:06EO

FEOO:06EO

FEOO:06E2

FEOO:06E5

FEOO:06E6

FEOO:06E6

FEOO:06E7

FEOO:06E8

C3 C3 50

E8 02

FD

24 20

74 F5

58

C3

BO OD

E8 E6 FF

BO OA

E8 El FF

C3

BO 20

E8 DB FF

C3 51 50DO E8

OUTPUT

RET

PUTCH:

RET

PUSH

PUTCH1

CALL

INPUT

AND

JE

POP

OUTPUT

RET

CRLF

MOV

CALL

MOV

CALL

RET

SPACE

MOV

CALL

RET

PRBYTE

PUSH

PUSH

SHR

MCREG, 03H

AXCHKATOD

LSREG

AL,20H

PUTCH1

AX TX,AL

AL, ODH

PUTCH

AL, OAH

PUTCH

AL,20H

PUTCH

CX

AXAL,1

;TURN OFF DLAB

;TURN ON DLAB

;TURN OFF DLAB

;SEE IF HOLDING

SAVE CX

SAVE AX

Page 67: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

atod

.cd(

iePAGE 35

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

1805

1806

1807

1808

1809

1810

1811

1812

1813

1814

1815

1816

1817

1818

1819

1820

1821

1822

1823

1824

1825

1826

1827

1828

1829

1830

^ 1831

UT.832

1833

1834

1835

1836

1837

1838

1839

1840

1841

1842

1843

1844

1845

1846

1847

1848

1849

1850

1851

1852

1853

1854

1855

FEOO:06EA

FEOO:06EC

FEOO:06EE

FEOO:06FO

FEOO:06F3

FEOO:06F4

FEOO:06F7

FEOO:06F8

FEOO:06F9

FEOO:06F9

FEOO:06FB

FEOO

.-06

FDFEOO:06FF

FEOO:0701

FEOO:0703

FEOO.-0706

FEOO:0707

FEOO:0707

FEOO:0708

FEOO:0709

FEOO:070A

FEOO:070B

FEOO:070C

FEOO:070F

FEOO:0712

FEOO

.-07

13FEOO:0715

FEOO:0718

FEOO:071B

FEOO:071E

FEOO:0721

FEOO:0724

FEOO:0724

FEOO:0726

FEOO:0727

FEOO:072A

FEOO:072D

FEOO:072F

FEOO:0732

FEOO:0735

FEOO:0735

FEOO:0737

FEOO:0738

FEOO:073B

FEOO:073E

FEOO:0740

FEOO:0743

FEOO:0744

FEOO:0745

DO E8

DO £8

DO £8

£8 06 00

58 £8 02 00

59

C3 24 OF

3C OA

7C 02

04 07

04 30

£8 BA FF

C3 50 53 51 52 50 E8 D7 FF

E8 CE FF

58 8A C4

£8 CE FF

E8 BA FF

£8 56 FF

BB 00

04

B9 10 00

8A 07

43 £8 BC FF

B8 B3 FF

£2 F5

£8 A3 FF

B9 OB 00

8A 07

43 E8 AB FF

£8 A2 FF

£2 F5

E8 92 FF

5A

59SB

SHR

SHR

SHR

CALL

POP

CALL

POP

RET

PUTCHNIBAND

CMP

JL

ADD

PN1

ADD

CALL

RET

SHOWSCSIPUSH

PUSH

PUSH

PUSH

PUSH

CALL

CALL

POP

MOV

CALL

CALL

CALL

MOV

MOV

SHOWSC1MOV

INC

CALL

CALL

LOOP

CALL

MOV

SHOWSC2

MOV

INC

CALL

CALL

LOOP

CALL

POP

POP

POP

AL,1

AL,1

AL,1

PUTCHNIB

AXPUTCHNIB

CX

AL,OFH

AL, OAH

PN1

AL, 07H

AL,30H

PUTCH

AXBX CXDX

AX

P KBYTE

SPACE

AXAL,AH

PRBYTE

CRLF

GETSCSIREG

BX, OFFSET CDATA

CX,16

AL, [BX]

BX

PRBYTE

SPACE

SHOWSC1

CRLF

CX,11

AL, [BX]

BX

PRBYTE

SPACE

SHOWSC2

CRLF

DXCX

BX

Page 68: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

atbd

.cid(

iePA

GE

36

1856

1857

1858

1859

1860

1861

1862

1863

1864

1865

1866

1867

1868

1869

1870

1871

1872

1873

1874

1875

1876

1877

1878

1879

1880

1881

f>1882

^Al883

1884

1885

1886

1887

1888

1889

1890

1891

1892

1893

1894

1895

1896

1897

1898

1899

1900

1901

1902

1903

1904

1905

1906

FEOO:0746

FEOO:0747

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

58

C3

POP

RET

SHOWDATA PUSH

PUSH

PUSH

PUSH

MOV

MOV

SHOWDA1MOV

PUSH

INC

MOV

INC

CALL

POP

CALL

CALL

LOOP

CALL

POP

POP

POP

POP

RET

AX AXBXCXDX

BX, OFFSET DUMMY

CX,16

AL, [B

X]AXBX

AL, [BX]

BX

PRBYTE

AXPRBYTE

SPACE

SHOWDA1

CRLF

DXCX

BXAX

FEOO:0748

AO SB 04

FEOO:074B

OC 20

FEOO:074D E9 25 00

FEOO:0750 AO 5B 04

; INCFLAG INCREMENTS AND OUTPUTS A FLAG BYTE

SETS

MOV

AL,FLAG

OR

AL,BITS

JMP

INCF1

SE

T6

MO

VA

L,F

LA

G

Page 69: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

TEST PROGRAM FOR A/D ENGINE

SCSI SUBROUTINES

App

endi

x 2

PAG

E

37

1907

1908

1909

1910

1911

1912

1913

1914

1915

1916

1917

1918

1919

1920

1925

1926

1927

1928

1929

1930

1931

1936

1937

1938

1939

1940

"^1942

1943

1944

1945

1946

1947

1948

1949

1950

1951

1952

1953

1954

1955

1956

1957

FEOO:0753

FEOO:0755

FEOO:0758

FEOO:075B

FEOO:075D

FEOO:0760

FEOO:0763

FEOO:0765

FEOO:0768

FEOO:0768

FEOO:076A

FEOO:0770

FEOO:0772

FEOO:0773

FEOO:0773

FEOO:0775

FEOO:0778

FEOO:077F

FEOO-.0780

FEOO:0783

FEOO:0785

FEOO:0

788

FEOO:078B

FEOO:078D

FEOO:0790

FEOO:0793

FEOO:0795

FEOO:0798

FEOO:079B

FEOO:079D

FEOOrlFFO

FEOO:1FFO

OC 40

E9 ID

AO 5B

OC 80

E9 15

AO SB

OC 01

E9 OD

OC FO

EB FE

C3

BO 00

A2 SB

C3

AO 5B

OC 02

E9 ED

AO 5B

OC 04

E9 E5

AO SB

OC 08

E9 DD

AO SB

OC 10

E9 D5

EA 00

00 04 00 04 00 04 04 FF 04 FF 04 FF 04

FF 00 00 FE

OR

JMP

SET7

MOV

OR

JMP

SETO

MOV

OR

JMP

FREEZE:

OR

OUTPUT

FREEZE1 JMP

RET

ZEROFLAGMOV

;INCFLAG INC

INCF1

MOV

OUTPUT

RET

SET!

MOV

OR

JMP

SET2

MOV

OR

JMP

SET3

MOV

OR

JMP

SET4

MOV

OR

JMP

ORG

JMP FAR

AL,BIT6

INCF1

AL,FLAG

AL,BIT7

INCF1

AL,FLAG

AL,BITO

INCF1

AL, OFOH

PARB,AL

SHORT

FREEZE1

AL,OOH

FLAG

FLAG,AL

PARE, FLAG

AL,FLAG

AL, BIT1

INCF1

AL,FLAG

AL,BIT2

INCF1

AL,FLAG

AL,BIT3

INCF1

AL,FLAG

AL,BIT4

INCF1

1FFOH

START

;SE

T

UP

RE

SET

PAG

E

Page 70: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

atdB.

cc>d

ePAGE 38

TEST PROGRAM FOR A/D ENGINE

DATA SPACE

1958

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

1976

1977

1978

1979

1980

1981

1982

1983

1984

1985

1986

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

0000:0000

0000:0000

0000:0000

0000:0400

0000:0440

0000:0441

0000:0442

0000:0443

0000:0444

0000:0444

0000:0445

0000:0446

0000:0447

0000:0448

0000:0449

0000:044A

0000:044B

0000:044C

0000: 044D

0000:044E

0000: 044F

0000:0450

0000:0451

0000:0452

0000:0454

0000:0456

0000:0458

0000:0459

0000:045A

0000:045B

0000:045C

01010101 010101 01010101 01010101 01

0101 0000

:

0000

:0000

:

0000

:0000

:

01 01 01 01 01

0000 041A

0000 04

1C0000 041D

0000 041E

0000 041F

TVEC

S:

SUBTITLE DATA SPACE

.DATA

.ORG

IPUR

.BLKW

256*2

; SCSI VARIABLES

CDATA

BLKB

BUFSZ

SCMODE

.BYTE

1SCADLO

.BYTE

1SCADMID .BYTE

1SCADHI

.BYTE

1 SCLN:

SCLNLO

.BYTE

1SCLNHI

.BYTE

1LASTSTAT BYTE

1COMM

BYTE

1LASTCOMM BYTE

1ABNORMAL BYTE

1ENDSTAT

BYTE

1HOSTID

BYTE

1XSTATUS

BYTE

1XMESSAGE BYTE

1IDENTIFY BYTE

1LENGTH

BYTE

1DATATEMP BYTE

1SENSEKEY BYTE

1

AUXREG EQU

;SENSEKEY EQU

ERRCLASS EQU

ERRTYPE

EQU

CDATA+26

CDATA+27

CDATA+28

CDATA+29

BYTE PTR AUXREG ETC.

; ERRTYPE EQUALS ZERO ON START UP

; ERRTYPE EQUALS FFH IF RESET DOESN'T SEEM TO WORK

OFEH

;DISCONNECT ERROR

OLDSTAT

EQU

CDATA+30

LASTCOM EQU

CDATA+31

; A TO D VARIABLES, BUFFER VARIABLES

BUFCNT:

INPTR:

OUTPTR:

HIADD:

HINIB:

RATE1:

.BLKH

.BLKW

.BLKH

.BYTE

.BYTE

.BYTE

; TEST VARIABLES

FLAG:

.BYTE

SSF:

.BYTE

Page 71: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

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x 2

PAG

E 39

TEST PROGRAM FOR A/D ENGINE

DATA SPACE

2009

2010

2011

2012

2013

2014

2015

2016

2017

0000:0450

0000:0600

0000:0600

0000:0800

0000:4000

0000:4000

0000:4000

01; SCSI VARIABLES

DEVID:

.BYTE

1

ORG

60OH

STACK:

.BLK

B 512

STACKT:

ORG

4000H

DUMMY:

.END

Page 72: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

App

endi

x 2

PAG

E

40

TE

ST

PRO

GR

AM

FO

R

A/D

E

NG

INE

D

AT

A

SPA

CE

**

**

**

**

**

**

*

SY

MB

OL

IC

R

EF

ER

EN

CE

T

AB

LE

*

**

**

**

**

**

**

ABASIC

0000

ADDDEC

- 0000

AOUTPDT

« 0000

AUXSTAT

7EOO

BINPUT

- 0000

BIT3

« 0000

BIT7

0000

BSTROBE

« 0000

BUFSZ

» 0000

CDB2

0000

CDB6

- 0000

CHOMODE

0000

CH2MODE

0000

CHKATOD1

7EOO

CLKO

« 0000

COMM

0000

CRLF

7EOO

DATATEMP

0000

DEMANDMD

« 0000

DISCONNECT

7EOO

DMAOO

- 0000

DMA04

- 0000

DMA08

0000

. DMAOC

0000

^DMASEGl

« 0000

BRRCLASS

0000

FLAG

0000

GBTSCSIREG

7EOO

HARDERR

» 0000

IDENTIFY

0000

INCF1

7EOO

INQUIRY

0000

IOBASE

« 0000

rvEcs

oooo

LCREG

« 7EOO

MCREG

- 7EOO

MSREG

7EOO

NOSENSE

0000

OUTPTR

0000

PARB

0000

PN1

7EOO

PUR

» 7EOO

PUTCH1

7EOO

PUTDATAX

7EOO

READREG

7EOO

REQSENSE

0000

RESELSEN

0000

0000 0000

ABIDIR

- 0000

0000 0020

ADDING

0000

0000 0000

ASTROBE

« 0000

0000 049E

BAD

0000

0000 0002

BITO

0000

0000 0008

BIT4

» 0000

0000 0080

BITHIDC

0000

0000 0004

BUFCNT

0000

0000 0040

CASCADMD

- 0000

0000 0004

CDB3

0000

0000 0008

CDOWNIN

» 0000

0000 0058

CH1

0000

0000 0042

CH3

- 0000

0000 03E2

CHKATOD2

7EOO

0000 0304

CLK1

0000

0000 0447

COMMAND

* 0000

0000 06D5

CUPIN

0000

0000 0450

DELAY

7EOO

0000 0000

DESTID

« 0000

0000 05D2

DISPAUX

7EOO

0000 0000

DMA01

- 0000

0000 0004

DMA05

- 0000

0000 0008

DMA09

« 0000

0000 OOOC

DMAOD

0000

0000 0083

DMASEG2

- 0000

0000 041C

ERRTYPE

0000

0000 045B

FREEZE

7EOO

0000 0674

GETSTAT

7EOO

0000 0004

HIADD

0000

0000 044E

IEREG

7EOO

0000 0775

INITATOD

7EOO

0000 0012

INTBIT

« 0000

0000 0300

IPUR

0000

0000 0000

LASTCOM

0000

0000 03FB

LENGTH

0000

0000 03FC

MINUSONE

« 0000

0000 03FE

NEXTATOD

7EOO

0000 0000

OLDSTAT

« 0000

0000 0456

OUTSEG

0000

0000 0301

PARC

0000

0000 0701

POLLING

7EOO

0000 0000

PURHI

« 0000

0000 06C2

PUTCHNIB

7EOO

0000 05BC

DUMMY

0000

0000 04A3

RECEIVE

0000

0000 0003

REQX

7EOO

0000 OOOB

RESERVD

* 0000

0000 0040

ABNORMAL

0000

0000 0000

AINPUT

- 0000

0000 0020

AUTOIN

« 0000

0000 OOFF

BADCOMM

- 0000

0000 0001

BIT1

« 0000

0000 0010

BITS

« 0000

0000 0000

BLOCKMD

- 0000

0000 0452

BUFPWR

- 0000

0000 OOCO

CDATA

0000

0000 0005

CDB4

- 0000

0000 0001

CDOWNOUT

- 0000

0000 0001

CH1MODB

- 0000

0000 0003

CH3MODE

- 0000

0000 03E5

CHKATODX

7EOO

0000 0305

CLK2

« 0000

0000 0018

COMPHASE

- 0000

0000 0008

CUPOUT

- 0000

0000 0492

DELAY1

7EOO

0000 0015

DEVID

0000

0000 0517

DLLSB

- 7EOO

0000 0001

DMA02

- 0000

0000 0005

DMA06

« 0000

0000 0009

DMAOA

« 0000

0000 OOOD

DMAOE

« 0000

0000 0081

DMASEG3

- 0000

0000 041D

FIFO

- 0000

0000 0768

FREEZE1

7EOO

0000 05C9

GOOD

- 0000

0000 0458

HINIB

0000

0000 03F9

IFIX

7EOO

0000 03E7

INP

- 0000

0000 0080

INTREGO

- 0000

0000 0000

IPURHI

- 0000

0000 041F

LASTCOMM

0000

0000 044F

LSREG

- 7EOO

0000 FFFF

MJV

- 0000

0000 0400

NMIREG

« 0000

0000 041E

ONE

- 0000

0000 0081

OWNID

« 0000

0000 0302

PARCON

- 0000

0000 053E

POLLINGX

7EOO

0000 FEOO

PURLO

- 0000

0000 06F9

PUTDATA

7EOO

0000 4000

RATED

- 0000

0000 0008

RELEASE

- 0000

0000 0336

RESATOD

7EOO

0000 0001

RESET

- 0000

0000 0449

ABORT

- 0000

0000 0010

AMASKBIT

- 0000

0000 0010

AUXREG

- 0000

0000 0005

BBASIC

- 0000

0000 0002

BIT2

- 0000

0000 0020

BIT6

- 0000

0000 0080

BOUTPUT

- 0000

0000 OOOC

BUFSIZE

- 0000

0000 0400

CDB1

- 0000

0000 0006

CDB5

- 0000

0000 0000

CHO

- 0000

0000 0041

CH2

- 0000

0000 0043

CHKATOD

7EOO

0000 03D2

CHKSTAT

« 0000

0000 0306

CLKCON

« 0000

0000 0010

CONTROL

- 0000

0000 0000

DATAREG

- 0000

0000 0492

DELAYP

7EOO

0000 045D

DISCON

- 0000

0000 03F8

DLMSB

- 7EOO

0000 0002

DMA03

- 0000

0000 0006

DMA07

- 0000

0000 OOOA

DMAOB

- 0000

0000 OOOB

DMAOF

- 0000

0000 0082

ENDSTAT

0000

0000 0308

FIX

7EOO

0000 0770

FROMEM

- 0000

0000 0000

GSREG1

7EOO

0000 0459

HOSTID

0000

0000 0456

IIREG

- 7EOO

0000 0001

INPTR

0000

0000 0020

INTREG1

- 0000

0000 0000

IPURLO

« 0000

0000 0448

LASTSTAT

0000

0000 03FD

MAXBUF

- 0000

0000 0001

MNV

- 0000

0000 OOAO

NOAUTOIN

- 0000

0000 0001

OUTP

« 0000

0000 0000

PARA

- 0000

0000 0303

PAUSECONST « 7EOO

0000 0549

PRBYTB

7EOO

0000 0000

PUTCH

7EOO

0000 05A4

PUTDATA1

7EOO

0000 12A5

RATB1

0000

0000 0004

REQ5

7EOO

0000 036F

RESEL

- 0000

0000 0000

RESETIT

7EOO

0000 0001

0000 0002

0000 041A

0000 0000

0000 0004

0000 0040

0000 0000

0000 1000

0000 0003

0000 0007

0000 0000

0000 0002

0000 03C7

0000 0002

0000 0307

0000 0001

0000 0019

0000 0495

0000 0004

0000 03F9

0000 0003

0000 0007

0000 OOOB

0000 OOOF

0000 044A

0000 0464

0000 0008

0000 0683

0000 044B

0000 03FA

0000 0454

0000 0021

0000 0000

0000 0446

0000 OQ9F

0000 0000

0000 0000

0000 0002

0000 0300

0000 0020

0000 06E6

0000 06CO

0000 05AA

0000 045A

0000 02DC

0000 0005

0000 OOA6

TE

ST

PRO

GR

AM

FO

R A

/D

EN

GIN

E

Page 73: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

DA

TA

SPA

CE

App

endi

x 2

SCADLO

SCLNLO

SCSI1

SCSIEND

SCSIL2

SCSIL6

SCSINQ

SCSIRSAV

SCSISEND3

SEND

SENDSTAT

SETO

SET3

SET 6

SETOH

SHIFTCNT

SHOWSC1

SOURCID

SPARC

SIX

TARLUN

TIM1

STACK

TRANSMID

OPDIN

STACK!

0000

0000

« 0000

7EOO

7EOO

7EOO

7EOO

7EOO

7EOO

0000

m 0000

7EOO

7EOO

7EOO

0000

- 0000

7EOO

- 0000

- 0000

7EOO

- 0000

- 0000

0000

« 0000

7EOO

0000

0000 0441

0000 0444

0000 030D

0000 035A

0000 0134

0000 015B

0000 017B

0000 036C

0000 0210

0000 OOOA

0000 0014

0000 0760

0000 0790

0000 0750

0000 0000

0000 0004

0000 0724

0000 0016

0000 0062

0000 OOA3

0000 OOOF

0000 0041

0000 0600

0000 0013

0000 0447

0000 0800

SCADMID

SCMODE

SCSICODE

SCSIEND1

SCSIL3

SCSIL7

SCSIQEND

SCSI SEND

SCSISNDI

SENDDATA

SENSEKEY

SET1

SET 4

SET7

SETPARMODE

SHOWAUX

SHOWSC2

SPACE

SPARCON

SYNCHTR

SSF

TIM2

TOMEM

TXOPDINX

VERIFY

0000

0000

7EOO

7EOO

7EOO

7EOO

7EOO

7EOO

7EOO

0000

0000

7EOO

7EOO

7EOO

- 0000

7EOO

7EOO

7EOO

m 0000

- 0000

0000

- 0000

- 0000

- 7EOO

7EOO

- 0000

0000 0442

0000 0440

0000 OOA9

0000 035A

0000 013E

0000 0162

0000 034E

0000 01D9

0000 0170

0000 0015

0000 0451

0000 0780

0000 0798

0000 0758

0000 0080

0000 0531

0000 0735

0000 06EO

0000 0063

0000 0011

0000 045C

0000 0042

0000 0004

0000 03F8

0000 0453

0000

SCLN

SCSEHDA

SCSIDFLT

SCSIEND2

SCSIL4

SCSIL8

SCSIREQS

SCSISEHD1

SCSISTAT

SENDDIAG

SERBASE

SET2

SETS

SETCLK

SETREG

SHOWBDFFER

SHOWSCSI

SPARA

SS1

TOTESTRDY

TIMCON

TRANSHI

OPDBC

OPDOUT

0000

7EOO

7EOO

7EOO

7EOO

7EOO

7EOO

7EOO

- 0000

- 0000

» 7EOO

7EOO

7EOO

7EOO

7EOO

7EOO

7EOO

- 0000

7EOO

7EOO

- 0000

- 0000

- 0000

7EOO

7EOO

0000 0444

0000 01E9

0000 0173

0000 035C

0000 014D

0000 0169

0000 02D7

0000 0235

0000 0017

0000 001A

0000 03F8

0000 0788

0000 0748

0000 038F

0000 04

C30000 052B

0000 0707

0000 0060

0000 02C7

0000 0372

0000 0000

0000 0043

0000 0012

0000 047C

0000 046C

SCLHHI

SCSIO

SCSIDISCON

SCSIL1

SCSIL5

SCSILOOP

SCSIREZ

SCSISEND2

SCSITRDY

SENDMESS

SERRESET

SET200

SET50

SETOFF

SEVEN

SHOWFLAG

SINGLEMD

SPARB

START

TlTIMO

TIMEOUT

TRANSLO

UPDBCX

UPDOUTX

0000

0000

» 0000

7EOO

7EOO

7EOO

7EOO

7EOO

7EOO

0000

7EOO

7EOO

7EOO

- 0000

0000

7EOO

- 0000

0000

7EOO

7EOO

- 0000

- 0000

- 0000

7EOO

7EOO

0000 0445

0000 030C

0000 0004

0000 OOEA

0000 0154

0000 OOED

0000

0343

0000 0202

0000

035A

0000 0016

0000 0695

0000 00

930000 009B

0000

00

0400

00 00

070000 0525

0000

0040

0000

0061

0000

0000

0000

0380

0000

0040

0000 0002

0000 0014

0000 0489

0000 0478

Page 74: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

Appendix 3 j)iptatx>d.c

#include "../online/header.h 1 struct header h;

#define MINETA (-50)#define MAXETA 50#define SHOWWIDTH 4#define DECIM 2#define NUMGET 4096#define TAPEBLOCK 8192#define XZERO 0#define BEGINTRACE 60#define YZERO 65#define XSIZE 1152#define YSIZE 820#define MAXCHAN 64#define PERNOISE 100#define GAINSWEEPS 1000#define ATODDEV "/dev/rsipO"#define BOUNDS 5 int numget=NUMGET;

struct stats {int wirenum;char name[5];int discr;

} park[]={1."KSV ",680,2."KBTE",1020,3."KBTN",1360,4."KBTV",1700,5."KRBE",2040,6."KRBN",2380,7."KRBV",2720,8."KSM ",3060,9."KTP ",680,

10."KKCN",1020,11."PUB ",1360,12."BLM ",1700,13."KKCE",2040,14."KKCV",2380,15."WWR ",2720,16."KKR ",3060,17."KDME",400,18."KDMN",404,19."KDMV",346,20."XXXX",347,21."XXXX",462,22."XXXX",466,23."XXXX",585,24."XXXX",586,25."XXXX",587,26."XXXX",590,27."XXXX",494,28."XXXX",495,29."XXXX",313,30."XXXX",500,31."XXXX", 625,32."XXXX",309,

^ _

#define LOW4BITS OxF#include <stdio.h>#include <sys/file.h>#include <sys/ioctl.h>

Page 75: AN INEXPENSIVE, BUFFERED ANALOG-TO-DIGITAL CONVERTER … · logic for the XT, timing logic, and SCSI interface. Board 2 is the analog board (JDR Microdevices wirewrap prototype card

Appendix 3

#include <signal.h>#include <sys/types.h>

#include "/usr/sip/sundev/sipreg.h" struct sip__errorcode sen;

#include <suntool/sunview.h>#include <suntool/canvas.h>#include <suntool/panel.h>#include <suntool/icon.h>#include <pixrect/pixrect_hs.h>

struct rect framesize = {XZERO,YZERO,XSIZE,YSIZE}; /* size and position of frame */

static int my_done=0;

static short seis_icon[]={#include "seis.icon"

DEFINE_ICON_FROM_IMAGE (my_icon, seis_icon) ;

char buf[TAPEBLOCK] ;char decstr[][7J= {"","other ","3rd "};int endit=0;

int intr=l; onintrO {

intr=0;

static Notify_value my_frame_destroyer(frame,status) Frame frame; Destroy_status status;

onintr();if(endit) return(notify_next_destroy_func(frame, status));notify_veto_destroy(frame);return(NOTIFY_DONE);

#define ATODIN 0#define FILEOUT 1#define FILESIN 10#define TMPFILE 10tfdefine EQFILE 11#define TAPEIN 12

/* variables used in triggering calculations */#define MAX_STA 32long ssum [MAX_STA]; /* short-term sums for one sweep */ long rsum [MAX_STA]; /* rectified short-term sums */ int sbars [MAX_STA]; /* regular short-term averages */ int rbars [MAX_STA]; /* rectified short-term averages */ int sbarbar [MAX_STA]; /* regular long-term averages */ int rbarbar [MAX_STA]; /* rectified long-term averages */ int etas [MAX_STA]; /* eta values for each station */ int ploteta [MAX_STA]; int oploteta [MAX_STA];int sta_trigger[MAX_STA]; /* individual station trigger */ int subnet[] - {3, 0,1,2,3,4,5,6,7,-1,3,8,9,10,11,12,13,14,15,-1,3,16, 17,18,19,20,21,22,23,-1,3,24,25,26,27,28,29,30,31,-!,-!};

int eta_num = 2 ; /* numerator of eta constant */ int eta den = 1 ; /* denominator of eta constant */

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Appendix 3 pjdt|tod.c

int eta_con = 5 ;int diffsam = 0 ;int sweeps = 3.;int aperture = 20.;

/* another eta constant *//* don't diff samps bef computatn *//* sees of data for short term av *//* sees for coincident statn trig */

int nsw__aperture, ns_sweep, sweep;

int dec; int dev;

int ptr= -1; int maxptr= -1; float gain=0.0; double atof(); int first= -1; int last= -1; int print_ave=0; int detector=0; int percent=0; int rate=100; int trigged=0; int plotx=l; int yincr; int firsttime=l; int tapein=0;

main(argc, argv) int argc; char **argv;

int i ;

signal(SIGINT,onintr);

dec=DECIM;if(dec<l)dec=l;if (argc==l) plot it (ATODDEV,NULL,ATODIN)else for(i=l;i<argc;i++) {

endit=0;ptr- -1;maxptr= -1;intr=l;firsttime=l;if(argv[i][0]=='-') {

switch(argvfi][1]) {);case

casecasecasecasecasecasecase

'd'

'f'g'' i''p'' x''D''P'

default

dec=atoi(argv if(dec<l)dec=l; break, first=atoi(argv[++i]); gain =atof(argv[++i])j last =atoi(argv[++i]); percent=atoi(argv [++i] plotx=atoi(argv[++i]); detector=l; dec=l; break; print_ave=l; break;

printf("plotatod: Unknown argument %s\n",argv[i])

break; break; break;

); break; break;

else if(strncmp("atod",argv[i], 4)==0)plotit(ATODDEV,NULL,ATODIN);

else if (strncmp("eq.",argv[i] ,3)===0)plotit(argv[i],NULL,EQFILE);

else if (strncmp("tmp",argv[i] ,3)===0)plotit("/usr/tmp/atod.out",NULL,TMPFILE);

else if(strncmp("tape",argv[i],4)==0) {plotit("/dev/rstO",NULL,TAPEIN); ^

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Appendix 3

numget=TAPEBLOCK;

else plotit(ATODDEV,argv[i] , FILEOUT);

plot it(input , output , type) char *input , * output; int type;

int if j,k,s,numchan,numst,numstin,ioc,yy,yyl,swidth,samp,num;int ysize;short *ibuf;Short x,xO,exO,y[MAXCHAN],yO[MAXCHAN],yzero;char argp[16];Frame frame;Canvas canvas;Pixwin *pw;char frame_label[120];Icon icon;struct pr_jprpos where;struct pixfont *font;int yz,xshow,dx,tempp;extern char *malloc();long stasum[32],stamax[32],stamin[32];float millivolts[32],const,val;char temp[6],ttime[16];int lastsam[MAX_STA],thissam,diff,xcounts;

if(percent==0)percent=PERNOISE;const=2048*16/5000; /* samples per millivolt including time 4 bits */dev=open(input,O_RDONLY);if(dev== -1) {

perror("plotatod");return(1);

if(type<FILESIN) {ioc=ioctl(dev,SIPIOC_REZERO); if(ioc== -1) perror("rezero");

if(type==EQFILE) {ioc=read(dev,&h,HEADSIZE); if(ioc!=HEADSIZE) {

perror("reading eq.file header"); return(1);

ioc=read(dev r buf r numget); if(ioc!=numget) {

perror("first read");return(1);

}ibuf=(short *)buf; for(numchan=0,i=l;i<257;i+=16) {

if((j=ibuf[i]&LOW4BITS) > numchan) numchan=j;}numchan++; /* number of multiplexers */numst=numstin=numchan*16; /* number of channels */printf("Number of channels input is %d.\n",numst);if(first>last) { tempp=first; first=last; last=tempp; }if(last== -1 II last>numst)last=numst;if(first<=0)first=l;numst=last-first+1;

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Appendix 3II2IS1S

printf("Plot channels %d through %d.\n", first, last) ; if (dec<4) sprintf (f rame_label f

"Input from %s for %d channels and plotting every %spoint." finput, numst, decstr[dec-l] ) ;

else sprintf (frame_label f"Input from %s for %d channel's and plotting every %dth point.",input , numst , dec ) ;

yincr=(YSIZE-12) /numst; ysizes=yincr*numst+12; framesize.r_height=ysize+25;

printf ("Begin autoscaling by reading data for %d seconds. \n" f GAINSWEEPS/ 100) ; for(i=first-l;i<last;i++) {

stamax[i]= -10000;stamin [i]=10000;stasum[i]=0;

}if (numchan<=2) { /* determine scaling of traces */

if (type>=FILESIN) { close (dev) ;dev=open ( input , 0_RDONLY) ; if(dev== -1) perror("plotatod") ; if (type==EQFILE) {

ioc=read(dev,&h,HEADSIZE) ; if (ioc!=HEADSIZE)perror ("Reading header") ;

} }for (j=0 f num=l; j<GAINS WEEPS; j++ f num++) {

ioc=getsweep(ibuf , numstin, l f type) ; if(ioc==EOF) {

printf ("Only %d sweeps of data decimated by %d. \n" f j,dec); j-GAINSWEEPS-1;

}for (i=first-l;i<last;i++) {

samp=ibuf [i] ;if (samp<stamin [i] ) stamin [i]=samp; if (samp>stamax[i] ) stamax[i]=samp; stasumfil+^samp; if (j==GAINS WEEPS -1) {

stasum[i]=stasum[i] /num;if (print_ave) printf ("%5s min=%5d max=%5d ave=%5d\n" f

park [i] .name, stamin [i] , stamaxfi] , stasumfi] ) ; /* calculate samples per pixel */ if (gain!=0.0) {

millivolts [i]=gain;stamin [i]=gain*const/yincr;

)else {

millivolts [i]=( (stamax[i] -stamin [i] ) *100 .0/percent) /const;stamin [i]=(stamax[i] -stamin [i] ) *100/ (percent *yincr) ;

if (stamin [i]<l) stamin [i]=l; sprintf (park [i] .name, "%4s",park [i] .name) ;

}/*printf ("%x " f samp&LOW4BITS) ;*/

} /*printf ("\n") ;*/

f ont=pf_open ( "/usr/lib/f onts/f ixedwidthf onts/screen . r . 7" ) ;where .pr= (Pixrect *) icon_get (&my_icon f ICON_IMAGE) ;where.pos.x=2;where. pos .y=60;pf_text (where, PIX_SRC, font, input) ;

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Appendix 311111!^

icon_set (&my_icon, ICON_IMAGE, where .pr, 0) ;

frame=window_create(0,FRAME,FRAME_LABEL, frame_label,FRAME_ICON, &my_icon,FRAME_OPEN_RECT, fiframesize,0);

canvas=window_create(frame,CANVAS,CANVAS_AUTO_SHRINK, FALSE,CANVAS_WIDTH, XSIZE,CANVAS_HEIGHT, ysize,0);

(void) notify_interpose_destroy_func (frame,my_frame_destroyer) ; pw=canvas_pixwin(canvas); window_set(frame,WIN_SHOW,TRUE,0); yyl«0;swidth=(XSIZE-BEGINTRACE+SHOWWIDTH)/SHOWWIDTH; yzero=yincr/2;for(i=0;i<numst;i++) yO[i]=yzero+i * yincr; dx=0;yz=yincr/2; pw_batch_on(pw); xshow=BEGINTRACE+swidth; yzero=0; for(i=first-l;i<last;i++) {

pw_vector(pw,0,yzero,BEGINTRACE,yzero,PIX_SRC,1);pw_text(pw,l,yzero+yz+6,PIX_SRC,NULL,park[i].name);sprintf(temp,"%3.Of",(float)stasum[i]/const);pw_text(pw,35,yzero+yz+8,PIX_SRC,font,temp);sprintf(temp,"%3.Of",millivolts[i]);pw_text(pw,35,yzero+yz-l,PIX_SRC,font,temp);yzero+=yincr;

}printf("Now begin plotting data.\n"); pw_vector(pw,0,yzero,BEGINTRACE,yzero,PIX_SRC,1); if(type<FILESIN) {

ioc=ioctl(dev,SIPIOC_REZERO,argp);if(ioc== -1) perror("rezero");

} else {

close(dev);dev=open(input,0_RDONLY);if(dev=« -1) perror("plotatod");if(type==EQFILE) {

ioc=read(dev,&h,HEADSIZE);}

}ptr= -1; /* reset getsweep */ maxptr= -1;

if(detector) {ns__sweep » (sweeps * rate) / dec; /* Note: decim div */nsw_aperture = aperture / sweeps; /* aperture of sweeps */

}x=BEGINTRACE; xO=BEGINTRACE; exO=BEGINTRACE; sweep^O; xcounts=0; while(intr && ((ioc^getsweep(ibuf,numstin,dec,type))!=EOF) ) {

yzero=yz;if(x==BEGINTRACE) {

for(i=0,j=2;i

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Appendix 3

if(i-=3 || i«8)ttime[i]=' else if (i==ll)ttime[i]=' .' else ttime[i]=(char) (ibuf

}ttime[15]='\0';

&LOW4BITS) +' 0' ;

if (detector) {for (s=f irst-1; s<last; s++) { /* just some stations */

samp = ibuf[s]; /* get a2d sample */ if(diffsam){ /* use differences? */

thissam = samp; /* save curr sample */ samp = thissam - lastsam[s] ; /* diff with last */ lastsam[s] = thissam;

} /* remember last samp */ diff = samp - sbarbarfs]; /* diff for abs func */ ssumfs] += samp; /* add to reg sums */ rsum[s] += diff<0? -diff :diff; /* and rectified sums */

}if(++sweep == ns_sweep) {

sweep=0; if( t rigger () ) {

pw_text (pw,x,ysize-l,PIX_SRC,NULL, "TRIGGER") ;

f or (i=f irst-1 ;i<last;i++) {yy=yzero- ( (ibuf [i] -stasum[i] ) / stamin [i] ) ; pw_vector (pw,xO,yO [i] , x,yy,PIX_SRC, 1) ; if (detector && trigged) {

if (ploteta[i]>0) {pw_vector (pw,exO,yzero-oploteta [i] , exO,yzero-ploteta [i] ,PIX_SRC, 1) ; if(x<exO) {

pw_vector (pw,exO,yzero-ploteta [i] ,XSIZE-2,yzero-ploteta [i] , PIX_SRC,1) ; pw_vector (pw^EGINTRACE^zero-ploteta [i] ,x f yzero-ploteta [i] ,PIX_SRC, 1)

}else pw_vector (pw,exO,yzero-ploteta [i] ,x,yzero-ploteta [i] ,PIX_SRC, 1) ;

}oploteta [i]=ploteta [i] ; if (i==(last-l) )exO=x;

}yO[i]=yy; y ze r o+=y inc r ;

}trigged=0; xO=x;if (++xcounts>=plotx) {xcounts=0; x+=dec; } if (x>*xshow) {

pw_text (pw,BEGINTRACE f ysize-l f PIX_SRC f NULL f ttime) ; pw_show (pw) ; if(x>=XSIZE) {

x=BEGINTRACE; xO=BEGINTRACE; xshow=BEGINTRACE+Swidth ;pw_writebackground(pw f BEGINTRACE, 0, swidth+lO f ysize, PIX_SRC) ;

} else {

xshow+=swidth ;pw_writebackground (pw, x, 0, swidth+10, ysize, PIX_SRC) ;

( void) not ify_di spa t ch () ;} if(intr) {

notify_dispatch() ;

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Appendix 3

pw_batch_off(pw);endit=l;window_main_loop(frame);

} close(dev);

static short *ibuffr;

int getsweep(buffer,numch,decim,type) short *buffer; int numch,decim,type;

register i,ii; int got,next;

ptr+=numch*decim-numch; for (i=0;i<numch;i++) {

if(ptr<maxptr)buffer[i]=ibuffr[ptr++]; else {

got=read(dev,buf, numget) ; if(intr==0)return(EOF); ibuffr=(short *)buf; if(got<numget) {

if(type<FILESIN) {got=ioctl(dev,SIPIOC_GETERRC,&sen); if(sen.siperr_sensekey ==4) {

printf(" AtoD buffer overflow. Resetting.\n");got-ioctl(dev,SIPIOC_REZERO);if(got== -1) perror("plotatod.rezero");

else return (EOF) ; }pt r=pt r-maxpt r ; maxptr=(got/2) ; buffer[i]=ibuffr[ptr++] ;

return (0) ;

/* trigger

trigger() { /* calc etas, station and master triggers */register i, s; /* return: l=master trigger, 0=no trigger */int eta r sbar, rbar r new_sbarbar, new_rbarbar, thresh;

if(firsttime){for(s=first-l; s< last; s++) {

sbarbar[s]=ssum[s]/ns_sweep;rbarbar[s]=rsum[s]/ns_sweep; }

firsttime=0;oploteta[s]= MINETA*(yincr-BOUNDS)/(MAXETA-MINETA); return(0); }

trigged=l;for(s=first-l; s< last; s++) {

sbar=ssum[s]/ns_sweep;rbar=rsum[s]/ns_sweep;

eta «= rbar -(eta num * rbarbar[s]) / eta den

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new_sbarbar = (sbar + 7 * sbarbar[s]) / 8; if(new_sbarbar == sbarbar[s]){

if(sbar > new_sbarbar)new_sbarbar++;if(sbar < new_sbarbar)new_sbarbar ; }

new_rbarbar = (rbar + 7 * rbarbar[s]) / if(new_rbarbar == rbarbar[s]){

if(rbar > new_rbarbar)new_rbarbar++;if(rbar < new rbarbar)new rbarbar ; }

sbarbar[s] rbarbar[s]

= new_sbarbar; = new rbarbar;

if(sta_trigger[s])sta_trigger[s] ;if(eta > 0)sta_trigger[s] = nsw_aperture;

8;

etas[s]=eta; sbars[s]=sbar; rbars[s]=rbar;ploteta[s]=eta;if(ploteta[s]< MINETA)ploteta[s]=MINETA;if(ploteta[s]> MAXETA)ploteta[s]=MAXETA;ploteta[s]-ploteta[s]*(yincr-BOUNDS)/(MAXETA-MINETA);

/* weighted avg *//* if no change *//* favor sbar... *//* over long avg */

/* weighted avg *//* if no change - *//* favor sbar... *//* over long avg */

/* age trigger *//* set statn trig */

/* save for diagn */

/* loop thru subnet vector looking for a particular subnet* whose number of triggered stations is >= to thresh for that net.* Structure of subnet where thresh=threshhold and sn=station num is* <thresh> <sn> <sn> ... -1 <thresh> <sn> <sn> ... -1 ... -1 -1* ie, thresh-sn groups separated by -1 all terminated by -1 -1 I

i-0;while( (thresh

while ( (sif( (thresh -

return(0);

subnet[i++])subnet[i++])

= sta_trigger[s]

-1-1 0 ) <= 0)return(1)

int trig_on(){};


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