An Introduction to BORPH

Hayden Kwok-Hay SoUniversity of Hong KongAug 2, 2008CASPER Workshop II

Reconfigurable Computing for EveryoneReconfigurable Computing for Everyone• Language• Design Environment• Applications• OS

• Language• Design Environment• Applications• OS

• System Integration

• System Integration

SoftwareHardware

BORPH

BORPHBORPH

Berkeley Operating system for ReProgrammable Hardware

OS for reconfigurable computersTreats reconfigurable hardware as computational

resources

UNIX interface to HW designsFamiliar to both software and hardware engineersDesign language independent

Goal:

Make FPGA-based reconfigurable computers easy to use

Make FPGA-based reconfigurable computers easy to use

Conventional View of FPGA SystemsConventional View of FPGA SystemsUser Process

(SW)

OS Kernel

User Process(SW)

User Process(SW)

User Library

Hardware Platform(Network, UART, HD…)

file IPC

Device Driver

Softwar

eHardwar

e

socketpipe

FPGA

Master-SlaveRelationship

“coprocessor”

BORPH LayersBORPH LayersUser Process

(SW)User Process

(SW)User Process

(SW)

Hardware Platform(Network, UART, HD…)

Device Driver

User Process(HW)

User Process(HW)

Hardware User Library

BORPH Kernel

Softwar

eHardwar

e

User Library

fileIPC socketpipe

ioregvirtual

file

Peer-to-PeerRelationship

Overview of BORPH ConceptsOverview of BORPH Concepts

Hardware process Hardware syscall

interface Interacting with an FPGA

ioreg virtual file interface Hardware file I/O

SW SW SW

Hardware Platform(Network, UART, HD…)

Device Driver

HW HW

Hardware User Library

BORPH KernelSoftw

are

Hardw

are

User Libraryfile

IPC socketpipe

ioreg

Hardware ProcessHardware Process An executing instance of a

hardware design SW: An executing instance of

a program

Normal UNIX process Has pid, check status with ps, kill, etc

Unit of management Created when a BORPH

Object File (BOF) file is exec-ed Kernel selects and configure

hardware region automatically

SW SW SW

Hardware Platform(Network, UART, HD…)

Device Driver

HW HW

Hardware User Library

BORPH KernelSoftw

are

Hardw

are

User Libraryfile

IPC socketpipe

ioreg

SW SW SW

Hardware Platform(Network, UART, HD…)

Device Driver

HW HW

Hardware User Library

BORPH KernelSoftw

are

Hardw

are

User Libraryfile

IPC socketpipe

ioreg

HW Processes I/OHW Processes I/O Standard UNIX I/O

mechanism File I/O, pipe, signal

I/O managed by kernel Similar to SW

Hide details from users e.g. HW-SW, HW-HW

UNIX file pipe

HW specific service ioreg virtual file system

Don’t ask “How do I … in HW”. Think: “What if it were SW?”

Don’t ask “How do I … in HW”. Think: “What if it were SW?”

ioreg Virtual File Systemioreg Virtual File System Maps user defined hardware constructs as virtual files

under the process’s /proc/<pid>/hw/ioreg/ directory Single word register Memory: On-chip + Off-chip FIFO

Example: /proc/123/hw/ioreg/COUNTERVAL

ioreg information embedded in the executing BOF file read and write system calls translated to message

packet by the kernel Any UNIX program can communicate with hardware processes

Shell: echo 1 > /proc/123/hw/ioreg/enable C: MEM_FILE = fopen(“/proc/123/hw/ioreg/MyMemory”, “r”); fread(swbuf, 1, MEM_SIZE, MEM_FILE); Python, Java, etc…

HWRHWR

BORPHKernel

BORPHKernel

cnte

n

cntv

al

counter

en val

MessageParsing

1

./counter.bof &[1] 2458 psPID TTY TIME CMD2456 pts/4 00:00:00 bash2458 pts/4 00:00:00 counter.bof2507 pts/4 00:00:00 ps cat /proc/2458/hw/ioreg/cntvalA3B498E0 cat /proc/2458/hw/ioreg/cntvalB289E906 echo 0 > /proc/2458/hw/ioreg/cnten cat /proc/2458/hw/ioreg/cntvalC102F34D kill -9 2458[1]+ Killed counter.bof

Configured

ExampleExamplebash$

bash$

bash$

bash$

bash$bash$

bash$

bash$

counter.bof

0

Hardware File I/OHardware File I/O Access to the general file system from hardware

processes Debug by printing

printf Read test vectors, record output

SW/HW processes chained by file pipe

BasebandProcessA/DAnalog

FrontendUpperLayer

Decode ResizeEdge

DetectEncode

video.in video.out

bash$ decode video.in | resize | edgdet.bof | encode > video.out

bash$ receiver.bof < file.in > file.out

Simulink-Based Design FlowSimulink-Based Design Flow Simulink: A block based

design environment on top of Matlab Familiar to communication/

protocol designers Cycle-accurate, bit-

accurate simulation in Simulink

Single-button to implementation Based on Xilinx System

Generator In-house library for BEE2

specific blocks I/O BORPH integration

From Simulink to BOFFrom Simulink to BOF

counter.bofcounter.bof

SystemInsertion

SystemInsertion

BlockInstantiation

BlockInstantiation

Synthesis,Map,

Place & Route

Synthesis,Map,

Place & Route

ConfigGeneration

ConfigGeneration

Current Implementation on BEE2Current Implementation on BEE2 BORPH on PowerPC

of center control FPGA

1 user FPGA programmed for each hardware process

Based on Linux 2.4.30 kernelSoftware reuseDebian root filesystem

BORPH

UserDesign

UserDesign

UserDesign

UserDesign

SelectMapMGTDirect ConnEthernet

System Architecture on BEE2System Architecture on BEE2

Bus mastering DMA controller on Control FPGA Improve configuration and data transfer

Direct HW access to SelectMap FIFO on User FPGA Improved File I/O speed

SelectMapControl

PL

B-O

PB

Brid

ge

PPC

MemoryController

EthernetController

Con

trol

F

PG

A

PL

B-O

PB

Brid

ge

PPC

On-ChipMemory

Use

r F

PG

A ioreg

ioreg

SharedBRAM

SharedFIFOSelectMap

FIFO

UserDesign

DMACntrl

A

bfsioiock

On to ROACH…On to ROACH…

1 AMCC PowerPC 440 EPx

1 Xilinx V5 FPGA BORPH runs on PPC

v2.0

1 hardware process at a time

BORPHUser

Design

MGTDirect ConnGb Ethernet

BORPH v2.0BORPH v2.0

Based on Linux 2.6.25 kernelFuture proof

ModularEasy to port to different platformse.g. Implementing ioreg interface for a new

platform requires only 6 functions. Many ports planned:

Backport to BEE2PC Desktop with FPGA card

SummarySummary

BORPH is here, ready to useFree, open sourceIf you know Linux, you can use it

BORPH is extensibleAble to run on anything that runs Linux

BORPH is more than a way to do I/OCovers all aspect of reconfigurable computing