EE141© Digital Integrated Circuits2nd Introduction

An Introduction to VLSI (Very Large Scale Integrated)

Circuit Design

Presented at ECE1001Oct. 12th, 2010

By Hua Tang

EE141© Digital Integrated Circuits2nd Introduction

Basic IC circuit component: MOS transistor

First transistorBell Labs, 1948

MOS: Metal Oxide Semiconductor

EE141© Digital Integrated Circuits2nd Introduction

Intel 4004 Micro-Processor

19711000 transistors1 MHz operation

EE141© Digital Integrated Circuits2nd Introduction

Intel Pentium (IV) microprocessor

200235 Million transistors1 GHz operation0.18μm technology

EE141© Digital Integrated Circuits2nd Introduction

Intel Core™2 Duo Processor 2006>100 Million transistors2 GHz operation65nm technology

EE141© Digital Integrated Circuits2nd Introduction

Intel Core™2 Quad Processor 2007>800 Million transistors2 GHz operation45nm technology ( the biggest change in CMOS transistortechnologies in 40 years)

20091 Billion transistors3.3 GHz operation23nm technology

EE141© Digital Integrated Circuits2nd Introduction

Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months

EE141© Digital Integrated Circuits2nd Introduction

Moore’s law in Microprocessors

400480088080

8085 8086286

386486 Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel

EE141© Digital Integrated Circuits2nd Introduction

Frequency

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

Lead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel

EE141© Digital Integrated Circuits2nd Introduction

Not Only Microprocessors

Analog Baseband

Digital Baseband(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

Cell Phone

HDTV

PDA

….

EE141© Digital Integrated Circuits2nd Introduction

Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

EE141© Digital Integrated Circuits2nd Introduction

What is a MOS Transistor?

VGS VT

RonS D

A Switch!

|VGS|

An MOS Transistor

EE141© Digital Integrated Circuits2nd Introduction

MOS Transistors - Types and SymbolsD

S

G

G

S

D

NMOS

PMOS

EE141© Digital Integrated Circuits2nd Introduction

The CMOS Inverter: A First Glance

V in Vout

CL

VDD

EE141© Digital Integrated Circuits2nd Introduction

CMOS Inverter

Polysilicon

In Out

VDD

GND

PMOS 2l

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

EE141© Digital Integrated Circuits2nd Introduction

CMOS InverterFirst-Order DC Analysis

VDD VDD

Vin = VDD Vin = 0

V =0outV =Vout

Rn

Rp

DD

EE141© Digital Integrated Circuits2nd Introduction

DC OperationVoltage Transfer Characteristic

V(x)

V(y)

VOH

VOL

VM

VOHVOL

fV(y)=V(x)

Switching Threshold

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

EE141© Digital Integrated Circuits2nd Introduction

Mapping between analog and digital signals

V IL V IH V in

Slope = -1

Slope = -1

V OL

V OH

Vout

“ 0” VOL

VIL

VIH

VOH

UndefinedRegion

“ 1”

EE141© Digital Integrated Circuits2nd Introduction

Definition of Noise Margins

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

EE141© Digital Integrated Circuits2nd Introduction

0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vou

t(V)

Transient Response

tpLH tpHL

The delay Essentially determines theclock speed of theprocessor

EE141© Digital Integrated Circuits2nd Introduction

Static CMOS (Complementary MOS)VDD

F(In1,In2,…InN)

In1In2

InN

In1In2InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are dual logic networks…

…

EE141© Digital Integrated Circuits2nd Introduction

NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

X Y

A B

Y = X if A and B

X Y

A

B Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1

EE141© Digital Integrated Circuits2nd Introduction

PMOS Transistors in Series/Parallel Connection

X Y

A B

Y = X if A AND B = A + B

X Y

A

B Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

EE141© Digital Integrated Circuits2nd Introduction

Example Gate: NAND

EE141© Digital Integrated Circuits2nd Introduction

Example Gate: NOR

EE141© Digital Integrated Circuits2nd Introduction

Full-AdderA B

Cout

Sum

Cin Fulladder

EE141© Digital Integrated Circuits2nd Introduction

The Binary Adder

S A B Ci =

A= BCi ABCi ABCi ABCi+ + +

Co AB BCi ACi+ +=

A B

Cout

Sum

Cin Fulladder

EE141© Digital Integrated Circuits2nd Introduction

The Ripple-Carry Adder

Worst case delay linear with the number of bits

Goal: Make the fastest possible carry path circuit

FA FA FA FA

A0 B0

S0

A1 B1

S1

A2 B2

S2

A3 B3

S3

Ci,0 Co,0

(Ci,1)

Co,1 Co,2

td = O(N)

tadder = (N-1)tcarry + tsum

EE141© Digital Integrated Circuits2nd Introduction

Complimentary Static CMOS Full Adder

28 Transistors

A B

B

A

Ci

Ci A

X

VDD

VDD

A B

Ci BA

B VDD

A

B

Ci

Ci

A

B

A CiB

Co

VDD

EE141© Digital Integrated Circuits2nd Introduction

Design Metrics

How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function

EE141© Digital Integrated Circuits2nd Introduction

Future Design Challenges

Processor architecture (multiple-core; interconnections)

Semi-conductor materials (current leakage; process variation)

Power consumption (power density; thermal dissipation)

EE141© Digital Integrated Circuits2nd Introduction

Career in VLSI designVLSI circuit design and tool development Intel IBM AMD Cadence Synopsys MentorGraphics....

EE141© Digital Integrated Circuits2nd Introduction

VLSI Design: FFT Butterfly Widely used in signal

processing Design Butterfly Unit

for 2-point FFT Components include

multiplier, adder, subtractor, and data management

8-point FFT composed of 12 butterfliesImage from www.cmlab.csie.ntu.edu.tw/cml/dsp/training/coding/transform/fft.html

By: Spencer Strunic Matt Webb

EE141© Digital Integrated Circuits2nd Introduction

FFT Butterfly Unit Layout

EE141© Digital Integrated Circuits2nd Introduction

Registers Store data Manipulate data

ALU Select between many different operations to

output Adder

Adds two 8-bit numbers Multiplier

Multiplies two 8-bit numbers By: Brian Linder Matt Leines

VLSI Design: 8-bit CPU

EE141© Digital Integrated Circuits2nd Introduction

8-bit CPU Layout

EE141© Digital Integrated Circuits2nd Introduction

Viterbi Decoder Cell phones Dial-up modems Satellite Deep-space

communications 802.11 wireless LANS Speech recognition

systems Magnetic disk drives DNA research

By: Scott Klar Bibhu Aryal Ryan Weidemann

EE141© Digital Integrated Circuits2nd Introduction

Final design of 4-state decoder

EE141© Digital Integrated Circuits2nd Introduction

Full Search Block Matching Block Matching Algorithm (BMA):

(1) popular motion estimation algorithm(2) key component of high-compression video codecs(3) used by several standards

n

nM

S

M

S

pp

p

p

Current frame (i+1) Previous frame (i)

Reference block A Search area Motion vector

By: Zheng Yi Chang Hairong

EE141© Digital Integrated Circuits2nd Introduction

Final design (8×8 pixel block, search size 24 pixels)

EE141© Digital Integrated Circuits2nd Introduction

FIR Filter

FIR – Finite-Impulse Response Involves calculations of finite convolution sums in

discrete-time systemsUseful for Digital Signal ProcessingEquation -

x is the input signal, h is the finite impulse response, y is the sum output and N is the order of the filter

By: Craig Bristow Joliot Chu

EE141© Digital Integrated Circuits2nd Introduction

FIR Filter System Design

x[n]h[k]:

CONTROL

Module 1 – Control Module

INPUT STORAGE

Module 2 – Input Module

COEFFICIENTSSTORAGE

Module 3 – Coefficients Module

ARITHMETIC

Module 4 – Arithmetic Module

RESULTS

STORAGE

Module 5 – Results Storage

EE141© Digital Integrated Circuits2nd Introduction

A Delta-Sigma Converter for WCDMA

By: Matt Webb, Hairong Chang

EE141© Digital Integrated Circuits2nd Introduction

A speech recognition system

By: Peng Li

EE141© Digital Integrated Circuits2nd Introduction

Contact Information:

Office: MWAH 276Hour: 2-4pm MWPhone: 726-7095Email: htang@d.umn.eduHttp: www.d.umn.edu/~htang

EE141© Digital Integrated Circuits2nd Introduction

Build an CPU yourself?BMOW project (Big Mess of Wires) Material cost: $3,000