An overview of recent panel-scale packaging developments ... SEMI PANEL... · An overview of recent...

© 2012

Copyrights © Yole Développement SARL. All rights reserved.

An overview of recent panel-scale packaging

developments throughout the industry

Jean-Marc Yannou [email protected]

Infineon

Nokia FCI

NXP STATs ChipPAC

AT&S

http://www.semi.org/eu/

© 2012 • 2


Evolution to PANEL-Scale-Packaging platforms

Coreless

FO WLP

2.5D Glass / Silicon

interposer substrates

Organic Laminate /

BU packages High performance substrates

for ASIC / CPU / GPU / MPU packages

High-density / low profile solution for

RF-PA, PMU, ASIC & CPU applications

New infrastructure for Wireless

Digital IC & memory packaging

Embedded die

Game changing infrastructure

for analog & mixed signals SiP modules

WLP packages

Leadframe

packages

(TODAY)

PANEL-Scale-Packaging platforms

© 2012 • 3


Hi-runner product with fan-out WLP Infineon/Intel eWLB for X-Gold213

• The first fan-out WLP package in high volume production is Infineon’s

(now Intel Mobile Communications) X-Gold 213 , a baseband+RF

transceiver+PMU+Audio processor System on Chip.

Courtesy of System Plus Consulting

Infineon X-Gold213

package size 8x8mm²

die size 5.1x5.1mm²

package thickness 700µm

ball pitch 500µm

RDL line & space width 20µm/20µm

min

pad passivation opening 60µm

© 2012 • 4


Hi-runner product with Embedded IC Texas Instruments’ TPS8267X (MicroSiP)

• The first « embedded IC in subsrate » in high volume production is TI’s TPS826X

built with AT&S’s ECP technology, a family of DC/DC converter SiP.

Courtesy of System Plus Consulting

Texas Instruments MicroSiP

package size 2.3x2.9mm²

die size 0.93x1.3mm²

package thickness 1mm (with passives)

ball pitch 800µm

RDL line & space width 120µm/120µm min

pad passivation opening 230µm

(techno=175µm min)

© 2012 • 5


Silicon interposer example

Physical description (assumptions) of the Virtex 7 2000 T

Courtesy of Yole and Amkor Technologies

Substrate 45x45mm²

4+2+4 layers

Manufactured by Ibiden

FPGA 'slices' 3 FPGA slices of 200mm² each

2 SERDES blocks of 100mm² each

Manufactured by TSMC in Taiwan

CMOS 28nm

Silicon interposer 31x31mm²

CMOS 65nm design rules

3 Cu damascene layers, 1 alu top layer

via diameters: 12µm

thickness: 100µm

Assembly interposer to substrate: C4 solder bumps, reflow soldering post bond capillary underfilling

CMOS slices to interposer: CuSn microbumps 45µm pitch thermocompression bonding

non-conductive paste underfill

© 2012 • 6


Key applicative requirement for future PANEL-scale packaging platforms

Coreless

FO WLP

2.5D Glass / Silicon

interposer substrates

High performance substrates

for ASIC / CPU / GPU / MPU packages

High-density / low profile solution for

RF-PA, PMU, ASIC & CPU applications

New infrastructure for Wireless Digital

IC & memory packaging

Embedded die

Game changing infrastructure

for analog & mixed signals SiP modules

Key applications

Servers / high

performance ASICs

Low perf.

ASICs / SOC

CPU / GPU

for computing

Mobile APE / BB

Performance Form factor Cost Reliability

Packaging substrate requirements

Memory packaging

Wireless digital ICs in mobile applications

Camera & Sensor

SiP modules

RF & PMU SiP

modules

Analog & power

SiP modules

High perf. ASICs

Analog & memory

packaging

++++ High bandwidth

/ low latency

+++ High heat /

long lifetime

++ High bandwidth

/ low power

+ Long lifetime

+ Density / thickness

++ medium volume /

fragmented markets

+++ High bandwidth

/ low power

+ Cost pressure from

mobile architecture

++ High heat / lifetime

++ low power / high

bandwidth

+++ High density /

3D vertical stacking

++++ High volume

standard / low cost

+ Board level

reliability / drop test

+++ High density /


+++ High density /


++ High density /


++ Low cost / high

volume

++ High heat

/ reliability

++ High electrical

performance

+ Good electrical /

thermal performances

++ increased electrical

performance (higher

wiring density)

+ Heat / lifetime

+ Reduced cost

(no core part)

++ Reduced thickness

(no core part)

+++ High density 3D

vertical stacking

++++ High density /


+++ High volume

standard / low cost

+++ High volume

standard / low cost

+ Thermal performance

/ Board level reliability

/ drop test

++ Heat / reliability

+ Board level


+ Board level


+ Heat or reliability

+ increased electrical

performance (higher

wiring density)

+ Reduced cost

(no core part)

++ Increased electrical

performance (higher

wiring density)

+ Increased electrical

performance (higher

wiring density)

+ Reduced thickness

(no core part)

++ Low cost / high

volume

++ Low cost / high

volume

PANEL approach needed

© 2012 • 7


Cost case example of a 64 IO device

0.0%

10.0%

20.0%

30.0%

40.0%

50.0%

60.0%

70.0%

80.0%

90.0%

100.0%

fcCSP 0.5mm64 IO

8x8mm

fcCSP 0.4mm64 IO

5x5mm

IC embeding0.5mm 64 IO

5x5mm

fan-outWLCSP

0.5mm 64 IO4.5x4.5mm,

300mmwafer

fan-inWLCSP

0.4mm 64 IO4x4mm

rela

tive

co

st

relative packaging & test cost of a 64 IO IC fan-in WLCSP (.4mm pitch, 300mm wafer) versus fcCSP (.4mm and .5mm)

2nd pass test

1st pass test

Assembly (sawing, placement,marking, molding, packing)

Substrate

RDL/bumping (or balling)

Wafer reconfiguration

© 2012 • 8


~ 25 key players worldwide developing >300mm diameter wafers PANEL-scale-packaging related platforms

http://images.google.fr/imgres?imgurl=http://www.chipmos.com.tw/_en/_img/_layout/logo.jpg&imgrefurl=http://www.chipmos.com.tw/_en/05_news/01_detail.aspx?MainID=2&ID=43&usg=__Gtt9b0MK6FzKbjs5wdHT2iJrtIE=&h=40&w=237&sz=5&hl=fr&start=3&tbnid=KGWwVTDaTxzm9M:&tbnh=18&tbnw=109&prev=/images?q=chipmos+logo&gbv=2&hl=fr

© 2012 • 9


~ key R&D players worldwide developing PANEL-scale-packaging related platforms

© 2012 • 10


Roll-to-roll (Glass / Polymer) infrastructure for PANEL packaging?

• CORNING (US) has recently started a new program on “Roll-to-roll” glass for LSI 2.5D glass

interposer development

– The collaboration is happening in the Binghamton University

– All the tools are in place for R&D developments of this concept of this unique “flexible roll-to-roll”

electronic type of infrastructure

Flexible interposer substrate using roll-to-roll infrastructure (courtesy of Binghamton University)

© 2012 • 11


Compared cost structures of the panel package technologies

HDI PCB

(18x21 inch²)

Embeded IC

in PCB

(18x21 inch²)

Fan-out

WLP 300mm

Si interposer

300mm

Materials 50% 35% 42% 32%

Total

equipment

depreciation

15% 35% 33% 42%

including Die level 5% 23% 8% 0%

including Panel level 10% 12% 25% 40%

Personnel 15% 10% 5.5% 3%

Others

(services,

energy,

water…)

20% 20% 19.5% 23%

effect of panel size effect of geographical

location (and panel size, to a lesser extent)

© 2012 • 12


Fan-out WLP cost function of wafer/panel size

• The cost simulation of a 26mm² single device fan-out package of 64mm² function of the reconfigured

wafer or panel size shows a potential cost reduction of 37% from 200mm wafers to 18x21 inch² rectangle

panels

• We observe that the panelization effect to the next panel size decreases as the panel size increases

• We confirm that the panelization cost decrease from 300mm wafers to 450x525mm panels is less than

30%

• The production transfer from 300mm wafers to 450mm wafers (with LDI) looks promising, with up to 22%

potential cost decrease

0.0000

0.0500

0.1000

0.1500

0.2000

0.2500

0.3000

0.3500

200mm wafer 300mm wafer 450mm wafer 450x525mm panel

Pac

kage

man

ufa

ctu

rin

g co

st p

er

dev

ice

($

)

-14%

-22%

-6%

-37%

-26%

© Yole Développement, March 2012

© 2012 • 13


Fan-out WLP cost modeling effect of the patterning technique: LDI versus litho

• The effect of changing the patterning technique from standard photolithography

over to Laser Direct Imaging seems more promising (12% cost decrease on

300mm wafers) than to change wafer sizes from 300mm to 450mm with the same

patterning technique (here, with LDI: 10%)

0.0%

2.0%

4.0%

6.0%

8.0%

10.0%

12.0%

14.0%

16.0%

from 200mm to300mm litho

from 300mm lithoto 300mm LDI

from 300mm LDI to450mm LDI

Co

st d

ecr

eas

e f

or

a 1

0x1

0m

m²

pac

kage

© 2012 • 14


FOWLP package infrastructure Roadmap

650x830mm – Gen 4 LCD

400x505mm – PCB laminate

470x370mm – LCD Gen 2

380x380mm – WLP / LCD / PCB

300x300mm – Semi / LCD / PCB

200mm

300mm

2009 - 2011 2012 2013 2014 > 2016 2015

450mm FOWLP 1st gen - single die • BB/APE

• BB modem

• RF Transceiver

• NFC

• ASIC

FOWLP 2nd gen - MCP / SiP / PoP • BB/APE

• PMU / PMIC

• RF connectivity combos, RF Tx, NFC

• Audio / Video codecs

• FPGA / ASICs / MCU

FO WLP

FO MCP

FO PoP FO SiP

High yield

Semiconductor

WLP infrastructure

Fusion

WLP / PCB / LCD

infrastructures

204x508mm (8”x20” ) - Semi / PCB laminate substrate

FOWLP 2nd gen - MCP / SiP / PoP • DRAM memories

• NAND Flash memories

• APE / BB modem

• RF Tx, RF connectivity

• PMU / PMIC

• Low end ASICs / MCU

3D PoP

© 2012 • 15


Fan-out WLP cost function of wafer/panel size

Conclusion

• 450mm wafers with LDI patterning seems a great

potential size to maximize the scaling effect with limited

development costs. Beyond this size, the cost decrease

benefits become negligible and the change of infrastructure

is expected to be more than just an adaptation

• In any case, special attention needs to be paid to YIELDS • Larger sizes amplify alignment, accuracy, bowing/warping

issues and have a negative yield impact

• Yields may well be the number one influential parameter on

costs!

• This is true for fan-out WLP and for embeded IC packaging

too.

© 2012 • 16


IC embeding cost in PCB function of the panel size

• The panel size has a very limited effect on the cost of the IC embeding technology.

– The most costly pieces of equipment operate at the die level (chip placement, cavity

etching)) or at the via level.

– Starting with 18x21 inch² panels, the technology is already very « panelized » : panel-

level equipment amortization cost per device is not significant with respect to other

costs.

– It is preferable to improve yields instead of migrating to a larger pane size, especially to

prevent costly damages on the « known good embeded dies ». This is the strategy

chosen by Shinko Electric (development of IC embeding on laminate strips for good

yields).

100 98.5 96 100 97 94

0

20

40

60

80

100

18"x21" 21"x24" 24"x32"rela

tive

pro

cess

co

st o

f IC

e

mb

ed

ing

in P

CB

(b

ase

d o

n A

T&S'

s EC

P p

roce

ss

flo

w)

relative process cost, base 100 is AT&S process, 95% yield

relative process cost, base 100 is AT&S process, 99% yield

© 2012 • 17


Embedded die package PANEL infrastructure Roadmap

2010 - 2012 2013 2014 2015 > 2016

POWER & ANALOG small SiP module applications:

- DC/DC converter

- IPD

- AF driver

- Small ASICs

- MOSFET

- IGBT

- RFID

1/4 PANEL

1/2 PANEL

Full

PANEL

4”x20” – 102x508mm /

PCB laminate substrate

8”x20” – 204x508mm /


16”x20” – 400x505mm /


RF & MIXED SIGNAL large SiP module applications :

- PMU / PMIC

- RFEM (SAW, PA, etc…)

- RF connectivity (WLAN/BT/FM)

- Audio/Video Codec

DIGITAL thin PoP module applications

- BB / APE

RF & MIXED SIGNAL SiP module applications :

- PMU / PMIC

- RFEM

- RF connectivity (WLAN/BT/FM)

- Audio/Video Codec

OSAT players

Substrate players

© 2012 • 18


CMOS (28nm) Interposer BEOL Wiring (65 nm node)

Micro-bump Pitch = 45µm

2.5D

interposer TSV Depth ~75µm

Diameter ~20µm

C4 Bump

BGA

laminate

PCB / PWB

Final Assembly of 2.5D Xilinx SiP module

FPGA #1 FPGA #2 FPGA #3 SERDES SERDES

© 2012 • 19


Depreciation Cost

61%, $441

Manufacturing Cost

21%, $149

Raw Wafer Cost

11%, $80

Labor Cost 2%, $13

Yield Losses 5%, $36

Wafer Manufacturing Cost Breakdown

Cost of the 3D silicon interposer as of Q4 2012

Amortization of DRIE

+ wafer (de-)bonder

and associated clean room surface

Materials, consumables (gas,

chemicals),

energy, water, maintenance

Silicon 300mm

diameter wafer

+ glass temporary carrier

Good dies per wafer 56 Interposer wafer manufacturing cost ($) 683

Interposer wafer price ($) 1707

Manufacturing cost per interposer die ($) 12 Interposer price per part ($) 30


© 2012 • 20


Interposer wafer price roadmap

• As more players start adopting silicon

interposers in production on different

product types, the equipped fabs such

as TSMC 7 will amortize their

equipment. Concurrently, new

equipment and material prices will

decrease, and more interposer

suppliers will emerge, triggering

competition. Taking all these factors

into account, we forecasted the

« price-down roadmap » of the Xilinx

Virtex-7 package

• The price of the interposer wafers is

expected to decrease considerably

over the coming months and years.

The package cost structure will

change over with an increasing

assembly service over interposer

price ratio

3000

1707

1000 650

450

1302

1286.21

1237

1177 1136

0

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

Q1 2012 Q4 2012 Q4 2013 Q4 2015 2017

Xilinx Virtex-7 2.5D Package Price Roadmap (without BGA balling/heat spreader)

by interposer wafer ($)

Price of assembly services per interposer wafer (substrate, IC bumping,bondings)

Interposer wafer price


© 2012 • 21


2.5D interposer substrate infrastructure Roadmap

2006 - 2011 2012 2013 2014 > 2016 2015

300mm – silicon

BEOL or RDL

200mm – glass TGV

200mm – silicon RDL

150mm - silicon RDL (MEMS)

300x300mm – low grade silicon / Solar

400x400mm – organic PI / Cu WLP

650x830mm – Gen 4 LCD

500x500mm – WLP / Solar

400x505mm – PCB laminate

450x370mm – LCD Gen 2 / flexible?

450mm – glass &

silicon BEOL or RDL

150mm – glass TGV

High perf. ASICs / FPGA / GPU 2.5D interposers

MEMS, Analog, RF & LED 2.5D interposers

300mm – glass RDL

NEW Ecosystem is needed !

APE-BB / CPU / MCU 2.5D interposers

http://images.google.fr/imgres?imgurl=http://www.chipmos.com.tw/_en/_img/_layout/logo.jpg&imgrefurl=http://www.chipmos.com.tw/_en/05_news/01_detail.aspx?MainID=2&ID=43&usg=__Gtt9b0MK6FzKbjs5wdHT2iJrtIE=&h=40&w=237&sz=5&hl=fr&start=3&tbnid=KGWwVTDaTxzm9M:&tbnh=18&tbnw=109&prev=/images?q=chipmos+logo&gbv=2&hl=fr

© 2012 • 22


Key infrastructures for today / tomorrow’s IC packaging

450mm

12”

8”

Semiconductor WLP

‘Thin-film’ industry

24”x24” – HDI PWB

18”x24” - HDI PWB

16”x20” – PCB substrates

10”x14”

- flexible PWB

PCB / PWB

‘Substrate’ industry

IC Packaging

‘Back-end’ industry

8”x4”

8”x4”

package ‘strips’

• 99.98% assembly yields

• Mature / proven infrastructure on

leadframe & organic laminates

• Cost optimized for all applications

• High process flexibility with 3D

stacking capability but performance,

form factor and cost reduction

issues

• Clear responsibilities between FE

and BE players

• OSAT’s & IDM’s driven

• ~ $40B industry with investment

capabilities < $2B

• > 98% assembly yields

• Capital intensive infrastructure but

growing fast

• Cost-effectiveness reached for small to

medium chip sizes

• Specific process window options but no

capability today for 3D

• Drive consolidation of FE / BE steps in

a single environment

• OSAT’s, IDM’s & Wafer foundries driven

• Leverage ~ $350B industry with

investment capabilities > $50B

• 75 – 85% assembly yields

• Panel area processing experience

• Game changing, new infrastructure for IC

packaging but not mature yet

• Cost-effectiveness for small chips only

• Restricted process window options but

strong readiness for 3D SiP modules

• Supply chain challenge to tackle as

substrate companies are becoming

assembly houses

• Substrate companies & IDM’s driven

• Industry with low investment capabilities

© 2012 • 23


Which package infrastructures did for “PANEL” based

450mm

Semiconductor

WLP ‘Thin-film’ industry

21”x24” – HDI PWB

18”x24” - HDI PWB

16”x20” – PCB substrates

10”x14”

- flexible PWB

PCB / PWB

‘Substrate’ industry

“Fusion” of semi WLP / LCD / PCB / Solar /

flexible electronic infrastructures

26”x32” – Gen4 LCD

24”x24”

20”x20”

16”x20”

14”x18” – Gen2 LCD

15”x15”

12”x12”

© 2012 • 24


Conclusion

• Embedded IC in substrate

– Little benefit of larger panels than 18x21 inches

– Priority is yield to decrease costs

– To parallelize die evel operations (die placement, cavity etching) can help reduce costs

• Fan-out WLP

– Significant cost decrease expected with new technologies and materials (example: LDI associated

with non-photosensitive dielectric)

– Move to 450mm diameter wafers or panels (18x21 inches) is an interesting option for further cost

decrease starting in 2014/2015

As many 300mm wafer peices of equipment can be reused

Little additional benefit expected from moving to large rectangle panels

• 2.5D Interposers

– Significant cost decrease will first stem from higher yields and volumes (amortization) on 300mm

diameter wafers

– On-going research for panelization looks promising in terms of long term cost down potential

Glass panels

LCD panel type of infrastructure

Organic substrates & interposers to strike back with finer pitches?

© 2012 • 25


Join our networks and stay informed!

Media business News / Magazines / Events

www.yole.fr

© 2009


HB-LED Packaging Technology & Market Trends

IR

Osram

Market Research

Reports Market research, Technology & Strategy

Consulting services networking event

www.connect-in-3D.com

http://www.yole.fr/pagesAn/products/Report_sample/3DIC.pdf




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