AN101

AN101 November 15, 2012 (Version 1.0)

Designing a Portable Multi-Channel Data Acquisition Unit forNon-Destructive Testing: A Step by Step Guide

This application brief will summarize the device selection process and a key

design consideration for a multi-channel data acquisition unit like those used

for non-destructive testing of metal containers for material defects, weld

integrity and stress. The key devices needed in the design include an Analog

to Digital Converter (ADC) to measure the refl ected signal, an FPGA to collect

converted data via a high-speed LVDS interface and control the display, a

regulator for on-board power distribution, a microcontroller to implement the

system level functions and a display to show captured images.

We will select the ADC from the wide variety of devices offered by Linear

Technology, the FPGA from Lattice Semiconductor, and the regulator from

Linear Technology. The selection of specifi c devices will be based on the

requirements of the example design and will help illustrate a common

approach to device selection that can be used in a variety of designs.

Introduction

AN101 November 15, 2012 (Version 2.0)APPLICATION NOTE

Figure 1: Portable Non-Destructive Testing of Welds

Many industrial applications require portable instrumentation for sensing

and measuring the outputs from high-speed analog sensors. In many cases,

multi-channel instruments are used when improved resolution is required.

For example, multiple sensor channels can be combined into an array to

improve resolution and depth perception, providing a 3D-like image of the

material structure. This can be done in a non-destructive fashion when

ultrasound or low energy lasers are used as the signal source.

A common example application for multi-channel data acquisition is in

materials testing where the detection of material defects must be done

without damaging or stressing the material. Testing pipes, boat hulls and

other metal containers make access diffi cult so the tester must be able to

‘image’ into the material far enough to detect defects not visible from the

surface. Figure 1 shows a portable non-destructive tester used in the fi eld

to measure welding integrity and metal thickness via ultrasound. Other

common techniques include x-rays and magnetics but these are typically

confi ned to lab use only.


Designing a Portable Multi-Channel Data Acquisition Unit for Non-Destructive Testing: A Step-By-Step Guide

The multi-channel data acquisition unit is a self-contained subsystem that

creates and image from the reflected signals targeting the material under

test. In the case of material defect detection, like that used to inspect welds,

the reflected waves will be distorted if there are cracks, voids or stresses in

the material. Defects hidden from visual inspection are of particular interest

and the use of multiple emitters and a corresponding array of sensors can be

very effective in spotting these hidden defects even in large pipes or hulls.

The block diagram in Figure 2 shows the high level organization of the multi-

channel data acquisition unit.

The main processing elements of the sensor subsystem are the LTC

4-channel Analog to Digital Converter (ADC) that measures the output of

the sensor array, and the Lattice FPGA that processes the data to create

an image of the unit under test. The data from the ADC is sent to the FPGA

over a high-speed serial LVDS data bus. Each of the 4 differential LVDS data

channels can use either one data signal or two data signals per channel

(either 2 signals or 4 signals per channel since they are transmitted as

differential pairs). This allows for a lower or higher serial transmission rate

depending on the capabilities of the receiving device. In order to capture the

desired image resolution we will require around a 50MHz sampling rate. We

will also require 12 bits of resolution from the ADC.

The FPGA must also be able to implement some Digital Signal Processing

(DSP) algorithms to determine the existence or location of any defects.

Defect free material will typically have a very regular echo profile while

cracks and voids will produce an atypical echo pattern. An image can be

constructed and sent to the display to inform the operator of any potential

defects, similar to the images generated by medical diagnostic ultrasound

equipment. Once the image is constructed, the FPGA can use a standard 24-

bit TTL interface to transmit the image to an LCD display.

The Data Acquisition unit will be battery powered and a multi-output LTC

regulator will be used to create the various power rails needed by the

system.

For the display we can use the Tianma TM060RBH01. It is a 6-inch color

display with a 24-bit TTL RGB interface and resolution of 480x800 that

would work well in a handheld unit. For the MCU we can use the Atmel

ATxmega128A4U to manage the user interface and configure the key

data acquisition components via the SPI bus. It can also implement the

display touch screen interface and has a USB port to transfer data to a host

computer.

Now that our key requirements and features have been identified we can

move to the component selection portion of the design.

Figure 2: Block Diagram for Multi-Channel Data Acquisition Unit

Application Description

DisplayTianma

FPGALattice

4 Channel ADC LTC

Regulator LTC

LVDS Bus

AnalogSensors

Multi-ChannelData Acquisition Unit

SPIMCUAtmelRechargeable

Battery 1.8V

Data

Clock

Frame

24bitRGB

1.2V

Touch SPI

1.8V

1.8V 1.2V

3.3V

2.8V

1.8V

1.8V

3.3V2.8V

USB



The next phase of the design project is component selection, where the

designer decides on the key elements to be used in the design. Component

selection is typically driven by the requirements of the design, which we

developed in the previous section.

Component Descriptions

In this section of the application note we will review the ADC, FPGA and

regulator as candidates for our example design.

Linear Technology ADC Offerings

Linear Technology has one of the widest offerings of ADC devices in the

market. For our example design we will need 4 channels, an LVDS interface

between the ADC and the FPGA, at least 12bits of resolution and around

50Mbps sample rate. The Linear Technology parametric search web page

is a very helpful tool in identifying likely devices and is available at: http://

www.linear.com/products/high_speed_adcs Figure 3 shows the search with

parameters based on our design requirements. Four potential devices result

from the search, but the LTC2172-12 looks like a good fit for our application

based on its performance of 65Msps (the lowest of those shown).

Figure 3: LTC ADC Search Parameters

LTC2172-12 12-bit 4-Channel ADC

The LTC2172-12 is a 4-channel, simultaneous sampling 12-bit A/D converter

designed for digitizing high frequency, wide dynamic range signals. It is

perfect for demanding communications applications with AC performance

that includes 71dB SNR and 90dB spurious free dynamic range (SFDR). An

ultralow jitter of 0.15psRMS allows under sampling of IF frequencies with

excellent noise performance.

A block diagram of the LTC2172-12 is shown in Figure 4. The digital outputs

are serial LVDS to minimize the number of data lines. Each channel outputs

two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS

drivers have optional internal termination and adjustable output levels to

ensure clean signal integrity. The ENC+ and ENC– inputs determine the data

rate of conversion and serial data output and an internal PLL multiplies the

input frequency by the required amount based on the operating mode.

Figure 4: LTC2172-12 ADC Block Diagram

The output data should be latched on the rising and falling edges of the data

clock out (DCO). A data frame output (FR) can be used to determine when

the data from a new conversion result begins. The minimum sample rate

for all serialization modes is 5Msps. An SPI compatible bus, not shown in

the diagram is used to configure the operation of the ADC and can access

special features like LVDS output characteristics, as well as entering and

exiting low power sleep and nap modes.

Interference from the A/D digital outputs is sometimes unavoidable. Digital

interference may be from capacitive or inductive coupling or coupling

through the ground plane. Even a tiny coupling factor can cause unwanted

tones in the ADC output spectrum. These unwanted tones can be randomized

by randomizing the digital output before it is transmitted off chip, which

reduces the unwanted tone amplitude.

Applying an exclusive-OR logic operation between the LSB and all other data

output bits randomizes the digital output. To decode, the reverse operation is

applied—an exclusive-OR operation is applied between the LSB and all other

bits. The FR and DCO outputs are not affected. The FPGA will do the required

decode operation.

Lattice iCE40 Family of FPGAs

The Lattice Semiconductor iCE40 LP-Series and HX-Series programmable

logic family are designed to deliver the lowest power consumption of

any comparable CPLD or FPGA device while delivering the exceptional

low-cost required in high-volume applications. iCE40 FPGA are fully user-

programmable and can self-configure from a configuration image stored in

on-chip, nonvolatile configuration memory (NVCM) or stored in an external

commodity SPI serial Flash PROM or downloaded from an external processor

over an SPI-like serial port. A block diagram of the iCE40 HX-Series

architectural features is shown in Figure 5.

Component Selection



Figure 5: iCE40 HX-Series Family Architecture

Each device consists of an array of Programmable Logic Blocks (PLBs) that

in tern are made up of 8 Logic Cells. Each logic cell consists of a 4-input

Look Up Table (LUT), a ‘D’-type flip-flop and fast carry logic. Additionally,

two-port 4Kbit RAM blocks are included on each device. Each RAM block has

selectable data width, simultaneous read/write access and the contents can

be pre-loaded during configuration.

Four I/O banks are available for on and off chip signals. Each bank has an

independent supply voltage and multiple Programmable Input/Output blocks.

Emulated LVDS/subLVDS outputs and LVCMOS I/O standards are supported

on all banks. I/O bank 3 supports LVDS input standards. The HX series

supports LVDS at up to 525Mbps.

In order to simplify clocking one or two phase locked loops (PLLs) are

included. These PLLs have very low power, support clock multiplication and

division, phase shifting capability in fixed 90O increments as well as static or

dynamic phase shifting.

Programmable interconnect is used between all programmable logic

functions and eight low-skew, high-fanout clock distribution networks are

available for speed critical signals.

The iCE40 HX-series is optimized for high performance applications where

video processing functions like up-scaling and high resolution (like HD780p

at 30/60Hz or HD1080p at 30Hz over a single LVDS channel) are required.

With 525Mbps LVDS support a wide variety of applications requiring high-

speed serial support are possible.

The iCE40 LP-series is optimized for lower performance applications where

low power is critical. A common application for these devices is in offloading

the management of low-speed sensors (which typically use I2C, SPI or

UART interfaces) from much higher power application processors. Interrupt

filtering, interrupt aggregation and auto polling done in the iCE40 can

dramatically reduce overall system power consumption.

Selecting the Lattice iCE40 Device

The HX-series supports LVDS speeds of up to 525Mbps, so that is the best

fit for our high-speed LVDS requirement of the LTC2172-12 device, which

will need around 500Mbps for our sample rate and LVDS configuration. The

iCE40 HX-series devices are listed in Table 1 below. For our example design

we will target the iCE40HX1K device with 95 IOs and 1,280 logic cells in

the 132csBGA package. At just 8x8mm the small package size works well

for our space constrained design. Also, this has the same footprint as the

iCE40HX4K and iCE40HX 8K devices so we can easily migrate to a large

capacity device if we need to add more capability, perhaps in response to a

specification change.

Device LUTs IOs

iCE40HX1K 1280 72/95/96

iCE40HX4K 3520 95/107

iCE40HX8K 7680 95/178/206

Table 1: Lattice iCE40HX Series Summary

Atmel MCU Offerings

Atmel microcontrollers deliver a rich blend of highly efficient, integrated

designs, proven technology, and groundbreaking innovation that is ideal

for today’s advanced applications. Building on decades of experience and

industry leadership, Atmel has proven architectures that are optimized

for low power, high-speed connectivity, optimal data bandwidth, and rich

interface support.

Atmel AVR 8- and 32-bit microcontrollers are optimized to speed time-to-

market and are based on the industry’s most code-efficient architecture

for C and Assembly programming. The Atmel AVR XMEGA Family of

Flash microcontrollers deliver the best possible combination of real-time

performance, high integration and low power consumption for 8/16-bit MCU

applications. In our application, an advanced 8/16-bit MCU is the best fit, so

we will look at the XMEGA Family for an appropriate device.

Atmel AVR XMEGA Family

The Atmel AVR XMEGA is a family of low power, high performance, and

peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC

architecture. By executing instructions in a single clock cycle, the AVR

XMEGA devices achieve CPU throughput approaching one million instructions

per second (MIPS) per megahertz, allowing the system designer to optimize

power consumption versus processing speed.



The AVR CPU combines a rich instruction set with 32 general-purpose

working registers. All 32 registers are directly connected to the arithmetic

logic unit (ALU), allowing two independent registers to be accessed in a

single instruction, executed in one clock cycle. The resulting architecture

is more code efficient while achieving throughputs many times faster than

conventional single-accumulator or CISC based microcontrollers.

The AVR XMEGA A4U devices provide the following features: in-system

programmable flash with read-while-write capabilities; internal EEPROM

and SRAM; four-channel DMA controller, eight-channel event system and

programmable multilevel interrupt controller, 34 general purpose I/O lines,

16-bit real-time counter (RTC); five flexible, 16-bit timer/counters with

compare and PWM channels; five USARTs; two two-wire serial interfaces

(TWIs); one full speed USB 2.0 interface; two serial peripheral interfaces

(SPIs); AES and DES cryptographic engine; one twelve-channel, 12-bit

ADC with programmable gain; one 2-channel 12-bit DAC; two analog

comparators (ACs) with window mode; programmable watchdog timer

with separate internal oscillator; accurate internal oscillators with PLL and

prescaler; and programmable brown-out detection.

In order to maximize performance and parallelism, the AVR CPU uses the

Harvard architecture with separate memories and buses for program and

data. Instructions in the program memory are executed with single-level

pipelining. While one instruction is being executed, the next instruction

is pre-fetched from the program memory. This enables instructions to be

executed on every clock cycle.

The XMEGA devices have five software selectable power saving modes. The

idle mode stops the CPU while allowing the SRAM, DMA controller, event

system, interrupt controller, and all peripherals to continue functioning. The

power-down mode saves the SRAM and register contents, but stops the

oscillators, disabling all other functions until the next TWI, USB resume, or

pin-change interrupt, or reset. In power-save mode, the asynchronous real-

time counter continues to run, allowing the application to maintain a timer

base while the rest of the device is sleeping. In standby mode, the external

crystal oscillator keeps running while the rest of the device is sleeping. This

allows very fast startup from the external crystal, combined with low power

consumption. In extended standby mode, both the main oscillator and the

asynchronous timer continue to run. To further reduce power consumption,

the peripheral clock to each individual peripheral can optionally be stopped

in active mode and idle sleep mode.

In our design we will require USB and two SPI ports- one for the Touch

interface to the Display and one to both the ADC and FPGA. We should

require around 128KB of program memory and 8KB of SRAM. After reviewing

the various devices from Table 1-1 in the ATxmega A4U Series data sheet

(listed in the Reference section of this application brief), the ATxmega128A4U

looks like a good candidate.

LTC Power Regulators

LTC has a wide range of power regulation devices. For our application we

will want a device that takes a minimum of board space, simplifies board

layout and fits into a common manufacturing flow. Linear Technology has

published a concise guide to selecting regulators and modules for Lattice

FPGAs. Table 2 shows a portion of the guide (the full guide is available at the

web site included in the Reference section of this application brief).

The Lattice iCE40 requires a 1.2V core voltage so this table works for the

iCE40 family even though it isn’t listed. We will be using a 5V rechargeable

battery so the middle row applies to our design. We don’t need much current

so the leftmost column is appropriate. We will need a multi-output regulator

to supply the other voltages needed in the system so the LTC3544 quad

monolithic regulator, shown in Figure 6, is the one to investigate in more

detail.

Figure 6: Block Diagram of LTC3544 Monolithic Quad Regulator

The LTC3544 is a quad, high efficiency, monolithic synchronous buck

regulator using a constant-frequency, current mode architecture. The four

regulators operate independently with separate run pins and can provide

up to 300ma (on one output), 200ma (on two outputs) and 100ma (on one

output).

The 2.25V to 5.5V input voltage range makes the LTC3544 well suited

for single Li-Ion/polymer battery-powered applications. 100% duty cycle

provides low dropout operation, extending battery runtime in portable

systems. Low ripple Burst Mode operation increases efficiency at light loads,

further extending battery runtime with typically only 20mV of ripple.

The LTC3544 has several features that make it an excellent fit for our design

requirements. The LTC3544 uses a soft-start to reduce surge currents

and reduce turn-on noise, which can otherwise interfere with system

initialization. Each of the four regulators has a separate enable pin, which

can be used to turn power off to a section of the design. This can be useful

when putting the system into a low power ‘sleep’ mode to extend operating

time.



Each regulator channel required only a few external components to

determine the output voltage and to complete the switching circuit- two

resistors, an inductor and a capacitor. Because the switching frequency is

2.25MHz surface mount components can be used, simplifying manufacturing

and reducing cost.

The LTC3544 data sheet, listed in the Reference section of this application

brief, provides detailed guidelines for selecting external components as well

as layout guidelines. LTSpice simulation files for an example design are also

available to speed development time.

Device Selection Summary

We have decided on the key components from which to construct our

example design. We selected the LTC regulator, LTC ADC and a Lattice FPGA.

Next we will show the use of available LTC and Lattice design tools, kits and

documentation to help with some key design choices and trade-offs.

Table 2: Selection Guide for LTC Power Modules with Lattice FPGAs

The main design consideration we are going to discuss is the implementa-

tion of the interface between the LTC ADC and the Lattice FPGA using the

high-speed serial LVD bus. Additionally we will identify evaluation board that

can be used to prototype our design allowing us to speed FPGA design and

software implementation.

LTC2172 LVDS Serial Interface Operation

The LTC2172 has a high-speed serial LVDS interface that allows it to com-

municate with digital logic at the full conversion rate. Figure 7 shows the

detailed operation of the LTC2172-12 LVDS bus. The analog input is sampled

as shown at the top of the figure, initiated by the encode (ENC+-) signal.

The encode signal can be sourced by an oscillator or by the FPGA to provide

an additional level of timing control. The DCO signal is the output clock and

is generated from the encode input by the internal PLL via a multiplication

process determined by the output configuration and ADC accuracy (from

configuration registers set via the SPI bus). The output data timing for the

configuration with 12-bit accuracy and 2 outputs per channel (as in our

example implementation) is shown at the bottom of Figure 7. Figure 7: Serial LVDS Bus Operation

The LVDS outputs from the LTC2172-12 can be connected directly to the

iCE40HX FPGA but some care must be taken to match the maximum fre-

quency of the iCE40HX LVDS I/Os. Operating the LTC2172-12 LVDS outputs

at 6 times the sampling frequency (by using 12-bits of accuracy and 2 output

Design Considerations



signals per channel) we can sample at or 50MHz rate using a 300MHz LVDS

bus speed. The iCE40HX supports LVDS speeds of up to 525Mbps, so it can

meet our required interface speed.

Using the LTC2172-12 Evaluation Board

The DC1525A evaluation board demonstrates the DC and AC performance

of the LTC2172-12 in conjunction with the DC1371 QuikEvalTM collection

system. The DC1371 is used to acquire data from the DC1525A and is con-

trolled by the Pscope™ System Software supplied by LTC. The combination

of the DC1525A and DC1371 boards is shown in Figure 7. Analog data from

the inputs on the left side of the figure are converted and made available to

the PScope system software over the USB connection on the right side of the

figure.

Figure 7: LTC2172 (DC1525A) Eval Board

PScope can be used to evaluate the characteristics of the LTC2172-12 ADC

and a screen short of PScope during operation is shown in Figure 8. For

example, the PScope software can report parameters such as SNR, THD,

SINAD and SFDR (shown on the right side of the display) as well as showing

a Fourier transform of the input signal (in the main window).

Figure 8: PScope Screen Shot

Lattice iCE40HX LVDS Bus

The iCE40 I/O Banks contain a number of programmable I/O pins (PIO’s). All

PIO pins support “single-ended” I/O standards, such as LVCMOS. However,

the iCE40 FPGAs also support differential I/O standards where a single data

value is represented by two complementary signals transmitted or received

using a pair of PIO pins. The PIO pins in I/O Bank 3 support Low-Voltage Dif-

ferential Swing (LVDS) and SubLVDS inputs.

LVDS channels are supported at up to 525Mbps. Figure 9 shows the block

diagram for the Lattice iCE40 LVDS inputs. For differential outputs I/O Bank

3 must be used. Specific pairs of PIO pins in I/O Bank 3 form a differential

input. Each pair consists of a DPxxA and DPxxB pin, where “xx” represents

the pair number. The DPxxB receives the true version of the signal while the

DPxxA receives the complement of the signal. Typically, the resulting signal

pair is routed on the printed circuit board (PCB) with matched 50Ω signal

impedance.

Figure 9: iCE40 LVDS Input

Each differential input pair requires an external 100Ω termination resistor,

as shown in Figure 9. The iCE40 LVDS I/Os can use either a 1.8V or 2.5V I/O

voltage. In our application we will use a 1.8V supply to be compatible with

the ADC LVDS output levels.

Differential outputs are built using a pair of single-ended PIO pins as shown

in Figure 10. Each differential I/O pair requires a three-resistor termination

network to adjust output characteristic to match those for the specific dif-

ferential I/O standard. The output characteristics depend on the values of the

parallel resistors (RP) and series resistor (RS). Differential outputs must be

located in the same I/O tile.



Figure 10: iCE40 LVDS Differential Inputs

The iCE40 I/Os also have double data rate registers on inputs and outputs.

For high-speed serial interfaces these registers can be used to quickly

process input or output signals so that the data rate inside the device is only

50% of the data rate at the pins. This reduces power dissipation and makes

it easier to satisfy internal signal timing constraints.

Using the iCE40HX1K Evaluation Kit

The inexpensive iCE40HX1K Evaluation Kit, shown in figure 11, can be

used to prototype the FPGA portion of the system and when combined with

the already mentioned LTC Evaluation boards the entire data acquisition

subsystem can be implemented. The LVDS bus is used to connect the main

evaluation boards and several reference designs are available to simplify

initial board bring-up and speed application code development.

Figure 11: iCE40HX1K Evaluation Board

Summary

The detailed design of the interface between the Linear Technology LTC2172

ADC and the Lattice iCE40 FPGA is considerably simplified by using the LVDS

bus. The small signal count of the bus makes component layout and routing

easier, reduces board noise and reduces component and board size. The

flexible LVDS capable I/Os on the iCE40 family make it easy to implement the

FPGA side of the interface. Readily available evaluation boards, reference de-

signs, software tools, layout and schematic files make it possible to quickly

prototype the design and immediately begin detailed design and testing. This

significantly reduces time to market.



This application note has provided a guide to the design considerations for high-speed data acquisition subsystem for a portable instrument used for non-

destructive testing. Device selection and the design considerations for the LVDS interface between the ADC and FPGA were covered in detail. A combination of

readily available evaluation boards, reference designs and software tools were shown that can easily prototype the entire subsystem to speed development. The

information provided can be applied to numerous similar designs.

For the reader who wants additional levels of detail on the products used in this application brief a list of valuable documents is given below.

1) Linear Technology Power Management Solutions for Lattice Programmable Logic Devices- Selection Guide

http://cds.linear.com/docs/Reference%20Design/Product_Guide_Lattice.pdf

2) Linear Technology LTC3544 Quad Output Regulator LTC3544 Data Sheet - http://cds.linear.com/docs/Datasheet/3544fa.pdf

3) Linear Technology LTC2172 Data Sheet - http://www.linear.com/product/LTC2172-12

4) Linear Technology DC1525A Demo Board - http://www.linear.com/demo/DC1525A-J

5) Linear Technology PScope Software - http://www.linear.com/PScope

6) Lattice iCE40HX Data Sheet - http://www.latticesemi.com/documents/iCE40HXdatasheet121003.pdf

7) Lattice iCE40 Handbook - http://www.latticesemi.com/documents/iCE40Handbook_120330.pdf

8) Lattice iCEblink40 Evaluation Kit - http://www.latticesemi.com/documents/EB73.pdf

9) Atmel ATxmega128A4U MCU Web Page - http://www.atmel.com/devices/ATXMEGA128A4U.aspx

10) Tianma Micro-Electronics TM060RBH01 Display Data Sheet - http://www.tianma-usa.com/web/uploads/spec/1020171517_TM060RBH01-00_V1.0.pdf

11) Nu Horizons Application Note Web Page - http://www.nuhorizons.com/application_notes/

12) Nu Horizons Development Tools Web Page - http://www.nuhorizons.com/development/

Products Used In Example Design

Linear TechnologyADC LTC2172-12 Demo Board DC1525A Software PScopeRegulator LTC3544

Lattice SemiconductorFPGA iCE40HX1K Demo Board iCEblink40

Atmel

MCU ATxmega128A4U

Tianma

Display TM060RBH01

Notice Of Disclaimer

Nu Horizons is disclosing this Application Note to you “AS-IS” with no warranty of any kind. This Application Note is one possible implementation of this feature,

application, or standard, and is subject to change without further notice from Nu Horizons. You are responsible for obtaining any rights you may require in

connection with your use or implementation of this Application Note. NU HORIZONS MAKES NO REPRESENTATIONS OR WARRANTIES, WHETHER EXPRESS

OR IMPLIED, STATUTORY OR OTHERWISE, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, OR FITNESS

FOR A PARTICULAR PURPOSE. IN NO EVENT WILL NU HORIZONS BE LIABLE FOR ANY LOSS OF DATA, LOST PROFITS, OR FOR ANY SPECIAL, INCIDENTAL,

CONSEQUENTIAL, OR INDIRECT DAMAGES ARISING FROM YOUR USE OF THIS APPLICATION NOTE.

References

Conclusion

Date post:	16-Apr-2015
Category:	Documents
Upload:	francisco-lopez
View:	39 times
Download:	4 times

AN101

Documents