AN161 – LTC6951 Synchronization Manual Design Examples … · · 2018-03-19Design Examples for...

Application Note 161

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March 2017

LTC6951 Synchronization ManualDesign Examples for EZSync, ParallelSync, EZParallelSync and EZ204SyncChris Pearson

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and LTC6951Wizard, EZ204Sync, EZParallelSync, EZSync and ParallelSync are trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners.

Table 1. Multichip Synchronization ComparisonArchitecture Jitter Sync Timing Requirements Multichip Phase Alignment (All Outputs)

EZSync Clock Distribution Low Easy Yes, on First Edge*

ParallelSync Reference Distribution Ultralow Moderate Yes, outputs aligned to reference on First Edge* and have a known latency to sync signal falling edge

EZ204Sync or EZParallelSync

Reference Divide and Distribution Ultralow Easy Yes, aligned to reference per each LTC6951 sync

*First Edge alignment implies all outputs requiring synchronization are phase aligned on the same sync event

concerns by providing three multichip synchronization options: EZSync™, ParallelSync™, and EZParallelSync™/EZ204Sync™. This application note provides step by step design examples for each multichip synchronization method.

Table 1 provides a summarized comparison of each synchronization method. Application Note 165 provides detailed descriptions and trade-offs of each synchronization method.

IntroductIonFor systems demanding a large number of synchronized clock signals, a clock tree using multiple clock devices is often required. Multiple clock devices can add system complexity when compared to a single clock distribution device. One complexity created is the ability to synchronize the clock phases and start times across multiple clock devices. The other challenge created is maintaining the desired low jitter clock performance when cascading multiple clock devices.

Linear Technology’s family of PLL/VCO and clock distribu-tion ICs address both the synchronization and performance

TAblE Of COnTEnTS

Introduction .........................................................................................................................1EZSync Design Example ..........................................................................................................2ParallelSync Design Example ................................................................................................. 10JESD204b ParallelSync Design Example 2 (based off DC2226 Demo board) .......................................... 21EZParallelSync Design Example .............................................................................................. 32EZ204Sync Design Example .................................................................................................... 42Appendix: Model Reference noise for lTC6951Wizard Simulations .................................................... 53


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EZSync Design Overview

EZSync is a simple way to generate synchronized clock outputs from multiple cascaded devices requiring only a simple logic signal or serial port interface (SPI) commands to achieve alignment.

Figure 1 introduces the following EZSync terminology: CONTROLLER, FOLLOWER, Follower-Driver, Follower-Synchronous, and Synchronization Disabled which are defined below:

COnTROllER: EZSync device set to CONTROL mode. A device in CONTROL mode controls the timing for all other EZSync devices.

A CONTROLLER has three EZSync output types: Follower-Driver, Follower-Synchronous and Synchronization Disabled.

For the LTC®6951, to enable CONTROL mode set register bits SN = SR = 0.

fOllOWER: EZSync device with at least one output set to FOLLOW mode. The FOLLOWER must be DC coupled to a Follower-Driver output.

During a SYNC event an output in FOLLOW mode is set to a logic low. Following a SYNC event, each FOLLOWER requires seven clocks cycles before the outputs in FOLLOW mode output a signal.

1.2GHz, CLOCK

1.2GHz, CLOCK

100MHzREFERENCE

LTC6951EZSync

CONTROLLER

LTC6954-1 #1EZSync FOLLOWER


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OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

IN+

IN–

OUT0SEL

OUT1SEL

OUT2SELSYNC

EZSync: SYNCHRONIZATION DISABLED

EZSync: FOLLOWER-SYNCHRONOUS

EZSync: FOLLOWER-DRIVER100Ω

IN+

IN–100Ω

10kVCC

VCP+ VVC0+

5V

V+

3.3V

10k

10k

10Ω

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

100MHz, CLOCK

37.5MHz, SYSREF

2.4GHz, CLOCK

300MHz, CLOCK

37.5MHz, SYSREF

300MHz, CLOCK

M0 = /4DLY0 = 0

M1 = /32DLY1 = 2

M2 = /4DLY2 = 0

OUT0SEL

OUT1SEL

OUT2SELSYNC

10kVCC

REF–

REF+50Ω

56.2Ω

56.2Ω

1.5nF1nF

68nF

10k

10k

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

37.5MHz, SYSREF

300MHz, CLOCK

37.5MHz, SYSREF

M0 = /32DLY0 = 2

M1 = /4DLY1 = 0

M2 = /32DLY2 = 2

1µF1µF

BVC0

SYNC

1µF

BB

0.47µF

1µF

1µF

CMACMBCMCTB

CP

TUNE

EZSyncSYNC PULSE

WIDTH ≥ 1ms

EZSyncSYNC PULSE SKEW

BETWEEN PARTS ≤ 10µs

figure 1. EZSync Design Example

EZSync dESIgn ExamplE

http://www.linear.com/LTC6951


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An LTC6954 output is set to FOLLOW mode when the respective LTC6954 SYNC_ENx register bit is set high.

follower-Driver: CONTROLLER’s clock output that is connected to a FOLLOWER’s clock input. DC coupling is required between the CONTROLLER output and FOL-LOWER input.

During a SYNC event, the Follower-Driver outputs are set to a logic low.

follower-Synchronous: CONTROLLER’s clock output that is synchronized to a FOLLOWER device’s clock outputs.

During a SYNC event the Follower-Synchronous output is set to a logic low.

Following a SYNC event the Follower-Synchronous and FOLLOWER clock edges are aligned based on the delay settings in the CONTROLLER’s and FOLLOWERs’ register map.

Synchronization Disabled: Outputs that are not synchro-nized to Follower-Driver or Follower-Synchronous outputs. These outputs remain active during synchronization.

Synchronizing the LTC6951 outputs in Figure 1 involves sending a common sync signal that meets EZSync tim-ing requirements. These are provided in Figure 1 and the LTC6951 EZSync Design Rules section.

The section titled LTC6951 EZSync Design Rules summa-rizes the EZSync design rules. The section titled EZSync Design Example section provides the design process used to develop the block diagram in Figure 1. The section titled Delay and Layout Recommendations provides how to minimize skew between parts by accounting for line length delays, FOLLOWER propagation delays and delta’s in FOLLOWER and CONTROLLER rise and fall times. The section titled Synchronization Routines, provides initial power-up, power-down and resynchronization sequences. The Expandable Solution section discusses how the block diagram in Figure 1 can expand to support more clock outputs.

lTC6951 EZSync Design Rules

1. CONTROLLER set to CONTROL Mode. For LTC6951 register settings:

a. SN = 0

b. SR = 0

2. FOLLOWER outputs set to FOLLOW Mode. For LTC6954 set register setting SYNC_ENX = 1 for each output.

3. EZSync CONTROLLER to FOLLOWER Connection re-quires DC coupling.

4. EZSync timing requirements:

a. Sync Pulse width > 1ms

b. Sync Pulse skew between parts <10µs

EZSync Design Example

This design example will use the LTC6951Wizard™ to aid in the design process. Download LTC6951Wizard at http://www.linear.com/LTC6951Wizard.

This example assumes the following list of design inputs:

Reference

fREF = 100MHz

lTC6951: EZSync COnTROllER

OUT0 2.4GHz Follower-Synchronous

OUT1 1.2GHz Follower-Driver Outputs

OUT2 1.2GHz Follower-Driver Outputs

OUT3 37.5MHz Follower-Synchronous

OUT4 100MHz Synchronization Disabled FPGA clock

lTC6954: EZSync fOllOWERs

F6954#1-OUT0 = 300MHzF6954#1-OUT1 = 37.5MHzF6954#1-OUT2 = 300MHz

F6954#2-OUT0 = 37.5MHzF6954#2-OUT1 = 300MHzF6954#2-OUT2 = 37.5MHz

Delay settings

Align the rising edge of LTC6951 and LTC6954 SYSREF signal to the falling edge of the clock signals.

Performance Optimization Request

Design for low jitter. Minimize the output skew between devices.

http://www.linear.com/LTC6951Wizard


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lTC6951 Setup

Based on the EZSync Design Rules and the above design inputs, the following steps provide input conditions for the LTC6951Wizard.

Step 1: Design input: optimize the LTC6951 charge pump current for low jitter.

Based on the LTC6951 data sheet the best jitter performance is obtained by maximizing the LTC6951 ICP current.

ICLK6951.CP = 11.2mA

Step 2: Design input: align LTC6951 SYSREF rising edge to the LTC6951 2.4GHz falling edge.

Assign the LTC6951 output invert bits as follows:

OINV06951 = 1 (OUT0 = 2.4GHz)

OINV16951 = 0 (OUT1 = SYSREF)

The section Delay and Layout Recommendations will discuss how to determine delay register settings to align LTC6951 Follower-Synchronous outputs and LTC6954 outputs. This example will assume the following inputs to the LTC6951Wizard tool

OUT0 Delay = 0*

OUT3 Delay = 7*

*These values are equivalent to Dx in Equation 2 under the section Delay and Layout Recommendations.

lTC6951Wizard

This section demonstrates the LTC6951Wizard’s ability to ease the register setting creation and loop filter design for the LTC6951. Under the LTC6951Wizard’s Help Menu a Help Guide is provided that will aid in understanding the operations performed in this section.

The values calculated in Steps 1 and 2 and conditions pro-vided at the start of this design example are summarized below for a quick reference. These values will be used for inputs to the LTC6951Wizard to calculate the register settings and loop filter values for both LTC6951s in this design example.

LTC6951Wizard Inputs for Figure 2:

f6951.REF = 100MHz f6951.OUT0 = 2.4GHz f6951.OUT1 = 1.2GHz f6951.OUT2 = 1.2GHz f6951.OUT3 = 37.5MHz f6951.OUT4 = 100MHz I6951.CP = 11.2mA OUT0 Delay = 0 OUT3 Delay = 7

Figures 2 and 3 provide the remaining steps necessary to complete the LTC6951 portion of this design. Several steps in these Figures 2 and 3 require the following ad-ditional information.

Importing Reference Noise

Refer to Appendix: Model Reference Noise for LTC6951Wizard Simulations, which describes how to import reference noise into the LTC6951Wizard and the impact of reference noise on loop filter calculations and output noise simulations. The CCHD575_REFNOISE.txt file provided with the LTC6951Wizard should be used for this example.

Loop Filter Selection

Figure 3’s step 10 selected Filter 2. Through experimenta-tion Filter 2 was found to be the best option to optimize performance and board space.


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figure 2. lTC6951Wizard Setup


1. Set ICP = 11.2mA

2. Select Sync tab. See Steps 2a to 2d on far right

3. Set Fref = 100MHz

4. Set Invert OUT0 = Yes

5. Select All Select

6. Set Fout0 = 2400MHz Fout1= Fout2 = 1200MHz Fout3 = 37.5MHz Fout4 = 100MHz

7. Import Reference Noise File CCHD575-100M.txt (Appendix: Model Reference Noise for LTC6951Wizard Simulations)

8. Select Compute Params

2a. Select CONTROLLER and EZSync

2b. Set Follower-Driver Outputs (OUT1 and OUT2) to Follower-Driver

2c. Set Follower-Synchronous Outputs (OUT0 and OUT3) to Synchronized and set Delay to 0 and 7, respectively.

2d. Set OUT4 to No Sync

9. Double click Opt Loop BW (Noise) to copy to Loop BW

10. Select Filter 2 and Design Filter, then set Component Values to closest standard component values.

11. Under File menu, select Save Settings. File name = EZSync (see far right)


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12. Under Options menu, select Copy Loop to System

13. Select System tab to view results

13. Under File menu, select Save Settings. File name = EZSync

lTC6954 Setup

Step 4: Design input: selecting LTC6954 FOLLOWER device for low jitter and minimal skew between devices.

The LTC6954 has four device options with various output signal types. The PECL output version, LTC6954-1, was selected over the other versions for the following reasons:

1. Lowest additive jitter

2. Smallest propagation delay variation over temperature

Step 5: Design input: align LTC6954 SYSREF rising edges to the LTC6954 300MHz falling edge.

The LTC6954 does not have an output invert bit. Therefore the LTC6954 input frequency was selected to allow the LTC6954 delay SPI register bits to perform an inversion.

With FIN6954 = 1.2GHz and the maximum LTC6954 output frequency = 300MHz, the LTC6954 delay settings can chose between 4 output phases:

DLYX6954 = 0 → 0 degrees offset DLYX6954 = 1 → 90 degrees offset DLYX6954 = 2 → 180 degrees offset DLYX6954 = 3 → 270 degrees offset

Setting the 300MHz outputs to a delay of 0 degrees and the 37.5MHz outputs to delay of 180 degrees will properly align the LTC6954 outputs.

DLY06954#1 = 0 DLY16954#1 = 2 DLY26954#1 = 0


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DLY06954#2 = 2 DLY16954#2 = 0 DLY26954#2 = 2

Step 6: Design input: minimize the output skew perfor-mance between the LTC6954-1 #1 and LTC6954-1 #2.

Per the LTC6954 data sheet output to output skew is best when all LTC6954 divider values are either equal to /1 or all divider values are greater than /1. In this example the LTC6954 input frequency was chosen such that all LTC6954 dividers are greater than /1.

Step 7: LTC6954 settings summarized:

Register settings:

SYNCENX6954 = 1 PDIVX6954 = 0 PDOUTX6954 = 0

M06954#1 = 4 DEL06954#1 = 0 M16954#1 = 32 DEL16954#1 = 2 M26954#1 = 4 DEL26954#1 = 0

M06954#2 = 32 DEL06954#2 = 2 M16954#2 = 4

DEL16954#2 = 0 M26954#2 = 32 DEL26954#2 = 2

Delay and layout Recommendations

Minimizing output skew between an LTC6951 EZSync CONTROLLER output and an EZSync FOLLOWER output can be performed by solving Equations 2 to 6 (refer to Figure 5).

Equations 1 and 2 align the starting edges of the CON-TROLLER’s Follower-Synchronous output and Follower’s outputs. Equation 1 is provided in the LTC6951 data sheet and shown below for consistency. Equation 2 expands upon Equation 1 by translating the trace lengths, FOLLOWER propagation delay and rise time to the nearest LTC6951 P-divider cycle delay value.

CONTROLLER Follower-Synchronous

DFSX = Dx + MFDY • 7 (1)

DFSX = Dx +MFDY • 7+

int(d2+ d3 – d1)+tpd(FOLLOWER)

+tr(FOLLOWER)

2

⎛

⎝

⎜⎜⎜⎜⎜

⎞

⎠

⎟⎟⎟⎟⎟

• f PD+ 0.5

⎛

⎝

⎜⎜⎜⎜⎜

⎞

⎠

⎟⎟⎟⎟⎟

(2)

L1

L2 L3

LTC6951 CONTROLLER

LTC6954 FOLLOWER

fPD

tpd(FOLLOWER)

tr(FOLLOWER)

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

CLK+

CLK–

CLK+

CLK–


EZSync: FOLLOWER-DRIVERNOTE: REQUIRES DC COUPLING

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

REF–

REF+PLLVCO P-DIVIDER

DFSX MFSX

MFDY

NOTE: AFTER AN EZSync PULSE, OUTPUTS IN FOLLOW MODE ARE HELD LOW UNTIL 7 FOLLOWER-DRIVERCLOCKS ARE RECEIVED

DFY MFY

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figure 5. Output Skew


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Equations 3 and 4 convert the board’s trace length to a signal delay.

Trace Length

dx = LX/Vp (3)

Vp =

cεr

(4)

Equation 5 calculates the FOLLOWER’s delay setting in terms of the CONTROLLER delay settings. Equation 6 calculates the desired delay delta between a Follower-Synchronous output and a FOLLOWER output.

FOLLOWER Output

Dy = DFY • MFDY (5)

DDelta(FStoFOLLOWER) = Dx – Dy (6)

where:

c: speed of light (m/s)

DFSX: LTC6951 Follower-Synchronous delay (s)

DFY: FOLLOWER delay (s)

Dx: desired delay of Follower-Synchronous output with respect to a FOLLOWER output when Dy = 0. Dx is the delay value input for the LTC6951Wizard tool in Figure 2.

Dy: desired delay of FOLLOWER output with respect to Follower-Synchronous output when Dx = 0.

DDelta(FStoFOLLOWER): desired delta delay between CONTROLLER and FOLLOWER outputs, in terms of the CONTROLLER delay settings.

dX: signal delay, electrical trace length(s)

fPD: LTC6951 P-Divider output frequency

LX: trace length (m)

MFDY: LTC6951 Follower-Driver divide value

MFSY: LTC6951 Follower-Synchronous divide value

MFY: FOLLOWER divide value

tpd(FOLLOWER): EZSync FOLLOWER propagation delay (s)

tr(FOLLOWER): EZSync FOLLOWER rise time

Vp: velocity of propagation (m/s)

εr: board material dielectric constant (relative permittivity)

Synchronization Routines

On initial power-up:

1. Program LTC6954 and LTC6951 SPI registers

2. Wait for LTC6951 bias voltages to stabilize

3. Calibrate LTC6951 VCO

4. Wait for VCO calibration to complete

5. Send EZSync pulse

Power-down:

1. Power down LTC6951 (PDALL = 1)


Resynchronization (post power-down):

1. Power up LTC6954 (PDALL = 0)

2. Power up LTC6951 (PDALL = 0)

3. Send EZSync pulse

Expandable Solution

EZSync solutions are infinitely expandable. As shown in Figure 6 the EZSync design example can be expanded by adding fanout buffers to distribute additional clocks. The remainder of this section provides considerations when selecting a fanout buffer, the fanout buffer register settings in Figure 6 and comments regarding further expansion.

The fanout buffer in Figure 6 does not require an EZSync pulse. Therefore the fanout buffer does not need to be an EZSync device. However, the fanout buffer must be capable of accepting a DC-coupled input from an EZSync CONTROLLER and driving a DC-coupled input to an EZSync FOLLOWER.

Each stage of a clock distribution architectures produces additive jitter. Referring to Equation 7, the addition of the fanout buffer will increase the total jitter.

JitterTotal =JitterCONTROLLER

2 + JitterFOLLOWER2

+JitterFANOUT−BUFFER2

(7)

The fanout buffers propagation delay, output rise time and trace lengths to the fanout buffer will need to be included in the delay calculations. Refer to Equation 2 delay calcula-tions in the Delay and Layout Recommendations section.


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figure 6. EZSync Expandable Solution

1.2GHz

1.2GHz

DC-COUPLED1.2GHz

DC-COUPLED

DC-COUPLED

1.2GHz

1.2GHz

DC-COUPLED

DC-COUPLED

100MHzREFERENCE

LTC6951EZSync

CONTROLLER

FANOUTBUFFER





LTC6950

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

LV/CM+

LV/CM–

PECL0+

PECL0–

PECL1+

PECL1–

PECL2+

PECL2–

PECL3+

PECL3–

IN+

IN–

OUT0SEL

OUT1SEL

OUT2SEL

SYNC

EZSync: SYNCHRONIZATION DISABLED


EZSync: FOLLOWER-DRIVER

100Ω

IN+

IN–100Ω

IN+

IN–100Ω

10kVCC

VCP+ VVC0+

5V

V+

3.3V

10k

10k

10Ω

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

100MHz, CLOCK

37.5MHz, SYSREF

2.4GHz, CLOCK

300MHz, CLOCK

37.5MHz, SYSREF

300MHz, CLOCK

M0 = /4DLY0 = 0

M1 = /32DLY1 = 2

M2 = /4DLY2 = 0

OUT0SEL

OUT1SEL

OUT2SELSYNC

10kVCC

REF–

REF+50Ω

56.2Ω

56.2Ω

1.5nF1nF

68nF

10k

10k

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

37.5MHz, SYSREF

300MHz, CLOCK

37.5MHz, SYSREF

M0 = /32DLY0 = 2

M1 = /4DLY1 = 0

M2 = /32DLY2 = 2

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IN+

IN–

OUT0SEL

OUT1SEL

OUT2SELSYNC

100Ω

IN+

IN–100Ω

10kVCC

10k

10k

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

300MHz, CLOCK

37.5MHz, SYSREF

300MHz, CLOCK

M0 = /4DLY0 = 0

M1 = /32DLY1 = 2

M2 = /4DLY2 = 0

OUT0SEL

OUT1SEL

OUT2SELSYNC

10kVCC

10k

10k

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

37.5MHz, SYSREF

300MHz, CLOCK

37.5MHz, SYSREF

M0 = /32DLY0 = 2

M1 = /4DLY1 = 0

M2 = /32DLY2 = 2

1µF1µF

BVC0

SYNC

1µF

BB

0.47µF

1µF

1µF

CMACMBCMCTB

CP

TUNE

EZSyncSYNC PULSE

WIDTH ≥ 1ms

EZSyncSYNC PULSE SKEW

BETWEEN PARTS ≤ 10µs

The LTC6950 in Stage 1 is set to distribution only mode, by powering down the PLL circuitry (PDPLL = 1) and connecting the Follower-Driver Signal to the LTC6950 VCO input. Below is a summary of the LTC6950 register settings for Figure 6:

SM1[5] = SM2[5] = 0x20 PDPLL = 1 IBIAS0 = IBIAS1 = IBIAS2 = IBIAS3 = 1 M0 = M1 = M2 = M3 = M4 = 1 PD_DIV4 = 1

All other registers setting can be set to 0.

For further expansion it is possible to choose larger fanout buffers or add additional fanout buffer stages. When designing a multi-stage clock distribution network, take into account the additive properties of

• channel to channel skew

• additive jitter (Equation 7)


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ParallelSync Design Overview

ParallelSync is a method to synchronize multiple LTC6951’s running in parallel driven by a common reference clock fanout buffer network. Synchronization is achieved through a common reference aligned sync signal.

Synchronizing the LTC6951 outputs in Figure 7 involves sending a common sync signal that meets setup and hold time requirements to the common reference signal. This architecture provides the ability to synchronize all LTC6951 outputs with a known latency to the sync signals falling edge. The ability to synchronize all LTC6951 outputs at a

known time is useful in systems that require known and precise initial placement of clock edges.

In Figure 7, the LTC6954-4 is the common reference clock fanout network. The LTC6954-4 was selected to configure OUT0 and OUT1 as LVDS signals to the LTC6951 refer-ence inputs. The LTC6954 LVDS outputs optimize power consumption and LTC9651 performance when compared to the LTC6954's PECL and CMOS options. In addition, OUT2 can be configured as a CMOS signal to drive the D flip-flop circuitry. The LTC6954 OUT2- CMOS output was selected, instead of the OUT2+ CMOS output, because OUT2- can be inverted which adds some SYNC to REF timing flexibility.

figure 7. ParallelSync Design Example 1 – Two lTC6951s

100MHzREFERENCE

SYNCPULSE

SYNC TO REF TIMINGSYNC HELD HIGH A MINIMUM OF 1ms

• • •

• • •

LTC6951 #1

LTC6951 #2

LTC6954-4

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REFERENCE DISTRIBUTION

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

IN+

IN–

OUT0SEL

OUT1SEL

OUT2SEL

50Ω

10kVCC

VCP+ VVC0+

5V

V+

3.3V

10k

10k

10Ω

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

250MHz, CLOCK

/1

/1

/1

REF–

REF+

100Ω

56.2Ω

56.2Ω

1.5nF1nF

68nF

1µF

1µF1µF

1µF

BVC0

SYNC

1µF

BB

0.47µF

1µF

1µF

CMACMBCMCTB

CP

TUNE

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

VCP+ VVC0+

5V

V+

3.3V 10Ω

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

250MHz, CLOCK

REF–

REF+

100Ω

56.2Ω

56.2Ω

1.5nF1nF

68nF

1µF

BVC0

SYNC

1µF

BB

0.47µF

1µF

1µF

CMACMBCMCTB

CP

TUNE

LTC6951REF INPUT

LTC6951SYNC PULSE

CK

D Q

CK

D Q

parallelSync dESIgn ExamplE


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The section titled ParallelSync Design Rules summarizes the ParallelSync design rules. The section titled Paral-lelSync Design Example 1 section provides the design process used to develop the block diagram in Figure 7. For a comparison of synchronization methods, this example mirrors the frequency plan of the EZParallelSync Design Example. Layout Recommendations discusses matching line lengths to minimize skew between parts. The section titled Synchronization Routines, provides initial power-up, power-down and resynchronization sequences. The Ex-pandable Solution section discusses how the block diagram in Figure 7 can expand to support more LTC6951 devices. ParallelSync Design example 2 provides the DC2226 JESD204B frequency plan. The DC2226 is a demo board that includes the LTC6951 and two JESD ADCs (LTC2123).

lTC6951 ParallelSync Design Rules

1. LTC6951 register settings:

a. RAO = 1 (enabled)

b. SN = 1

c. SR = 1

2. Meet LTC6951 data sheet SYNC to REF setup and hold times.

ParallelSync Design Example 1

This design example will use the LTC6951Wizard to aid in the design process. Download LTC6951Wizard at http://www.linear.com/LTC6951Wizard.

This example assumes the following list of design inputs.

Reference

fREF = 100MHz

lTC6951s

Four 1GHz clock signals

Six 250MHz clock signals

RDIV = 1

RAO = 1

Delay settings

Align LTC6951 outputs rising edge to LTC6951 reference input rising edge.


Design for low jitter. Minimize the output skew between the LTC6951#1 and LTC6952#2

lTC6951 Setup

Based on the ParallelSync Design Rules and the above design inputs the following steps provide input conditions for the LTC6951Wizard.

Step 1: Design input: assign output frequencies to optimize the LTC6951 fPFD for low jitter.

ParallelSync’s Design Rule 1 sets RAO = 1, making OUT0 part of the PLL feedback loop. As a result OUT0 affects the LTC6951 PLL’s PFD frequency (fPFD). Maximizing the LTC6951 fPFD allows for a wider loop bandwidth and as a result optimal jitter performance. For more details, refer to the LTC6951 data sheet sections Reference Source Considerations and In-Band Output Phase Noise. The LTC6951 maximum fPFD frequency is 100MHz.

Referring to the LTC6951 data sheet, Equations 8 and 9 can be derived when RAO6951 = 1.

f6951.PFD =

f6951.OUT0NDIV6951

(8)

f6951.PFD =

fREFRDIV6951

(9)

Equations 8 and 9 can be rearranged as follows:

f6951.OUT0fREF

=NDIV6951RDIV6951

(10)

Substituting the desired output clock frequencies and known fREF = 100MHz into Equation 45, determine the least common multiple for NDIV and RDIV. Then use Equations 8 and 9 to determine fPFD.

If f6951.OUT0 = 250MHz:

250MHz/100MHz = NDIV6951/RDIV6951

NDIV6951 = 5

RDIV6951 = 2

fPFD = 50MHz

If f6951.OUT0 = 1GHz:

1GHz/100MHz = NDIV6951/RDIV6951

NDIV6951 = 10

RDIV6951 = 1

fPFD = 100MHz




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Assigning f6951.OUT0 to 1GHz allows for the largest fPFD and as a result minimizes the LTC6951 output jitter.

OUT4 is an LVDS output with an 800MHz maximum out-put frequency and higher jitter than the other LTC6951 CML outputs. The rest of the output frequencies can be assigned as desired.

f6951#1.OUT0 = f6951#2.OUT0 = 1GHz f6951#1.OUT1 = f6951#2.OUT1 = 1GHz f6951#1.OUT2 = f6951#2.OUT2 = 250MHz f6951#1.OUT3 = f6951#2.OUT3 = 250MHz f6951#1.OUT4 = f6951#2.OUT4 = 250MHz

Note: The EZParallelSync Design Example uses the same output frequencies as this ParallelSync Design Example 1. However, because EZParallelSync Design Rule 1 limits OUT0’s frequency selection a smaller fPFD (50MHz) was used. The smaller fPFD resulted in the EZParallelSync example having ~10fs degraded jitter performance when compared to this example. The frequencies in these two examples were chosen specifically to highlight this dif-ference. Depending on the desired reference and output frequencies, differences in fPFD between these two syn-chronization methods may or may not result. This note is directed at the LTC6951, as other Linear Technology PLL/VCOs may not have the LTC6951’s pre-scalar divider architecture. As a result the LTC6951 EZParallelSync Design rule #1 may not apply to other PLL/VCOs.


Based on the LTC6951 data sheet the best jitter performance is obtained by maximizing the LTC6951 ICP current.


Step 3: Design input: minimize the output skew perfor-mance between the LTC6951#1 and LTC6952#2.

The LTC6951 device to device skew is best when the LTC6951 register value FILT = 0.

lTC6951Wizard


The values calculated in Steps 1-3 and conditions provided at the start of this design example are summarized below for a quick reference. These values will be used for inputs to the LTC6951Wizard to calculate the register settings and loop filter values for both LTC6951s in this design example.

LTC6951Wizard inputs for Figure 9:

f6951.REF = 100MHz f6951.OUT0 = 1GHz f6951.OUT1 = 1GHz f6951.OUT2 = 250MHz f6951.OUT3 = 250MHz f6951.OUT4 = 250MHz I6951.CP = 11.2mA NDIV6951 = 10 RDIV6951 = 1 FILT6951 = 0 RAO6951 = 1

Figures 9 and 10 provide the remaining steps necessary to complete the LTC6951 portion of this design. Several steps in these Figures 9 and 10 require the following ad-ditional information.


Refer to Appendix: Model Reference Noise for LTC6951Wizard Simulations, which describes how to import reference noise into the LTC6951Wizard and the impact of reference noise on loop filter calculations and output noise simulations. Example 1 in the appendix cre-ates the reference noise profile for this example.


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Delay setting: DLYX BITS

For this example, the request was made to align the rising edge of the LTC6951 outputs with the rising edge of the LTC6951 reference input. The LTC6951 Wizard automati-cally calculates the DLYX bits based off of Equation 11.

Figure 9, step 2b sets the Delay value = 0. A LTC6951Wizazd Delay value = 0 forces the LTC6951Wizard to calculate the LTC6951 DLYX settings to align the LTC6951 output and reference input rising edges. Figure 10 shows the DLYX bits = 2 based off the wizard calculation. Figure 11 shows that the LTC6951 output and reference inputs rising edges are aligned.

Solving Equation 11 for Dx (DLYX) from the values pro-vided below match the LTC6951Wizard Delay results in Figures 10 and 11.

Dx = Dxi+CEILING 18

N •M0⎛

⎝⎜

⎞

⎠⎟ •N •M0 – 18 (11)

Dxi = 0 (aligns to reference)

18, number of PDIV cycles

N = 5

M0 = 8

Dx = 0+CEILING 18

10 • 2⎛

⎝⎜

⎞

⎠⎟ • 2 •10 – 18

Dx = 2 (DLYX delay settings)

OUTPUT INVERT

LTC6951

CLK+

CLK–

OUTX+

OUTX– 100ΩOINVX

SET OINVX = 0

STANDARD OUTX CONNECTION

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OUTPUT INVERT

LTC6951

CLK+

CLK–

OUTX+

OUTX– 100ΩOINVX

SET OINVX = 1

HARDWARE INVERTED OUTX CONNECTION

figure 8. lTC6951 OInVX STATE

SYNCENX Bits

Ensure the LTC6951 SYNCENX bits are set to a 1 for all signals that require synchronization. Refer to Figure 9, Step 2b.

LTC6951 OINV Bit

Figure 9, step 6 sets the OINVX values for each output. Figure 8 provides a recommendation for OINVX settings based on schematic connections to the device being clock. In this example all LTC6951 outputs will use the Standard OUTX Connection, setting OINVX = 0 (not inverted).




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1. Set ICP = 11.2mA

2. Select Sync tab. See Steps 2a and 2b on far right



5. Set Fout0 = Fout1 = 1000MHz Set Fout2 = Fout3 = Fout4 = 250MHz

6 Set Invert OUTx = No

7. Set FILT = No, check box to lock value


2a. Select STANDALONE and ParallelSync

2b. For each Output, select Synchronized and set Delay = 0

9. Verify R Div = 1 and N Div matches previous calculation



12. Under File menu, select Save Settings. File name = ParallelSync (see far right)


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15. Under File menu, select Save Settings. File name = ParallelSync

figure 10. lTC6951Wizard Setup Continued


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figure 11. lTC6951Wizard Delay Settings

16. Select Loop Design

17. Select Scope Plot

18. Select Plot

1 RDIVCYCLE

20 PDIVCYCLES

2 PDIVCYCLES

18 PDIVCYCLES

DLYX = 0

1 RDIV Cycle = M0 • N • R PDIV CyclesM0=2, N=10, R = 11 RDIV Cycle = 20 PDIV Cycles


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lTC6954 Setup


Skew in reference signals will result in skew between LTC6951s. Therefore, it is recommended to design the reference distribution device for low skew and match trace lengths on the reference signals during board layout.

With ParallelSync, the LTC6951 outputs are phase aligned to the LTC6951’s internal reference divider’s output. As a result, a fanout buffer can be used for reference distri-bution. In this example the LTC6954 was chosen for the fanout buffer with dividers set to 1.

M06954 = 1

M16954 = 1

M26954 = 1

According to the LTC6954 data sheet, best skew per-formance is obtained when either one of following two conditions are met:

• Condition 1: all LTC6954 output divider settings equal 1

• Condition 2: all LTC6954 output divider settings are >1.

Step 5: Verify LTC6954 output to LTC6951 connection.

It is required to choose an identical reference schematic from Figure 12 for both LTC6951s. This ensures both LTC6951 PLLs align to the same reference edge.

For this example, both LTC6951 reference inputs can use Figure 12’s Hardware Inverted Reference Connection with a LTC6954 divide value equal to 1. Figure 12’s Sync to Ref Timing Circuit should use a divide value of 1. It is also recommended to use the LTC6954 OUTX- CMOS output, which has an output invert bit, for the Sync to Ref Timing Circuit.

DELAY

LTC6954-4

OUTX+

OUTX– 100ΩOINVX

DIVIDE

/1

LT6951 INPUT

REFERENCEINPUT

STANDARD REFERENCE CONNECTION

OUTX+

OUTX– 100Ω

HARDWARE INVERTED REFERENCE CONNECTION

SYNC

CK

D Q

CK

D Q

REF+

REF–

LTC6951

DELAY

LTC6954-4

OINVX

DIVIDE

/1

LT6951 INPUT

REFERENCEINPUT

REF+

REF–

LTC6951

OUTX+

OUTX–

SYNC TO REF TIMING CIRCUIT

USING PREFERRED REFERENCE SCHEMATIC

DELAY

LTC6954-4

OINVX

DIVIDE

/1

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LT6954 OUTX–

(CMSINV = 1)

LT6954 OUTX–

(CMSINV = 0)

LT6951SYNC INPUT

LT6951SYNC INPUT

LT6951REFERENCE INPUT

REFERENCEINPUT

SYNCLTC6951

• • •

• • •

• • •

figure 12. Reference Distribution Connection


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figure 13. Trace length Matching

L#1.OUT4

L#2.OUT4

LREF#1

LREF#2

LTC6951 #1

LTC6954

REFIN

LTC6951 #2

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

CLK+

CLK–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

REF–

REF+

CSSCLKSDATA

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L#1.OUT3

L#1.OUT0

L#1.OUT1

L#1.OUT2

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

CLK+

CLK–REF–

REF+

CSSCLKSDATA

L#2.OUT3

L#2.OUT0

L#2.OUT1

L#2.OUT2


OUTXSEL Pin Settings OUT0SEL = VCC (LVDS) OUT1SEL = VCC (LVDS) OUT2SEL = GND (CMOS)

Register Settings

When all LTC6954 divide values equal 1, the LTC6954 DLYX and SYNCEN settings have no effect phase relationship and can be set to any value.

SYNCEN06954 = 1 M06954 = 1 DEL06954 = 0 PDIV06954 = 0 PDOUT06954 = 0


SYNCEN26954 = 1 M26954 = 1 DEL26954 = 0 PDIV26954 = 0 PDOUT26954 = 0 CMSINV26954 = 0

layout Recommendations

To minimize LTC6951 output skew match electrical trace lengths as shown in Equations 12 and 13 (refer to Figure 13).

LREF#1 = LREF#2 (12)

L#1.OUTX = L#2.OUTX (13)


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2. If MX6954 > 1, Toggle LTC6954 SYNC pin (minimum 1ms)


4. Calibrate all LTC6951 VCOs

5. Send SYNC pulse to LTC6951 Sync pins (see LTC6951 SYNC Pulse Width section)

Power-down:



Resynchronization(post power-down):

1. Power Up LTC6954 (PDALL = 0)

2. Power Up LTC6951 (PDALL = 0)



lTC6951 Sync Pulse Width

The requirements for the sync pulse width depend on the LTC6951 Rdivider setting. When the LTC6951 internal reference divider equals 1, the latency from the reference input to any output will be consistent. In this configuration the sync pulse width should be greater than 1ms.

When R = 1

Sync Pulse Width > 1ms (12)

When the LTC6951 internal reference divider is > 1, the latency from the reference input to any output has R dif-ferent possibilities depending on where SYNC falls relative to R DIV. By creating a SYNC pulse exactly REFCYCLES wide, all outputs will begin with the same latency to the reference input every time a synchronization event occurs. Equations 14 and 15 calculate the SYNC pulse width that allows for consistent latency, when R > 1.

When R>1

REFCYCLES = R • Ceiling(1ms • fREF/R) +1 (14)

Sync Pulse Width = REFCYCLES/fREF (15)

Refer to the LTC6951 data sheet for more details.

Expandable Solution

The ParallelSync solution is infinitely expandable. As shown in Figure 14 the ParallelSync design example 1 can be repeated by adding an additional fanout buffer to distribute the reference.

Distributing a reference aligned synchronization signal in a multi-stage fanout architecture across multiple daugh-ter cards is an additional challenge with the ParallelSync architecture. Each stage in the reference fanout network has a propagation delay that should be accounted for. Figure 14 accounts for propagation delays by retiming the sync signal in both reference distribution stages.

The LTC6950 in Stage 1 is set to distribution only mode, by powering down the PLL circuitry (PDPLL = 1) and connecting the reference to the LTC6950 VCO input. It is also recommended to use the LTC6950 LVCM– CMOS output, which has an output invert bit, for the Sync to Ref timing circuit.

Below is a summary of the LTC6950 register settings for Figure 14:

SM1[5] = SM2[5] = 0x20 PDPLL = 1 IBIAS0 = IBIAS1 = IBIAS2 = IBIAS3 = 1 M0 = M1 = M2 = M3 = M4 = 1

All other registers setting can be set to 0.

For further expansion it is possible to choose larger fanout buffers in Stages 1 or 2 and/or cascade additional reference distribution stages between Stage 1 and Stage 2. When designing a multi-stage reference distribution network, take into account the additive properties of


• noise floor at frequency offsets less than the LTC6951 loop filter’s pass-band.


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figure 14. ParallelSync Expandable Solution

LTC6950DISTRIBUTIONONLY MODE

STAGE 1REFERENCE DISTRIBUTION

TO CARD #1

TO CARD #2

TO CARD #3

TO CARD #4

PECL0+

PECL0–

PECL1+

PECL1–

PECL2+

PECL2–

PECL4+

PECL4–

LVCM+

LVCM–

/1

/1

/1

/1

CK

D Q

CK

D Q

TO CARD #1

TO CARD #2

TO CARD #3

TO CARD #4

SYNCDISTRIBUTION

SYNCPULSE

DAUGHTER CARD #1

DAUGHTER CARD #2

DAUGHTER CARD #3

DAUGHTER CARD #4

100MHzREFERENCE

LTC6951 #1

LTC6951 #2

LTC6954-4

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STAGE 2REFERENCE DISTRIBUTION

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

IN+

IN–

OUT0SEL

OUT0SEL

OUT2SEL

10kVCC

VCP+ VVC0+

5V

V+

3.3V

10k

10k

10Ω

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

250MHz, CLOCK

/1

/1

/1

REF–

REF+

100Ω

56.2Ω

56.2Ω

1.5nF1nF

68nF

1µF

BVC0

SYNC

1µF

BB

0.47µF

1µF

1µF

CMACMBCMCTB

CP

TUNE

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

VCP+ VVC0+

5V

V+

3.3V10Ω

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

250MHz, CLOCK

REF–

REF+

100Ω

56.2Ω

56.2Ω

1.5nF1nF

68nF

1µF

BVC0

SYNC

1µF

BB

0.47µF

1µF

1µF

CMACMBCMCTB

CP

TUNE

CK

D Q

CK

D Q

100Ω


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JESd204B parallelSync dESIgn ExamplE 2

This example provides CLOCK and SYSREF signals to two ADC’s and one FPGA. The selection of LTC6951 CLOCK and SYSREF output pins were selected to ease board layout and to optimize performance.

board layout

On the DC2226, an LTC6951 was placed next to each ADC to minimize the ADC CLOCK and SYSREF trace lengths. Minimizing the trace lengths between the LTC6951 and the ADC has the effect of increasing the reference trace length between the LTC6954 and the LTC6951, or vice

figure 15. ParallelSync Design Example 2 – JESD204b

100MHzREFERENCE

SYNCPULSE

SYNC TO REF TIMINGSYNC HELD HIGH A MINIMUM OF 1ms

• • •

• • •

LTC6951 #2U10

LTC6951 #1U13

LTC6954-4

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OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

IN+

IN–

OUT0SEL

OUT0SEL

OUT2SEL

50Ω

10kVCC

VCP+ VVC0+

5V

V+

3.3V

10k

10k

10Ω

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

125MHz, FPGA CLOCK

15.625MHz, ADC2 SYSREF

2GHz, MUTED

250MHz, ADC2 CLOCK

PWRDN

/1

/1

/1

REF–

REF+

100Ω

56.2Ω

56.2Ω

1.5nF1nF

68nF

1µF

1µF1µF

1µF

BVC0

SYNC

1µF

BB

470nF

1µF

1µF

CMACMBCMCTB

CP

TUNE

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

VCP+ VVC0+

5V

V+

3.3V10Ω

15.625MHz, FPGA SYSREF

15.625MHz, ADC1 SYSREF

2GHz, MUTED

250MHz, ADC1 CLOCK

PWRDN

REF–

REF+

100Ω

56.2Ω

56.2Ω

1.5nF1nF

68nF

1µF

BVC0

SYNC

1µF

BB

470nF

1µF

1µF

CMACMBCMCTB

CP

TUNE

LTC6951REF INPUT

LTC6951SYNC PULSE

CK

D Q

CK

D Q

JESD204b ParallelSync Design Overview

Figure 15 demonstrates the LTC6951 in JESD204B subclass 1 ParallelSync configuration. The frequencies chosen mirror that of the DC2226 JESD204B subclass 1 demonstration board which includes two LTC2123 JESD204B ADCs.

The reference and synchronization sections of this design are identical to the ParallelSync Design Example 1. Design information for these sections will refer back to the relevant section in ParallelSync Design Example 1.


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versa. Longer trace lengths typically increase the prob-ability of unwanted signals or noise coupling onto the signal of interest.

Unwanted noise or signals coupling onto either the LTC6951 reference input or LTC6951 clock output can create random or deterministic clock jitter, respectively. Random ADC clock jitter degrades the ADC SNR, where deterministic jitter degrades the ADC SFDR. For this reason the LTC6951 reference input and LTC6951 clock outputs are both critical signals. However, when making trade-offs on trace length, it is recommended to treat the ADC clock signal as the more sensitive signal for the following reasons:

filtering: LTC6951 reference inputs signals are naturally filtered by the existing narrowband PLL loop filter. The PLL loop filter does not affect LTC6951 output to output skew. Conversely, unwanted signals coupling onto an ADC clock can only be removed by adding a clock filter, which increases BOM cost and degrades clock to clock skew.

Impedance Matching: PLL reference frequencies are typically slower than ADC clock frequencies. Slower fre-quencies ease impedance matching and signal integrity concerns.

lTC6951 Output Selection

With ParallelSync, The LTC6951 OUT0 path is part of the PLL feedback loop (RAO = 1), which disables OUT0’s delay functionality. Since not all LTC6951 outputs were needed and OUT0 delay feature is disabled, the OUT0 output buf-fer is powered down. The OUT0 divider network remains enabled to support the PLL feedback loop. Refer to the LTC6951 data sheet for more information regarding how the RAO bit affects the OUT0 operation. In addition, by not selecting OUT0 as a device clock this allowed for more flexibility in selecting the LTC6951 fPFD. Careful selection of fPFD optimizes the LTC6951 jitter performance. This point will be discussed more in the design example.

The LTC6951’s OUT4 is an LVDS output. The other four LTC6951 outputs are CML outputs. LTC6951#2’s and LTC6951#1’s OUT4 pins were selected for the FPGA CLOCK and SYSREF signal, because the FPGA accepted LVDS signal levels.

The remaining three CML LTC6951 outputs, OUT1, OUT2, and OUT3 are identical in operation and performance. A CML output was chosen to drive the ADC Clock inputs, because the LTC6951 CML outputs have lower jitter than the LTC6951 OUT4 LVDS output. OUT1 and OUT3 were chosen to drive the ADC CLOCK and SYSREF due to layout considerations. OUT2 is closer to the LTC6951 reference input. Since not all outputs were required in this example, OUT2 was powered down to limit board coupling concerns between OUT2 and the LTC6951 reference input.

The section titled ParallelSync Design Example 2 section provides the design process used to develop the block diagram in Figure 15. Layout Recommendations discusses matching line lengths to minimize skew between parts. The section titled Synchronization Routines, provides initial power-up, power-down and resynchronization sequences. The Expandable Solution section discusses how the block diagram in Figure 7 can expand to support more LTC6951 devices.

ParallelSync Design Example 2



Reference

fREF 100MHz

lTC6951s

f6951#1.OUT1 = 250MHz

f6951#1.OUT3 = 15.625MHz

f6951#1.OUT4 = 15.625MHz

f6951#2.OUT1 = 250MHz

f6951#2.OUT3 = 15.625MHz

f6951#2.OUT4 = 125MHz

RAO = 1

Delay settings Best performance


Design for low jitter. Minimize the output skew between the LTC6951#1 and LTC6952#2




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lTC6951 Setup

Based on the ParallelSync Design Rules and the above design inputs, the following steps provide input conditions for the LTC6951Wizard.

Step 1: Design input: determine OUT0’s frequency to optimize the LTC6951 fPFD for low jitter.

ParallelSync’s Design Rule 1 sets RAO = 1, making OUT0 part of the PLL feedback loop. As a result OUT0 affects the LTC6951 PLL’s PFD frequency (fPFD). Maximizing the LTC6951 fPFD allows for a wider loop bandwidth and as a result optimal jitter performance. For more details, refer to the LTC6951 data sheet sections Reference Source Considerations and In-Band Output Phase Noise. The LTC6951 specified maximum fPFD frequency is 100MHz.

The LTC6951Wizard automatically calculates the optimal OUT0 frequency in Figures 18 and 20, when PwrDown is chosen for OUT0.

f6951#1.OUT0 = PwrDown f6951#2.OUT0 = PwrDown


Refer to Step 2 in the ParallelSync Design Example 1


Refer to Step 3 in the ParallelSync Design Example 1

lTC6951Wizard


The values calculated in Steps 1-3 and conditions provided at the start of this design example are summarized below for a quick reference. These values will be used for inputs

to the LTC6951Wizard to calculate the register settings and loop filter values for both LTC6951s in this design example.

LTC6951Wizard inputs for Figures 18 and 19:

f6951.REF = 100MHz f6951#1.OUT0 = PwrDown f6951#1.OUT1 = 250MHz f6951#1.OUT3 = 15.625MHz f6951#1.OUT4 = 15.625MHz

f6951#2.OUT0 = PwrDown f6951#2.OUT1 = 250MHz f6951#2.OUT3 = 15.625MHz f6951#2.OUT4 = 125MHz

FILT6951 = 0 RAO6951 = 1

Figures 18 to 24 provide the remaining steps necessary to complete the LTC6951 portion of this design. Several steps in these figures require the following additional information.



Delay setting: CLOCK DLYX Bits

For this example, the request was made to set delays values of the LTC6951 outputs for best performance. Less than optimal performance can result if the reference frequency mixes with an LTC6951 output frequency on the board. An initial attempt to avoid mixing produce will set the LTC6951 outputs delays so that the LTC6951 input reference edges and the LTC6951 output clock edges oc-cur at different times.


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Step 3a: Determine the LTC6951 PDIV cycles that coin-cide with the LTC6951 OUT1’s 250MHz clock rising and falling edges.

Clock _CYCLE =fPIV

fOUT1

Clock _CYCLE =2GHz

250MHz

Clock _CYCLE = 8 PDIV Cycles

(16)

Clock Rising Edge = 8 PDIV Cycles • x + Dxi (17)

Clock Falling Edge = 8 PDIV Cycles • x + 4 + Dxi (18)

Where,

x is any integer,

Dxi adjusted delay setting, when Dxi = 0 the output aligns to the reference.

Step 3b: Determine the number of LTC6951 PDIV cycles with respect to LTC6951 Reference input frequency.

REF _CYCLE =

fPIV

fREF (19)

REF _CYCLE =

2GHz100MHz

REF_CYCLE = 20 PDIV cycles

REF Rising Edge = 20 PDIV Cycles • y (20)

REF Falling Edge = 20 PDIV Cycles • y + 10 (21)

Step 3c: Determine the LTC6951 PDIV cycles that coincide with the LTC6951 OUT3’s 250MHz SYSREF rising edge.

SYSREF _CYCLE =

fPIV

fREF (22)

SYSREF _CYCLE =

2GHz15.625MHz

SYSREF_CYCLE = 128 PDIV cycles

SYSREF Rising Edge = 128 PDIV Cycles • x + Dxi (23)

To maximize JESD204B SYSREF to CLOCK setup and hold times the SYSREF signals rising edge should occur on the falling edge of the CLOCK signal.

Step 3d: Determine Dxi by plotting results as shown below in Figure 16

Dxi = 1 or Dxi = 3 meet the desired criteria of not having the clock edges coincide with the reference edges. A Dxi = 3 for the Clock and Dxi = 7 for the SYSREF were chosen for Step 10 in Figure 20.

PDIV CYClES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

REF EDGES ↑ ↓ ↑ ↓ ↑

CLK EDGES (Dxi=0) ↑ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑

CLK EDGES (Dxi=1) ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓

CLK EDGES (Dxi=2) ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓

CLK EDGES (Dxi=3) ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓

SYSREF EDGES (Dxi=7) ↑

figure 16. lTC6951 Reference, Clock and SYSREf Edge location


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Step 3e: Verify the LTC6951Wizard DLYx calculation.

The LTC6951 Wizard automatically calculates the DLYX bits based off of Equation 24. This same equation is found in the LTC6951 data sheet.

Solving Equation 24 for Dx (DLYX) from the values provided below match the LTC6951Wizard Delay results in Figure 22.

Dx = Dxi+CEILING 18

N •M0⎛

⎝⎜

⎞

⎠⎟ •N •M0 – 18 (24)

Dx = DLYx value in LTC6951 SPI map

Dxi = adjusted delay setting, a 0 aligns output rising edge to reference rising edge

18, number of PDIV cycles

N = 20

M0 = 1

For Clock:

Dxi = 3

Dx = 3+CEILING 18

20 •1⎛

⎝⎜

⎞

⎠⎟ • 20 •1– 18

Dx = 5 (Clock DLYX delay settings)

For SYSREF:

Dxi = 7

Dx = 7+CEILING 18

20 •1⎛

⎝⎜

⎞

⎠⎟ • 20 •1– 18

Dx = 9 (SYSREF DLYX delay settings)

figure 17. lTC6951 OInVX STATE

OUTPUT INVERT

LTC6951

CLK+

CLK–

OUTX+

OUTX– 100ΩOINVX

SET OINVX = 0


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OUTPUT INVERT

LTC6951

CLK+

CLK–

OUTX+

OUTX– 100ΩOINVX

SET OINVX = 1


SYNCENX Bits


LTC6951 OINV Bit

Figure 20, step 13 sets the OINVX values for each output. Figure 17 provides a recommendation for OINVX settings based on schematic connections to the device being clock. In this example all LTC6951 outputs will use the Standard OUTX Connection, setting OINVX = 0 (not inverted).




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7. Calculate number of PDIV cycles per REF CYCLEPDIV CYCLES = Fpd/Fref PDIV CYCLES = 2GHz/100MHz PDIV CYCLES = 20

8 Calculate number of PDIV cycles per CLOCK CYCLEPDIV CYCLES = Fpd/Fout1 PDIV CYCLES = 2GHZ/250MHz PDIV CYCLES = 8

9. Use PDIV CYCLES to calculate CLOCK and SYSREF Delays (refer to Delay Calculations)

figure 18. ParallelSync Design Example 2, DC2226 U13

2a. Select STANDALONE and ParallelSync

2b. Initially, for each Output, select Synchronized and set Delay = 0

1. Set ICP = 11.2mA




5. Set Fout0 = PwrDown Fout1 = 250MHz Fout2 = PwrDown Fout3 = 15.625MHz Fout4 = 16.625MHz


figure 19. ParallelSync Design Example 2, DC2226 U13 (Continued)


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10. Set CLOCK Delay =3 and SYSREF Delay = 7 (calculated from Step 9)

11. Set Invert OUTX = No




14 Double click Opt Loop BW (Noise) to copy to Loop BW


16. Under File menu, select Save Settings. File name = ParallelSyncEX2_U13 (see far right)


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19. Under File menu, select Save Settings. File name = ParallelSyncEX2_U13


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20. Modify System Tab to create LTC6951#2 (U10) settings. Set OUT4 register’s values to: DLY4 = 5 /M4 = 16

21. Under File menu, select Save Settings. File name = ParallelSyncEX2_U10


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1 RDIVCYCLE

20 PDIVCYCLES

18 PDIVCYCLES

DLYX = 0

DLY1 = 5 PDIV CYCLESDLY3 = 9 PDIV CYCLES

1 RDIV Cycle = M0 • N • R PDIV CyclesM0 = 1, N = 20, R = 11 RDIV Cycle = 20 PDIV Cycles

figure 24. ParallelSync Design Example 2 (Continued)



24. Select Plot


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lTC6954 Setup




Refer to Step 4 to Step 6 in the ParallelSync Design Example 1


Refer to the Layout Recommendation section in the ParallelSync Design Example 1








Power-down after JESD204b alignment sequence is complete:

1. Power down LTC6951 SYSREF OUTX (MCX = 2)

(NOTE: power down LTC6951 output, but leave LTC6951 output divider enable to avoid resynchronizing all clocks)

If JESD204 requires re-alignment:

1. Power up LTC6951 SYSREF OUTX (MCX = 1)

lTC6951 Sync Pulse Width

Refer to the LTC6951 Sync Pulse Width section in the ParallelSync Design Example 1. For this example the LTC6951 RDIV = 1.

Expandable Solution

The ParallelSync solution is infinitely expandable, refer ParallelSync Design Example 1 Section titled Expandable Solution and Figure 14 in for more details


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figure 25. EZParallelSync Design Example – Two lTC6951s

EZParallelSync Design Overview

EZParallelSync is a simple way to synchronize multiple LTC6951’s running in parallel driven by a common refer-ence clock divider/distribution network. Synchronization is easily achieved through SPI commands. The LTC6951 SYNC pin can be used in lieu of the SPI command.

In Figure 25, the LTC6954 is the common reference clock divider/distribution network. The LTC6954 acts as an exter-nal reference divider (RDIV) to provide two LTC6951s with

phase aligned reference frequencies. The external RDIV allows the LTC6951s internal RDIVs to equal 1. Setting the LTC6951 RDIV = 1 allows for output phase alignment across multiple LTC6951s to a common reference edge.

This architecture provides the ability to synchronize any LTC6951 to any other LTC6951 at any time. As a result if any LTC6951 is not used continuously then the un-used LTC6951 can be completely powered down. When needed the powered down LTC6951 can be powered up and resynchronized independently without recalibrating

100MHzREFERENCE

LTC6951 #1

LTC6951 #2

LTC6954-4

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EZSyncSYNC PULSE

WIDTH ≥ 1ms


OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

IN+

IN–

OUT0SEL

OUT2SEL

SYNC

50Ω

10kVCC

VCP+ VVC0+

5V

V+

3.3V

10k

10Ω

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

/2

/2

REF–

REF+

100Ω

80.6Ω

80.6Ω

1.5nF1nF

68nF

1µF

1µF1µF

1µF

BVC0

1µF

BB

470nF

1µF

1µF

CMACMBCMCTB

CP

TUNE

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

VCP+ VVC0+

5V

V+

3.3V10Ω

REF–

REF+

100Ω

80.6Ω

80.6Ω

1.5nF1nF

68nF

1µF

BVC0

CSSCLKSDI

CSSCLKSDI

1µF

BB

470nF

1µF

1µF

CMACMBCMCTB

CP

TUNE

250MHz, CLOCK

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

250MHz, CLOCK

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCKSPI

SYNC

SPISYNC

EZparallelSync dESIgn ExamplE


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the LTC6951 VCO and without performing a full system clock synchronization. This ability to asynchronously synchronize independent LTC6951 with EZParallelSync is also useful in plug and play (hot plug) applications.

This example uses the same fOUT0 and the same fREF for all LTC6951s. A variant of EZParallelSync is EZ204Sync. The EZ204Sync Design Example provides an example where different OUT0 or REF frequencies are used.

The section titled EZParallelSync Design Rules summa-rizes the EZParallelSync design rules. The section titled EZParallelSync Design Example section provides the design process used to develop the block diagram in Figure 25. Layout Recommendations discusses matching line lengths to minimize skew between parts. The section titled Syn-chronization Routines, provides power-up, power-down and resynchronization sequences. The Expandable Solution section discusses how the block diagram in Figure 25 can expand to support more LTC6951 devices.

lTC6951 EZParallelSync Design Rules

When compared to ParallelSync, EZParallelSync has the ad-ditional design rule that the LTC6951 OUT0 pin is assigned to the lowest output frequency per LTC6951. Refer to the LTC6951 data sheet for details related to PDIV and RAO.

1. LTC6951 OUT0 pin assigned to the lowest output fre-quency


a. RDIV = 1

b. RAO = 1 (enabled)

3. X •

f6951# 1.OUT0

f6951# 1.REF=

f6951#N.OUT0

f6951#N.REF (25)

Which can also be written as

X • NDIV6951#1 = NDIV6951#N (26)

Where N can be any integer > 1 and X is an integer. In most cases X = 1.

EZParallelSync Design Example



Reference

fREF = 100MHz

lTC6951s

f6951#1.OUT0 = f6951#2.OUT0 = 250MHz

f6951#1.OUT1 = f6951#2.OUT1 = 1GHz

f6951#1.OUT2 = f6951#2.OUT2 = 1GHz

f6951#1.OUT3 = f6951#2.OUT3 = 250MHz

f6951#1.OUT4 = f6951#2.OUT4 = 250MHz

RDIV = 1

RAO = 1

Delay settings Align LTC6951 outputs rising edge to LTC6951 reference input rising edge.


Design LTC6951 for low jitter. Minimize the output skew between the LTC6951#1 and LTC6952#2

Part Placement and Routing

The LTC6954 and both LTC6951s will be placed on the top side of the board. For the most direct routing connect:• LTC6954 OUTX+ to LTC6951 IN–

• LTC6954 OUTX– to LTC6951 IN+

This creates a reference signal inversion at the LTC6951 inputs.

lTC6951 Setup

Based on the EZParallelSync Design Rules and the above design inputs, the following steps provide input conditions for the LTC6951Wizard.

Step 1: Design Rule 1 verification

The first design rule is met since the slowest output fre-quency, 250MHz, is assigned to OUT0.


To ensure Design Rule 2’s RDIV = 1 requirement is met, calculate M06954, M26954, and both LTC6951’s f6951.REF and NDIV6951 values. M06954 and M26954 refer to the LTC6954 divide value.




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The second design rule states that RDIV6951#1 = 1 and RAO6951 = 1. Referring to the LTC6951 data sheet the following two equations are provided when RAO6951 = 1.

f6951# 1.PFD =

f6951# 1.REF

RDIV6951# 1 (27)

f6951# 1.PFD =

f6951# 1.OUT0

NDIV6951# 1 (28)

Referring to the LTC6954 data sheet the following equa-tion is provided.

f6951# 1.REF =

fREF

M06954 (29)

Since RDIV6951#1 = 1, Equations 27, 28, and 29 can be rearranged as follows:

NDIV6951# 1 =

M06954 • f6951# 1.OUT0

fREF (30)

Substituting the known values for fREF = 100MHz and f6951#1.OUT0 = 250MHz into Equation 30 results in

NDIV6951# 1 =

M06954 • 250MHz

100MHz (31)

Which simplifies to

NDIV6951#1 = 2.5 • M06954 (32)

Based on the LTC6951 data sheet, to optimize for the lowest jitter possible f6951#1.PFD should be as large as pos-sible, which allows for a wider bandwidth loop filter. This statement assumes the reference input signal noise level is not limiting the LTC6951’s in-band noise performance. Therefore, solve Equation 32 for the least common integer multiple for NDIV and M0.

NDIV6951#1 = 5

M06954 = 2

Next solve Equation 29 and 27.

f6951#1.REF = 50MHz

f6951#1.PFD = 50MHz

Since LTC6951#1 and LTC6951#2 have an identical fre-quency plan.

NDIV6951#1 = NDIV6951#2 = 5

M06954 = M26954 = 2

f6951#1.REF = f6951#2.REF = 50MHz


Based on the results from step 2, Design Rule 3 is met.

f6951#1.OUT0/f6951#1.REF = f6951#2.OUT0/f 6951#2.REF

Step 4: Design input: optimize the LTC6951 for low jitter.

Based on the LTC6951 data sheet, the jitter performance is obtained by maximizing the fPFD frequency (see Step 2) and maximizing the LTC6951 ICP current.


Note: The ParallelSync Design Example #1 uses the same output frequencies as this EZParallelSync Design Example. However, because ParallelSync does not require the low-est output frequency on OUT0 (EZParallelSync Design Rule 1) a larger fPFD (100MHz) could be obtained. The larger fPFD resulted in the ParallelSync example having ~10fs improved jitter performance when compared to this example. The frequencies in these two examples were chosen specifically to highlight this difference. Depending on the desired reference and output frequencies, differences in fPFD between these two synchronization methods may or may not result. This note is directed at the LTC6951, as other Linear Technology PLL/VCOs may not have the LTC6951’s pre-scalar divider architecture. As a result the LTC6951 EZParallelSync Design rule #1 may not apply to other PLL/VCOs.



lTC6951Wizard



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The values calculated in Steps 1 to 5 and conditions pro-vided at the start of this design example are summarized below for a quick reference. These values will be used for inputs to the LTC6951Wizard to calculate the register settings and loop filter values for both LTC6951s in this design example.

LTC6951Wizard inputs for Figure 27:

f6951.REF = 50MHz f6951.OUT0 = 250MHz f6951.OUT1 = 1GHz f6951.OUT2 = 1GHz f6951.OUT3 = 250MHz f6951.OUT4 = 250MHz I6951.CP = 11.2mA NDIV6951 = 5 RDIV6951 = 1 FILT6951 = 0 RAO6951 = 1

Figures 27 and 28 provide the remaining steps necessary to complete the LTC6951 portion of this design. Several steps in Figures 27 and 28 require the following additional information.



Delay setting: DLYX BITS

For this example, the request was made to align the rising edge of the LTC6951 outputs with the rising edge of the LTC6951 reference input. The LTC6951 Wizard automati-cally calculates the DLYX bits based off of Equation 33. This same equation is found in the LTC6951 data sheet.

Figure 27, step 2b sets the Delay value = 0. An LTC6951Wizard Delay value = 0 forces the LTC6951Wizard to calculate the LTC6951 DLYX settings to align the LTC6951 output and reference input rising edges. Figure 28 shows the DLYX bits = 22 based off the wizard calculation. Figure 29 shows that the LTC6951 output and reference inputs rising edges are aligned.

Dx = Dxi+CEILING 18

N •M0⎛

⎝⎜

⎞

⎠⎟ •N •M0 – 18 (33),

Solving Equation 33 from the values shown match the LTC6951Wizard results, shown in Figures 28 and 29.

Dxi = 0 (align to reference) 18, number of PDIV cycles N = 5 M0 = 8

Dx = 0+CEILING 18

5 • 8⎛

⎝⎜

⎞

⎠⎟ • 5 • 8 – 18

Dx = 22 (delay settings)

SYNCENX BITS


LTC6951 OINV Bit

Figure 27, step 7 sets the OINVX values for each output. Figure 26 provides a recommendation for OINVX settings based on schematic connections. In this example all LTC6951 outputs will use the Standard OUTX Connection, setting OINVX = 0 (not inverted).



figure 26. lTC6951 OInVX State

OUTPUT INVERT

LTC6951

CLK+

CLK–

OUTX+

OUTX– 100ΩOINVX

SET OINVX = 0


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OUTPUT INVERT

LTC6951

CLK+

CLK–

OUTX+

OUTX– 100ΩOINVX

SET OINVX = 1



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2a. Select STANDALONE and EZParallelSync

1. Set ICP = 11.2mA


3. Set Fref = 50MHz


5. Set Fout0 = Fout3 = Fout4 = 250MHz Set Fout1 = Fout2 = 1000MHz







12. Under File menu, select Save Settings. File name = EZParallelSync (see far right)


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13. Under File menu, select Save Settings. File name = EZParallelSync

figure 28. lTC6951Wizard Setup Continued


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40 PDIV CYCLES

22 PDIVCYCLES

18 PDIVCYCLES

DLYX = 0

1 REF Cycle = M0 • N • R PDIV CyclesM0 = 8, N = 51 REF Cycle = 40 PDIV Cycles



24. Select Plot

figure 29. lTC6951Wizard Delay Settings


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lTC6954 Setup

Step 6: Design input: minimize the output skew between the LTC6951#1 and LTC6952#2.

The LTC6951 outputs are phase aligned to the reference input. Skew in reference signals will result in skew between LTC6951s. Therefore, it is recommended to match trace lengths on the reference signals during board layout.

According to the LTC6954 data sheet best skew per-formance is obtained when either one of following two conditions are met:

• Condition 1: all LTC6954 output divider settings equal 1

• Condition 2: all LTC6954 output divider settings are >1.

In Step 2 the LTC6954 was design for optimal outputs skew, since Condition 2 was met.

M06954 = 2

M26954 = 2


It is recommended to choose an identical reference sche-matic from Figure 30 for both LTC6951s. This ensures both LTC6951 PLLs align to the same reference edge.

For this example, both reference inputs were required to use Figure 30’s Hardware Inverted Reference Connection. Therefore, set DEL06954 = DEL26954.

If it is desired to connect LTC6951#1 to Figure 30’s Standard Reference Connection and LTC6951#2 to the Hardware Inverted Reference Connection, then the reference inputs will be inverted with respect to each other.

To account for this schematic inversion, invert one of the LTC6954 output signals by delaying one LTC6954 output a ½ cycle using the LTC6954 delay bits (see Table C1). Using the LTC6954 delay registers in this manner is only possible when all LTC6954 divide values are even numbers. Table 2. lTC6954 Register Settings, when Schematic Chooses Different Reference Connections

lTC6954 OUTX

lTC6954 Register Settings

MX DElX

LTC6951: Standard Reference Connection Even Number Y*

LTC6951: Hardware Inverted Reference Connection Even Number

min MX( )2

+ Y*

* Y, integer, same value for all DELX

Step 8: LTC6954 register settings summarized:


PDIV16954 = 1



DELAY

LTC6954-4

OUTX+

OUTX– 100ΩDELX

DIVIDE

MX

LT6951 INPUT

REFERENCEINPUT


OUTX+

OUTX– 100Ω


REF+

REF–

LTC6951

DELAY

LTC6954-4

DELX

DIVIDE

MX

LT6951 INPUT

REFERENCEINPUT

REF+

REF–

LTC6951

AN161 F30

• • •

• • •


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To minimize LTC6951 output skew match electrical trace lengths as shown in Equations 34 and 35 (refer to Figure 31).

LREF#1 = LREF#2 (34)

L#1.OUTX = L#2.OUTX (35)




2. Toggle LTC6954 SYNC pin (minimum 1ms)



5. Toggle all LTC6951 SPI SSYNC bits or SYNC pins (minimum 1ms)

Power down Idle LTC6951:

1. Power down idle LTC6951 (PDALL = 1)

2. Power down LTC6954 OUTX connected to idle LTC6951 (PD_OUTX = 1)

Resynchronization of Idle LTC6951:

1. Power up idle LTC6951 (PDALL = 0)

2. Power up LTC6954 OUT X connected to idle LTC6951 (PD_OUTX = 0)

3. Toggle LTC6951 SPI SSYNC bit or SYNC pin (minimum 1ms)

Expandable Solution

The EZParallelSync solution is infinitely expandable. As shown in Figure 32, the EZParallelSync design example can be repeated by adding an EZSync CONTROLLER to distribute the reference.

For ease of synchronization, in Figure 32 the divide by two function was moved from Stage 2 to the LTC6950 in Stage 1. As a result, Stage 2 can now use a low noise fanout buffer such as the LTC6957.

For further expansion, it is possible to cascade additional reference distribution stages between Stage 1 and Stage 2. When designing a multi-stage reference divider/distribu-tion network, take into account the additive properties of:


• noise floor at frequency offsets less than the LTC6951 loop filter’s pass-band. Refer to Appendix: Model Refer-ence Noise for LTC6951Wizard Simulations.

If some LTC6951’s can power down during operation, then selecting reference distribution parts with the ability to power down individual outputs can save additional power.


L#1.OUT4

L#2.OUT4

LREF#1

LREF#2

LTC6951 #1

LTC6954

REFIN

LTC6951 #2

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

CLK+

CLK–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

REF–

REF+

CSSCLKSDATA

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L#1.OUT3

L#1.OUT0

L#1.OUT1

L#1.OUT2

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

CLK+

CLK–REF–

REF+

CSSCLKSDATA

L#2.OUT3

L#2.OUT0

L#2.OUT1

L#2.OUT2


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figure 32. EZParallelSync Expandable Solution


STAGE 1REFERENCE DIVIDEANDDISTRIBUTION

TO CARD #1

TO CARD #2

TO CARD #3

TO CARD #4

PECL0+

PECL0–

PECL1+

PECL1–

PECL2+

PECL2–

PECL4+

PECL4–

LVCM+

LVCM–

/2

/2

/2

/2

DAUGHTER CARD #1

DAUGHTER CARD #2

DAUGHTER CARD #3

DAUGHTER CARD #4

EZSyncSYNC PULSE

WIDTH ≥ 1ms

100MHzREFERENCE

LTC6951 #1

LTC6951 #2

LTC6957-2

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STAGE 2FANOUT BUFFER

SYNC

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

IN+

IN–

FILTA

FILTB

10k

VCP+ VVC0+

5V

V+

3.3V

10k

10Ω

OUT1+

OUT1–

OUT2+

OUT2–

250MHz, CLOCK

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

REF–

REF+

100Ω

80.6Ω

56.2Ω

1.5nF1nF

68nF

1µF

BVC0

CSSCLKSDI

1µF

BB

0.47µF

1µF

1µF

CMACMBCMCTB

CP

TUNE

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

VCP+ VVC0+

5V

V+

3.3V10Ω

250MHz, CLOCK

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

REF–

REF+

100Ω

80.6Ω

56.2Ω

1.5nF1nF

68nF

1µF

BVC0

CSSCLKSDI

1µF

BB

0.47µF

1µF

1µF

CMACMBCMCTB

CP

TUNE

100Ω

SPISYNC

SPISYNC


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EZ204Sync Design Overview

EZ204Sync is a subset of EZParallelSync, which is op-timized to provide a method to synchronize JESD204B CLOCK and SYSREF signals with asynchronous SPI SYNC commands to an unlimited number of LTC6951s. The LTC6951 SYNC pin can also be used in lieu of the SPI sync command.

Figure 33 separates the CLOCK and SYSREF signals onto separate LTC6951s. In Figure 33, these are denoted as CLOCK LTC6951 and SYSREF LTC6951. This architecture

requires an external EZSync reference divider/distribution network, such as the LTC6954 shown in Figure 33.

By using an EZSync reference divider, the CLOCK and SYSREF reference phases are phase aligned following an EZSync event. The external reference divider (RDIV) allows for the LTC6951s’ internal RDIV to equal 1. Setting the LTC6951 RDIV = 1 allows for output phase alignment across multiple LTC6951s to a common reference edge.

This architecture provides the ability to synchronize any LTC6951 to any other LTC6951 at any time. As a result,

figure 33. EZ204Sync Design Example – Two lTC6951s

100MHzREFERENCE

CLOCKLTC6951

SYSREFLTC6951

LTC6954-4

AN161 F33

SYNC PULSEWIDTH ≥ 1ms


50MHz

3.125MHz

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

IN+

OUT0SEL

OUT2SELSYNC

10kVCC

VCP+ VVC0+

5V

V+

3.3V

10k

10Ω

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

M0 = /2DLY0 = 1

M0 = /32DLY2 = 16

REF–

REF+

100Ω

80.6Ω

80.6Ω

1.5nF1nF

68nF

1µF

BVC0

1µF

BB

470nF

1µF

1µF

CMACMBCMCTB

CP

TUNE

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

VCP+ VVC0+

5V

V+

3.3V 10Ω

REF–

REF+

100Ω

2050Ω0.33nF

8.2nF

1µF

BVC0

CSSCLKSDI

CSSCLKSDI

1µF

BB

470nF

1µF

1µF

CMACMBCMCTB

CP

TUNE

250MHz, CLOCK

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

15.625MHz, SYSREF

15.625MHz, SYSREF

15.625MHz, SYSREF

15.625MHz, SYSREF

15.625MHz, SYSREFSPI

SYNC

SPI SYNC

FIRST CLOCK EDGEAFTER SYSREF

2ns/DIV

OUT0: 250MHzOUT0: SYSREF

OUT2: 1GHzOUT2: SYSREF

OUT1: 1GHzOUT1: SYSREF

OUT4: 250MHzOUT4: SYSREFOUT3: 250MHzOUT3: SYSREF

AN161 F33a

EZ204Sync dESIgn ExamplE


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if any LTC6951 is not used continuously, then the un-used LTC6951s can be completely powered down. When needed, the powered down LTC6951s can be powered up and resynchronized independently without recalibrating its VCO and without performing a full system clock syn-chronization. This ability to asynchronously synchronize independent LTC6951s with EZ204Sync is useful for JESD204B subclass 1 applications.

The section titled EZ204Sync Design Guidelines sum-marizes the EZ204Sync design rules. The section titled EZ204Sync Design Example section provides the design process used to develop the block diagram in Figure 33. Layout Recommendations discusses matching line lengths to minimize skew between parts. The section titled Syn-chronization Routines provides the initial power-up, power-down and resynchronization sequences. The Expandable Solution section discusses how the block diagram in Figure 33 can expand to support more LTC6951 devices.

EZ204Sync Design Rules

When compared to ParallelSync, EZ204Sync has the ad-ditional design rule that the LTC6951 OUT0 pin is assigned to the lowest output frequency per LTC6951. Refer to the LTC6951 data sheet for details related to PDIV and RAO.

1. LTC6951 OUT0 pin assigned to the lowest output fre-quency per LTC6951


a. RDIV = 1

b. RAO = 1 (enabled)

3. X •

fSYS6951.OUT0fSYS6951.REF

=fCLK6951.OUT0fCLK6951.REF

(36)

Which can also be written as

X • NDIVSYS6951 = NDIVCLK6951 (37)

Where X is an integer. In most cases X = 1.

EZ204Sync Design Example



Reference

fREF = 100MHz

ClOCK-lTC6951

fCLK6951.OUT0 = 250MHz

fCLK6951.OUT1 = 1GHz

fCLK6951.OUT2 = 1GHz



RDIV = 1

RAO = 1

SYSREf-lTC6951

fSYS6951.OUTX =

fCLK6951.OUT016

(38)

RDIV = 1

RAO = 1


Design CLOCK LTC6951 for low jitter.Design SYSREF LTC6951 for low power.Optimize skew between CLOCK LTC6951 to SYSREF LTC6951 outputs.

Part Placement And Routing

The LTC6954 and both LTC6951s will be placed on the top side of the board. For the most direct routing connect:• LTC6954 OUTX+ to LTC6951 IN–

• LTC6954 OUTX– to LTC6951 IN+

This creates a reference signal inversion at the LTC6951 inputs.

Clock lTC6951 Setup

Based on the EZ204Sync Design Rules and the above design inputs the following steps provide input conditions for the LTC6951Wizard.


The first design rule is met since the slowest clock fre-quency, 250MHz, is assigned to OUT0.

Step 2: Design Rules 2 and 3 verification

Calculate fCLK6951.REF, M06954, and NDIVCLK6951 to meet Design Rule 3.

The second design rule states that RDIV = 1 and RAO = 1. Referring to the LTC6951 data sheet the following two equations are provided when RAO = 1.

fCLK6951.PFD =

fCLK6951.REFRDIVCLK6951

(39)




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fCLK6951.PFD =

fCLK6951.OUT0NDIVCLK6951

(40)

Referring to the LTC6954 data sheet, the following equa-tion is provided.

fCLK6951.REF =

fREFM06954

(41)

Since RDIVCLK6951 = 1, Equations 39, 40, and 41 can be rearranged as follows:

NDIVCLK6951 = M06954 •

fCLK6951.OUT0fREF

(42)

Substituting the known values for fREF = 100MHz, fCLK6951.OUT0 = 250MHz into Equation 41 results in

NDIVCLK6951 = M06954 •

250MHz100MHz

(43)

Which simplifies to

NDIVCLK6951 = 2.5 • M06954 (44)

Based on the LTC6951 data sheet, to optimize for the lowest jitter possible, fCLK6951.PFD should be as large as possible, which allows for a wider bandwidth loop filter. This statement assumes the reference input signal noise level is not limiting the LTC6951’s in-band noise perfor-mance. Therefore, solve Equation 44 for the least common integer multiple of NDIV and M0.

NDIVCLK6951 = 5

M06954 = 2

Next solve Equation 41.

fCLK6951.REF = 50MHz

Step 3: Design input: optimize the CLOCK LTC6951 for low jitter.

Based on the LTC6951 data sheet the jitter performance is obtained by maximizing the LTC6951 ICP current.


Step 4: Design input: optimize the skew performance between the CLOCK LTC6951 and SYSREF LTC6951.


SYSREf lTC6951 Setup

Step 5: Calculate the SYSREF frequencies, using Equation 38.

fSYS6951.OUTX = 15.625MHz

In other applications there may be more than one SYSREF frequency. If this is the case assign the lowest SYSREF frequency to OUT0 to meet Design Rule 1.

Step 6: Design Rules 2 and 3 verification

Calculate fSYS6951.REF, M26954, and NDIVSYS6951 to meet Design Rules 2 and 3.

Solve Equations 36 and 37 from Design Rule 3 for fSYS6951.REF and NDIVSYS6951, by using known values for fSYS6951.OUT0 = 15.625MHz, fCLK6951.OUT0 = 250MHz, fCLK6951.REF = 50MHz, and NDIVCLK6951 = 5

X •

fSYS6951.OUT0fSYS6951.REF

=fCLK6951.OUT0fCLK6951.REF

(36)

By setting X = 1,

1 • (15.625MHz/fSYS6951.REF) = (250MHz/50MHz)

fSYS6951.REF = 3.125MHz

X • NDIVSYS6951 = NDIVCLK6951 (37)

1 • NDIVSYS6951 = 5

NDIVSYS6951 = NDIVCLK6951 = 5

Rewriting Equation 41 for the SYSREF LTC6951, solve for M2.

M26954 =

fREFfSYS6951.REF

(45)

M26954 = 100MHz/3.125MHz

M26954 = 32

Step 7: Design input: optimize the SYSREF LTC6951 for low power.

SYSREF is only used for the JESD204B alignment rou-tines and is not a high performance clock. Therefore, the SYSREF LTC6951 can be placed in a lower power mode than the CLOCK LTC6951.

Set ISYS6951.CP = 2mA


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lTC6951Wizard

This section demonstrates the LTC6951Wizard’s ability to ease the register setting creation and loop filter design for both the SYSREF LTC6951 and CLOCK LTC6951. Under the LTC6951Wizard’s Help Menu a Help Guide is provided that will aid in understanding the operations performed in this section.

The values calculated in Steps 1 to 7 and conditions pro-vided at the start of this design example are summarized below for a quick reference.

LTC6951Wizard inputs for the SYSREF LTC6951 in Figure 35

fSYS6951.REF = 3.125MHz fSYS6951.OUTX = 15.625MHz ISYS6951.CP = 2mA NDIVSYS6951 = 5 RDIVSYS6951 = 1 FILTSYS6951 = 0 RAOSYS6951 = 1

LTC6951Wizard inputs for the CLOCK LTC6951 in Figure 36

fCLK6951.REF = 50MHz fCLK6951.OUT0 = 250MHz fCLK6951.OUT1 = 1GHz fCLK6951.OUT2 = 1GHz fCLK6951.OUT3 = 250MHz fCLK6951.OUT4 = 250MHz ICLK6951.CP = 11.2mA NDIVCLK6951 = 5 RDIVCLK6951 = 1 FILTCLK6951 = 0 RAOCLK6951 = 1

Figures 35, 36 and 37 provide the remaining steps nec-essary to complete the LTC6951 portion of this design. Several steps in Figures 35 to 37 require the following additional information.


Refer to Appendix: Model Reference Noise for LTC6951Wizard Simulations, which describes how to import reference noise into the LTC6951Wizard and the

impact of reference noise on loop filter calculations and output noise simulations. Examples 2 & 3 in the appendix create the reference noise profile for this example.

SYNCENX BITS

Ensure the CLOCK LTC6951 and SYSREF LTC6951 SYNCENX bits are set to a 1 for all signals that require synchronization. Refer to Figure 35 Step 2b and Figure 36 Step 15b.


Figure 35’s step 11 selected Filter 1 for the SYSREF LTC6951. The simplest filter was selected for board space and cost reasons, because SYSREF jitter performance is not important.

Figure 36’s step 24 selected Filter 2 for the CLOCK LTC6951. Through experimentation Filter 2 was found to be the best option to optimize performance and board space.

LTC6951 OINV Bit

Figure 35, step 6 and Figure 36, step 19 set the OINVX values for each output. The LTC6951 OINV value can be determined by referring to the schematics shown Figure 34. These OINVX settings, along with the DEL[X] settings above, program the LTC6951’s SYSREF rising edge to start a ½ CLOCK cycle before its paired LTC6951 CLOCK’s rising edge.

figure 34. lTC6951 OInVX State

OUTPUT INVERT

LTC6951

OUTX+

OUTX– 100ΩOINVX

WHEN CONNECTED TOCLK: SET OINVX = 1SYSREF: SET OINVX = 0


AN161 F34

OUTPUT INVERT

LTC6951

OUTX+

OUTX– 100ΩOINVX

WHEN CONNECTED TOCLK: SET OINVX = 0SYSREF: SET OINVX = 1


CLK+ ORSYSREF+

CLK– ORSYSREF–

CLK+ ORSYSREF+

CLK– ORSYSREF–


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DELAY Settings

Figure 37, step 28 references Equation 46. Equation 46 calculates DEL[X] in PDIV cycles. The same DEL[x] value will be used for both SYSREF LTC6951 and CLOCK LTC6951 pairs. In Equation 46 the number 18 refers to the number of PDIV cycles when DEL[X] = 0. For more information refer to the LTC6951 data sheet OUTPUT SYNCHRONIZATION section titled Synchronization Events.

DEL[X]= Y •M0SYS6951 – 18+

M0CLK6951M[X]CLK6951

– 1 (46)

where Y is smallest integer that ensures DEL[X]>0.

As shown in Figure 37, step 28

DEL1 = 1 • 128 – 18 + (8/2) – 1 = 113

DEL2 = 1 • 128 – 18 + (8/2) – 1 = 113

DEL3 = 1 • 128 – 18 + (8/8) – 1 = 110

DEL4 = 1 • 128 – 18 + (8/8) – 1 = 110

If Equation 46 calculates a DEL[X] > 255 PDIV cycles (maximum delay setting), try increasing the LTC6951 PDIV value used in Figures 35 and 36. This will create a larger delay range. Repeat the steps in Figures 35 and 36 after the PDIV value is increased (check the box next to PDIV in the LTC6951Wizard Design tab to avoid auto-calculating a new PDIV).

SYSREF LTC6951 ALCEN Bit

Figure 37, step 33 sets the SYSREF LTC6951 ALCEN bit high. If ALCHI or ALCLO are being monitored, then ALCEN is set high to reset the ALC flags during power-down and power-up routines for the SYSREF LTC6951. Refer to the Synchronization Routines section.


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figure 35. lTC6951Wizard: SYSREf lTC6951



1. Set ICP = 2mA


3. Set Fref = 3.125MHz

4. Select All = Fout0

5. Set Fout = 15.625MHz







12. Record M0 Div Value.In this example: M0 Div = 128

13. Under File menu, select Save Settings. File name = SYSREF6951 (see far right)


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figure 36. lTC6951Wizard: ClOCK lTC6951





25. Record all Mx Div values.In this example: M0 Div = 8 M3 Div = M4 Div = 8 M1 Div = M2 Div = 2

26. Under File menu, select Save Settings. File name = CLKREF6951 (see far right)


14.Set ICP = 11.2mA

15.Select Sync tab. See Steps 15a and 15b on far right

16.Set Fref = 50MHz

17.Select All Select

18.Set Fout0 = Fout3 = Fout4 = 250MHz Set Fout1 = Fout2 = 1000MHz

19 Set Invert OUTx = Yes

20.Set FILT = No, check box to lock value

21.Select Compute Params


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figure 37. lTC6951Wizard Delay Settings and System Tab

27. Under File menu, select Load Settings. File name = CLOCK6951

28. Enter DLYX calculated values (see Equation 46)


30 Select System tab to view results

31. Under File menu, Select Save Settings. File name = CLOCK6951

32. Repeat Steps 27 to 31 for File name: SYSREF6951

33. For the SYSREF6951, ensure the ALCEN box is checked before saving

lTC6954 Setup

Step 8: Design input: optimize the skew performance between the CLOCK LTC6951 and SYSREF LTC6951.

According to the LTC6954 data sheet best skew perfor-mance is obtained when all output divider settings are >1, as was determined in Steps 2 and 5 (M06954 = 2, M26954 = 32).

As an aside, if M06954 had been set to 1 and M26954 > 2 than the LTC6954 output skew would have degraded 25ps. One work around to improve this would be to double fREF so M06954 could be set to 2.


The design inputs above required this example to use the Hardware Inverted Reference Connection for the distributed reference signals, see Figure 38. Hardware reference inver-sions create an extra design consideration, because both LTC6954 output reference signals will be synchronized on the falling edge, while the LTC6951 PLL locks to the reference rising edge, also shown in Figure 38.

To account for the hardware reference signal inversion, the LTC6954 output signals should be inverted. To invert the LTC6954 output, delay the LTC6954 outputs a ½


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DELAY

LTC6954-4

OUTX+

OUTX– 100ΩDELX

DIVIDE

MX

CLOCKLT6951 INPUT

REFERENCEINPUT


OUTX+

OUTX– 100Ω


SYNCHRONIZED ON RISING EDGES

SYNCHRONIZED ON FALLING EDGES

REF+

REF–

LTC6951

DELAY

LTC6954-4

DELX

DIVIDE

MX

CLOCKLT6951 INPUT

REFERENCEINPUT

REF+

REF–

LTC6951

• • •

• • •

SYSREFLT6951 INPUT

SYSREFLT6951 INPUT

AN161 F38

• • •

• • •

output cycle using the LTC6954 delay bits. Inverting the LTC6954 outputs with the delay register creates a design constraint because inversion is only possible when the LTC6954 divider value is set to an even number. In this example both M06954 and M26954 are even numbers, which makes inverting the outputs possible with the LTC6954.

As an aside, if M06954 had been set to 1 the LTC6954 output could not be inverted, because the LTC6954 does not have an output inversion bit. To resolve this issue the designer would either need to change to the preferred schematic in Figure 38 or double fREF which allows M06954 to be set to 2.Table 3. Standard Reference Connection

lTC6954 OUTX


MX DElX

To CLOCK LTC6951 Any Y*

To SYSREF LTC6951 Any Y*

*Y, integer, same value for all DELX

Table 4. Hardware Inverted Reference Connection

lTC6954 OUTX


MX DElX

To CLOCK LTC6951 Even Number

MXCLOCK2

+ Y*

To SYSREF LTC6951 Even Number

MXSYSREF2

+ Y*

*Y, integer, same value for all DELX

Both reference signals are inverted for this example, refer to Table 4.

LTC6954.M0 = 2 LTC6954.DEL0 = LTC6954.M0/2 = 1 LTC6954.M2 = 32 LTC6954.DEL2 = LTC6954.M2/2 = 16

Step 10: LTC6954 register settings summarized:


PDIV16954 = 1

SYNCEN06954 = 1 M26954 = 32 DEL26954 = 16 PDIV26954 = 0 PDOUT26954 = PDALLSYS6951


Minimizing SYSREF to CLOCK skew is recommended to ensure setup and hold times are met for proper JESD204B alignment sequence functionality. To minimize skew match electrical trace lengths in the CLOCK and SYSREF paths as shown in Equation 45 (refer to Figure 39).

LREF.CLK + LCLK.OUTX = LREF.SYS + LSYS.OUTX (45)


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LCLK.OUT4

LSYS.OUT4

LREFCLK

LREFSYS

CLOCKLTC6951

LTC6954

REFIN

SYSREFLTC6951

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

CLK+

CLK–

SYSREF+

SYSREF–OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

REF–

REF+

CSSCLKSDATA

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LCLK.OUT3

LCLK.OUT0

LCLK.OUT1

LCLK.OUT2

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

REF–

REF+

CSSCLKSDATA

LSYS.OUT3

LSYS.OUT0

LSYS.OUT1

LSYS.OUT2





2. Toggle LTC6954 SYNC pin (minimum 1ms)



5. Toggle all LTC6951 SPI SSYNC bits or SYNC pins (minimum 1ms)

Power down SYSREF after JESD204b alignment sequence is complete:

1. Power down SYSREF LTC6951 (PDALL = 1)

2. Power down LTC6954 OUT2 (PD_OUT2 = 1)

If JESD204 requires re-alignment:

1. Power up SYSREF LTC6951 (PDALL = 0)

2. Power up LTC6954 OUT2 (PD_OUT2 = 0)

3. Toggle SYSREF LTC6951 SPI SSYNC bit or SYNC pin (minimum 1ms)

Expandable Solution

The EZ204Sync solution is infinitely expandable. As shown in Figure 40 the EZ204Sync design example can be re-peated by adding an EZSync CONTROLLER to distribute the reference to multiple LTC6954s.

For further expansion it is possible to cascade additional reference distribution stages between Stage 1 and Stage 2. Refer to the EZSync Design Example for more details.

When designing a multi-stage reference divider/distribu-tion network, take into account the additive properties of


• noise floor at frequency offsets less than the CLOCK LTC6951 loop filter’s pass-band. Refer to Appendix: Model Reference Noise for LTC6951Wizard Simulations.

If some LTC6951’s can power down during operation, then selecting reference distribution parts with the ability to power down individual outputs can save additional power.


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figure 40. EZ204Sync Expandable Solution


STAGE 1EZSync CONTROLLER


TO CARD #1

TO CARD #2

TO CARD #3

TO CARD #4

PECL0+

PECL0–

PECL1+

PECL1–

PECL2+

PECL2–

PECL4+

PECL4–

/1

/1

/1

/1

TO CARD #1

TO CARD #2

TO CARD #3

TO CARD #4

DAUGHTER CARD #1

DAUGHTER CARD #2

DAUGHTER CARD #3

DAUGHTER CARD #4

EZSyncSYNC PULSE

WIDTH ≥ 1msSYNC

FOR FURTHER EXPANSION1. REPLACE LTC6954 WITH LTC69502. CASCADE MORE REFERENCE DISTRIBUTION

STAGES BETWEEN STAGE 1 AND STAGE 2

100MHzREFERENCE

CLOCKLTC6951

SYSREFLTC6951

LTC6954-4

AN161 F40

STAGE 2EZSync FOLLOWER


50MHz

3.125MHz

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

IN+

IN–

OUT0SEL

OUT2SEL

SYNC

10kVCC

VCP+ VVC0+

5V

V+

3.3V

10k

10Ω

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

250MHz, CLOCK

250MHz, CLOCK

250MHz, CLOCK

1GHz, CLOCK

1GHz, CLOCK

M0 = /2DLY0 = 1

M0 = /32DLY2 = 16

REF–

REF+

100Ω

80.6Ω

80.6Ω

1.5nF1nF

68nF

1µF

BVC0

1µF

BB

470nF

1µF

1µF

CMACMBCMCTB

CP

TUNE

OUT4+

OUT4–

OUT3+

OUT3–

OUT0+

OUT0–

OUT1+

OUT1–

OUT2+

OUT2–

VCP+ VVC0+

5V

V+

3.3V10Ω

15.625MHz, SYSREF

15.625MHz, SYSREF

15.625MHz, SYSREF

15.625MHz, SYSREF

15.625MHz, SYSREF

REF–

REF+

100Ω

2050Ω0.33nF

68nF

1µF

BVC0

1µF

BB

470nF

1µF

1µF

CMACMBCMCTB

CP

TUNE

100Ω

EZSync SYNC PULSE SKEWBETWEEN PARTS <10µs

CSSCLKSDI

CSSCLKSDI

SPISYNC

SPISYNC

VCO


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Reference noise

Noise profiles of different reference oscillators can change the calculated results of the loop filter bandwidth and LTC6951 jitter performance. Significant changes in these results occur when the reference oscillator noise floor is greater than the LTC6951’s normalized in-band noise (see Figure 41). In-band noise refers to the noise at offset frequencies less than the loop filters bandwidth. Refer to the LTC6951 data sheet for more information on reference noise characteristics.

JITTER(fsRMS) LOOP BW(kHz) 547 28 132 194 90 307

REF #1REF #2CCHD–575

OFFSET FREQUENCY (MHz)1k 10k 100k 1M 10M 100M

–160

–150

–140

–130

–120

–110

–100

–90

–80

PHAS

E NO

ISE

(dBc

/Hz)

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figure 41. Comparing lTC6951Wizard Results with Different Reference Profiles

appEndIx: modEl rEfErEncE noISE for ltc6951Wizard SImulatIonS

figure 43. Importing Reference noise Profiles into lTC6951Wizard

1. Select “Import Noise Data, Ref Noise”

2. Select appropriate file

3. Check “Use Imported Ref Noise”

figure 42. lTC6951Wizard Reference noise file format

When designing loop filters and simulating jitter perfor-mance with the LTC6951Wizard, it is recommended to import the noise profile of the desired reference network for best results. Figures 42 and 43 provide the informa-tion required to import a reference noise file into the LTC6951Wizard. The remainder of this appendix provides information and examples to aid in estimating the phase noise of a reference distribution network. The examples in this appendix are based off the reference distribution networks provided in the LTC6951 Sync Manual’s design examples.


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figure 44. Reference Distribution

FAN-OUT BUFFER


REFERENCE

AN161 F44

Distributed Reference noise

A distributed reference’s phase noise is the product of the reference phase noise and the additive phase noise of the fanout buffer.

not available, Equation 48 scales the phase noise from the nearest available frequency to the desired frequency.

PNY(X) = PN Y–DS(X) – 20 •LOG

fY–DSfREF

⎛

⎝⎜

⎞

⎠⎟

(48)

Where:

fY-DS, carrier frequency of phase noise curve (PNY-DS)

fREF, desired reference frequency at LTC6951 refer-ence input

PNY, phase noise at fREF

PNY-DS, phase noise at fY-DS provided in reference’s data sheet or distribution IC’s data sheet

X, offset frequency in Hz

Example 1: Distributed Reference (ParallelSync)

Estimate the reference phase noise curve to import into LTC6951Wizard using Crystek’s CCHD-575 100MHz reference and the LTC6954-4 as the LVDS fanout buffer.

Step 1: Refer to vendor’s data sheets for phase noise curves provided in table below.

Offset frequency (Hz)

CCHD-575 100MHz (dbc/Hz)

lTC6954-4 122.88MHz

(dbc/Hz)

10 –90 –140

100 –121 –148

1k –143.5 –156

10k –155 –161

100k –162 –162

1M –166 –162

10M –168 –162

100M –168 –162

Step 2: Use Equation 48 to adjust the LTC6954-4 phase noise profile from 122.88MHz to 100MHz:

PN6954(X) = PN6954 –DS(X) – 20 •LOG 122.88MHz

100MHz⎛

⎝⎜

⎞

⎠⎟

PN6954(X) = PN6954-DS(X) – 1.8

Equation 47 calculates the estimated total phase noise of the reference distribution network.

PNTOT(X) = 20 •

LOG 10PNREF(X)

20⎛

⎝⎜

⎞

⎠⎟

⎛⎝⎜

⎞⎠⎟2

+ 10PNDIS(X)

20

⎛

⎝⎜

⎞

⎠⎟

⎛⎝⎜

⎞⎠⎟2

(47)

Where:

PNDIS, Reference distribution IC phase noise at fREF

PNREF, Reference phase noise at fREF

PNTOT, Combined PNDIS and PNREF phase noise at fREF

X, offset frequency in Hz

To minimize the fanout buffer phase noise contribution, choose a fanout buffer whose additive in-band phase noise is 6dB lower than the in-band reference phase noise. In most cases the out-of-band phase noise can be neglected, since the PLL’s loop filter removes out-of-band noise.

Low noise reference and fanout buffer data sheets usually provide phase noise plots at specific carrier frequencies. From these phase noise plots it is possible to estimate the combined phase noise profile of the reference and fanout buffer. If phase noise plots at the desired frequency are


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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.



lTC6954-4 100MHz (dbc/Hz)

10 –90 –141.8100 –121 –149.81k –143.5 –157.810k –155 –162.8100k –162 –162.81M –166 –163.810M –168 –163.8100M –168 –163.8

Step 3: Calculate the total reference distribution network phase noise using the values in Step 2 with Equation 47.

Offset frequency

(Hz)


lTC6954-4 100MHz (dbc/Hz)

PnTOT 100MHz (dbc/Hz)

10 –90 –141.8 –90100 –121 –149.8 –1211k –143.5 –157.8 –143.3

10k –155 –162.8 –154.3100k –162 –162.8 –159.81M –166 –163.8 –161.8

10M –168 –163.8 –162.4100M –168 –163.8 –162.4

Step 4: Create an LTC6951Wizard reference input file (see Figure 42) from data in the Offset Frequency and PNTOT columns in Step 3.

Divided And Distributed Reference noise

Selecting a reference divide and distribution IC has the same concerns as selecting a fanout buffer. Additional noise effects with this architecture due to aliasing can be observed as the divider value increases. As a result the accuracy of the following examples may degrade with larger divide values.

Example 2: Divided And Distributed Reference (EZParallelSync and EZ204Sync ClOCK6951)

Estimate the reference phase noise curve to import into LTC6951Wizard using Crystek’s CCHD-575 100MHz ref-erence and the LTC6954-4 as the LVDS reference divide/distribution IC. The LTC6954-4 divider will be set to 2 to create a 50MHz reference at the LTC6951 input.

Step 1: Refer to vendor’s data sheets for phase noise curves provided in table below



lTC6954-4 30.72MHz

(122.88MHz/4) (dbc/Hz)

10 –90 –140100 –121 –1521k –143.5 –16110k –155 –166100k –162 –1661M –166 –16610M –168 –166100M –168 –166

Step 2: Use Equation 48 to adjust the CCHD-575 and LTC6954-4 phase noise profiles to 50MHz

CCHD-575:

PNCCHD(X) = PNCCHD−DS(X) – 20 •LOG 100MHz

50MHz⎛

⎝⎜

⎞

⎠⎟

PNCCHD(X) = PNCCHD-DS(X) - 6

LTC6954-4:

PN6954(X) = PN6954−DS(X) – 20 •LOG 30.72MHz

50MHz⎛

⎝⎜

⎞

⎠⎟

PN6954(X) = PN6954-DS(X) + 4.2


CCHD-575 50MHz

(dbc/Hz)

lTC6954-4 50MHz

(dbc/Hz)10 –96 –135.8100 –127 –147.81k –149.5 –156.810k –161 –161.8100k –168 –161.81M –172 –161.810M –174 –161.8100M –174 –161.8

figure 45. Reference Divide and Distribution

FAN-OUT BUFFER

REFERENCE DIVIDEAND DISTRIBUTION

REFERENCE /N

/N

/N

/NAN161 F45


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LT 0317 • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 2017

Step 3: Calculate the total reference distribution network phase noise using the values in step 2 with Equation 47.

Offset frequency

(Hz)

CCHD-575 50MHz

(dbc/Hz)

lTC6954-4 50MHz

(dbc/Hz)

PnTOT 50MHz

(dbc/Hz)10 –96 –135.8 –96

100 –127 –143.8 –126.91k –149.5 –151.8 –148.8

10k –161 –156.8 –158.4100k –168 –157.8 –160.91M –172 –157.8 –161.4

10M –174 –157.8 –161.5100M –174 –157.8 –161.5


Example 3: Divided and Distributed Reference (EZ204Sync SYSREf6951)

Estimate the reference phase noise curve to import into LTC6951Wizard using Crystek’s CCHD-575 100MHz ref-erence and the LTC6954-4 as the LVDS reference divide/distribution IC. The LTC6954-4 divider will be set to 32 to create a 3.125MHz reference at the SYSREF LTC6951 input.

Step 1: Refer to vendor’s data sheets for phase noise curves provided in table below.



lTC6954-4 30.72MHz

(122.88MHz/4) (dbc/Hz)

10 –90 –140100 –121 –1521k –143.5 –16110k –155 –166100k –162 –1661M –166 –16610M –168 –166100M –168 –166

Step 2: Use Equation 48 to adjust the CCHD-575 and LTC6954-4 phase noise profiles to 3.125MHz

CCHD-575:

PNCCHD(X) = PNCCHD−DS(X) – 20 •LOG 100MHz

3.125MHz⎛

⎝⎜

⎞

⎠⎟

PNCCHD(X) = PNCCHD-DS(X) – 30.1

LTC6954-4

PN6954(X) = PN6954−DS(X) – 20 •LOG 30.72MHz

3.125MHz⎛

⎝⎜

⎞

⎠⎟

PN6954(X) = PN6954-DS(X) -19.9


CCHD-575 3.125MHz (dbc/Hz)

lTC6954-4 3.125MHz (dbc/Hz)

10 –120.1 –159.9100 –151.1 –171.91k –173.6 –180.910k –185.1 –185.9100k –192.1 –185.91M –196.1 –185.910M –198.1 –185.9100M –198.1 –185.9

Step 3: Calculate the total reference distribution network phase noise using the values in step 2 with Equation 47.

Offset frequency

(Hz)

CCHD-575 3.125MHz (dbc/Hz)

lTC6954-4 3.125MHz (dbc/Hz)

PnTOT 3.125MHz (dbc/Hz)

10 –120.1 –159.9 –120.1100 –151.1 –171.9 –151.11k –173.6 –180.9 –172.9

10k –185.1 –185.9 –182.5100k –192.1 –185.9 –184.91M –196.1 –185.9 –185.5

10M –198.1 –185.9 –185.6100M –198.1 –185.9 –185.6


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