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ANALOG ELECTRONICS II

FET DC BIASINGFET DC BIASING

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ANALOG ELECTRONICS II - BEE2233 FKEE UMP

Learning Objectives

1

2

Describe various configuration of FET biasing1

Analyze various configuration of FET biasing.2

Upon completion of the chapter the student

should be able to:

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Introduction

In FET, relationship betweeninput and output are not linearthat will sketched an output thatpresenting a curve compared toBJT where it is linear.

Graphical approach will be usedto examine the dc analysis forFET because it is most popularlyused rather than mathematicalapproach

The input of BJT and FETcontrolling variables are thecurrent and the voltage levelsrespectively

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Overview

Common FET Biasing Circuits

JFETFixed Bias

Self-Bias

Voltage-Divider Bias Depletion-Type MOSFET

Self-Bias

Voltage-Divider Bias Enhancement-Type MOSFET

Feedback Configuration

Voltage-Divider BiasANALOG ELECTRONICS II - BEE2233 FKEE UMP

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General Relationships

For all FETs:

For JFETs and Depletion-Type MOSFETs:

For Enhancement-Type MOSFETs:

AIG

0SD

II =

2

P

GSDSSD )

V

V(1II =

2)(TGSD

VVkI =

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Fixed-Bias Configuration

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

VS=0V

VGS

= -VGG

VGS

=VG

- VS

So:V

G=V

GS

VDS

=VD

-V

SSo: V

D=V

DS

Using KVL: VDS

+ IDR

D- V

DD. = 0

VDS

= VDD

- IDR

D

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Investigating the input loop

IG=0A, therefore

VRG=IGRG=0V

Applying KVL for the input loop, -VGG-VGS=0

VGG=-VGS

It is called fixed-bias configurationdue to VGG is a fixed power supply so

VGS is fixedThe resulting current, 2)1(

P

GS

DSSD

V

VII =

t t t

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nvest gat ng t e grap ca

approach..

Using below tables, wecan draw the graph

The intersection of these points isknown as quiescent point/operating

point

VGS ID

0 IDSS

0.3VP IDSS/2

0.5 IDSS/4

VP 0mA

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Bear in mind

Measured value in the circuit isdefined as the quiescent values

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Example

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

Solution:

VGSQ , IDQ, VDS ,VD, VG ,VS.

VGSQ

= -2V

IDQ

= 5.625mA

VDS

= VDD

- IDR

D= 4.75V.

VDS

=VD

-V

SSo: V

D=V

DS=4.75V.

VGS

=VG

- VS

So:V

G=V

GS= - 2V

VS=0V

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Example

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

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Self-Bias Configuration

What is the differences between self bias configuration and fixed-bias

configuration?

Why when analyzing dc analysis the resistor RG will be replaced by a short

circuit equivalence?

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Self-Bias Calculations

For the indicated input loop:

To draw or sketch and analyzing the graphical approach of this configuration,

To solve this equation select an ID < IDSS and use the component value for RS.

Plot this point: ID and VGS and draw a line from the origin of the axis to this point.

Next plot the transfer curve using IDSS and VP (VP = VGSoff in specification sheets) and a

few points such as ID = IDSS/4 and ID = IDSS/2 etc.

Where the first line intersects the transfer curve is the Q-point.

Use the value of ID at the Q-point (IDQ) to solve for the other voltages:

SDGSRIV =

RDDDSDSD

SDS

DSDDDDS

VVVVV

RIV

RRIVV

=+=

=

+= )(The output loop:

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Defining Q-point

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Check your understanding..

Find IDQ, VGSQ and IDSS

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Check your understanding..

Find ID and VDS

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