1
Analog to digital and digital to analog convertersanalog converters
A/D converter D/A converter
ADC DAC
a2d d2a
Number bases
Decimal, base 10, numbers 0 - 9, ,
Binary, base 2, numbers 0 and 1
Oktal, base 8, numbers 0 - 7
Hexadecimal, base 16, numbers 0 – 9 and A - F
2
The structure of a decimal number
Integer number
0123 1061041031022346
Number with decimals
3-2-1-0 1071051081055.857
Scaling factor
Scaling factor
The structure of a hexadecimal number
Integer number
012 16A16216992A
Number with fractions
3-2-1-0 16616B16D1655.DB6
Scaling factor
16616B16D1655.DB6
Scaling factor
3
The structure of a binary number
891011 21202021101000101001
Integer number
891011 21202021 1010 0010 1001
012 2120211011101 1101
4567 20212020
Number with fractions
0123 20212021 Scaling factor
2120211011 101.1101
-43-2-1- 21202121
8-7-6-5- 21212021
Scaling factor
Conversion between bases
Decimal to hexadecimal
1610A10
1610146
162346
161022
1629
16146
99909
LSD, bit 0
Next bit, bit 1
Next bit bit 2
Hexadecimalbase
161099
160
16
1610 92A2346
Next bit, bit 2
Stop when zero
4
Conversion between bases cont.
222932346
Decimal to octal
LSD bit 028
2938
58536
8293
4844
836
LSD, bit 0
Next bit, bit 1
Next bit, bit 2
Octal base
810 44522346
4840
84 Next bit, bit 3
Stop when zero
Conversion between bases cont.
0011732346 115861173 00293586
Decimal to binaryBinary base
02
11732
2
5862
02
932
121146
2293 0
2073
2146 1
2136
273
02018
236 0
209
218 1
214
29
210 1010001010012346
0202
24 0
201
22 1
210
21
Stop when zero
5
Conversion between bases cont.Hexadecimal to binary
216 1101101000113AD
One hexadecimal digit = four binary bits
Word length
8 bits = byte (char)
16 bits = word (short, short integer, some times integer)
32 bits = long word or double word
(long, long integer, some times integer)
64 bits = long long wordDepending on compiler
6
Floating point numbers
IEEE75431 30 23 22 0
S Exponent, E Mantissa, M
31 30 23 22 0
1.M21N 127ES 255E0
Sign bit 38126 101,82numberSmallest
3823127 103.4222numberLargest
Fixed point
• Integer values
0123 2a2a2a2a0123
• Fractional numbers
4321 2b2b2b2b -43-2-1- 2b2b2b2b4321
7
Negative numbers
Sign bitSign bit
Fractional number with sign bit
-43-2-1- 2b2b2b2bsign4321
Two´s complement
2121 valuevaluevaluevalue
2´s complement LSBtooneadd11100101bitsallinvert0001101026 2210
11100110
1
11100101
2210101010 000110100010011026382638
10
22
1200001100
11100110
001001101110011000100110
8
General A/D- and D/A-quantities
n2Nn bits gives different values2Nn bits gives different values
Resolution [Volts]2
U
N
UΔ
nmaxmax
11or n2
1
N
1
Unipolar and bipolar converters
Out
Unipolar Bipolar
2n/2-1
In
-Umax (1-2-(n-1))·Umax
/2-2n/2
9
Conversion error, SQNR
UU
log20Δ
Ulog20
levelerrormaximal
levelmaximallog20SQNR
max
max10max1010unipolar
Unipolar
N22levelerrormaximal max
1n61n6.022log1n202log20
22UU
log20 101n10
nmax
max10
Conversion error, SQNRBipolar
2U
log202U
log20amplitudemaximal
log20SQNR
max
10
max
1010
N2U
log20
2Δ
log20levelerrormaximal
log20SQNRmax
bipolar
n6n6.022logn202log20
22U
2U
log20 10n10
nmax
max
10
Number of bits 8 12 16 20 24SQNR [dB] 48 72 96 120 144SQNR [dB] 48 72 96 120 144
Truncation error
10
Demonstration
Logarithmic convertercompander
A- and µ-law companding
0.4
0.5
0.6
0.7
0.8
0.9
1
µ-law, µ=255
A-law, A=87.56
µ p g
Europe
USA
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
0.1
0.2
0.3
11
Operational amplifiers
High input impedance
Low input impedance
High amplification
Comparator
+
Ui
-
Uref
Uin
Uout
positiveUUU
negativeUUU
outrefin
outrefin
12
Comparator, compare to zero
+
-
Uin
Uout
positiveU0U
negativeU0U
outin
outin
Comparator cont.
positiveUUU
negativeUUU
outin2in1
outin2in1
13
Inverting amplifier
Virtual ground
in1
2out
2
out
1
in21 U
R
RU
R
U0
R
0UII
Summing amplifierThe virtual ground makes the input signals independent
in,22
3in,1
1
3out
3
out
2
in,2
1
in,1321 U
R
RU
R
RU
R
U0
R
0U
R
0UIII
14
Non-inverting amplifier
High input g pimpedance
in1
2
1
21out U
R
R1
R
RRU
Buffer
+
Uin
Uout-
inout UU
15
Buffer cont.
outload UU sourcein UU
Buffer cont.
16
General amplifier symbol.
Differential amplifier
in21
2in1
43
21
1
4out U
R
RU
RR
RR
R
RU
17
Differential amplifier cont.Only one resistance value
in2in1out UUU
Differential amplifier cont.
R
Uin
Uout+
-
R
R
RDifferential
input
18
Integrating amplifier
Ut
CR
UU in
out
D/A-convertersResistance ladder converter
Voltage span
MU
X
Voltage levels
Voltage span
Analog output
Binary control signal
Digital input
19
Current summing D/AOne bit
2
U
2
UU max
1max
LSBout,
Current summing D/A
Two bits
4
U
2
UU max
2max
LSBout,
UUU max
1max
1bitout 2211bitout,
20
Current summing D/A
Four bits
-
R
-Uref
D0
16R
D1
8R
D2
4R
D3
2R
I I/2 I/4 I/8
Uout+
R-2R ladder D/AOne bit
Constant current
R
U
R2
U
R2
UI refrefref
R2
U
2
II reff
2
U
2
URIΔ max
1max
ff
21
R-2R ladder D/ATwo bitsConstant current
R-2R ladder D/AFour bits
Constant current
-
RfD0
2R
-Uref
2R2R
I/8
RI
I/16I/4I/2
I/2 I/4 I/8 I/16RR
D1D2D3
2R2R
Uout+
22
Smoothing filter
0 6
0.8
1
D/A-converted signal
0 0.2 0.4 0.6 0.8 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Time
Am
plit
ud
e
0.2
0.4
0.6
0.8
1
Smoothed DAC signal
de
0 0.2 0.4 0.6 0.8 1
-1
-0.8
-0.6
-0.4
-0.2
0
Time
Am
plit
ud
Demonstration
23
A/D convertersFlash converterVoltage span
Analog input
Deco
ding
ne
tReference levels
Analog input
Digital output
A/D convertersFlash converter cont.
40 refU
24refref UU
Interval Bits from comparators
Binary word
000 00
001 01
011 10
4
3
2refref UU
refref U
U
4
3
011 10
111 11
24
Up-counting ADC
Analog input Uin
+
-
D/A converter
Start conversion
n bits
Digital output
Comparator
CounterStart conversion
Conversion ready
g a ou pu
Up-counting ADC cont.
25
Up-counting ADC cont.
Limitations
● Large variation in conversion timeThe conversion time depends onthe level of the input voltage
● Unpredictable conversion time
Up-counting ADC cont
Analog input UiAnalog input Uin
+
-
D/A converter
n bits
Comparator
CounterStart conversion
Conversion ready
Digital output
26
ADC using successive approximation
ADC cont.We test bit by bit starting with MSB and tests if the voltagegiven by that bit should be part of the result
UVoltage
UVoltage
UVoltage
UVoltage
UVoltage
U Umax
Uin
Umax
Uin
Umax
Uin
Umax
Uin
Umax
Uin
U
4
Umax
8
Umax
16
Umax
Analog input value
1011
The conversion will take as many clock cyclesas there are bits in the binary word
TimeTimeTimeTimeTime2
Umax
27
Single-slope integrating ADC cont.
tCR
Uref
The counter value is proportional to the vlotage level
Single-slope integrating ADC
S
UU
+
Analog input U
+
-R
C
Comparator
Integrator
-Uref
Stopconversion
t
CR
Ut
CR
UU refref
out
-Analog input Uin
Control logic Counter
Start/stopcount
n bits
Digital output
Clock
28
Dual-slope integrating ADC
Dual-slope integrating ADC cont.
in tU
UVoltage
refin
1Phase tCR
U
tCR
UUU ref
1Phase2Phase
Variable slope Fixed slope
Uin
RCUref
RC
Phase 1Fixed interval tref
Phase 2Variable interval tx
Time
29
Aliasing
Sampling cont.
Sampling theorem:For faithful reproduction of the sampledsignal the sampling frequency has to bemore than twice the highest signal frequencyg g q y
Fsampling > fsignal, max
30
Sampling cont.
Cut off frequency
OversamplingCut off frequency
31
Demonstration
Sample & Hold
High input impedance
Low output impedance
Low discharge of capacitor
32
Sample & Hold cont.
1
Sampled signal with hold circuits
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Am
plit
ud
e
0 0.2 0.4 0.6 0.8 1
-1
-0.8
-0.6
Time
1
Sampled signal with track and hold circuit
Sample & Hold cont.
-0 4
-0.2
0
0.2
0.4
0.6
0.8
1
Am
plit
ud
e
0 0.2 0.4 0.6 0.8 1
-1
-0.8
-0.6
0.4
Time
33
Sigma-delta modulator
Sigma-delta modulators and noise
Noise shapingNoise shaping
34
Demonstration
ADC with multiplexed inputs
tsA
nalo
g in
put
35
ADC with multiplexed inputs cont.
● Maximal sampling frequency withsingle channel maxs,f
● Maximal sampling frequency with
N channels N
f maxs,
N
Angle decoders
Incremental decoders
Direction detectionNo direction detection
36
Angle decoders cont.
Absolute decoders
Angle decoders cont.Absolute decoders
Decimal Bit 2 Bit 1 Bit 0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
37
Angle decoders cont.Absolute decoders cont.
Bit 2 Bit 1 Bit 0 Decimal Correct/False
0 1 1 3 Correct
0 1 0 2 False
1 1 0 6 False
1 0 0 4 Correct
Angle decoders cont.Absolute decoders cont.
Gray codingDecimal coding
Decimal Bit 2 Bit 1 Bit 0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
Decimal Bit 2 Bit 1 Bit 0
0 0 0 0
1 0 0 1
2 0 1 1
3 0 1 0
4 1 1 0
5 1 0 1
6 1 1 0
7 1 1 1
5 1 1 1
6 1 0 1
7 1 0 0
More than one bit change value Only one bit changes value
38
Voltage to frequency converters
Converter specifications
• Voltage spanR l ti• Resolution
• Accuracy• Conversion time (ADC)• Settling time (DAC)• Offset error• Offset error• Amplification (scale factor) error• Linearity error
39
Converter specifications cont.Offset error
Converter specifications cont.Amplification (scale factor) error
2n-1
Out
1In
0
(1-2-n)·Umax0 2-n·Umax
40
Converter specifications cont.Linearity error
Skew in parallel communication
Bit 0Bit 0
Bit 1
Bit 2
Skew
Bit 3
