IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO. 3, AUGUST 1979 161

Analog-to-Digital Conversion Based on aVoltage-to-Frequency Converter

J. M. VANDEURSEN AND J. A. PEPERSTRAETE

Abstract-In this paper we discuss a method of analog-to-digital con-version based on a voltage-to-frequency converter (VFC). The basicprinciple of a VEC circuit is given in order to derive the exact relation-ship between the characteristics of the output pulse train and the inputvoltage. We illustrate this theoretical analysis with an example of asimple VFC circuit. The VFC output signal has to be transformed in abinary number proportional to the VFC input voltage. This is done bya digital circuit interfacing the VFC and the computer and a simplecalculation in the computer. Finally, we discuss some elements in-fluencing the quantization error of the conversion.

I. INTRODUCTIONANALOG-TO-DIGITAL conversion can be realized with a

simple and low-cost method based on a voltage-to-fre-quency converter (VFC). The output of a VFC is a digitalpulse train whose repetition rate is proportional to the ampli-tude input of the analog signal (Fig. 1).We only need a simple digital circuit to convert the pulse

train in a binary word. One frequently suggests to perform thisconversion by counting the number of pulses of the VFC out-put signal within a constant period tc, This number id propor-tional to the frequency of the VFC and thus to the analoginput signal. However, with this method, the conversion time,which is equal to the period t C wil become quite long so thatthe sampling rate f, applied on the input signal will be low.For a resolution of n bits, the difference between the maxi-

mum number of pulses and the minimum number has to beequalto2 - I

tc tc =2 n I

t+ t_

with1

t-= f+ = max. frequency of the VFC

= - f = mi. frequency of the VFCor

te (2" 1)t+ *t 1

and

tS-t = 2n 1 t t (21n I t t__

Manuscript received October 13, 1978; revised February 30, 1979.The authors are with the Katholieke Universiteit Leuven, B-3030

Heverlee, Belgium.

Yin

t

vout

I U I II1 1 I IFig. 1. Analog input signal and corresponding output signal of a VFC.

As we know, components of a signal with a frequency higherthan f5/2 are filtered out by samphng. Therefore, we proposean alternative way of converting the output signal of the VFCinto an binary number: we measure the period of the outputsignal by counting the number of pulses of a stable high-frequency clock within I period. A simple calculation in thecomputer which reads this number is sufficient to get a num-ber proportional to the analog signal.The most important requirements to the VFC for this

application are: accuracy, conversion linearity, and tempera-ture stability. Such converters are now available. Some ofthem are realized in an integrated circuit, others need no ex-ternal adjustments to achieve the rated performance. Sincethe supplementary circuit to perform the whole A-D con-version is digital there are good perspectives for constructingan A-D as an adjustment-free digital integrated circuit.

II. LINEAR VOLTAGE-FREQUENCY CONVERSIONA. Basic Principle ofthe CircuitThe first step in the circuit is an integration of a positive

voltage v which only differs from the input voltage vin by aconstant and by the sign (eventually)

m}n.~VVi +K.unc (3)heVEThe starting value of the integration is a constant level VI(Fig. 2(a))

t

v0=+vl +f u dt.

When the level V2 is reached, the logic level of the outputsignal v0It, changes (Fig. 2(b)) and the integrator falls to thelevel VI during the following period t'. Then the output levelof the VFC is changed again and a new integration starts. Theintegration is realized by loading a capacitance (starting froma voltage VI) with a current proportional to the voltage v(Fig. 3). Therefore, the capacitance can be connected with avoltage-controlled current source or placed in the feedback

0018-9421/79/0800-0161 $00.75 © 1979 IEEE

v=+ Vin K. (3)

162 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO. 3, AUGUST 1979

V.

ill ~~~~~~~~~~~I I- ~~~~~~~~~~~~~~~~~~~~~~~~~~~I

'Y; --

L_ _ /

II

out tO

w

Fig. 2. Correspondance between vi, the output signal of the integrator(a) and vout, the output signal of the VFC (b).

_|ntveOu IV,* detec tor

r C _. nivecu 2 (1V2 ) -

Fig. 3. Scheme of a VFC.

3

f (2, 31I 1 1t

To = t + t. The deviation from linearity can be calculated asfollows:

Fig. 4 shows graphically (4) and (6) (respectively, curves 1 and2). We suppose that the curves are realized by the circuit

I between the frequencies ft and f+. We represent (4) and (6)by, respectively,

(tFv=F(f). (7)

For the values of f, with f/ .f Cf, F2(f) can be approx-imated by a straight line, F3 (f), so that

1611=1621=1631with

61 = F3 (f)- F2(-)

63 = F3 (f+)- F2 (f+)62 =max [F3(f)- F2(f)], with f-<f<f+. (8)

61 = 63 if the slope k' of F3(f) is the same as the slope of astraight line between the points A [f., F2 (f[)] and B [f+,F2 (+)]. This slope is

F2 (f+) - F2 (f)f+- f-

If we substitute F2 (f) by the expression in (6) it followsthat

k '= (9)a

with

Fig. 4. Relation between the voltage vand l/t (1) andf(2), respectively.

loop of an operational amplifier. For the detection of thelevels VI and V2 one uses comparators or a flip-flop.

It is important to notice that, in this method, there is a

linear relation between the voltage v and lit, with t equalto the distance between the pulses (Fig. 2(a))

u = k *-.I

a - t'(f++f_)+ tl2f _f

The equation for F3 (f) is

(10)

u=61 ++bk' .f (11with

b = F2(f4) - k'ft. (12The difference 6 = F3 (f) - F2 (f) follows from (6) and (1 1)

=51 +b+kff- kf

(13)

The frequency fof the output signal of the VFC (Fig. 2(b)) is

1 1To t .±t' (5)

The relation between the voltage v and the output frequency ffollows from (4) and (5)

t + t'I

(6)

The voltage v is only approximately linear with the frequencyf: the pulsewidth tP has to be much smaller than the period

The maximum value of 6 is 62 according to (8). We fmd 62by substituting fin (1 3) by the value that makes the derivativeof 8 equal to zero.

df°0 (14)

The solutions of (14) are

t

We are only interested in the solution that lies between ft andf+. This has to be (1 - x/W)/t' since (1 + /a)/t' > lit' and

V2

(a)VI +

(b)

k f

1)

2)

VANDEURSEN AND PEPERSTRAETE: ANALOG-TO-DIGITAL CONVERTER

+ 8 V

39kQ0

VInI

Fig. 5. A simple and low-cost VFC circuit.

lIt' > f. Substituting this solution into (13), we get 62 . Nowwe require that

152 1 = 1611or

61+b+k' - 1 (15)blbfk to -l-_t'(l =Y)15

If 161 l= 162 163 1 than ±1b I is the greatest deviationbetween F2(f) and the approximation by a straight lineF3 (f). So it is also the maximum error on the linearity ofF2 (f). From (6), (9), (12), (15) it follows that

161ik [1f f +(1-Ya)']2 (16)

The relative error on the linearity is given by 161 I/A V whereA V is the input voltage range corresponding to the outputfrequency range 4 - f. We can express it as a percentage ofthe voltage range

16, I± ' 100 percent. (17)

B. Example ofa CircuitA circuit, proposed in [1 , has been tested. We only choose

another value of the supply voltage to get a symmetricalinput voltage range between - 5 and +5 V (Fig. 5).The signal v1 of Fig. 2 is realized in the point A by the

capacitance Cl and a voltage-controlled current source consist-ing of a current mirror of two p-n-p transistors. Since thevoltage in the point B is fixed, the current through the inputresistor (39 kQ) is proportional to the input voltage. Thecurrent in the transistors of the current mirror is the same. Wealso used a polycarbonate capacitance for C, to assure agreater temperature stability. The correspondance betweenthe input voltage and the output signal frequency is given inTable I.The relation between input voltage and output frequency as

determined by (3) and (6) is given in the first and secondcolumn. The results in the second column show a nonlinearityof ±0.4 percent. A part of this nonlinearity is caused bytaking the output frequency as a measure for the input voltageinstead of the value of l/t as we showed earlier. The deviationso introduced is calculated in (16) and (17). For this circuit

TABLE IINPUT VOLTAGE-OUTPUT FREQUJENCY RELATIONSHIP IN THE

CIRCUIT OF FIG. 5

Input voltage vin Output frequency Corresponding(Volts) = 1

t+t value of (kHz)(kHz)

f () 1 A

- 5.00 25.60 ) 1.97 26-67 2.16- 4.00 23.63 2.01 24.51 2.14- 3.00 21.62 2.00 22-372.00 ~~~~~~~~2.13- 2.00 19.62 2.01 20.24 2.12- 1.00 17.61 2.02 18 12 2.15

0.00 15.59 2.03 15-97 2.12+ 1.00 13-56 2.06 13-85 2.15+ 2.00 11.50 2.06 11.70 2.12+ 3.00 9.44 2.08 9.58 2.13+ 4.00 7.36 2.10 7.45 2.15+ 5.00 5.26 5.30

(tC 1.5 ps) it amounts to ±0.39 percent. So it forms thegreatest contribution to the total nonlinearity.Columns one and three in Table I show the relation between

the input voltage and the value lIt as given by (3) and (4).The linearity is improved but the improvement cannot beshowed perfectly since the accuracy of the results in columnthree is of the same order of magnitude as the accuracy of themeasurement. (The error on the values in the first and thirdcolumn is, respectively, ± 10 mV and ±10 Hz.)For a good interpretation of the results of Table I one has to

know that they give only an impression of the linearity ofthecircuit. We have not taken into account the time and tempera-ture stability. The output frequency is also sensitive to supplyvoltage variations. (The sensitivity equals 1.3 kHz/V for thepositive supply voltage and 0.8 kHz/V for the negative supplyvoltage.) Finally, we have to notice that in some VFC's thepulsewidth of the output signal is greater than the time t'necessary for the signal vi (Fig. 2) to drop from a voltage V2to a voltage VI: Indeed, in a high-performance VFC with anonlinearity of only 0.01 percent, t has to be less than 800 ns(if f_ = 0 and f+ = 10 kHz). A pulsewidth equal to t' would betoo small. Therefore, one designs a circuit with a pulsewidthequal to t plus a certain constant value. Some examples aregiven in [21-[51. Then also t = To - t6 but t is not equal tothe distance between the pulses (Fig. 6).

III. ANALOG-TO-DIGITAL CONVERSION WITH A VFCThe digital circuit following the VFC measures the period

of the output signal of the VFC. A binary counter counts thepulses of a clock with a frequency much higher than the VFCfrequency. The counter is started at the beginning of a periodof the VFC signal. At the end of that period, the outputbinary number of the counter is latched and it can be read inby a computer. This number N is proportional to the periodof the VFC signal if the clock period is constant (after a cor-rection according to the measuring method, as we shall seelater).The circuit and the different signals in it are given in the

163

164 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO. 3, AUGUST 1979

Fig. 6. Correspondance between the output signal of the integrator andthe output signal of a high-performance VFC.

Fig. 7. Digital circuit producing a binary number proportional to theVFC output perod.

Figs. 7 and 8. We use JK master-slave flip-flops with theproperty that prest overrides clear. Therefore, the presetsignal has to be generated by a NAND with the clear signal atthe input.

Preset: (Q, 'Q2 *X instead of (Q1 ' Q2).

So, at the moment t2 (Fig. 8), the preset goes off when theclear comes up. Only then the clear can influence the flip-flop. (Notice: "Off' means: no influence on the circuit,which corresponds to a logical "1" level, for "up" the inverseis valid). The flip-flop outputs realize a counting of the clockpulses during the time [to, t1 J when the preset and the clearare "off." The circuit is synchronuous. For this applicationit is faster than an asynchronuous circuit and almost as simple:the asynchronuous circuit does not need the NAND gates atthe inputs J2 and K2. On the other hand, the NAND gate atthe input K2 also realizes 7 which is necessary in the asyn-chronuous circuit too. We also used twice a flip-flop outputfollowed by an inverter instead of the inverse flip-flop output:the inverter has to introduce a delay of the signal to avoidspikes at the output of a NAND as illustrated in Fig. 9.The counter is started at the moment t1 by the signal Z.

From t2 the output signal of the counter also appears at theoutput of the latch. During the time [t2, t3] the latch outputfollows the counter output and form t3 the latch output re-mains fixed on its value at the moment t3. The counter iscleared on t4, on the second clock transition after t3 rather

Latch X

~~~~~~~~~~Clear X

Clock T |1FhflFnFn

iiIl

Z - K2

O it2 p3 t4tI

Fig. 8. Different signals in the circuit of Fig. 7.

than on the first transition, because this transition can coin-cide with t3. From ts a new counting cycle starts.The number N, appearing at the output of the latch at the

moment t3, satisfies the following equation (taking into ac-count the definitions (19) and Fig. 8):N Tk =d

if

fk =I

= clock frequency = a constant

and

fo = y = VFC output frequency.

Since

d=To-(d1 +d2)

d1 =2Tk+x Tk,and

d2 =y Tk,(18) becomes

TON ° - {2+x+y)Tk

(18)

(19)

with 0 <x K 1

with O<y< I

with 0 <x + y < 2

or

N + 3 + (x + y -

and

NT± z=To1Tk

if

NzxN+ 3

Z = Ix + y - 1 1,

Tk

where z <+ 1.

VANDEURSEN AND PEPERSTRAETE: ANALOG-TO-DIGITAL CONVERTER

x

-- ---_

y (delayed )

z

Fig. 9. Use of a delay in the case of simultaneous changing inputs of a NAND gate.

Forn = 10 andft=0Hz,f,= 10kHz

fk = 10.24 MHz.(20)

where z is an unknown quantity. We conclude that N'Tk de-termines To with a maximum error equal to Tk. The accuracycorresponds with the resolution of the measurement.To complete the conversion, the computer has to calculate

a number proportional to the frequency of the VFC and thusto the analog input signal. From (20) and the defmition ofN' it follows that

fkfo = ±q. (21)

The error q is due to the fact that in the denominator of (21)N' ± z is rounded off to N' =N + 3. The quantization errorQ is the maximum value of q, corresponding to a value of zequal to 1.

Q = fk _ fk

(N+ 3)- I N+ 3

or

fk

Q(N+3)2 - (N+-3)According to (21)N+ 3 4fk/fo and

Q = J o . (22)fk -fo

The quantization error is a function of the frequencyfo and ismaximal for the maximum frequency f+

2

Qmax =fk - fv

(23)

If we want a resolution of n bits then Qmax has to satisfy thefollowing unequality:

Qmax < 2n -1 (24)

The minimum clock frequency fk to reach such a resolutionfollows from (23) and (24)

f2(2n

1)+~~~~f. (25)

This frequency corresponds to the limit of the TTL logic. Fora resolution better than 10 bits we have to choose anotherlogic: Schottky-TTL, high-speed TTL, and ECL.

If the maximum speed in a certain logic is called fk,maxthen the lowest value of Qmax (formula (23)) is given by

f 2Q

fk, max fiA further lowering of Qmax in that logic is only possible bylowering f. Since f+ determines the conversion speed, wehave to make a compromise between conversion speed andresolution.

Finally, we remark that, according to the theory of SectionII-A and (4) it would be more accurate to measure the distancebetween the pulses and to calculate llt instead of measuringthe period To = t + t' and calculating the frequency fo = 1 ITo.However, as we mentioned at the end of Section II-B, manyaccurate VFC's have a pulsewidth greater than tz so that thedistance between the pulses is lower than t (see definitions onFig. 2(a): t = risetime of the signal vi, tI = fall time).

In this case, the time t cannot be measured but, knowingthat t' is low, mostly it is superfluous.Eventually we can calculate t from To if t6 is known (speci-

fied by the constructor).If

tIU =

Tk

then

t =u Tk

and

t==To - t' = To - u Tk.

Taking into account (20) for Tot=(N ± Z) Tk u Tk

t= (N + 3 - u) Tk ± z * Tk

x

y

Z =(x. y

Thus

To = N'Tk ± z * TkTo = (N' ± z) Tk

165

166 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS AND CONTROL INSTRUMENTATION, VOL. IECI-26, NO. 3, AUGUST 1979

and

1 fkt N+3-u -'

hnearity of some simple VFC circuits: one can substitute theoutput frequency by llt as a measure of the input voltage.

(26) (t equals the VFC output period minus the time to dechargea capacitance in the circuit.)

This formula replaces (21).

CONCLUSIONSThis method to convert the VFC output signal in a binary

word proportional to the VFC input voltage has two advan-tages: it is faster than performing the conversion by countingthe number of pulses of the VFC output within a constanttime. Also, there is a possibility to improve the conversion

REFERENCES

[11 R. Tenny, "Linear VCO made from a 555 timer," Electron. Des.,p. 96, Oct. 1975.

[21 "High-accuracy voltage-to-frequency converter," Panelectronics,no.2,p.46,1976.

[3] "Spannungs-Frequenz-Wandler fir 1 MHz," Elektronik Industrie11/12, p. 229, 1975.

[4] Burr-Brown Catalog, pp. 18-19, 1976.[5] Analog Devices, Data Sheets C361-1O-10/75 and C376-8-1/76.

Analysis and Design of Pulse Ratio ModulatedFeedback Control Systems

GIUSEPPE DE MARIA AND LORENZO SCIAVICCO

Abstract-An exact method of analysis is presented for a class ofpulse-modulated feedback control systems which can be modeled by amultiple-loop nonlinear feedback system. The nonlinearity has a hys-teresis characteristic. By means of the Tsypkin-Hamel criterion, suit-ably modified, a set of equations is obtained, determining the switchingfrequency, duty cycle, and steady-state dc error. Based on the graphi-cal form of these equations, a design procedure is set forth. Specificcases have been examined and peculiar phenomena are evidenced;experimental data verify both the chosen model and the suggested pro-cedures. A simplified pulse ratio modulator is also presented.

INTRODUCTIONTHE DC/DC CONVERTERS may be considered as pulse

modulators; the modulation laws usually implemented arethose relative to pulse-frequency modulation (PFM) and pulse-width modulation (PWM) techniques. The pulse-ratio modula-tion (PRM) technique, providing several advantages comparedto the conventional pulse-modulation methods, has been de-veloped for applications in a space vehicle attitude controlsystem. Because the capability to operate with a high degreeof accuracy and to overcome certain bandwidth problems, as-sociated with other modulation techniques, the PRM appearsto hold excellent possibilities for application in a broad range

Manuscript received March 7, 1978; revised March 26, 1979. Thiswork was supported by the Consiglio Nazionale delle Ricerche.The authors are with the Istituto Elettrotecnico, University of Naples,

80125-Naples, Italy.

of control systems, such as power conditioning circuitry ortemperature controlPulse modulators can be classified as synchronous and asyn-

chronous [1] In the synchronous ones (PWM) the timingsignals are obtained from an external oscillator; in the asyn-chronous or free-running converters the oscillations requiredfor the conversion are maintained by the regulation feedbackpath (in relay control system) and/or by internal feedbackpath which determines, jointly with the nonlinearity shape,the modulation law (PFM and PRM). The internal feedbackpath, as shown in the foliowimg, enables one to increase theworking frequency with respect to relay control systems andhence to reduce the ripple magnitude on the regulated output.Whereas different methods of analysis and design exist for

PWM, PFM, and ON-OFF feedback control systems [21 -[8],only few papers are known concerning the pulse ratio modu-lator working principles [9] and methods of analysis of PRMfeedback systems based on the time-domain approach [10],[11] or on simulation techniques [1],in spite of its interest-ing application possibilities.The design of a PRM feedback system is quite complicated:

the system is indeed nonlinear and the self-oscillation and theoutput regulation are influenced by the same feedback paths.In order to face this problem a mathematical model is pro-posed for the PRM.In developing analysis and design procedures for PRM feed-

back control systems, methods for the determination of free

0018-9421/79/0800-0166$00.75 © 1979 IEEE